1 /*- 2 * Copyright (c) 1985 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Computer Consoles Inc. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)psl.h 7.2 (Berkeley) 05/08/91 11 */ 12 13 /* 14 * TAHOE processor status longword. 15 */ 16 #define PSL_C 0x00000001 /* carry bit */ 17 #define PSL_V 0x00000002 /* overflow bit */ 18 #define PSL_Z 0x00000004 /* zero bit */ 19 #define PSL_N 0x00000008 /* negative bit */ 20 #define PSL_ALLCC 0x0000000f /* all cc bits - unlikely */ 21 #define PSL_T 0x00000010 /* trace enable bit */ 22 #define PSL_IV 0x00000020 /* integer overflow enable bit */ 23 #define PSL_FU 0x00000040 /* float underflow enable */ 24 #define PSL_DBL 0x00000080 /* f.p. prescision indicator */ 25 #define PSL_SFE 0x00000100 /* system-forced-exception */ 26 #define PSL_IPL 0x001f0000 /* interrupt priority level */ 27 #define PSL_PRVMOD 0x00000000 /* previous mode (kernel mode) */ 28 #define PSL_CURMOD 0x01000000 /* current mode (all on is user) */ 29 #define PSL_IS 0x04000000 /* interrupt stack */ 30 #define PSL_TP 0x40000000 /* trace pending */ 31 32 #define PSL_MBZ 0xbae0fe00 /* must be zero bits */ 33 34 #define PSL_USERSET (PSL_CURMOD) 35 #define PSL_USERCLR (PSL_IS|PSL_IPL|PSL_MBZ|PSL_SFE|PSL_DBL|PSL_FU) 36