1 /******************************Module*Header**********************************\
2 *
3 * Module Name: d3dkmdt.h
4 *
5 * Content: Windows Display Driver Model (WDDM) kernel mode
6 * data type definitions
7 *
8 * Copyright (c) Microsoft Corporation.
9 * Licensed under the MIT License.
10 *
11 \*****************************************************************************/
12 #ifndef _D3DKMDT_H
13 #define _D3DKMDT_H
14
15 #if !defined(_D3DKMDDI_H_) && \
16 !defined(_D3DKMDDI_PEXT_H_) && \
17 !defined(_DXGDMM_H_) && \
18 !defined(_VIDPRIV_H_) && \
19 !defined(_DISPMPRT_H_) && \
20 !defined(_DMM_DIAG_H_) && \
21 !defined(_D3DKMTHK_H_)
22 #error This header should not be included directly!
23 #endif
24
25 #include "d3dukmdt.h"
26
27 #define NTSTATUS int32_t
28
29 /*
30 * Some of the Windows return codes, which needs to be translated to Linux
31 * IOCTL return codes. Positive values are success codes and need to be
32 * returned from the driver IOCTLs. libdxcore.so depends on returning
33 * specific return codes.
34 */
35 #define STATUS_SUCCESS ((NTSTATUS)(0))
36 #define STATUS_OBJECT_NAME_INVALID ((NTSTATUS)(0xC0000033L))
37 #define STATUS_DEVICE_REMOVED ((NTSTATUS)(0xC00002B6L))
38 #define STATUS_INVALID_HANDLE ((NTSTATUS)(0xC0000008L))
39 #define STATUS_ILLEGAL_INSTRUCTION ((NTSTATUS)(0xC000001DL))
40 #define STATUS_NOT_IMPLEMENTED ((NTSTATUS)(0xC0000002L))
41 #define STATUS_PENDING ((NTSTATUS)(0x00000103L))
42 #define STATUS_ACCESS_DENIED ((NTSTATUS)(0xC0000022L))
43 #define STATUS_BUFFER_TOO_SMALL ((NTSTATUS)(0xC0000023L))
44 #define STATUS_OBJECT_TYPE_MISMATCH ((NTSTATUS)(0xC0000024L))
45 #define STATUS_GRAPHICS_ALLOCATION_BUSY ((NTSTATUS)(0xC01E0102L))
46 #define STATUS_NOT_SUPPORTED ((NTSTATUS)(0xC00000BBL))
47 #define STATUS_TIMEOUT ((NTSTATUS)(0x00000102L))
48 #define STATUS_INVALID_PARAMETER ((NTSTATUS)(0xC000000DL))
49 #define STATUS_NO_MEMORY ((NTSTATUS)(0xC0000017L))
50 #define STATUS_OBJECT_NAME_COLLISION ((NTSTATUS)(0xC0000035L))
51 #define STATUS_OBJECT_NAME_NOT_FOUND ((NTSTATUS)(0xC0000034L))
52 #define STATUS_UNSUCCESSFUL ((NTSTATUS)(0xC0000001L))
53 #define STATUS_INVALID_PARAMETER ((NTSTATUS)(0xC000000DL))
54 #define NT_SUCCESS(status) (status >= 0)
55
56 typedef enum {
57 PowerActionNone = 0,
58 PowerActionReserved,
59 PowerActionSleep,
60 PowerActionHibernate,
61 PowerActionShutdown,
62 PowerActionShutdownReset,
63 PowerActionShutdownOff,
64 PowerActionWarmEject,
65 PowerActionDisplayOff
66 } POWER_ACTION, *PPOWER_ACTION;
67
68 typedef enum _DEVICE_POWER_STATE {
69 PowerDeviceUnspecified = 0,
70 PowerDeviceD0,
71 PowerDeviceD1,
72 PowerDeviceD2,
73 PowerDeviceD3,
74 PowerDeviceMaximum
75 } DEVICE_POWER_STATE, *PDEVICE_POWER_STATE;
76
77 #pragma region Desktop Family
78 #if WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_DESKTOP)
79
80 #pragma warning(push)
81 #pragma warning(disable:4201) // anonymous unions warning
82 #pragma warning(disable:4214) // nonstandard extension used: bit field types other than int
83
84 //
85 // Available only for Vista (LONGHORN) and later and for
86 // multiplatform tools such as debugger extensions
87 //
88 #if (NTDDI_VERSION >= NTDDI_LONGHORN) || defined(D3DKMDT_SPECIAL_MULTIPLATFORM_TOOL)
89
90 //
91 // Hardcoded overlay count
92 //
93 #define D3DKMDT_MAX_OVERLAYS_BITCOUNT 2
94 #define D3DKMDT_MAX_OVERLAYS (1 << D3DKMDT_MAX_OVERLAYS_BITCOUNT)
95
96
97 //////////////////// VidPN management DDI handles /////////////////////////////////////////////////////////
98 DECLARE_HANDLE(D3DKMDT_HVIDPN);
99 DECLARE_HANDLE(D3DKMDT_HVIDEOPRESENTSOURCESET);
100 DECLARE_HANDLE(D3DKMDT_HVIDEOPRESENTTARGETSET);
101 DECLARE_HANDLE(D3DKMDT_HVIDPNTOPOLOGY);
102 DECLARE_HANDLE(D3DKMDT_HVIDPNSOURCEMODESET);
103 DECLARE_HANDLE(D3DKMDT_HVIDPNTARGETMODESET);
104 DECLARE_HANDLE(D3DKMDT_HMONITORSOURCEMODESET);
105 DECLARE_HANDLE(D3DKMDT_HMONITORFREQUENCYRANGESET);
106 DECLARE_HANDLE(D3DKMDT_HMONITORDESCRIPTORSET);
107
108 // Alias VOID* to make LDDM kernel mode interface prototypes using adapter handles self-explanatory.
109 typedef VOID* D3DKMDT_ADAPTER;
110
111
112
113 //////////////////// VidPN management DDI constants /////////////////////////////////////////////////////////
114
115 // Special values representing that given variable has not been initialized to a valid value intended
116 // to catch development time errors. A valid parameter should never have this value.
117 #define D3DKMDT_DIMENSION_UNINITIALIZED (UINT)(~0)
118 #define D3DKMDT_FREQUENCY_UNINITIALIZED (UINT)(~0)
119
120 // Special values representing that given parameter is not-specified.
121 // A parameter having this value should be ignored.
122 #define D3DKMDT_DIMENSION_NOTSPECIFIED (UINT)(~1)
123 #define D3DKMDT_FREQUENCY_NOTSPECIFIED (UINT)(~1)
124
125
126
127 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
128 // Purpose: Video mode standard descriptor type, listing standards that are explicitly supported by Windows.
129 //
130 // Remarks: This enum specifies based on which standard the video signal timing parameters should be computed.
131 // Note that NTSC, PAL, and SECAM mode variants are treated as individual groups to avoid complicating
132 // the DDI with the notion of "sub-standard" (because they don't differ from each other in the parameters
133 // used to describe the video signal in the DDI and the parameters that they do differ in are of no
134 // interest to us in DMM).
135 //
136 typedef enum _D3DKMDT_VIDEO_SIGNAL_STANDARD
137 {
138 D3DKMDT_VSS_UNINITIALIZED = 0,
139
140 // VESA standards
141 D3DKMDT_VSS_VESA_DMT = 1, // See VESA Display Monitor Timings specification
142 D3DKMDT_VSS_VESA_GTF = 2, // See VESA Generalized Timing Formula standard
143 D3DKMDT_VSS_VESA_CVT = 3, // See VESA Coordinated Video Timings standard
144
145 // De-facto standards
146 D3DKMDT_VSS_IBM = 4,
147 D3DKMDT_VSS_APPLE = 5,
148
149 // Legacy STV standards W x H{i|p} @ ( VR / HR )
150 D3DKMDT_VSS_NTSC_M = 6, // 720 x 525i @ (59.94 [Hz] / 15,734.27[Hz])
151 D3DKMDT_VSS_NTSC_J = 7, // 720 x 525i @ (59.94 [Hz] / 15,734.27[Hz])
152 D3DKMDT_VSS_NTSC_443 = 8, // 720 x 525i @ (59.94 [Hz] / 15,734.27[Hz])
153 D3DKMDT_VSS_PAL_B = 9, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
154 D3DKMDT_VSS_PAL_B1 = 10, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
155 D3DKMDT_VSS_PAL_G = 11, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
156 D3DKMDT_VSS_PAL_H = 12, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
157 D3DKMDT_VSS_PAL_I = 13, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
158 D3DKMDT_VSS_PAL_D = 14, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
159 D3DKMDT_VSS_PAL_N = 15, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
160 D3DKMDT_VSS_PAL_NC = 16, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
161 D3DKMDT_VSS_SECAM_B = 17, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
162 D3DKMDT_VSS_SECAM_D = 18, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
163 D3DKMDT_VSS_SECAM_G = 19, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
164 D3DKMDT_VSS_SECAM_H = 20, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
165 D3DKMDT_VSS_SECAM_K = 21, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
166 D3DKMDT_VSS_SECAM_K1 = 22, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
167 D3DKMDT_VSS_SECAM_L = 23, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
168 D3DKMDT_VSS_SECAM_L1 = 24, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
169
170 // CEA/EIA standards
171 D3DKMDT_VSS_EIA_861 = 25,
172 D3DKMDT_VSS_EIA_861A = 26,
173 D3DKMDT_VSS_EIA_861B = 27,
174
175 // More legacy STV standards
176 D3DKMDT_VSS_PAL_K = 28, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
177 D3DKMDT_VSS_PAL_K1 = 29, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
178 D3DKMDT_VSS_PAL_L = 30, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
179 D3DKMDT_VSS_PAL_M = 31, // 720 x 525i @ (59.94 [Hz] / 15,734 [Hz])
180
181 D3DKMDT_VSS_OTHER = 255
182 }
183 D3DKMDT_VIDEO_SIGNAL_STANDARD;
184
185
186
187 //////////////////// Video present sources //////////////////////////////////////////////////////////////////
188
189
190 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
191 // Purpose: Video present source descriptor type.
192 //
193 typedef struct _D3DKMDT_VIDEO_PRESENT_SOURCE
194 {
195 // Unique ID used to reference the respective video present source by the miniport and the OS.
196 D3DDDI_VIDEO_PRESENT_SOURCE_ID Id;
197
198 // Other video present source descriptor properties go here.
199 DWORD dwReserved;
200 }
201 D3DKMDT_VIDEO_PRESENT_SOURCE;
202
203
204 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
205 // Purpose: VidPN source mode enumeration type descriptor type.
206 //
207 // Remarks: This type is used to specify whether a VidPN source mode is a graphics or a text mode
208 // (see VIDEO_PRESENT_SOURCE_MODE for more details).
209 //
210 typedef enum _D3DKMDT_VIDPN_SOURCE_MODE_TYPE
211 {
212 D3DKMDT_RMT_UNINITIALIZED = 0,
213 D3DKMDT_RMT_GRAPHICS = 1,
214 D3DKMDT_RMT_TEXT = 2,
215 D3DKMDT_RMT_GRAPHICS_STEREO = 3,
216 D3DKMDT_RMT_GRAPHICS_STEREO_ADVANCED_SCAN = 4
217 }
218 D3DKMDT_VIDPN_SOURCE_MODE_TYPE;
219
220
221 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
222 // Purpose: Pixel value access mode descriptor type.
223 //
224 // Remarks: Use Direct to represent VidPN source modes with colors stored directly in the primary surface.
225 // Use PresetPalette to represent VidPN source modes with colors' indices stored in the primary
226 // surface and actual color values stored in a palette specific to the video card, that must
227 // be queried from the video miniport.
228 // Use SettablePalette to represent VidPN source modes with colors' indices stored in the primary
229 // surface and actual color values stored in a settable palette that can be dynamically set on
230 // the video card, by specifying it to the video miniport.
231 //
232 typedef enum _D3DKMDT_PIXEL_VALUE_ACCESS_MODE
233 {
234 D3DKMDT_PVAM_UNINITIALIZED = 0,
235 D3DKMDT_PVAM_DIRECT = 1,
236 D3DKMDT_PVAM_PRESETPALETTE = 2,
237 D3DKMDT_PVAM_SETTABLEPALETTE = 3,
238 }
239 D3DKMDT_PIXEL_VALUE_ACCESS_MODE;
240
241
242 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
243 // Purpose: Descriptor type of the color basis with respect to which the pixels' colors are expanded,
244 // or conversely, based on which the color values are synthesized.
245 //
246 // Remarks: The commonly used color bases in graphics industry are RGB, which has the basis (red, green, blue),
247 // as well as YPbPr and YCbCr, which have scaled variants of basis:
248 // (1, blue-1, red-1)*intensity(red,green,blue).
249 // Tri-stimulus linear RGB is well suited for real-time rendering, since most filtering algorithms
250 // use tri-stimulus values to approximate light's spectral transformations caused by its interaction
251 // with the environment, primarily due to the fact that there is a linear relationship between the
252 // perceived light level and the light's spectral intensity. Ideally, all processing of video content
253 // (i.e. scaling, filtering, etc) should be performed in a linear RGB space.
254 // Y'PbPr spaces store data using a nonlinear curve which is approximately the inverse of a gamma
255 // 2.2 curve (i.e. x^0.45). This allows more precision to be stored in darker intensities where the
256 // human eye is more sensitive.
257 // sRGB (more accurately, sR'G'B') stores light intensities relative to a gamma curve.
258 // scRGB stores linear values and requires much higher precision to represent the same perceptually
259 // similar signal.
260 // The light-intensity based YPbPr and YCbCr is better suited for persistence of pre-rendered content,
261 // such as video streaming. This is due to the fact that a human visual system is more responsive to
262 // small differences in photons' intensity rather than frequency (i.e. perceived color), and, hence,
263 // a light-intensity based color expansion over a finite dynamic range, yields a better perceptual
264 // image quality for the human eye than a tri-stimulus based color expansion in that same range
265 // (e.g non-linear Y8Cb8Cr8 appears slightly better than R8G8B8 and is comparable to R9G9B9).
266 // To represent monochrome modes, use Intensity. Grayscale imaging is heavily used in medical imaging.
267 // Note: the apostrophe notation Y'PbPr is used to remind you that you are working with non-linear data.
268 //
269 typedef enum _D3DKMDT_COLOR_BASIS
270 {
271 D3DKMDT_CB_UNINITIALIZED = 0,
272 D3DKMDT_CB_INTENSITY = 1,
273 D3DKMDT_CB_SRGB = 2,
274 D3DKMDT_CB_SCRGB = 3,
275 D3DKMDT_CB_YCBCR = 4,
276 D3DKMDT_CB_YPBPR = 5,
277 }
278 D3DKMDT_COLOR_BASIS;
279
280 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
281 // Purpose: Descriptor type of the color coefficients dynamic range, whose linear combination with the
282 // respective color basis produces final pixel values.
283 //
284 // Remarks: Examples include (5,6,5,0) for R5G6B5, (8,8,8,8) for R8G8B8A8, and (24, 0, 0, 0) for 24-bit
285 // grayscale pixel encoding format.
286 // NOTE: Currently this is only used for target modes, none of which has the 4th channel (e.g. alpha).
287 // We are keeping the 4th field for extensibility purpose to avoid miniport interface revision
288 // if 4-channel video interfaces became available between display adapter and monitor.
289 //
290 typedef struct _D3DKMDT_COLOR_COEFF_DYNAMIC_RANGES
291 {
292 UINT FirstChannel;
293 UINT SecondChannel;
294 UINT ThirdChannel;
295 UINT FourthChannel;
296 }
297 D3DKMDT_COLOR_COEFF_DYNAMIC_RANGES;
298
299
300 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
301 // Purpose: 2D region descriptor type.
302 //
303 // Remarks: We define our own rather than reusing SIZE type to avoid dependency on SDK headers.
304 //
305 typedef struct _D3DKMDT_2DREGION
306 {
307 UINT cx;
308 UINT cy;
309 }
310 D3DKMDT_2DREGION;
311
312
313 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
314 // Purpose: 2D offset descriptor type.
315 //
316 // Remarks: We define our own rather than reusing SIZE type to avoid dependency on SDK headers.
317 //
318 typedef D3DKMDT_2DREGION D3DKMDT_2DOFFSET;
319
320
321 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
322 // Purpose: Graphics video present source mode descriptor type.
323 //
324 // Remarks: Graphics video present source mode is the dominantly used subtype of the video present source
325 // modes (other being the text video present source mode).
326 // Note that whenever video present source mode's visible size,
327 // VIDEO_PRESENT_SOURCE_MODE.GRAPHICS_RENDERING_FORMAT.sizeVisible is not equal to the respective
328 // video mode's visible size, VIDEO_PRESENT_TARGET_MODE.sizeVisible, h/w scaling is undertaken by
329 // the video output codec.
330 //
331 // Miniport is free to support any D3D pixel format for its graphics modes that is meaningful
332 // as a primary surface pixel format.
333 //
334 typedef struct _D3DKMDT_GRAPHICS_RENDERING_FORMAT
335 {
336 // Size of the primary surface required for this VidPN source mode.
337 D3DKMDT_2DREGION PrimSurfSize;
338
339 // Size of the visible part of the primary surface, used for panned modes including zoom modes.
340 // The visible region size is required to be the same as the primary surface
341 D3DKMDT_2DREGION VisibleRegionSize;
342
343 // Number of bytes between the start of one scan line and the next.
344 DWORD Stride;
345
346 // Pixel format type
347 D3DDDIFORMAT PixelFormat;
348
349 // Color basis with respect to which rendering client encodes pixel values.
350 D3DKMDT_COLOR_BASIS ColorBasis;
351
352 // Access mode for the pixel value information.
353 D3DKMDT_PIXEL_VALUE_ACCESS_MODE PixelValueAccessMode;
354 }
355 D3DKMDT_GRAPHICS_RENDERING_FORMAT;
356
357
358 typedef enum _D3DKMDT_TEXT_RENDERING_FORMAT
359 {
360 D3DKMDT_TRF_UNINITIALIZED = 0
361 }
362 D3DKMDT_TEXT_RENDERING_FORMAT;
363
364
365 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
366 // Purpose: Video present source mode ID type.
367 typedef UINT D3DKMDT_VIDEO_PRESENT_SOURCE_MODE_ID;
368
369 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
370 // Purpose: VidPN source mode descriptor type.
371 //
372 // Remarks: VidPN source (rendering) mode is the mode of operation of a given video present source and determines
373 // the format of this source's primary surface to which the graphics subsystem is rendering
374 // the visual image to be presented to the user, and from which the video output codec is reading
375 // the visual image content to be converted into a respective video mode signal.
376 //
377 typedef struct _D3DKMDT_VIDPN_SOURCE_MODE
378 {
379 D3DKMDT_VIDEO_PRESENT_SOURCE_MODE_ID Id;
380
381 // Specifies whether the mode is a graphics or a text rendering mode.
382 D3DKMDT_VIDPN_SOURCE_MODE_TYPE Type;
383
384 union
385 {
386 // Descriptor of the graphics rendering mode (valid only if Type==D3DKMDT_RMT_GRAPHICS).
387 D3DKMDT_GRAPHICS_RENDERING_FORMAT Graphics;
388
389 // Descriptor of the text rendering mode (valid only if Type==D3DKMDT_RMT_TEXT).
390 D3DKMDT_TEXT_RENDERING_FORMAT Text;
391 }
392 Format;
393 }
394 D3DKMDT_VIDPN_SOURCE_MODE;
395
396
397
398 //////////////////////// Video present targets///////////////////////////////////////////////////////////////
399
400
401 // NOTE: Child device (e.g. video output) HPD awareness is used to represent the level of external
402 // device (e.g. monitor) connectivity sensed by a display adapter. Child device can either be
403 // always connected to an external device (e.g. integrated LCD in a mobile system) or have:
404 // 1. No HPD-awareness iff miniport is *not* aware of external device arrivals/departures
405 // whether through interrupts or polling,
406 // 2. Polled HPD-awareness iff miniport can not asynchronously notify the OS about external
407 // device arrivals/departures, but OS can sporadically poll for its presence, and of a
408 // monitor, causing visual artifacts on each poll.
409 // 3. Interruptible HPD-awareness iff miniport can asynchronously notify the OS about
410 // external device arrivals/departures.
411 typedef enum _DXGK_CHILD_DEVICE_HPD_AWARENESS {
412 HpdAwarenessUninitialized = 0,
413 HpdAwarenessAlwaysConnected = 1,
414 HpdAwarenessNone = 2,
415 HpdAwarenessPolled = 3,
416 HpdAwarenessInterruptible = 4
417 } DXGK_CHILD_DEVICE_HPD_AWARENESS, *PDXGK_CHILD_DEVICE_HPD_AWARENESS;
418
419 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
420 // Purpose: Monitor orientation descriptor type.
421 //
422 typedef enum _D3DKMDT_MONITOR_ORIENTATION
423 {
424 D3DKMDT_MO_UNINITIALIZED = 0,
425 D3DKMDT_MO_0DEG = 1,
426 D3DKMDT_MO_90DEG = 2,
427 D3DKMDT_MO_180DEG = 3,
428 D3DKMDT_MO_270DEG = 4
429 }
430 D3DKMDT_MONITOR_ORIENTATION;
431
432
433 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
434 // Purpose: Video output technology descriptor type.
435 //
436 // Remarks: Video output technology is used to determine the hard-coded list of video modes supported
437 // by the monitor, when monitor descriptor is not available.
438 //
439 typedef enum _D3DKMDT_VIDEO_OUTPUT_TECHNOLOGY
440 {
441 D3DKMDT_VOT_UNINITIALIZED = -2,
442 D3DKMDT_VOT_OTHER = -1,
443 D3DKMDT_VOT_HD15 = 0,
444 D3DKMDT_VOT_SVIDEO = 1,
445 D3DKMDT_VOT_COMPOSITE_VIDEO = 2,
446 D3DKMDT_VOT_COMPONENT_VIDEO = 3,
447 D3DKMDT_VOT_DVI = 4,
448 D3DKMDT_VOT_HDMI = 5,
449 D3DKMDT_VOT_LVDS = 6,
450 D3DKMDT_VOT_D_JPN = 8,
451 D3DKMDT_VOT_SDI = 9,
452 D3DKMDT_VOT_DISPLAYPORT_EXTERNAL = 10,
453 D3DKMDT_VOT_DISPLAYPORT_EMBEDDED = 11,
454 D3DKMDT_VOT_UDI_EXTERNAL = 12,
455 D3DKMDT_VOT_UDI_EMBEDDED = 13,
456 D3DKMDT_VOT_SDTVDONGLE = 14,
457 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3_M1)
458 D3DKMDT_VOT_MIRACAST = 15,
459 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1)
460 D3DKMDT_VOT_INDIRECT_WIRED = 16,
461 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1)
462 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3_M1)
463 D3DKMDT_VOT_INTERNAL = 0x80000000,
464
465 // Remove when DDI is unlocked.
466 D3DKMDT_VOT_SVIDEO_4PIN = D3DKMDT_VOT_SVIDEO,
467 D3DKMDT_VOT_SVIDEO_7PIN = D3DKMDT_VOT_SVIDEO,
468 D3DKMDT_VOT_RF = D3DKMDT_VOT_COMPOSITE_VIDEO,
469 D3DKMDT_VOT_RCA_3COMPONENT = D3DKMDT_VOT_COMPONENT_VIDEO,
470 D3DKMDT_VOT_BNC = D3DKMDT_VOT_COMPONENT_VIDEO,
471 }
472 D3DKMDT_VIDEO_OUTPUT_TECHNOLOGY;
473
474 typedef enum _DXGKMDT_OPM_CONNECTOR_TYPE
475 {
476 DXGKMDT_OPM_CONNECTOR_TYPE_OTHER = -1,
477 DXGKMDT_OPM_CONNECTOR_TYPE_HD15 = 0,
478 DXGKMDT_OPM_CONNECTOR_TYPE_SVIDEO = 1,
479 DXGKMDT_OPM_CONNECTOR_TYPE_COMPOSITE_VIDEO = 2,
480 DXGKMDT_OPM_CONNECTOR_TYPE_COMPONENT_VIDEO = 3,
481 DXGKMDT_OPM_CONNECTOR_TYPE_DVI = 4,
482 DXGKMDT_OPM_CONNECTOR_TYPE_HDMI = 5,
483 DXGKMDT_OPM_CONNECTOR_TYPE_LVDS = 6,
484 DXGKMDT_OPM_CONNECTOR_TYPE_D_JPN = 8,
485 DXGKMDT_OPM_CONNECTOR_TYPE_SDI = 9,
486 DXGKMDT_OPM_CONNECTOR_TYPE_DISPLAYPORT_EXTERNAL = 10,
487 DXGKMDT_OPM_CONNECTOR_TYPE_DISPLAYPORT_EMBEDDED = 11,
488 DXGKMDT_OPM_CONNECTOR_TYPE_UDI_EXTERNAL = 12,
489 DXGKMDT_OPM_CONNECTOR_TYPE_UDI_EMBEDDED = 13,
490 DXGKMDT_OPM_CONNECTOR_TYPE_RESERVED = 14,
491 DXGKMDT_OPM_CONNECTOR_TYPE_MIRACAST = 15,
492 DXGKMDT_OPM_CONNECTOR_TYPE_TRANSPORT_AGNOSTIC_DIGITAL_MODE_A = 16,
493 DXGKMDT_OPM_CONNECTOR_TYPE_TRANSPORT_AGNOSTIC_DIGITAL_MODE_B = 17,
494 DXGKMDT_OPM_COPP_COMPATIBLE_CONNECTOR_TYPE_INTERNAL = 0x80000000
495 } DXGKMDT_OPM_CONNECTOR_TYPE;
496
497 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
498 // Purpose: Monitor orientation awareness descriptor type.
499 //
500 typedef enum _D3DKMDT_MONITOR_ORIENTATION_AWARENESS
501 {
502 D3DKMDT_MOA_UNINITIALIZED = 0,
503 D3DKMDT_MOA_NONE = 1,
504 D3DKMDT_MOA_POLLED = 2,
505 D3DKMDT_MOA_INTERRUPTIBLE = 3
506 }
507 D3DKMDT_MONITOR_ORIENTATION_AWARENESS;
508
509
510 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
511 // Purpose: Video present target descriptor type.
512 //
513 typedef struct _D3DKMDT_VIDEO_PRESENT_TARGET
514 {
515 // Unique ID used to reference the respective video present target by the miniport and the OS.
516 D3DDDI_VIDEO_PRESENT_TARGET_ID Id;
517
518 // Type of the video output technology (see D3DKMDT_VIDEO_OUTPUT_TECHNOLOGY for more details).
519 D3DKMDT_VIDEO_OUTPUT_TECHNOLOGY VideoOutputTechnology;
520
521 // Type of the video output's HPD awareness (see D3DKMDT_VIDEO_OUTPUT_HPD_AWARENESS for more details).
522 DXGK_CHILD_DEVICE_HPD_AWARENESS VideoOutputHpdAwareness;
523
524 D3DKMDT_MONITOR_ORIENTATION_AWARENESS MonitorOrientationAwareness;
525
526 // NOTE: On monitor arrival, OS will leave monitor mode set empty for monitors connected to video outputs
527 // supporting SDTV modes, expecting miniport to populate modes it wants to expose for that monitor.
528 //
529 // NOTE: This predicate is also used when selecting video output for presentation on a TV via
530 // APIs that don't support explicit specification of monitors/video outputs (e.g. VIDEOPARAMETERS).
531 //
532 // Predicate specifying whether corresponding video output supports SDTV modes.
533 BOOLEAN SupportsSdtvModes;
534 }
535 D3DKMDT_VIDEO_PRESENT_TARGET;
536
537
538
539 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
540 // Purpose: Video present target mode GTF compliance descriptor type.
541 typedef enum _D3DKMDT_GTFCOMPLIANCE
542 {
543 D3DKMDT_GTF_UNINITIALIZED = 0,
544 D3DKMDT_GTF_COMPLIANT = 1,
545 D3DKMDT_GTF_NOTCOMPLIANT = 2
546 }
547 D3DKMDT_GTFCOMPLIANCE;
548
549
550 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
551 // Purpose: VidPN target mode preference descriptor type.
552
553 typedef enum _D3DKMDT_MODE_PREFERENCE
554 {
555 D3DKMDT_MP_UNINITIALIZED = 0,
556 D3DKMDT_MP_PREFERRED = 1,
557 D3DKMDT_MP_NOTPREFERRED = 2,
558 }
559 D3DKMDT_MODE_PREFERENCE;
560
561
562 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
563 // Purpose: Video signal info descriptor type.
564 //
565 // Remarks: Video signal info is the mode of operation of a given video output that's driving a connected
566 // moitor and is driven by an internal video output codec.
567 // Note that this descriptor supersedes subset of the XDDM's VIDEO_MODE_INFORMATION structure
568 // related to video mode. In XDDM, both video and rendering modes were described in this struct.
569 // LDDM separates these two notions, and hence their descriptors.
570 // The video standard field, vidStandard, should be used for video mode comparisons, when it's
571 // set to a well-defined video standard. Note that most of the standard modes do not comply with
572 // the VESA GTF frequency constraints.
573 //
574 // If color basis of the target mode does not correspond to that of the source mode, appropriate
575 // color conversion is performed by the respective video output codec.
576 //
577 typedef struct _D3DKMDT_VIDEO_SIGNAL_INFO
578 {
579 // Video mode standard this mode is defined by (if any).
580 D3DKMDT_VIDEO_SIGNAL_STANDARD VideoStandard;
581
582 // Video signal's size in pixels (i.e. HTotal & VTotal).
583 D3DKMDT_2DREGION TotalSize;
584
585 // Presented image's size in active pixels (i.e. HActive & VActive).
586 D3DKMDT_2DREGION ActiveSize;
587
588 // Vertical refresh frequency (in Hz).
589 D3DDDI_RATIONAL VSyncFreq;
590
591 // Horizontal refresh frequency (in Hz).
592 D3DDDI_RATIONAL HSyncFreq;
593
594 // Pixel clock rate (in Hz).
595 SIZE_T PixelRate;
596
597 union
598 {
599 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3_M1)
600 struct
601 {
602 // Scan line ordering (e.g. progressive, interlaced).
603 D3DDDI_VIDEO_SIGNAL_SCANLINE_ORDERING ScanLineOrdering : 3;
604
605 // Vertical refresh frequency divider
606 UINT VSyncFreqDivider : 6;
607
608 UINT Reserved : 23;
609
610 } AdditionalSignalInfo;
611 #endif // DXGKDDI_INTERFACE_VERSION_WDDM1_3_M1
612
613 // Scan line ordering (e.g. progressive, interlaced).
614 D3DDDI_VIDEO_SIGNAL_SCANLINE_ORDERING ScanLineOrdering;
615 };
616 }
617 D3DKMDT_VIDEO_SIGNAL_INFO;
618
619
620 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
621
622 #define D3DKMDT_BITS_PER_COMPONENT_06 0x01
623 #define D3DKMDT_BITS_PER_COMPONENT_08 0x02
624 #define D3DKMDT_BITS_PER_COMPONENT_10 0x04
625 #define D3DKMDT_BITS_PER_COMPONENT_12 0x08
626 #define D3DKMDT_BITS_PER_COMPONENT_14 0x10
627 #define D3DKMDT_BITS_PER_COMPONENT_16 0x20
628
629 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
630
631
632 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
633 // Purpose: Video present target mode ID type.
634 typedef UINT D3DKMDT_VIDEO_PRESENT_TARGET_MODE_ID;
635
636 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
637 // Purpose: Describe bit-fields for wire format and preference
638 // In the D3DKMDT_VIDPN_TARGET_MODE structure all fields are valid and the wire format fields indicate
639 // supported bit depts per color encoding format.
640 // In the DXGK_SET_TIMING_PATH_INFO structure the Preference field is unused so should be ignored by the
641 // driver and will be set to zero by the OS in case of future usage. The wire format fields are used to
642 // indicate which wire format has been selected so only one bit across the five fields will be set.
643 //
644
645 typedef union _D3DKMDT_WIRE_FORMAT_AND_PREFERENCE
646 {
647 struct
648 {
649 D3DKMDT_MODE_PREFERENCE Preference : 2;
650
651 // Flags indicating supported formats of color components transmitted between source and target
652 UINT Rgb : 6;
653 UINT YCbCr444 : 6;
654 UINT YCbCr422 : 6;
655 UINT YCbCr420 : 6;
656 UINT Intensity : 6;
657 };
658 UINT Value;
659 } D3DKMDT_WIRE_FORMAT_AND_PREFERENCE, *PD3DKMDT_WIRE_FORMAT_AND_PREFERENCE;
660
661
662 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
663 // Purpose: Video present target mode descriptor type.
664 typedef struct _D3DKMDT_VIDPN_TARGET_MODE
665 {
666 // Identifier unique within the set this mode is part of.
667 D3DKMDT_VIDEO_PRESENT_TARGET_MODE_ID Id;
668
669 // Video signal parameters.
670 D3DKMDT_VIDEO_SIGNAL_INFO VideoSignalInfo;
671
672 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
673 union
674 {
675 D3DKMDT_WIRE_FORMAT_AND_PREFERENCE WireFormatAndPreference;
676 struct
677 {
678 D3DKMDT_MODE_PREFERENCE Preference : 2;
679 UINT :30;
680 };
681 };
682 #else
683 // Predicate specifying whether this mode is preferred by the adapter given the mode pinned on
684 // the source of the respective present path.
685 D3DKMDT_MODE_PREFERENCE Preference;
686 #endif // (DXGKDDI_INTERFACE_VERSION < DXGKDDI_INTERFACE_VERSION_WDDM2_2)
687
688 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_9)
689
690 D3DDDI_RATIONAL MinimumVSyncFreq;
691
692 #endif // (DXGKDDI_INTERFACE_VERSION < DXGKDDI_INTERFACE_VERSION_WDDM2_9)
693
694 }
695 D3DKMDT_VIDPN_TARGET_MODE;
696
697 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
698 // Purpose: VESA Display ID detailed timing type I.
699
700 #pragma pack(push, 1)
701 #define DISPLAYID_DETAILED_TIMING_TYPE_I_SIZE 20
702
703 // Enum specifying monitor's aspect ratio (see DISPLAYID_DETAILED_TIMING_TYPE_I.AspectRatio)
704 enum _DISPLAYID_DETAILED_TIMING_TYPE_I_ASPECT_RATIO
705 {
706 DIDDT1_AspectRatio_1x1 = 0, // 000 = 1:1
707 DIDDT1_AspectRatio_5x4 = 1, // 001 = 5:4
708 DIDDT1_AspectRatio_4x3 = 2, // 010 = 4:3
709 DIDDT1_AspectRatio_15x9 = 3, // 011 = 15:9
710 DIDDT1_AspectRatio_16x9 = 4, // 100 = 16:9
711 DIDDT1_AspectRatio_16x10 = 5, // 101 = 16:10
712 };
713
714 enum _DISPLAYID_DETAILED_TIMING_TYPE_I_SCANNING_MODE
715 {
716 DIDDT1_Progressive = 0, // 0 = Progressive mode
717 DIDDT1_Interlaced = 1, // 1 = Interlaced mode
718 };
719
720 enum _DISPLAYID_DETAILED_TIMING_TYPE_I_STEREO_MODE
721 {
722 DIDDT1_Monoscopic = 0, // 00 = Monoscopic (no stereo) mode
723 DIDDT1_Stereo = 1, // 01 = Stereo mode
724 DIDDT1_Dependent = 2, // 10 = Stereo mode despends on user action
725 };
726
727 enum _DISPLAYID_DETAILED_TIMING_TYPE_I_SYNC_POLARITY
728 {
729 DIDDT1_Sync_Positive = 0,
730 DIDDT1_Sync_Negative = 1,
731 };
732
733 typedef struct _DISPLAYID_DETAILED_TIMING_TYPE_I
734 {
735 struct
736 {
737 ULONG PixelClock : 24; // Pixel clock / 10000
738 ULONG AspectRatio : 3; // Aspect ratio
739 ULONG Reserved : 1;
740 ULONG ScanningType : 1; // Frame scanning type
741 ULONG StereoMode : 2; // 3D stereo mode
742 ULONG PreferredTiming : 1; // preferred timing
743 };
744
745 USHORT HorizontalActivePixels; // Horizontal active image pixel number
746 USHORT HorizontalBlankPixels; // Horizontal blank pixel number
747 struct
748 {
749 USHORT HorizontalFrontPorch : 15; // Horizontal offset (front porch) pixel number
750 USHORT HorizontalSyncPolarity : 1; // Horizontal sync polarity
751 };
752 USHORT HorizontalSyncWidth; // Horizontal sync pixel number
753
754 USHORT VerticalActiveLines; // Number of lines of vertical active image
755 USHORT VerticalBlankLines; // Number of lines of vertical blank
756 struct
757 {
758 USHORT VerticalFrontPorch : 15; // Number of lines of vertical offset (front porch)
759 USHORT VerticalSyncPolarity : 1; // Vertical sync polarity
760 };
761 USHORT VerticalSyncWidth; // Number of lines of vertical sync
762 }DISPLAYID_DETAILED_TIMING_TYPE_I;
763
764 C_ASSERT(sizeof(DISPLAYID_DETAILED_TIMING_TYPE_I) == DISPLAYID_DETAILED_TIMING_TYPE_I_SIZE);
765
766 #pragma pack(pop)
767
768 typedef struct _DXGK_TARGETMODE_DETAIL_TIMING
769 {
770 // Video standard this detail timing comes from.
771 D3DKMDT_VIDEO_SIGNAL_STANDARD VideoStandard;
772
773 // ID of this detail timing in VideoStandard.
774 UINT TimingId;
775
776 // Detail timing.
777 DISPLAYID_DETAILED_TIMING_TYPE_I DetailTiming;
778 }DXGK_TARGETMODE_DETAIL_TIMING;
779
780
781 // Structure of hardware capability
782 typedef struct _D3DKMDT_VIDPN_HW_CAPABILITY
783 {
784 UINT DriverRotation : 1;
785 UINT DriverScaling : 1;
786 UINT DriverCloning : 1;
787 UINT DriverColorConvert : 1;
788 UINT DriverLinkedAdapaterOutput : 1;
789 UINT DriverRemoteDisplay : 1;
790 UINT Reserved : 26;
791 }
792 D3DKMDT_VIDPN_HW_CAPABILITY;
793
794
795 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
796 // Purpose: Video present target mode ID type.
797 typedef UINT D3DKMDT_MONITOR_SOURCE_MODE_ID;
798
799
800 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
801 // Purpose: Monitor capability origin type.
802 typedef enum _D3DKMDT_MONITOR_CAPABILITIES_ORIGIN
803 {
804 D3DKMDT_MCO_UNINITIALIZED = 0, // mode information is coming from the:
805 D3DKMDT_MCO_DEFAULTMONITORPROFILE = 1, // + default monitor profile.
806 D3DKMDT_MCO_MONITORDESCRIPTOR = 2, // + monitor's descriptor.
807 D3DKMDT_MCO_MONITORDESCRIPTOR_REGISTRYOVERRIDE = 3, // + registry override of the monitor descriptor.
808 D3DKMDT_MCO_SPECIFICCAP_REGISTRYOVERRIDE = 4, // + registry override of a specific capability.
809 D3DKMDT_MCO_DRIVER = 5, // + display adapter driver.
810 }
811 D3DKMDT_MONITOR_CAPABILITIES_ORIGIN;
812
813 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
814 // Purpose: Monitor timing type.
815 typedef enum _D3DKMDT_MONITOR_TIMING_TYPE
816 {
817 D3DKMDT_MTT_UNINITIALIZED = 0, // mode timing information is coming from:
818 D3DKMDT_MTT_ESTABLISHED = 1, // + established timings block.
819 D3DKMDT_MTT_STANDARD = 2, // + standard timings block.
820 D3DKMDT_MTT_EXTRASTANDARD = 3, // + extra standard timings block.
821 D3DKMDT_MTT_DETAILED = 4, // + detailed timings block.
822 D3DKMDT_MTT_DEFAULTMONITORPROFILE = 5, // + default monitor profile.
823 D3DKMDT_MTT_DRIVER = 6, // + display adapter driver.
824 }
825 D3DKMDT_MONITOR_TIMING_TYPE;
826
827 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
828 // Purpose: Video present target mode descriptor type.
829 typedef struct _D3DKMDT_MONITOR_SOURCE_MODE
830 {
831 // Identifier unique within the set this mode is part of.
832 D3DKMDT_MONITOR_SOURCE_MODE_ID Id;
833
834 // Video signal parameters.
835 D3DKMDT_VIDEO_SIGNAL_INFO VideoSignalInfo;
836
837 // Color basis with respect to which monitor is presenting the pixels sampled from the video signal.
838 D3DKMDT_COLOR_BASIS ColorBasis;
839
840 // Supported dynamic range of each of the pixel color component coefficients by the monitor's
841 // presentational technology - e.g. for a DFP LCD with 12-bit bit-depth, this will be (4, 4, 4, 0).
842 // A TV supporting 10-bit per component YCbCr this will be (10, 10, 10, 0) regardless of chroma compression.
843 D3DKMDT_COLOR_COEFF_DYNAMIC_RANGES ColorCoeffDynamicRanges;
844
845 // Origins of the monitor source mode information.
846 D3DKMDT_MONITOR_CAPABILITIES_ORIGIN Origin;
847
848 // Predicate specifying whether this mode is preferred by the monitor connected to the respective video output.
849 D3DKMDT_MODE_PREFERENCE Preference;
850 }
851 D3DKMDT_MONITOR_SOURCE_MODE;
852
853
854 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
855 // Purpose: Frequency range type.
856 typedef struct _D3DKMDT_FREQUENCY_RANGE
857 {
858 // Minimum vertical refresh frequency (in Hz) supported by the monitor.
859 D3DDDI_RATIONAL MinVSyncFreq;
860
861 // Maximum vertical refresh frequency (in Hz) supported by the monitor.
862 D3DDDI_RATIONAL MaxVSyncFreq;
863
864 // Minimum horizontal refresh frequency (in Hz) supported by the monitor.
865 D3DDDI_RATIONAL MinHSyncFreq;
866
867 // Maximum horizontal refresh frequency (in Hz) supported by the monitor.
868 D3DDDI_RATIONAL MaxHSyncFreq;
869 }
870 D3DKMDT_FREQUENCY_RANGE;
871
872
873 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
874 // Purpose: Monitor frequency range constraint type.
875 typedef enum _D3DKMDT_MONITOR_FREQUENCY_RANGE_CONSTRAINT
876 {
877 D3DKMDT_MFRC_UNINITIALIZED = 0,
878 D3DKMDT_MFRC_ACTIVESIZE = 1,
879 D3DKMDT_MFRC_MAXPIXELRATE = 2
880 }
881 D3DKMDT_MONITOR_FREQUENCY_RANGE_CONSTRAINT;
882
883
884 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
885 // Purpose: Monitor frequency range type.
886 typedef struct _D3DKMDT_MONITOR_FREQUENCY_RANGE
887 {
888 // Origins of the monitor frequency range information.
889 D3DKMDT_MONITOR_CAPABILITIES_ORIGIN Origin;
890
891 // Frequency range limits.
892 D3DKMDT_FREQUENCY_RANGE RangeLimits;
893
894 // Type of the frequency range constraint.
895 D3DKMDT_MONITOR_FREQUENCY_RANGE_CONSTRAINT ConstraintType;
896
897 // Constraint under which this frequency range is supported.
898 union
899 {
900 // Active region size this frequency range applies to.
901 D3DKMDT_2DREGION ActiveSize;
902
903 // Maximum pixel clock rate (in Hz) to which this pixel rate applies.
904 SIZE_T MaxPixelRate;
905
906 } Constraint;
907 }
908 D3DKMDT_MONITOR_FREQUENCY_RANGE;
909
910
911
912
913 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
914 // VidPN present paths
915
916 // VidPN present path index used during enumeration of paths satisfying certain criteria
917 // (e.g. originating from the same source).
918 typedef SIZE_T D3DKMDT_VIDPN_PRESENT_PATH_INDEX;
919
920 // Purpose: VidPN present path scaling type.
921 typedef enum _D3DKMDT_VIDPN_PRESENT_PATH_SCALING
922 {
923 D3DKMDT_VPPS_UNINITIALIZED = 0,
924
925 // For the following transformation, spatial resolutions must be equal on both the source and the target.
926
927 // Source content is not modified in any way.
928 D3DKMDT_VPPS_IDENTITY = 1,
929
930 // For the following three transformations, spatial resolution of the source differs from that of the target.
931
932 // Source content is centered on the target.
933 D3DKMDT_VPPS_CENTERED = 2,
934
935 // Source content is scaled to fit the target, no aspect ratio preserving.
936 D3DKMDT_VPPS_STRETCHED = 3,
937
938 // Source content is scaled to fit the target. Aspect ratio preserving.
939 D3DKMDT_VPPS_ASPECTRATIOCENTEREDMAX = 4,
940
941 // Scaling that cannot be described by any other D3DKMDT_VPPS_XXX value
942 D3DKMDT_VPPS_CUSTOM = 5,
943
944
945 // Reserved for internal OS use
946 D3DKMDT_VPPS_RESERVED1 = 253,
947
948 // Source content scaling mode is not pinned.
949 D3DKMDT_VPPS_UNPINNED = 254,
950
951 // OS does not specify the scaling mode, and miniport should decide based on its own settings.
952 D3DKMDT_VPPS_NOTSPECIFIED = 255
953 }
954 D3DKMDT_VIDPN_PRESENT_PATH_SCALING;
955
956
957 // Purpose: VidPN present path rotation type.
958 typedef enum _D3DKMDT_VIDPN_PRESENT_PATH_ROTATION
959 {
960 D3DKMDT_VPPR_UNINITIALIZED = 0,
961
962 // Source content is not modified in any way.
963 D3DKMDT_VPPR_IDENTITY = 1,
964
965 // Source content is rotated 90 degrees.
966 D3DKMDT_VPPR_ROTATE90 = 2,
967
968 // Source content is rotated 180 degrees.
969 D3DKMDT_VPPR_ROTATE180 = 3,
970
971 // Source content is rotated 270 degrees.
972 D3DKMDT_VPPR_ROTATE270 = 4,
973
974 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3_PATH_INDEPENDENT_ROTATION)
975 // Source content is not modified in any way. Driver should rotate this content an extra 90 degrees.
976 D3DKMDT_VPPR_IDENTITY_OFFSET90 = 5,
977
978 // Source content is rotated 90 degrees. Driver should rotate this content an extra 90 degrees.
979 D3DKMDT_VPPR_ROTATE90_OFFSET90 = 6,
980
981 // Source content is rotated 180 degrees. Driver should rotate this content an extra 90 degrees.
982 D3DKMDT_VPPR_ROTATE180_OFFSET90 = 7,
983
984 // Source content is rotated 270 degrees. Driver should rotate this content an extra 90 degrees.
985 D3DKMDT_VPPR_ROTATE270_OFFSET90 = 8,
986
987 // Source content is not modified in any way. Driver should rotate this content an extra 180 degrees.
988 D3DKMDT_VPPR_IDENTITY_OFFSET180 = 9,
989
990 // Source content is rotated 90 degrees. Driver should rotate this content an extra 180 degrees.
991 D3DKMDT_VPPR_ROTATE90_OFFSET180 = 10,
992
993 // Source content is rotated 180 degrees. Driver should rotate this content an extra 180 degrees.
994 D3DKMDT_VPPR_ROTATE180_OFFSET180 = 11,
995
996 // Source content is rotated 270 degrees. Driver should rotate this content an extra 180 degrees.
997 D3DKMDT_VPPR_ROTATE270_OFFSET180 = 12,
998
999 // Source content is not modified in any way. Driver should rotate this content an extra 270 degrees.
1000 D3DKMDT_VPPR_IDENTITY_OFFSET270 = 13,
1001
1002 // Source content is rotated 90 degrees. Driver should rotate this content an extra 270 degrees.
1003 D3DKMDT_VPPR_ROTATE90_OFFSET270 = 14,
1004
1005 // Source content is rotated 180 degrees. Driver should rotate this content an extra 270 degrees.
1006 D3DKMDT_VPPR_ROTATE180_OFFSET270 = 15,
1007
1008 // Source content is rotated 270 degrees. Driver should rotate this content an extra 270 degrees.
1009 D3DKMDT_VPPR_ROTATE270_OFFSET270 = 16,
1010 #endif // DXGKDDI_INTERFACE_VERSION
1011
1012 // Source content rotation setting is not pinned.
1013 D3DKMDT_VPPR_UNPINNED = 254,
1014
1015 // OS does not specify the rotation mode, and miniport should decide based on its own settings.
1016 D3DKMDT_VPPR_NOTSPECIFIED = 255
1017 }
1018 D3DKMDT_VIDPN_PRESENT_PATH_ROTATION;
1019
1020 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3_PATH_INDEPENDENT_ROTATION)
1021
1022 __inline
D3DKMDT_VPPR_GET_OFFSET_ROTATION(D3DKMDT_VIDPN_PRESENT_PATH_ROTATION Rotation)1023 D3DKMDT_VIDPN_PRESENT_PATH_ROTATION D3DKMDT_VPPR_GET_OFFSET_ROTATION(D3DKMDT_VIDPN_PRESENT_PATH_ROTATION Rotation)
1024 {
1025 if ((Rotation >= D3DKMDT_VPPR_IDENTITY) &&
1026 (Rotation <= D3DKMDT_VPPR_ROTATE270_OFFSET270))
1027 {
1028 Rotation = (D3DKMDT_VIDPN_PRESENT_PATH_ROTATION)(((Rotation - 1) / 4) + 1);
1029 }
1030 return Rotation;
1031 }
1032
1033 __inline
D3DKMDT_VPPR_GET_CONTENT_ROTATION_PART(D3DKMDT_VIDPN_PRESENT_PATH_ROTATION Rotation)1034 D3DKMDT_VIDPN_PRESENT_PATH_ROTATION D3DKMDT_VPPR_GET_CONTENT_ROTATION_PART(D3DKMDT_VIDPN_PRESENT_PATH_ROTATION Rotation)
1035 {
1036 if ((Rotation >= D3DKMDT_VPPR_IDENTITY_OFFSET90) &&
1037 (Rotation <= D3DKMDT_VPPR_ROTATE270_OFFSET270))
1038 {
1039 Rotation = (D3DKMDT_VIDPN_PRESENT_PATH_ROTATION)(((Rotation - 1) % 4) + 1);
1040 }
1041 return Rotation;
1042 }
1043
1044 __inline
D3DKMDT_VPPR_GET_CONTENT_ROTATION(D3DKMDT_VIDPN_PRESENT_PATH_ROTATION Rotation)1045 D3DKMDT_VIDPN_PRESENT_PATH_ROTATION D3DKMDT_VPPR_GET_CONTENT_ROTATION(D3DKMDT_VIDPN_PRESENT_PATH_ROTATION Rotation)
1046 {
1047 if ((Rotation >= D3DKMDT_VPPR_IDENTITY_OFFSET90) &&
1048 (Rotation <= D3DKMDT_VPPR_ROTATE270_OFFSET270))
1049 {
1050 D3DKMDT_VIDPN_PRESENT_PATH_ROTATION ContentPart = D3DKMDT_VPPR_GET_CONTENT_ROTATION_PART(Rotation);
1051 D3DKMDT_VIDPN_PRESENT_PATH_ROTATION OffsetPart = D3DKMDT_VPPR_GET_OFFSET_ROTATION(Rotation);
1052 Rotation = (D3DKMDT_VIDPN_PRESENT_PATH_ROTATION)((((ContentPart - 1) + (OffsetPart - 1)) % 4) + 1);
1053 }
1054 return Rotation;
1055 }
1056 #endif // DXGKDDI_INTERFACE_VERSION
1057
1058
1059 #define D3DKMDT_SCALING_SUPPORT_MASK 0x1f;
1060
1061 // Purpose: Specifies what scaling modes are supported given current path configuration.
1062 typedef struct _D3DKMDT_VIDPN_PRESENT_PATH_SCALING_SUPPORT
1063 {
1064 UINT Identity : 1;
1065 UINT Centered : 1;
1066 UINT Stretched : 1;
1067 UINT AspectRatioCenteredMax : 1;
1068 UINT Custom : 1;
1069 } D3DKMDT_VIDPN_PRESENT_PATH_SCALING_SUPPORT;
1070
1071 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3_PATH_INDEPENDENT_ROTATION)
1072 #define D3DKMDT_ROTATION_SUPPORT_MASK 0xff;
1073 #else
1074 #define D3DKMDT_ROTATION_SUPPORT_MASK 0xf;
1075 #endif // DXGKDDI_INTERFACE_VERSION
1076
1077 // Purpose: Specifies what rotation modes are supported given current path configuration.
1078 typedef struct _D3DKMDT_VIDPN_PRESENT_PATH_ROTATION_SUPPORT
1079 {
1080 UINT Identity : 1;
1081 UINT Rotate90 : 1;
1082 UINT Rotate180 : 1;
1083 UINT Rotate270 : 1;
1084 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3_PATH_INDEPENDENT_ROTATION)
1085 UINT Offset0 : 1;
1086 UINT Offset90 : 1;
1087 UINT Offset180 : 1;
1088 UINT Offset270 : 1;
1089 #endif // DXGKDDI_INTERFACE_VERSION
1090 } D3DKMDT_VIDPN_PRESENT_PATH_ROTATION_SUPPORT;
1091
1092 // Purpose: Combines all the transformation related fields into one structure.
1093 typedef struct _D3DKMDT_VIDPN_PRESENT_PATH_TRANSFORMATION
1094 {
1095 // Scaling applied to the content presented on this video present path.
1096 D3DKMDT_VIDPN_PRESENT_PATH_SCALING Scaling;
1097
1098 // Scaling support given the currently pinned modes.
1099 D3DKMDT_VIDPN_PRESENT_PATH_SCALING_SUPPORT ScalingSupport;
1100
1101 // Rotation applied to the content presented on this video present path.
1102 D3DKMDT_VIDPN_PRESENT_PATH_ROTATION Rotation;
1103
1104 // Rotation support given the currently pinned modes.
1105 D3DKMDT_VIDPN_PRESENT_PATH_ROTATION_SUPPORT RotationSupport;
1106 } D3DKMDT_VIDPN_PRESENT_PATH_TRANSFORMATION;
1107
1108 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
1109 // Purpose: VidPN present path importance ordinal type.
1110 //
1111 // Note: Higher order importance ordinals can be used (upto 255), but only the first 10 have been explicitly named.
1112 //
1113 typedef enum _D3DKMDT_VIDPN_PRESENT_PATH_IMPORTANCE
1114 {
1115 D3DKMDT_VPPI_UNINITIALIZED = 0,
1116 D3DKMDT_VPPI_PRIMARY = 1,
1117 D3DKMDT_VPPI_SECONDARY = 2,
1118 D3DKMDT_VPPI_TERTIARY = 3,
1119 D3DKMDT_VPPI_QUATERNARY = 4,
1120 D3DKMDT_VPPI_QUINARY = 5,
1121 D3DKMDT_VPPI_SENARY = 6,
1122 D3DKMDT_VPPI_SEPTENARY = 7,
1123 D3DKMDT_VPPI_OCTONARY = 8,
1124 D3DKMDT_VPPI_NONARY = 9,
1125 D3DKMDT_VPPI_DENARY = 10,
1126 }
1127 D3DKMDT_VIDPN_PRESENT_PATH_IMPORTANCE;
1128
1129 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
1130 // Purpose: VidPN present path content ordinal type.
1131 //
1132 // Indicates whether the content being displayed is video or graphics.
1133 //
1134 typedef enum _D3DKMDT_VIDPN_PRESENT_PATH_CONTENT
1135 {
1136 D3DKMDT_VPPC_UNINITIALIZED = 0,
1137
1138 // Miniport should optimize presentation of the present path for graphics content.
1139 D3DKMDT_VPPC_GRAPHICS = 1,
1140
1141 // Miniport should optimize presentation of the present path for video content.
1142 D3DKMDT_VPPC_VIDEO = 2,
1143
1144 // OS does not specify the content type, and miniport should decide based on its own settings.
1145 D3DKMDT_VPPC_NOTSPECIFIED = 255
1146 }
1147 D3DKMDT_VIDPN_PRESENT_PATH_CONTENT;
1148
1149 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
1150 // Purpose: VidPN present path macrovision information.
1151 //
1152 // Contains macrovision caps and controls.
1153 //
1154 typedef enum _D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION_TYPE
1155 {
1156 D3DKMDT_VPPMT_UNINITIALIZED = 0,
1157
1158 D3DKMDT_VPPMT_NOPROTECTION = 1,
1159
1160 D3DKMDT_VPPMT_MACROVISION_APSTRIGGER = 2,
1161
1162 D3DKMDT_VPPMT_MACROVISION_FULLSUPPORT = 3,
1163
1164 }
1165 D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION_TYPE;
1166
1167 typedef struct _D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION_SUPPORT
1168 {
1169 UINT NoProtection : 1;
1170 UINT MacroVisionApsTrigger : 1;
1171 UINT MacroVisionFull : 1;
1172 UINT Reserved : 29;
1173 }
1174 D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION_SUPPORT;
1175
1176 #define D3DKMDT_MACROVISION_OEMCOPYPROTECTION_SIZE 256
1177
1178 typedef struct _D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION
1179 {
1180 // Macrovision controls.
1181 D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION_TYPE CopyProtectionType;
1182 UINT APSTriggerBits;
1183 BYTE OEMCopyProtection[D3DKMDT_MACROVISION_OEMCOPYPROTECTION_SIZE];
1184
1185 // Level of available copy protection support.
1186 D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION_SUPPORT CopyProtectionSupport;
1187 } D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION;
1188
1189 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
1190 // Purpose: VidPN present path gamma ramp descriptor type.
1191 //
1192 typedef struct _D3DKMDT_GAMMA_RAMP
1193 {
1194 D3DDDI_GAMMARAMP_TYPE Type;
1195 SIZE_T DataSize;
1196
1197 // If (Type == D3DDDI_GAMMARAMP_DEFAULT), (DataSize == 0) and (Data.pRaw == NULL )
1198 union
1199 {
1200 D3DDDI_GAMMA_RAMP_RGB256x3x16* pRgb256x3x16; // Type == D3DDDI_GAMMARAMP_RGB256x3x16.
1201 D3DDDI_GAMMA_RAMP_DXGI_1* pDxgi1; // Type == D3DDDI_GAMMARAMP_DXGI_1.
1202 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_3)
1203 D3DKMDT_3x4_COLORSPACE_TRANSFORM* p3x4; // Type == D3DDDI_GAMMARAMP_MATRIX_3x4.
1204 #endif // DXGKDDI_INTERFACE_VERSION_WDDM2_3
1205 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_6)
1206 D3DKMDT_COLORSPACE_TRANSFORM_MATRIX_V2* pMatrixV2; // Type == D3DDDI_GAMMARAMP_MATRIX_V2.
1207 #endif // DXGKDDI_INTERFACE_VERSION_WDDM2_6
1208 VOID* pRaw;
1209 }
1210 Data;
1211 }
1212 D3DKMDT_GAMMA_RAMP;
1213
1214
1215 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
1216 // Purpose: Video present target to source mapping.
1217 //
1218 // Remarks: This type is used to describe a mapping from a single video present target to a single
1219 // video present source in a VidPN topology.
1220 //
1221 typedef struct _D3DKMDT_VIDPN_PRESENT_PATH
1222 {
1223 D3DDDI_VIDEO_PRESENT_SOURCE_ID VidPnSourceId;
1224
1225 D3DDDI_VIDEO_PRESENT_TARGET_ID VidPnTargetId;
1226
1227 // Video present path importance ordinal (e.g. path presenting the primary view may have higher
1228 // importance set on it in order to guarantee that it gets the best source/target mode sets).
1229 D3DKMDT_VIDPN_PRESENT_PATH_IMPORTANCE ImportanceOrdinal;
1230
1231 // Contains all the transformation related fields.
1232 D3DKMDT_VIDPN_PRESENT_PATH_TRANSFORMATION ContentTransformation;
1233
1234 // Storing deltas for visible/active pixels mapping rather than visible pixels'
1235 // size & offset has the added benefit of ideal/default state being zeros.
1236
1237 // Monitor screen's offset of visible pixels' top-left corner from
1238 // video signal's active pixels top-left corner.
1239 // Note: Default = (0,0).
1240 D3DKMDT_2DOFFSET VisibleFromActiveTLOffset;
1241
1242 // Monitor screen's offset of visible pixels' bottom-right corner from
1243 // video signal's active pixels bottom-right corner.
1244 // Note: Default = (0,0).
1245 D3DKMDT_2DOFFSET VisibleFromActiveBROffset;
1246
1247 // Video signal color basis with respect to which video output codec encodes the pixels from the respective
1248 // source's primary surface (e.g. on HDMI this can be either RGB or YCbCr).
1249 D3DKMDT_COLOR_BASIS VidPnTargetColorBasis;
1250
1251 // Supported dynamic range of each of the color bases' coefficients by the video output codec's output
1252 // E.g. With a DAC scaning out A2R10G10B10 primary surface at R8G8B8 color resolution, this would be (8,8,8,0),
1253 D3DKMDT_COLOR_COEFF_DYNAMIC_RANGES VidPnTargetColorCoeffDynamicRanges;
1254
1255 // Indicates the content being diplayed. The driver can use this to determine whether the flicker filter
1256 // and overscan should be enabled or disabled.
1257 D3DKMDT_VIDPN_PRESENT_PATH_CONTENT Content;
1258
1259 // Contains all the copy protection related fields.
1260 D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION CopyProtection;
1261
1262 // A lookup table (LUT) used to compensate intensity of presented content for the color response of the monitor
1263 // connected to present path's target.
1264 D3DKMDT_GAMMA_RAMP GammaRamp;
1265 }
1266 D3DKMDT_VIDPN_PRESENT_PATH;
1267
1268
1269 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
1270 // Purpose: Specifies whether to ignore monitor connectivity checks or enforce them.
1271 //
1272 typedef enum _D3DKMDT_MONITOR_CONNECTIVITY_CHECKS
1273 {
1274 D3DKMDT_MCC_UNINITIALIZED = 0,
1275 D3DKMDT_MCC_IGNORE = 1,
1276 D3DKMDT_MCC_ENFORCE = 2
1277 }
1278 D3DKMDT_MONITOR_CONNECTIVITY_CHECKS;
1279
1280
1281 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
1282 // Purpose: Type of the owner whose mode set does not change during an enumeration.
1283 //
1284 // Remarks: When OS pins/unpins a mode in one of VidPN's mode sets, the only mode set that is guaranteed to
1285 // stay the same is the mode set whose mode was pinned/unpinned. Enumeration pivot lets the OS
1286 // specify to the miniport which mode set it should not update (because this mode set could not have
1287 // been invalidated as a result of the change the OS made to the VidPN.
1288 //
1289 typedef enum _D3DKMDT_ENUMCOFUNCMODALITY_PIVOT_TYPE
1290 {
1291 D3DKMDT_EPT_UNINITIALIZED,
1292 D3DKMDT_EPT_VIDPNSOURCE,
1293 D3DKMDT_EPT_VIDPNTARGET,
1294 D3DKMDT_EPT_SCALING,
1295 D3DKMDT_EPT_ROTATION,
1296 D3DKMDT_EPT_NOPIVOT
1297 }
1298 D3DKMDT_ENUMCOFUNCMODALITY_PIVOT_TYPE;
1299
1300 //
1301 // Monitor descriptor related types.
1302 //
1303
1304 typedef UINT D3DKMDT_MONITOR_DESCRIPTOR_ID;
1305
1306 typedef enum _D3DKMDT_MONITOR_DESCRIPTOR_TYPE
1307 {
1308 D3DKMDT_MDT_UNINITIALIZED = 0,
1309 D3DKMDT_MDT_VESA_EDID_V1_BASEBLOCK = 1,
1310 D3DKMDT_MDT_VESA_EDID_V1_BLOCKMAP = 2,
1311 D3DKMDT_MDT_OTHER = 255
1312 }
1313 D3DKMDT_MONITOR_DESCRIPTOR_TYPE;
1314
1315 typedef struct _D3DKMDT_MONITOR_DESCRIPTOR
1316 {
1317 D3DKMDT_MONITOR_DESCRIPTOR_ID Id;
1318 D3DKMDT_MONITOR_DESCRIPTOR_TYPE Type;
1319 SIZE_T DataSize;
1320 VOID* pData;
1321 D3DKMDT_MONITOR_CAPABILITIES_ORIGIN Origin;
1322 }
1323 D3DKMDT_MONITOR_DESCRIPTOR;
1324
1325
1326 typedef enum _D3DKMDT_STANDARDALLOCATION_TYPE
1327 {
1328 D3DKMDT_STANDARDALLOCATION_SHAREDPRIMARYSURFACE = 1,
1329 D3DKMDT_STANDARDALLOCATION_SHADOWSURFACE = 2,
1330 D3DKMDT_STANDARDALLOCATION_STAGINGSURFACE = 3,
1331 D3DKMDT_STANDARDALLOCATION_GDISURFACE = 4,
1332 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1)
1333 D3DKMDT_STANDARDALLOCATION_VGPU = 5,
1334 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1)
1335 } D3DKMDT_STANDARDALLOCATION_TYPE;
1336
1337 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WIN8)
1338 typedef enum _D3DKMDT_GRAPHICS_PREEMPTION_GRANULARITY
1339 {
1340 D3DKMDT_GRAPHICS_PREEMPTION_NONE = 0,
1341 D3DKMDT_GRAPHICS_PREEMPTION_DMA_BUFFER_BOUNDARY = 100,
1342 D3DKMDT_GRAPHICS_PREEMPTION_PRIMITIVE_BOUNDARY = 200,
1343 D3DKMDT_GRAPHICS_PREEMPTION_TRIANGLE_BOUNDARY = 300,
1344 D3DKMDT_GRAPHICS_PREEMPTION_PIXEL_BOUNDARY = 400,
1345 D3DKMDT_GRAPHICS_PREEMPTION_SHADER_BOUNDARY = 500,
1346 } D3DKMDT_GRAPHICS_PREEMPTION_GRANULARITY;
1347
1348 typedef enum _D3DKMDT_COMPUTE_PREEMPTION_GRANULARITY
1349 {
1350 D3DKMDT_COMPUTE_PREEMPTION_NONE = 0,
1351 D3DKMDT_COMPUTE_PREEMPTION_DMA_BUFFER_BOUNDARY = 100,
1352 D3DKMDT_COMPUTE_PREEMPTION_DISPATCH_BOUNDARY = 200,
1353 D3DKMDT_COMPUTE_PREEMPTION_THREAD_GROUP_BOUNDARY = 300,
1354 D3DKMDT_COMPUTE_PREEMPTION_THREAD_BOUNDARY = 400,
1355 D3DKMDT_COMPUTE_PREEMPTION_SHADER_BOUNDARY = 500,
1356 } D3DKMDT_COMPUTE_PREEMPTION_GRANULARITY;
1357
1358 typedef struct _D3DKMDT_PREEMPTION_CAPS
1359 {
1360 D3DKMDT_GRAPHICS_PREEMPTION_GRANULARITY GraphicsPreemptionGranularity;
1361 D3DKMDT_COMPUTE_PREEMPTION_GRANULARITY ComputePreemptionGranularity;
1362 } D3DKMDT_PREEMPTION_CAPS;
1363
1364 typedef struct _D3DKMT_WDDM_1_2_CAPS
1365 {
1366 D3DKMDT_PREEMPTION_CAPS PreemptionCaps;
1367 union
1368 {
1369 struct
1370 {
1371 UINT SupportNonVGA : 1;
1372 UINT SupportSmoothRotation : 1;
1373 UINT SupportPerEngineTDR : 1;
1374 UINT SupportKernelModeCommandBuffer : 1;
1375 UINT SupportCCD : 1;
1376 UINT SupportSoftwareDeviceBitmaps : 1;
1377 UINT SupportGammaRamp : 1;
1378 UINT SupportHWCursor : 1;
1379 UINT SupportHWVSync : 1;
1380 UINT SupportSurpriseRemovalInHibernation : 1;
1381 UINT Reserved : 22;
1382 };
1383 UINT Value;
1384 };
1385 } D3DKMT_WDDM_1_2_CAPS;
1386
1387
1388 #endif // DXGKDDI_INTERFACE_VERSION
1389
1390 typedef struct _D3DKMDT_SHAREDPRIMARYSURFACEDATA
1391 {
1392 UINT Width;
1393 UINT Height;
1394 D3DDDIFORMAT Format;
1395 D3DDDI_RATIONAL RefreshRate;
1396 D3DDDI_VIDEO_PRESENT_SOURCE_ID VidPnSourceId;
1397 } D3DKMDT_SHAREDPRIMARYSURFACEDATA;
1398
1399 typedef struct _D3DKMDT_SHADOWSURFACEDATA
1400 {
1401 UINT Width;
1402 UINT Height;
1403 D3DDDIFORMAT Format;
1404 UINT Pitch; //out: Driver must return Pitch as this allocation will be lockabale
1405 } D3DKMDT_SHADOWSURFACEDATA;
1406
1407 //Staging Surface is a surface created potentially
1408 //during present when a direct Blt to primary is
1409 //not possible in cases like multimon or sprites.
1410 //This surface is always in the format of D3DDDIFMT_X8R8G8B8
1411
1412 typedef struct _D3DKMDT_STAGINGSURFACEDATA
1413 {
1414 UINT Width; //in: Width of the staging buffer
1415 UINT Height; //in: Height of the staging buffer
1416 UINT Pitch; //out: Driver must return Pitch as this allocation will be lockabale
1417 } D3DKMDT_STAGINGSURFACEDATA;
1418
1419 typedef struct _D3DKMDT_GDISURFACEFLAGS
1420 {
1421 union
1422 {
1423 struct
1424 {
1425 UINT Reserved : 32;
1426 };
1427 UINT Value;
1428 };
1429 } D3DKMDT_GDISURFACEFLAGS;
1430
1431 typedef enum _D3DKMDT_GDISURFACETYPE
1432 {
1433 D3DKMDT_GDISURFACE_INVALID = 0,
1434 D3DKMDT_GDISURFACE_TEXTURE = 1,
1435 D3DKMDT_GDISURFACE_STAGING_CPUVISIBLE = 2,
1436 D3DKMDT_GDISURFACE_STAGING = 3,
1437 D3DKMDT_GDISURFACE_LOOKUPTABLE = 4,
1438 D3DKMDT_GDISURFACE_EXISTINGSYSMEM = 5,
1439 D3DKMDT_GDISURFACE_TEXTURE_CPUVISIBLE = 6,
1440 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3_M1)
1441 D3DKMDT_GDISURFACE_TEXTURE_CROSSADAPTER = 7,
1442 D3DKMDT_GDISURFACE_TEXTURE_CPUVISIBLE_CROSSADAPTER = 8, // Reserved for OS
1443 #endif // DXGKDDI_INTERFACE_VERSION
1444 } D3DKMDT_GDISURFACETYPE;
1445
1446 typedef struct _D3DKMDT_GDISURFACEDATA
1447 {
1448 UINT Width;
1449 UINT Height;
1450 D3DDDIFORMAT Format;
1451 D3DKMDT_GDISURFACETYPE Type;
1452 D3DKMDT_GDISURFACEFLAGS Flags;
1453 UINT Pitch; // out: The driver must return pitch if allocation is CPU visible
1454 } D3DKMDT_GDISURFACEDATA;
1455
1456 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1)
1457
1458 typedef struct _D3DKMDT_VIRTUALGPUSURFACEDATA
1459 {
1460 UINT64 Size;
1461 UINT Alignment;
1462 UINT DriverSegmentId;
1463 UINT PrivateDriverData;
1464 } D3DKMDT_VIRTUALGPUSURFACEDATA;
1465
1466 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1)
1467
1468 typedef struct _D3DKMDT_PALETTEDATA
1469 {
1470 BYTE Red;
1471 BYTE Green;
1472 BYTE Blue;
1473 BYTE Unused;
1474 } D3DKMDT_PALETTEDATA;
1475
1476 //
1477 //Red - Bits to be put in the Red portion of the color registers.
1478 //
1479 //Green - Bits to be put in the Green portion of the color registers.
1480 //
1481 //Blue - Bits to be put in the Blue portion of the color registers.
1482 //
1483
1484 typedef struct _DXGKARG_SETPALETTE
1485 {
1486 D3DDDI_VIDEO_PRESENT_SOURCE_ID VidPnSourceId;
1487 UINT FirstEntry;
1488 UINT NumEntries;
1489 D3DKMDT_PALETTEDATA* pLookupTable;
1490 } DXGKARG_SETPALETTE;
1491
1492 //
1493 //NumEntries - Number of entries in the LookupTable of color values.
1494 //
1495 //FirstEntry - Location in the device palette to which the first entry in the
1496 // LookupTable of colors should be copied to. The other entries in the
1497 // LookupTable should be copied sequentially, from this starting point into
1498 // the device's palette.
1499 //
1500 //pLookupTable - Array of color entries to copy into the device's color
1501 // registers/palette. The color entries can be accessed as a genric 32 bit
1502 // value or as Red/Green/Blue/Unused fields.
1503 //
1504
1505 typedef struct _D3DKMT_MOVE_RECT
1506 {
1507 POINT SourcePoint;
1508 RECT DestRect;
1509 }D3DKMT_MOVE_RECT;
1510
1511 //
1512 // Display information structure.
1513 //
1514
1515 #ifndef PHYSICAL_ADDRESS
1516 typedef LARGE_INTEGER PHYSICAL_ADDRESS;
1517 #endif
1518
1519 typedef struct _DXGK_DISPLAY_INFORMATION
1520 {
1521 UINT Width;
1522 UINT Height;
1523 UINT Pitch;
1524 D3DDDIFORMAT ColorFormat;
1525 PHYSICAL_ADDRESS PhysicAddress;
1526 D3DDDI_VIDEO_PRESENT_TARGET_ID TargetId;
1527 ULONG AcpiId;
1528 } DXGK_DISPLAY_INFORMATION, *PDXGK_DISPLAY_INFORMATION;
1529
1530
1531 //////////////////// I2C ////////////////////////////////////////////////////////////////////////////////////
1532
1533 #define DXGKMDT_I2C_NO_FLAGS 0
1534 #define DXGKMDT_I2C_DEVICE_TRANSMITS_DATA_LENGTH 1
1535
1536 //////////////////// OPM (Output Protection Manager) ////////////////////////////////////////////////////////
1537
1538 #pragma pack( push, 1 )
1539
1540 #define DXGKMDT_OPM_OMAC_SIZE 16
1541 #define DXGKMDT_OPM_128_BIT_RANDOM_NUMBER_SIZE 16
1542 #define DXGKMDT_OPM_ENCRYPTED_PARAMETERS_SIZE 256
1543 #define DXGKMDT_OPM_CONFIGURE_SETTING_DATA_SIZE 4056
1544 #define DXGKMDT_OPM_GET_INFORMATION_PARAMETERS_SIZE 4056
1545 #define DXGKMDT_OPM_REQUESTED_INFORMATION_SIZE 4076
1546 #define DXGKMDT_OPM_HDCP_KEY_SELECTION_VECTOR_SIZE 5
1547 #define DXGKMDT_OPM_PROTECTION_TYPE_SIZE 4
1548
1549 DEFINE_GUID(DXGKMDT_OPM_GET_CURRENT_HDCP_SRM_VERSION, 0x99c5ceff, 0x5f1d, 0x4879, 0x81, 0xc1, 0xc5, 0x24, 0x43, 0xc9, 0x48, 0x2b);
1550 DEFINE_GUID(DXGKMDT_OPM_GET_CONNECTED_HDCP_DEVICE_INFORMATION, 0x0db59d74, 0xa992, 0x492e, 0xa0, 0xbd, 0xc2, 0x3f, 0xda, 0x56, 0x4e, 0x00);
1551 DEFINE_GUID(DXGKMDT_OPM_GET_CONNECTOR_TYPE, 0x81d0bfd5, 0x6afe, 0x48c2, 0x99, 0xc0, 0x95, 0xa0, 0x8f, 0x97, 0xc5, 0xda);
1552 DEFINE_GUID(DXGKMDT_OPM_GET_SUPPORTED_PROTECTION_TYPES, 0x38f2a801, 0x9a6c, 0x48bb, 0x91, 0x07, 0xb6, 0x69, 0x6e, 0x6f, 0x17, 0x97);
1553 DEFINE_GUID(DXGKMDT_OPM_GET_VIRTUAL_PROTECTION_LEVEL, 0xb2075857, 0x3eda, 0x4d5d, 0x88, 0xdb, 0x74, 0x8f, 0x8c, 0x1a, 0x05, 0x49);
1554 DEFINE_GUID(DXGKMDT_OPM_GET_ACTUAL_PROTECTION_LEVEL, 0x1957210a, 0x7766, 0x452a, 0xb9, 0x9a, 0xd2, 0x7a, 0xed, 0x54, 0xf0, 0x3a);
1555 DEFINE_GUID(DXGKMDT_OPM_GET_ACTUAL_OUTPUT_FORMAT, 0xd7bf1ba3, 0xad13, 0x4f8e, 0xaf, 0x98, 0x0d, 0xcb, 0x3c, 0xa2, 0x04, 0xcc);
1556 DEFINE_GUID(DXGKMDT_OPM_GET_ADAPTER_BUS_TYPE, 0xc6f4d673, 0x6174, 0x4184, 0x8e, 0x35, 0xf6, 0xdb, 0x52, 0x0, 0xbc, 0xba);
1557 DEFINE_GUID(DXGKMDT_OPM_GET_ACP_AND_CGMSA_SIGNALING, 0x6629a591, 0x3b79, 0x4cf3, 0x92, 0x4a, 0x11, 0xe8, 0xe7, 0x81, 0x16, 0x71);
1558 DEFINE_GUID(DXGKMDT_OPM_GET_OUTPUT_ID, 0x72cb6df3, 0x244f, 0x40ce, 0xb0, 0x9e, 0x20, 0x50, 0x6a, 0xf6, 0x30, 0x2f);
1559 DEFINE_GUID(DXGKMDT_OPM_GET_DVI_CHARACTERISTICS, 0xa470b3bb, 0x5dd7, 0x4172, 0x83, 0x9c, 0x3d, 0x37, 0x76, 0xe0, 0xeb, 0xf5);
1560 DEFINE_GUID(DXGKMDT_OPM_GET_OUTPUT_HARDWARE_PROTECTION_SUPPORT, 0x3b129589, 0x2af8, 0x4ef0, 0x96, 0xa2, 0x70, 0x4a, 0x84, 0x5a, 0x21, 0x8e);
1561 DEFINE_GUID(DXGKMDT_OPM_GET_CODEC_INFO, 0x4f374491, 0x8f5f, 0x4445, 0x9d, 0xba, 0x95, 0x58, 0x8f, 0x6b, 0x58, 0xb4);
1562 DEFINE_GUID(DXGKMDT_OPM_SET_PROTECTION_LEVEL, 0x9bb9327c, 0x4eb5, 0x4727, 0x9f, 0x00, 0xb4, 0x2b, 0x09, 0x19, 0xc0, 0xda);
1563 DEFINE_GUID(DXGKMDT_OPM_SET_ACP_AND_CGMSA_SIGNALING, 0x09a631a5, 0xd684, 0x4c60, 0x8e, 0x4d, 0xd3, 0xbb, 0x0f, 0x0b, 0xe3, 0xee);
1564 DEFINE_GUID(DXGKMDT_OPM_SET_HDCP_SRM, 0x8b5ef5d1, 0xc30d, 0x44ff, 0x84, 0xa5, 0xea, 0x71, 0xdc, 0xe7, 0x8f, 0x13);
1565 DEFINE_GUID(DXGKMDT_OPM_SET_PROTECTION_LEVEL_ACCORDING_TO_CSS_DVD, 0x39ce333e, 0x4cc0, 0x44ae, 0xbf, 0xcc, 0xda, 0x50, 0xb5, 0xf8, 0x2e, 0x72);
1566
1567 typedef enum _DXGKMDT_CERTIFICATE_TYPE
1568 {
1569 DXGKMDT_OPM_CERTIFICATE = 0,
1570 DXGKMDT_COPP_CERTIFICATE = 1,
1571 DXGKMDT_UAB_CERTIFICATE = 2,
1572 DXGKMDT_INDIRECT_DISPLAY_CERTIFICATE = 3,
1573 DXGKMDT_FORCE_ULONG = 0xFFFFFFFF
1574 } DXGKMDT_CERTIFICATE_TYPE;
1575
1576 typedef enum _DXGKMDT_OPM_VIDEO_OUTPUT_SEMANTICS
1577 {
1578 DXGKMDT_OPM_VOS_COPP_SEMANTICS = 0,
1579 DXGKMDT_OPM_VOS_OPM_SEMANTICS = 1,
1580 DXGKMDT_OPM_VOS_OPM_INDIRECT_DISPLAY = 2
1581 } DXGKMDT_OPM_VIDEO_OUTPUT_SEMANTICS;
1582
1583 typedef enum _DXGKMDT_DPCP_PROTECTION_LEVEL
1584 {
1585 DXGKMDT_OPM_DPCP_OFF = 0,
1586 DXGKMDT_OPM_DPCP_ON = 1,
1587 DXGKMDT_OPM_DPCP_FORCE_ULONG = 0x7fffffff
1588
1589 } DXGKMDT_OPM_DPCP_PROTECTION_LEVEL;
1590
1591 typedef enum _DXGKMDT_OPM_HDCP_FLAG
1592 {
1593 DXGKMDT_OPM_HDCP_FLAG_NONE = 0x00,
1594 DXGKMDT_OPM_HDCP_FLAG_REPEATER = 0x01
1595 } DXGKMDT_OPM_HDCP_FLAG;
1596
1597 typedef enum _DXGKMDT_OPM_STATUS
1598 {
1599 DXGKMDT_OPM_STATUS_NORMAL = 0x00,
1600 DXGKMDT_OPM_STATUS_LINK_LOST = 0x01,
1601 DXGKMDT_OPM_STATUS_RENEGOTIATION_REQUIRED = 0x02,
1602 DXGKMDT_OPM_STATUS_TAMPERING_DETECTED = 0x04,
1603 DXGKMDT_OPM_STATUS_REVOKED_HDCP_DEVICE_ATTACHED = 0x08
1604 } DXGKMDT_OPM_STATUS;
1605
1606 // NUAE stands for Non-User Accessible Enclosure
1607 typedef enum _DXGKMDT_OPM_BUS_TYPE_AND_IMPLEMENTATION
1608 {
1609 DXGKMDT_OPM_BUS_TYPE_OTHER = 0x00000000,
1610 DXGKMDT_OPM_BUS_TYPE_PCI = 0x00000001,
1611 DXGKMDT_OPM_BUS_TYPE_PCIX = 0x00000002,
1612 DXGKMDT_OPM_BUS_TYPE_PCIEXPRESS = 0x00000003,
1613 DXGKMDT_OPM_BUS_TYPE_AGP = 0x00000004,
1614 DXGKMDT_OPM_BUS_IMPLEMENTATION_MODIFIER_INSIDE_OF_CHIPSET = 0x00010000,
1615 DXGKMDT_OPM_BUS_IMPLEMENTATION_MODIFIER_TRACKS_ON_MOTHER_BOARD_TO_CHIP = 0x00020000,
1616 DXGKMDT_OPM_BUS_IMPLEMENTATION_MODIFIER_TRACKS_ON_MOTHER_BOARD_TO_SOCKET = 0x00030000,
1617 DXGKMDT_OPM_BUS_IMPLEMENTATION_MODIFIER_DAUGHTER_BOARD_CONNECTOR = 0x00040000,
1618 DXGKMDT_OPM_BUS_IMPLEMENTATION_MODIFIER_DAUGHTER_BOARD_CONNECTOR_INSIDE_OF_NUAE = 0x00050000,
1619 DXGKMDT_OPM_BUS_IMPLEMENTATION_MODIFIER_NON_STANDARD = 0x80000000,
1620 DXGKMDT_OPM_COPP_COMPATIBLE_BUS_TYPE_INTEGRATED = 0x80000000
1621 } DXGKMDT_OPM_BUS_TYPE_AND_IMPLEMENTATION;
1622
1623 typedef enum _DXGKMDT_OPM_HDCP_PROTECTION_LEVEL
1624 {
1625 DXGKMDT_OPM_HDCP_OFF = 0,
1626 DXGKMDT_OPM_HDCP_ON = 1,
1627 DXGKMDT_OPM_HDCP_FORCE_ULONG = 0x7fffffff
1628 } DXGKMDT_OPM_HDCP_PROTECTION_LEVEL;
1629
1630 typedef enum _DXGKMDT_OPM_TYPE_ENFORCEMENT_HDCP_PROTECTION_LEVEL
1631 {
1632 DXGKMDT_OPM_TYPE_ENFORCEMENT_HDCP_OFF = DXGKMDT_OPM_HDCP_OFF,
1633 DXGKMDT_OPM_TYPE_ENFORCEMENT_HDCP_ON_WITH_NO_TYPE_RESTRICTION = DXGKMDT_OPM_HDCP_ON, // No Type restriction on output topology nodes
1634 DXGKMDT_OPM_TYPE_ENFORCEMENT_HDCP_ON_WITH_TYPE1_RESTRICTION = DXGKMDT_OPM_HDCP_ON + 1, // Restrict to Type 1 compliant output topology nodes
1635 DXGKMDT_OPM_TYPE_ENFORCEMENT_HDCP_FORCE_ULONG = 0x7fffffff
1636 } DXGKMDT_OPM_TYPE_ENFORCEMENT_HDCP_PROTECTION_LEVEL;
1637
1638 typedef enum _DXGKMDT_OPM_CGMSA
1639 {
1640 DXGKMDT_OPM_CGMSA_OFF = 0,
1641 DXGKMDT_OPM_CGMSA_COPY_FREELY = 1,
1642 DXGKMDT_OPM_CGMSA_COPY_NO_MORE = 2,
1643 DXGKMDT_OPM_CGMSA_COPY_ONE_GENERATION = 3,
1644 DXGKMDT_OPM_CGMSA_COPY_NEVER = 4,
1645 DXGKMDT_OPM_REDISTRIBUTION_CONTROL_REQUIRED = 0x08,
1646 } DXGKMDT_OPM_CGMSA;
1647
1648 typedef enum _DXGKMDT_OPM_ACP_PROTECTION_LEVEL
1649 {
1650 DXGKMDT_OPM_ACP_OFF = 0,
1651 DXGKMDT_OPM_ACP_LEVEL_ONE = 1,
1652 DXGKMDT_OPM_ACP_LEVEL_TWO = 2,
1653 DXGKMDT_OPM_ACP_LEVEL_THREE = 3,
1654 DXGKMDT_OPM_ACP_FORCE_ULONG = 0x7fffffff
1655 } DXGKMDT_OPM_ACP_PROTECTION_LEVEL;
1656
1657 typedef enum _DXGKMDT_OPM_PROTECTION_TYPE
1658 {
1659 DXGKMDT_OPM_PROTECTION_TYPE_OTHER = 0x80000000,
1660 DXGKMDT_OPM_PROTECTION_TYPE_NONE = 0x00000000,
1661 DXGKMDT_OPM_PROTECTION_TYPE_COPP_COMPATIBLE_HDCP = 0x00000001,
1662 DXGKMDT_OPM_PROTECTION_TYPE_ACP = 0x00000002,
1663 DXGKMDT_OPM_PROTECTION_TYPE_CGMSA = 0x00000004,
1664 DXGKMDT_OPM_PROTECTION_TYPE_HDCP = 0x00000008,
1665 DXGKMDT_OPM_PROTECTION_TYPE_DPCP = 0x00000010,
1666 DXGKMDT_OPM_PROTECTION_TYPE_TYPE_ENFORCEMENT_HDCP = 0x00000020,
1667 DXGKMDT_OPM_PROTECTION_TYPE_MASK = 0x8000003F
1668 } DXGKMDT_OPM_PROTECTION_TYPE;
1669
1670 typedef enum _DXGKMDT_OPM_PROTECTION_STANDARD
1671 {
1672 DXGKMDT_OPM_PROTECTION_STANDARD_OTHER = 0x80000000,
1673 DXGKMDT_OPM_PROTECTION_STANDARD_NONE = 0x00000000,
1674 DXGKMDT_OPM_PROTECTION_STANDARD_IEC61880_525I = 0x00000001,
1675 DXGKMDT_OPM_PROTECTION_STANDARD_IEC61880_2_525I = 0x00000002,
1676 DXGKMDT_OPM_PROTECTION_STANDARD_IEC62375_625P = 0x00000004,
1677 DXGKMDT_OPM_PROTECTION_STANDARD_EIA608B_525 = 0x00000008,
1678 DXGKMDT_OPM_PROTECTION_STANDARD_EN300294_625I = 0x00000010,
1679 DXGKMDT_OPM_PROTECTION_STANDARD_CEA805A_TYPEA_525P = 0x00000020,
1680 DXGKMDT_OPM_PROTECTION_STANDARD_CEA805A_TYPEA_750P = 0x00000040,
1681 DXGKMDT_OPM_PROTECTION_STANDARD_CEA805A_TYPEA_1125I = 0x00000080,
1682 DXGKMDT_OPM_PROTECTION_STANDARD_CEA805A_TYPEB_525P = 0x00000100,
1683 DXGKMDT_OPM_PROTECTION_STANDARD_CEA805A_TYPEB_750P = 0x00000200,
1684 DXGKMDT_OPM_PROTECTION_STANDARD_CEA805A_TYPEB_1125I = 0x00000400,
1685 DXGKMDT_OPM_PROTECTION_STANDARD_ARIBTRB15_525I = 0x00000800,
1686 DXGKMDT_OPM_PROTECTION_STANDARD_ARIBTRB15_525P = 0x00001000,
1687 DXGKMDT_OPM_PROTECTION_STANDARD_ARIBTRB15_750P = 0x00002000,
1688 DXGKMDT_OPM_PROTECTION_STANDARD_ARIBTRB15_1125I = 0x00004000,
1689 } DXGKMDT_OPM_PROTECTION_STANDARD;
1690
1691 typedef enum _DXGKMDT_OPM_IMAGE_ASPECT_RATIO_EN300294
1692 {
1693 DXGKMDT_OPM_ASPECT_RATIO_EN300294_FULL_FORMAT_4_BY_3 = 0,
1694 DXGKMDT_OPM_ASPECT_RATIO_EN300294_BOX_14_BY_9_CENTER = 1,
1695 DXGKMDT_OPM_ASPECT_RATIO_EN300294_BOX_14_BY_9_TOP = 2,
1696 DXGKMDT_OPM_ASPECT_RATIO_EN300294_BOX_16_BY_9_CENTER = 3,
1697 DXGKMDT_OPM_ASPECT_RATIO_EN300294_BOX_16_BY_9_TOP = 4,
1698 DXGKMDT_OPM_ASPECT_RATIO_EN300294_BOX_GT_16_BY_9_CENTER = 5,
1699 DXGKMDT_OPM_ASPECT_RATIO_EN300294_FULL_FORMAT_4_BY_3_PROTECTED_CENTER = 6,
1700 DXGKMDT_OPM_ASPECT_RATIO_EN300294_FULL_FORMAT_16_BY_9_ANAMORPHIC = 7,
1701 DXGKMDT_OPM_ASPECT_RATIO_FORCE_ULONG = 0x7FFFFFFF
1702 } DXGKMDT_OPM_IMAGE_ASPECT_RATIO_EN300294;
1703
1704 typedef enum _DXGKMDT_OPM_INTERLEAVE_FORMAT
1705 {
1706 DXGKMDT_OPM_INTERLEAVE_FORMAT_OTHER = 0,
1707 DXGKMDT_OPM_INTERLEAVE_FORMAT_PROGRESSIVE = 2,
1708 DXGKMDT_OPM_INTERLEAVE_FORMAT_INTERLEAVED_EVEN_FIRST = 3,
1709 DXGKMDT_OPM_INTERLEAVE_FORMAT_INTERLEAVED_ODD_FIRST = 4,
1710 DXGKMDT_OPM_INTERLEAVE_FORMAT_FORCE_ULONG = 0xFFFFFFFF
1711
1712 } DXGKMDT_OPM_INTERLEAVE_FORMAT;
1713
1714 typedef enum _DXGKDT_OPM_DVI_CHARACTERISTICS
1715 {
1716 DXGKMDT_OPM_DVI_CHARACTERISTIC_1_0 = 1,
1717 DXGKMDT_OPM_DVI_CHARACTERISTIC_1_1_OR_ABOVE = 2,
1718 DXGKMDT_OPM_DVI_CHARACTERISTICS_FORCE_ULONG = 0xFFFFFFFF
1719 } DXGKDT_OPM_DVI_CHARACTERISTICS;
1720
1721 typedef enum _DXGKMDT_OPM_OUTPUT_HARDWARE_PROTECTION
1722 {
1723 DXGKMDT_OPM_OUTPUT_HARDWARE_PROTECTION_NOT_SUPPORTED = 0x0,
1724 DXGKMDT_OPM_OUTPUT_HARDWARE_PROTECTION_SUPPORTED = 0x1
1725 } DXGKMDT_OPM_OUTPUT_HARDWARE_PROTECTION;
1726
1727 typedef struct _DXGKMDT_OPM_RANDOM_NUMBER
1728 {
1729 BYTE abRandomNumber[DXGKMDT_OPM_128_BIT_RANDOM_NUMBER_SIZE];
1730 } DXGKMDT_OPM_RANDOM_NUMBER, *PDXGKMDT_OPM_RANDOM_NUMBER;
1731
1732 typedef struct _DXGKMDT_OPM_OMAC
1733 {
1734 BYTE abOMAC[DXGKMDT_OPM_OMAC_SIZE];
1735 } DXGKMDT_OPM_OMAC, *PDXGKMDT_OPM_OMAC;
1736
1737 typedef struct _DXGKMDT_OPM_ENCRYPTED_PARAMETERS
1738 {
1739 BYTE abEncryptedParameters[DXGKMDT_OPM_ENCRYPTED_PARAMETERS_SIZE];
1740 } DXGKMDT_OPM_ENCRYPTED_PARAMETERS, *PDXGKMDT_OPM_ENCRYPTED_PARAMETERS;
1741
1742 typedef struct _DXGKMDT_OPM_GET_INFO_PARAMETERS
1743 {
1744 DXGKMDT_OPM_OMAC omac;
1745 DXGKMDT_OPM_RANDOM_NUMBER rnRandomNumber;
1746 GUID guidInformation;
1747 ULONG ulSequenceNumber;
1748 ULONG cbParametersSize;
1749 BYTE abParameters[DXGKMDT_OPM_GET_INFORMATION_PARAMETERS_SIZE];
1750 } DXGKMDT_OPM_GET_INFO_PARAMETERS, *PDXGKMDT_OPM_GET_INFO_PARAMETERS;
1751
1752 typedef struct _DXGKMDT_OPM_COPP_COMPATIBLE_GET_INFO_PARAMETERS
1753 {
1754 DXGKMDT_OPM_RANDOM_NUMBER rnRandomNumber;
1755 GUID guidInformation;
1756 ULONG ulSequenceNumber;
1757 ULONG cbParametersSize;
1758 BYTE abParameters[DXGKMDT_OPM_GET_INFORMATION_PARAMETERS_SIZE];
1759 } DXGKMDT_OPM_COPP_COMPATIBLE_GET_INFO_PARAMETERS, *PDXGKMDT_OPM_COPP_COMPATIBLE_GET_INFO_PARAMETERS;
1760
1761 typedef struct _DXGKMDT_OPM_HDCP_KEY_SELECTION_VECTOR
1762 {
1763 BYTE abKeySelectionVector[DXGKMDT_OPM_HDCP_KEY_SELECTION_VECTOR_SIZE];
1764 } DXGKMDT_OPM_HDCP_KEY_SELECTION_VECTOR;
1765
1766 typedef struct _DXGKMDT_OPM_CONNECTED_HDCP_DEVICE_INFORMATION
1767 {
1768 DXGKMDT_OPM_RANDOM_NUMBER rnRandomNumber;
1769 ULONG ulStatusFlags;
1770 ULONG ulHDCPFlags;
1771 DXGKMDT_OPM_HDCP_KEY_SELECTION_VECTOR ksvB;
1772 BYTE Reserved[11];
1773 BYTE Reserved2[16];
1774 BYTE Reserved3[16];
1775 } DXGKMDT_OPM_CONNECTED_HDCP_DEVICE_INFORMATION;
1776
1777 typedef struct _DXGKMDT_OPM_REQUESTED_INFORMATION
1778 {
1779 DXGKMDT_OPM_OMAC omac;
1780 ULONG cbRequestedInformationSize;
1781 BYTE abRequestedInformation[DXGKMDT_OPM_REQUESTED_INFORMATION_SIZE];
1782 } DXGKMDT_OPM_REQUESTED_INFORMATION, *PDXGKMDT_OPM_REQUESTED_INFORMATION;
1783
1784 typedef struct _DXGKMDT_OPM_STANDARD_INFORMATION
1785 {
1786 DXGKMDT_OPM_RANDOM_NUMBER rnRandomNumber;
1787 ULONG ulStatusFlags;
1788 ULONG ulInformation;
1789 ULONG ulReserved;
1790 ULONG ulReserved2;
1791 } DXGKMDT_OPM_STANDARD_INFORMATION;
1792
1793 typedef struct _DXGKMDT_OPM_ACTUAL_OUTPUT_FORMAT
1794 {
1795 DXGKMDT_OPM_RANDOM_NUMBER rnRandomNumber;
1796 ULONG ulStatusFlags;
1797 ULONG ulDisplayWidth;
1798 ULONG ulDisplayHeight;
1799 DXGKMDT_OPM_INTERLEAVE_FORMAT ifInterleaveFormat;
1800 ULONG d3dFormat;
1801 ULONG ulFrequencyNumerator;
1802 ULONG ulFrequencyDenominator;
1803 } DXGKMDT_OPM_ACTUAL_OUTPUT_FORMAT;
1804
1805 typedef struct _DXGKMDT_OPM_ACP_AND_CGMSA_SIGNALING
1806 {
1807 DXGKMDT_OPM_RANDOM_NUMBER rnRandomNumber;
1808 ULONG ulStatusFlags;
1809 ULONG ulAvailableTVProtectionStandards;
1810 ULONG ulActiveTVProtectionStandard;
1811 ULONG ulReserved;
1812 ULONG ulAspectRatioValidMask1;
1813 ULONG ulAspectRatioData1;
1814 ULONG ulAspectRatioValidMask2;
1815 ULONG ulAspectRatioData2;
1816 ULONG ulAspectRatioValidMask3;
1817 ULONG ulAspectRatioData3;
1818 ULONG ulReserved2[4];
1819 ULONG ulReserved3[4];
1820 } DXGKMDT_OPM_ACP_AND_CGMSA_SIGNALING;
1821
1822 typedef struct _DXGKMDT_OPM_OUTPUT_ID
1823 {
1824 DXGKMDT_OPM_RANDOM_NUMBER rnRandomNumber;
1825 ULONG ulStatusFlags;
1826 UINT64 OutputId;
1827 } DXGKMDT_OPM_OUTPUT_ID;
1828
1829 typedef struct _DXGKMDT_OPM_CONFIGURE_PARAMETERS
1830 {
1831 DXGKMDT_OPM_OMAC omac;
1832 GUID guidSetting;
1833 ULONG ulSequenceNumber;
1834 ULONG cbParametersSize;
1835 BYTE abParameters[DXGKMDT_OPM_CONFIGURE_SETTING_DATA_SIZE];
1836 } DXGKMDT_OPM_CONFIGURE_PARAMETERS, *PDXGKMDT_OPM_CONFIGURE_PARAMETERS;
1837
1838 typedef struct _DXGKMDT_OPM_SET_PROTECTION_LEVEL_PARAMETERS
1839 {
1840 ULONG ulProtectionType;
1841 ULONG ulProtectionLevel;
1842 ULONG Reserved;
1843 ULONG Reserved2;
1844 } DXGKMDT_OPM_SET_PROTECTION_LEVEL_PARAMETERS;
1845
1846 typedef struct _DXGKMDT_OPM_SET_ACP_AND_CGMSA_SIGNALING_PARAMETERS
1847 {
1848 ULONG ulNewTVProtectionStandard;
1849 ULONG ulAspectRatioChangeMask1;
1850 ULONG ulAspectRatioData1;
1851 ULONG ulAspectRatioChangeMask2;
1852 ULONG ulAspectRatioData2;
1853 ULONG ulAspectRatioChangeMask3;
1854 ULONG ulAspectRatioData3;
1855 ULONG ulReserved[4];
1856 ULONG ulReserved2[4];
1857 ULONG ulReserved3;
1858 } DXGKMDT_OPM_SET_ACP_AND_CGMSA_SIGNALING_PARAMETERS;
1859
1860 typedef struct _DXGKMDT_OPM_SET_HDCP_SRM_PARAMETERS
1861 {
1862 ULONG ulSRMVersion;
1863 } DXGKMDT_OPM_SET_HDCP_SRM_PARAMETERS;
1864
1865 typedef struct _DXGKMDT_OPM_CREATE_VIDEO_OUTPUT_FOR_TARGET_PARAMETERS
1866 {
1867 LUID AdapterLuid;
1868 D3DDDI_VIDEO_PRESENT_TARGET_ID TargetId;
1869 DXGKMDT_OPM_VIDEO_OUTPUT_SEMANTICS Vos;
1870 } DXGKMDT_OPM_CREATE_VIDEO_OUTPUT_FOR_TARGET_PARAMETERS;
1871
1872 typedef struct _DXGK_BRIGHTNESS_CAPS
1873 {
1874 union
1875 {
1876 struct
1877 {
1878 UINT SmoothBrightness : 1; // 0x00000001
1879 UINT AdaptiveBrightness : 1; // 0x00000002
1880 UINT NitsBrightness : 1; // 0x00000004
1881 UINT Reserved : 29; // 0xFFFFFFF8
1882 };
1883
1884 UINT Value;
1885 };
1886 } DXGK_BRIGHTNESS_CAPS;
1887
1888 typedef struct _DXGK_BRIGHTNESS_STATE
1889 {
1890 union
1891 {
1892 struct
1893 {
1894 UINT SmoothBrightness : 1; // 0x00000001
1895 UINT Reserved : 31; // 0xFFFFFFFE
1896 };
1897
1898 UINT Value;
1899 };
1900 } DXGK_BRIGHTNESS_STATE;
1901
1902 typedef enum
1903 {
1904 DxgkBacklightOptimizationDisable = 0,
1905 DxgkBacklightOptimizationDesktop = 1,
1906 DxgkBacklightOptimizationDynamic = 2,
1907 DxgkBacklightOptimizationDimmed = 3,
1908 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
1909 DxgkBacklightOptimizationEDR = 4,
1910 #endif // DXGKDDI_INTERFACE_VERSION_WDDM2_2
1911 } DXGK_BACKLIGHT_OPTIMIZATION_LEVEL;
1912
1913 typedef struct _DXGK_BACKLIGHT_INFO
1914 {
1915 OUT USHORT BacklightUsersetting;
1916 OUT USHORT BacklightEffective;
1917 OUT D3DDDI_GAMMA_RAMP_RGB256x3x16 GammaRamp;
1918 } DXGK_BACKLIGHT_INFO;
1919
1920 typedef struct _DXGK_BRIGHTNESS_SENSOR_DATA_CHROMATICITY
1921 {
1922 float ChromaticityX;
1923 float ChromaticityY;
1924 } DXGK_BRIGHTNESS_SENSOR_DATA_CHROMATICITY;
1925
1926 typedef struct _DXGK_BRIGHTNESS_SENSOR_DATA
1927 {
1928 UINT32 Size;
1929 union
1930 {
1931 struct
1932 {
1933 UINT AlsReadingValid : 1;
1934 UINT ChromaticityValid : 1;
1935 UINT ColorTemperatureValid : 1;
1936 UINT Reserved : 29;
1937 } Flags;
1938 UINT ValidSensorValues;
1939 };
1940 float AlsReading;
1941 DXGK_BRIGHTNESS_SENSOR_DATA_CHROMATICITY Chromaticity;
1942 float ColorTemperature;
1943 } DXGK_BRIGHTNESS_SENSOR_DATA;
1944
1945
1946 typedef struct _DXGK_BRIGHTNESS_SET_IN
1947 {
1948 UINT32 BrightnessMillinits;
1949 UINT32 TransitionTimeMs;
1950 DXGK_BRIGHTNESS_SENSOR_DATA SensorReadings;
1951 } DXGK_BRIGHTNESS_SET_IN, *PDXGK_BRIGHTNESS_SET_IN;
1952
1953 typedef struct _DXGK_BRIGHTNESS_GET_OUT
1954 {
1955 UINT32 CurrentBrightnessMillinits;
1956 UINT32 TargetBrightnessMillinits;
1957 } DXGK_BRIGHTNESS_GET_OUT, *PDXGK_BRIGHTNESS_GET_OUT;
1958
1959 typedef struct _DXGK_BRIGHTNESS_NIT_RANGE
1960 {
1961 UINT32 MinimumLevelMillinit;
1962 UINT32 MaximumLevelMillinit;
1963 UINT32 StepSizeMillinit;
1964 } DXGK_BRIGHTNESS_NIT_RANGE;
1965
1966 #define DXGK_BRIGHTNESS_MAXIMUM_NIT_RANGE_COUNT 16
1967
1968 typedef struct _DXGK_BRIGHTNESS_GET_NIT_RANGES_OUT
1969 {
1970 UINT32 NormalRangeCount;
1971 UINT32 RangeCount;
1972 UINT32 PreferredMaximumBrightness;
1973 DXGK_BRIGHTNESS_NIT_RANGE SupportedRanges[DXGK_BRIGHTNESS_MAXIMUM_NIT_RANGE_COUNT];
1974 } DXGK_BRIGHTNESS_GET_NIT_RANGES_OUT, *PDXGK_BRIGHTNESS_GET_NIT_RANGES_OUT;
1975
1976 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3)
1977
1978 typedef struct _D3DKMT_WDDM_1_3_CAPS
1979 {
1980 union
1981 {
1982 struct
1983 {
1984 UINT SupportMiracast : 1;
1985 UINT IsHybridIntegratedGPU : 1;
1986 UINT IsHybridDiscreteGPU : 1;
1987 UINT SupportPowerManagementPStates : 1;
1988 UINT SupportVirtualModes : 1;
1989 UINT SupportCrossAdapterResource : 1;
1990 UINT Reserved : 26;
1991 };
1992 UINT Value;
1993 };
1994 } D3DKMT_WDDM_1_3_CAPS;
1995
1996 #define DXGK_MAX_METADATA_NAME_LENGTH 32
1997 typedef enum
1998 {
1999 DXGK_ENGINE_TYPE_OTHER,
2000 DXGK_ENGINE_TYPE_3D,
2001 DXGK_ENGINE_TYPE_VIDEO_DECODE,
2002 DXGK_ENGINE_TYPE_VIDEO_ENCODE,
2003 DXGK_ENGINE_TYPE_VIDEO_PROCESSING,
2004 DXGK_ENGINE_TYPE_SCENE_ASSEMBLY,
2005 DXGK_ENGINE_TYPE_COPY,
2006 DXGK_ENGINE_TYPE_OVERLAY,
2007 DXGK_ENGINE_TYPE_CRYPTO,
2008 DXGK_ENGINE_TYPE_MAX
2009 } DXGK_ENGINE_TYPE;
2010
2011 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2012
2013 typedef struct _DXGK_NODEMETADATA_FLAGS
2014 {
2015 union
2016 {
2017 struct
2018 {
2019 UINT ContextSchedulingSupported : 1;
2020
2021 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2022
2023 UINT RingBufferFenceRelease : 1;
2024 UINT SupportTrackedWorkload : 1;
2025 UINT Reserved : 13;
2026
2027 UINT MaxInFlightHwQueueBuffers : 16;
2028
2029 #else
2030
2031 UINT Reserved : 31;
2032
2033 #endif // !(DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2034
2035 };
2036 UINT32 Value;
2037 };
2038 } DXGK_NODEMETADATA_FLAGS;
2039
2040 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2041
2042 typedef struct _DXGK_NODEMETADATA
2043 {
2044 DXGK_ENGINE_TYPE EngineType;
2045 WCHAR FriendlyName[DXGK_MAX_METADATA_NAME_LENGTH];
2046
2047 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2048 DXGK_NODEMETADATA_FLAGS Flags;
2049 #else
2050 UINT32 Reserved;
2051 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2052
2053 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0)
2054 BOOLEAN GpuMmuSupported;
2055 BOOLEAN IoMmuSupported;
2056 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0)
2057 } DXGK_NODEMETADATA;
2058
2059 typedef DXGK_NODEMETADATA DXGKARG_GETNODEMETADATA;
2060
2061 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4)
2062
2063 typedef struct _DXGK_GPUCLOCKDATA_FLAGS
2064 {
2065 union
2066 {
2067 struct
2068 {
2069 UINT ContextManagementProcessor : 1;
2070 UINT Reserved : 31;
2071 };
2072 UINT32 Value;
2073 };
2074 } DXGK_GPUCLOCKDATA_FLAGS;
2075
2076 typedef struct _DXGK_NODE_PERFDATA
2077 {
2078 ULONGLONG Frequency; // out: Clock frequency of the engine in hertz
2079 ULONGLONG MaxFrequency; // out: Max engine clock frequency
2080 ULONGLONG MaxFrequencyOC; // out: Max engine over clock frequency
2081 ULONG Voltage; // out: Voltage of the engine in milli volts mV
2082 ULONG VoltageMax; // out: Max voltage levels in milli volts.
2083 ULONG VoltageMaxOC; // out: Max voltage level while overclocked in milli volts.
2084 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2085 ULONGLONG MaxTransitionLatency; // out: Max transition latency to change the frequency in 100 nanoseconds
2086 #endif
2087 } DXGK_NODE_PERFDATA;
2088
2089 typedef struct _DXGK_ADAPTER_PERFDATA
2090 {
2091 ULONGLONG MemoryFrequency; // out: Clock frequency of the memory in hertz
2092 ULONGLONG MaxMemoryFrequency; // out: Max memory clock frequency
2093 ULONGLONG MaxMemoryFrequencyOC; // out: Clock frequency of the memory while overclocked in hertz.
2094 ULONGLONG MemoryBandwidth; // out: Amount of memory transferred in bytes
2095 ULONGLONG PCIEBandwidth; // out: Amount of memory transferred over PCI-E in bytes
2096 ULONG FanRPM; // out: Fan rpm
2097 ULONG Power; // out: Power draw of the adapter in tenths of a percentage
2098 ULONG Temperature; // out: Temperature in deci-Celsius 1 = 0.1C
2099 UCHAR PowerStateOverride; // out: Overrides dxgkrnls power view of linked adapters.
2100 } DXGK_ADAPTER_PERFDATA;
2101
2102 typedef struct _DXGK_ADAPTER_PERFDATACAPS
2103 {
2104 ULONGLONG MaxMemoryBandwidth; // out: Max memory bandwidth in bytes for 1 second
2105 ULONGLONG MaxPCIEBandwidth; // out: Max pcie bandwidth in bytes for 1 second
2106 ULONG MaxFanRPM; // out: Max fan rpm
2107 ULONG TemperatureMax; // out: Max temperature before damage levels
2108 ULONG TemperatureWarning; // out: The temperature level where throttling begins.
2109 } DXGK_ADAPTER_PERFDATACAPS;
2110
2111 #define DXGK_MAX_GPUVERSION_NAME_LENGTH 32
2112 typedef struct _DXGK_GPUVERSION
2113 {
2114 WCHAR BiosVersion[DXGK_MAX_GPUVERSION_NAME_LENGTH]; //out: The gpu bios version
2115 WCHAR GpuArchitecture[DXGK_MAX_GPUVERSION_NAME_LENGTH]; //out: The gpu architectures name.
2116 } DXGK_GPUVERSION;
2117
2118 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4)
2119
2120 typedef struct _DXGK_GPUCLOCKDATA
2121 {
2122 ULONGLONG GpuFrequency;
2123 ULONGLONG GpuClockCounter;
2124 ULONGLONG CpuClockCounter;
2125
2126 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4)
2127 DXGK_GPUCLOCKDATA_FLAGS Flags;
2128 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4)
2129 } DXGK_GPUCLOCKDATA;
2130
2131 typedef DXGK_GPUCLOCKDATA DXGKARG_CALIBRATEGPUCLOCK;
2132
2133 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3)
2134
2135 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0)
2136
2137 typedef struct _D3DKMT_WDDM_2_0_CAPS
2138 {
2139 union
2140 {
2141 struct
2142 {
2143 UINT Support64BitAtomics : 1;
2144 UINT GpuMmuSupported : 1;
2145 UINT IoMmuSupported : 1;
2146
2147 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4)
2148 UINT FlipOverwriteSupported : 1;
2149 UINT SupportContextlessPresent : 1;
2150 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2151 UINT SupportSurpriseRemoval : 1;
2152 UINT Reserved : 26;
2153 #else
2154 UINT Reserved : 27;
2155 #endif // !(DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2156 #else
2157 UINT Reserved : 29;
2158 #endif // !(DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4)
2159 };
2160 UINT Value;
2161 };
2162 } D3DKMT_WDDM_2_0_CAPS;
2163
2164 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_7)
2165
2166 typedef struct _D3DKMT_WDDM_2_7_CAPS
2167 {
2168 union
2169 {
2170 struct
2171 {
2172 UINT HwSchSupported : 1; // Specifies whether the GPU supports hardware scheduling
2173 UINT HwSchEnabled : 1; // Specifies whether the hardware scheduling is currently enabled for this GPU
2174 UINT HwSchEnabledByDefault : 1; // Set to 1 if the OS default policy is to enable hardware scheduling for this GPU
2175 UINT IndependentVidPnVSyncControl : 1;
2176 UINT Reserved : 28;
2177 };
2178 UINT Value;
2179 };
2180 } D3DKMT_WDDM_2_7_CAPS;
2181
2182 #endif
2183
2184 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_9)
2185
2186 // DXGK_FEATURE_SUPPORT constants
2187
2188 // When a driver doesn't support a feature, it doesn't call into QueryFeatureSupport with that feature ID.
2189 // This value is provided for implementation convenience of enumerating possible driver support states
2190 // for a particular feature.
2191 #define DXGK_FEATURE_SUPPORT_ALWAYS_OFF ((UINT)0)
2192
2193 // Driver support for a feature is in the experimental state
2194 #define DXGK_FEATURE_SUPPORT_EXPERIMENTAL ((UINT)1)
2195
2196 // Driver support for a feature is in the stable state
2197 #define DXGK_FEATURE_SUPPORT_STABLE ((UINT)2)
2198
2199 // Driver support for a feature is in the always on state,
2200 // and it doesn't operate without this feature enabled.
2201 #define DXGK_FEATURE_SUPPORT_ALWAYS_ON ((UINT)3)
2202
2203 typedef struct _D3DKMT_WDDM_2_9_CAPS
2204 {
2205 union
2206 {
2207 struct
2208 {
2209 _Field_range_(DXGK_FEATURE_SUPPORT_ALWAYS_OFF, DXGK_FEATURE_SUPPORT_ALWAYS_ON)
2210 UINT HwSchSupportState : 2; // DXGK_FEATURE_SUPPORT_* value that specifies driver support state for GPU supports hardware scheduling
2211 UINT HwSchEnabled : 1; // Specifies whether the hardware scheduling is currently enabled for this GPU
2212 UINT SelfRefreshMemorySupported : 1; // Specifies whether Self Refresh Memory is supported for this GPU
2213 UINT Reserved : 28;
2214 };
2215 UINT Value;
2216 };
2217 } D3DKMT_WDDM_2_9_CAPS;
2218
2219 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_9)
2220
2221 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM3_0)
2222
2223 typedef struct _D3DKMT_WDDM_3_0_CAPS
2224 {
2225 union
2226 {
2227 struct
2228 {
2229 _Field_range_(DXGK_FEATURE_SUPPORT_ALWAYS_OFF, DXGK_FEATURE_SUPPORT_ALWAYS_ON)
2230 UINT HwFlipQueueSupportState : 2; // DXGK_FEATURE_SUPPORT_* value that specifies driver support state for GPU supports hardware flip queue
2231 UINT HwFlipQueueEnabled : 1; // Specifies whether the hardware flip queue is currently enabled for this GPU
2232 UINT DisplayableSupported : 1; // Specifies whether displayable feature is supported
2233 UINT Reserved : 28;
2234 };
2235 UINT Value;
2236 };
2237 } D3DKMT_WDDM_3_0_CAPS;
2238
2239 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM3_0)
2240
2241
2242 typedef struct _D3DKMT_TRACKEDWORKLOAD_SUPPORT
2243 {
2244 _In_ UINT PhysicalAdapterIndex;
2245 _In_ DXGK_ENGINE_TYPE EngineType;
2246 _Out_ BOOL Support;
2247 } D3DKMT_TRACKEDWORKLOAD_SUPPORT;
2248
2249 typedef struct _D3DKMT_NODEMETADATA
2250 {
2251 _In_ UINT NodeOrdinalAndAdapterIndex; // WDDMv2: High word is physical adapter index, low word is node ordinal
2252 _Out_ DXGK_NODEMETADATA NodeData;
2253 } D3DKMT_NODEMETADATA;
2254
2255 typedef struct _D3DKMT_QUERYCLOCKCALIBRATION
2256 {
2257 D3DKMT_HANDLE hAdapter; // in: The adapter to query clock information for
2258 UINT32 NodeOrdinal; // in: Node ordinal of the requested engine.
2259 UINT32 PhysicalAdapterIndex; // in: The physical adapter index, in an LDA chain
2260 DXGK_GPUCLOCKDATA ClockData; // out: Output frequency, Gpu clock, and Cpu clock on the specified engine
2261 } D3DKMT_QUERYCLOCKCALIBRATION;
2262
2263 typedef enum _DXGK_RENDER_PIPELINE_STAGE
2264 {
2265 DXGK_RENDER_PIPELINE_STAGE_UNKNOWN = 0,
2266 DXGK_RENDER_PIPELINE_STAGE_INPUT_ASSEMBLER = 1,
2267 DXGK_RENDER_PIPELINE_STAGE_VERTEX_SHADER = 2,
2268 DXGK_RENDER_PIPELINE_STAGE_GEOMETRY_SHADER = 3,
2269 DXGK_RENDER_PIPELINE_STAGE_STREAM_OUTPUT = 4,
2270 DXGK_RENDER_PIPELINE_STAGE_RASTERIZER = 5,
2271 DXGK_RENDER_PIPELINE_STAGE_PIXEL_SHADER = 6,
2272 DXGK_RENDER_PIPELINE_STAGE_OUTPUT_MERGER = 7,
2273 } DXGK_RENDER_PIPELINE_STAGE;
2274
2275 typedef enum _DXGK_PAGE_FAULT_FLAGS
2276 {
2277 DXGK_PAGE_FAULT_WRITE = 0x1, // when set, indicates that a write to a GPU virtual address failed
2278 DXGK_PAGE_FAULT_FENCE_INVALID = 0x2, // when set, indicates that a fence value for the packet that generated
2279 // the page fault could not be determined
2280 DXGK_PAGE_FAULT_ADAPTER_RESET_REQUIRED = 0x4, // when set, indicates that the page fault put the GPU in a state that requires a full adapter reset
2281 DXGK_PAGE_FAULT_ENGINE_RESET_REQUIRED = 0x8, // when set, indicates that the page fault put the GPU in a state that requires GPU engine reset
2282 DXGK_PAGE_FAULT_FATAL_HARDWARE_ERROR = 0x10, // when set, indicates that the system hardware, not just the GPU, cannot continue,
2283 // and the OS should issue a bugcheck
2284 DXGK_PAGE_FAULT_IOMMU = 0x20, // when set, indicates that the faulting GPU virtual address was mapped using IoMmu,
2285 // when not set, the faulting GPU virtual address was mapped using GPU memory management unit.
2286
2287 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2288
2289 DXGK_PAGE_FAULT_HW_CONTEXT_VALID = 0x40, // when set, indicates that the faulting hardware queue was not identified, but faulting HW context was.
2290 DXGK_PAGE_FAULT_PROCESS_HANDLE_VALID = 0x80, // when set, indicates that the faulting hardware queue or context was not identified,
2291 // but process handle that submitted the faulted buffer was.
2292
2293 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2294
2295 } DXGK_PAGE_FAULT_FLAGS;
2296
2297 typedef enum _DXGK_GENERAL_ERROR_CODE
2298 {
2299 DXGK_GENERAL_ERROR_PAGE_FAULT = 0,
2300 DXGK_GENERAL_ERROR_INVALID_INSTRUCTION = 1,
2301 } DXGK_GENERAL_ERROR_CODE;
2302
2303 typedef struct _DXGK_FAULT_ERROR_CODE
2304 {
2305 union
2306 {
2307 struct
2308 {
2309 UINT IsDeviceSpecificCode : 1; // when set to 1, indicates the low 31 bits correspond to a device specific error code.
2310 // when set to 0, indicates the low 31 bits correspond to a code defined by DXGK_GENERAL_ERROR_CODE.
2311 DXGK_GENERAL_ERROR_CODE GeneralErrorCode : 31; // General error code defined by DXGK_GENERAL_ERROR_CODE.
2312 };
2313 struct
2314 {
2315 UINT IsDeviceSpecificCodeReservedBit : 1; // Same as IsDeviceSpecificCode member above:
2316 // when set to 1, indicates the low 31 bits correspond to a device specific error code.
2317 // when set to 0, indicates the low 31 bits correspond to a code defined by DXGK_GENERAL_ERROR_CODE.
2318 UINT DeviceSpecificCode : 31; // A device specific error code.
2319 };
2320 };
2321 } DXGK_FAULT_ERROR_CODE;
2322
2323 typedef struct _D3DKMT_DRIVERCAPS_EXT
2324 {
2325 union
2326 {
2327 struct
2328 {
2329 UINT VirtualModeSupport : 1;
2330 UINT Usb4MonitorSupport : 1;
2331 UINT Reserved : 30;
2332 };
2333 UINT Value;
2334 };
2335 } D3DKMT_DRIVERCAPS_EXT;
2336
2337 #define DXGK_PRIMITIVE_API_SEQUENCE_NUMBER_UNKNOWN ULONGLONG_MAX
2338 #define DXGK_BIND_TABLE_ENTRY_UNKNOWN UINT_MAX
2339
2340 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0)
2341
2342
2343 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1)
2344
2345 typedef union _DXGK_MONITORLINKINFO_USAGEHINTS
2346 {
2347 struct
2348 {
2349 UINT Hidden : 1; // 0x00000001
2350 UINT Reserved :31; // 0xFFFFFFFE
2351 };
2352 UINT Value;
2353 } DXGK_MONITORLINKINFO_USAGEHINTS, *PDXGK_MONITORLINKINFO_USAGEHINTS;
2354
2355 typedef union _DXGK_MONITORLINKINFO_CAPABILITIES
2356 {
2357 struct
2358 {
2359 UINT Stereo : 1; // 0x00000001
2360 UINT WideColorSpace : 1; // 0x00000002
2361 UINT HighColorSpace : 1; // 0x00000004
2362
2363 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2364 UINT DynamicColorSpace : 1; // 0x00000008
2365 UINT DynamicBitsPerColorChannel : 1; // 0x00000010
2366 UINT DynamicColorEncodingFormat : 1; // 0x00000020
2367 UINT DedicatedTimingGeneration : 1; // 0x00000040
2368 #endif // DXGKDDI_INTERFACE_VERSION_WDDM2_2
2369
2370 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4)
2371 UINT TargetIndependentPrimary : 1; // 0x00000080
2372 UINT SyncLockIdentical : 1; // 0x00000100
2373 UINT Hdr10Plus : 1; // 0x00000200
2374 #endif // DXGKDDI_INTERFACE_VERSION_WDDM2_4
2375
2376 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2377 UINT DolbyVisionLowLatency : 1; // 0x00000400
2378 #endif // DXGKDDI_INTERFACE_VERSION_WDDM2_5
2379
2380 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_6)
2381 UINT VariableRefresh : 1; // 0x00000800
2382 #endif // DXGKDDI_INTERFACE_VERSION_WDDM2_6
2383
2384 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_6)
2385 UINT Reserved :20; // 0xFFFFF000
2386 #elif (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2387 UINT Reserved :21; // 0xFFFFF800
2388 #elif (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4)
2389 UINT Reserved :22; // 0xFFFFFC00
2390 #elif (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2391 UINT Reserved :25; // 0xFFFFFF80
2392 #else
2393 UINT Reserved :29; // 0xFFFFFFF8
2394 #endif // DXGKDDI_INTERFACE_VERSION
2395 };
2396 UINT Value;
2397 } DXGK_MONITORLINKINFO_CAPABILITIES, *PDXGK_MONITORLINKINFO_CAPABILITIES;
2398
2399 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1)
2400
2401
2402 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2403
2404 #if defined(__cplusplus) && !defined(SORTPP_PASS)
2405
2406 typedef enum _DXGK_DISPLAY_USAGE : BYTE
2407 {
2408 DXGK_DU_INVALID = 0,
2409 DXGK_DU_GENERIC = 1,
2410 DXGK_DU_AR = 2,
2411 DXGK_DU_VR = 3,
2412 DXGK_DU_MEDICAL_IMAGING = 4,
2413 DXGK_DU_ACCESSORY = 5,
2414 DXGK_DU_MAX = 6
2415 } DXGK_DISPLAY_USAGE, *PDXGK_DISPLAY_USAGE;
2416
2417 typedef enum _DXGK_DISPLAY_TECHNOLOGY : BYTE
2418 {
2419 DXGK_DT_INVALID = 0,
2420 DXGK_DT_OTHER = 1,
2421 DXGK_DT_LCD = 2,
2422 DXGK_DT_OLED = 3,
2423 DXGK_DT_PROJECTOR = 4,
2424 DXGK_DT_MAX = 5
2425 } DXGK_DISPLAY_TECHNOLOGY, *PDXGK_DISPLAY_TECHNOLOGY;
2426
2427 typedef enum _DXGK_DISPLAY_DESCRIPTOR_TYPE: BYTE
2428 {
2429 DXGK_DDT_INVALID = 0,
2430 DXGK_DDT_EDID,
2431 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2432 DXGK_DDT_DISPLAYID,
2433 #endif
2434 } DXGK_DISPLAY_DESCRIPTOR_TYPE, *PDXGK_DISPLAY_DESCRIPTOR_TYPE;
2435
2436 #else
2437 typedef BYTE DXGK_DISPLAY_USAGE;
2438 typedef BYTE DXGK_DISPLAY_TECHNOLOGY;
2439 typedef BYTE DXGK_DISPLAY_DESCRIPTOR_TYPE;
2440 #endif // defined(__cplusplus) && !defined(SORTPP_PASS)
2441
2442 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2443
2444 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2445
2446 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
2447 // Capabilities, preferences and other information reported by display only capable adapters.
2448
2449 typedef struct _D3DKMT_DISPLAY_CAPS
2450 {
2451 union
2452 {
2453 struct
2454 {
2455 UINT64 PreferPhysicallyContiguous : 1;
2456 UINT64 Reserved : 63;
2457 };
2458 UINT64 Value;
2459 };
2460 } D3DKMT_DISPLAY_CAPS;
2461
2462 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2463
2464 #pragma pack( pop )
2465
2466 #endif // (NTDDI_VERSION >= NTDDI_LONGHORN) || defined(D3DKMDT_SPECIAL_MULTIPLATFORM_TOOL)
2467
2468 #pragma warning(pop)
2469
2470
2471 #endif /* WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_DESKTOP) */
2472 #pragma endregion
2473
2474 #endif /* _D3DKMDT_H */
2475
2476
2477