1 /* 2 * Copyright (c) 2002, 2021, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2012, 2021 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_PPC_MACROASSEMBLER_PPC_HPP 27 #define CPU_PPC_MACROASSEMBLER_PPC_HPP 28 29 #include "asm/assembler.hpp" 30 #include "oops/accessDecorators.hpp" 31 #include "runtime/rtmLocking.hpp" 32 #include "utilities/macros.hpp" 33 34 // MacroAssembler extends Assembler by a few frequently used macros. 35 36 class ciTypeArray; 37 38 class MacroAssembler: public Assembler { 39 public: MacroAssembler(CodeBuffer * code)40 MacroAssembler(CodeBuffer* code) : Assembler(code) {} 41 42 // Indicates whether and, if so, which registers must be preserved when calling runtime code. 43 enum PreservationLevel { 44 PRESERVATION_NONE, 45 PRESERVATION_FRAME_LR, 46 PRESERVATION_FRAME_LR_GP_REGS, 47 PRESERVATION_FRAME_LR_GP_FP_REGS 48 }; 49 50 // 51 // Optimized instruction emitters 52 // 53 largeoffset_si16_si16_hi(int si31)54 inline static int largeoffset_si16_si16_hi(int si31) { return (si31 + (1<<15)) >> 16; } largeoffset_si16_si16_lo(int si31)55 inline static int largeoffset_si16_si16_lo(int si31) { return si31 - (((si31 + (1<<15)) >> 16) << 16); } 56 57 // load d = *[a+si31] 58 // Emits several instructions if the offset is not encodable in one instruction. 59 void ld_largeoffset_unchecked(Register d, int si31, Register a, int emit_filler_nop); 60 void ld_largeoffset (Register d, int si31, Register a, int emit_filler_nop); 61 inline static bool is_ld_largeoffset(address a); 62 inline static int get_ld_largeoffset_offset(address a); 63 64 inline void round_to(Register r, int modulus); 65 66 // Load/store with type given by parameter. 67 void load_sized_value( Register dst, RegisterOrConstant offs, Register base, size_t size_in_bytes, bool is_signed); 68 void store_sized_value(Register dst, RegisterOrConstant offs, Register base, size_t size_in_bytes); 69 70 // Move register if destination register and target register are different 71 inline void mr_if_needed(Register rd, Register rs); 72 inline void fmr_if_needed(FloatRegister rd, FloatRegister rs); 73 // This is dedicated for emitting scheduled mach nodes. For better 74 // readability of the ad file I put it here. 75 // Endgroups are not needed if 76 // - the scheduler is off 77 // - the scheduler found that there is a natural group end, in that 78 // case it reduced the size of the instruction used in the test 79 // yielding 'needed'. 80 inline void endgroup_if_needed(bool needed); 81 82 // Memory barriers. 83 inline void membar(int bits); 84 inline void release(); 85 inline void acquire(); 86 inline void fence(); 87 88 // nop padding 89 void align(int modulus, int max = 252, int rem = 0); 90 91 // 92 // Constants, loading constants, TOC support 93 // 94 95 // Address of the global TOC. 96 inline static address global_toc(); 97 // Offset of given address to the global TOC. 98 inline static int offset_to_global_toc(const address addr); 99 100 // Address of TOC of the current method. 101 inline address method_toc(); 102 // Offset of given address to TOC of the current method. 103 inline int offset_to_method_toc(const address addr); 104 105 // Global TOC. 106 void calculate_address_from_global_toc(Register dst, address addr, 107 bool hi16 = true, bool lo16 = true, 108 bool add_relocation = true, bool emit_dummy_addr = false); calculate_address_from_global_toc_hi16only(Register dst,address addr)109 inline void calculate_address_from_global_toc_hi16only(Register dst, address addr) { 110 calculate_address_from_global_toc(dst, addr, true, false); 111 }; calculate_address_from_global_toc_lo16only(Register dst,address addr)112 inline void calculate_address_from_global_toc_lo16only(Register dst, address addr) { 113 calculate_address_from_global_toc(dst, addr, false, true); 114 }; 115 116 inline static bool is_calculate_address_from_global_toc_at(address a, address bound); 117 // Returns address of first instruction in sequence. 118 static address patch_calculate_address_from_global_toc_at(address a, address bound, address addr); 119 static address get_address_of_calculate_address_from_global_toc_at(address a, address addr); 120 121 #ifdef _LP64 122 // Patch narrow oop constant. 123 inline static bool is_set_narrow_oop(address a, address bound); 124 // Returns address of first instruction in sequence. 125 static address patch_set_narrow_oop(address a, address bound, narrowOop data); 126 static narrowOop get_narrow_oop(address a, address bound); 127 #endif 128 129 inline static bool is_load_const_at(address a); 130 131 // Emits an oop const to the constant pool, loads the constant, and 132 // sets a relocation info with address current_pc. 133 // Returns true if successful. 134 bool load_const_from_method_toc(Register dst, AddressLiteral& a, Register toc, bool fixed_size = false); 135 136 static bool is_load_const_from_method_toc_at(address a); 137 static int get_offset_of_load_const_from_method_toc_at(address a); 138 139 // Get the 64 bit constant from a `load_const' sequence. 140 static long get_const(address load_const); 141 142 // Patch the 64 bit constant of a `load_const' sequence. This is a 143 // low level procedure. It neither flushes the instruction cache nor 144 // is it atomic. 145 static void patch_const(address load_const, long x); 146 147 // Metadata in code that we have to keep track of. 148 AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index 149 AddressLiteral constant_metadata_address(Metadata* obj); // find_index 150 // Oops used directly in compiled code are stored in the constant pool, 151 // and loaded from there. 152 // Allocate new entry for oop in constant pool. Generate relocation. 153 AddressLiteral allocate_oop_address(jobject obj); 154 // Find oop obj in constant pool. Return relocation with it's index. 155 AddressLiteral constant_oop_address(jobject obj); 156 157 // Find oop in constant pool and emit instructions to load it. 158 // Uses constant_oop_address. 159 inline void set_oop_constant(jobject obj, Register d); 160 // Same as load_address. 161 inline void set_oop (AddressLiteral obj_addr, Register d); 162 163 // 164 // branch, jump 165 // 166 // set dst to -1, 0, +1 as follows: if CCR0bi is "greater than", dst is set to 1, 167 // if CCR0bi is "equal", dst is set to 0, otherwise it's set to -1. 168 void inline set_cmp3(Register dst); 169 // set dst to (treat_unordered_like_less ? -1 : +1) 170 void inline set_cmpu3(Register dst, bool treat_unordered_like_less); 171 172 inline void pd_patch_instruction(address branch, address target, const char* file, int line); 173 NOT_PRODUCT(static void pd_print_patched_instruction(address branch);) 174 175 // Conditional far branch for destinations encodable in 24+2 bits. 176 // Same interface as bc, e.g. no inverse boint-field. 177 enum { 178 bc_far_optimize_not = 0, 179 bc_far_optimize_on_relocate = 1 180 }; 181 // optimize: flag for telling the conditional far branch to optimize 182 // itself when relocated. 183 void bc_far(int boint, int biint, Label& dest, int optimize); 184 void bc_far_optimized(int boint, int biint, Label& dest); // 1 or 2 instructions 185 // Relocation of conditional far branches. 186 static bool is_bc_far_at(address instruction_addr); 187 static address get_dest_of_bc_far_at(address instruction_addr); 188 static void set_dest_of_bc_far_at(address instruction_addr, address dest); 189 private: 190 static bool inline is_bc_far_variant1_at(address instruction_addr); 191 static bool inline is_bc_far_variant2_at(address instruction_addr); 192 static bool inline is_bc_far_variant3_at(address instruction_addr); 193 public: 194 195 // Convenience bc_far versions. 196 inline void blt_far(ConditionRegister crx, Label& L, int optimize); 197 inline void bgt_far(ConditionRegister crx, Label& L, int optimize); 198 inline void beq_far(ConditionRegister crx, Label& L, int optimize); 199 inline void bso_far(ConditionRegister crx, Label& L, int optimize); 200 inline void bge_far(ConditionRegister crx, Label& L, int optimize); 201 inline void ble_far(ConditionRegister crx, Label& L, int optimize); 202 inline void bne_far(ConditionRegister crx, Label& L, int optimize); 203 inline void bns_far(ConditionRegister crx, Label& L, int optimize); 204 205 // Emit, identify and patch a NOT mt-safe patchable 64 bit absolute call/jump. 206 private: 207 enum { 208 bxx64_patchable_instruction_count = (2/*load_codecache_const*/ + 3/*5load_const*/ + 1/*mtctr*/ + 1/*bctrl*/), 209 bxx64_patchable_size = bxx64_patchable_instruction_count * BytesPerInstWord, 210 bxx64_patchable_ret_addr_offset = bxx64_patchable_size 211 }; 212 void bxx64_patchable(address target, relocInfo::relocType rt, bool link); 213 static bool is_bxx64_patchable_at( address instruction_addr, bool link); 214 // Does the instruction use a pc-relative encoding of the destination? 215 static bool is_bxx64_patchable_pcrelative_at( address instruction_addr, bool link); 216 static bool is_bxx64_patchable_variant1_at( address instruction_addr, bool link); 217 // Load destination relative to global toc. 218 static bool is_bxx64_patchable_variant1b_at( address instruction_addr, bool link); 219 static bool is_bxx64_patchable_variant2_at( address instruction_addr, bool link); 220 static void set_dest_of_bxx64_patchable_at( address instruction_addr, address target, bool link); 221 static address get_dest_of_bxx64_patchable_at(address instruction_addr, bool link); 222 223 public: 224 // call 225 enum { 226 bl64_patchable_instruction_count = bxx64_patchable_instruction_count, 227 bl64_patchable_size = bxx64_patchable_size, 228 bl64_patchable_ret_addr_offset = bxx64_patchable_ret_addr_offset 229 }; bl64_patchable(address target,relocInfo::relocType rt)230 inline void bl64_patchable(address target, relocInfo::relocType rt) { 231 bxx64_patchable(target, rt, /*link=*/true); 232 } is_bl64_patchable_at(address instruction_addr)233 inline static bool is_bl64_patchable_at(address instruction_addr) { 234 return is_bxx64_patchable_at(instruction_addr, /*link=*/true); 235 } is_bl64_patchable_pcrelative_at(address instruction_addr)236 inline static bool is_bl64_patchable_pcrelative_at(address instruction_addr) { 237 return is_bxx64_patchable_pcrelative_at(instruction_addr, /*link=*/true); 238 } set_dest_of_bl64_patchable_at(address instruction_addr,address target)239 inline static void set_dest_of_bl64_patchable_at(address instruction_addr, address target) { 240 set_dest_of_bxx64_patchable_at(instruction_addr, target, /*link=*/true); 241 } get_dest_of_bl64_patchable_at(address instruction_addr)242 inline static address get_dest_of_bl64_patchable_at(address instruction_addr) { 243 return get_dest_of_bxx64_patchable_at(instruction_addr, /*link=*/true); 244 } 245 // jump 246 enum { 247 b64_patchable_instruction_count = bxx64_patchable_instruction_count, 248 b64_patchable_size = bxx64_patchable_size, 249 }; b64_patchable(address target,relocInfo::relocType rt)250 inline void b64_patchable(address target, relocInfo::relocType rt) { 251 bxx64_patchable(target, rt, /*link=*/false); 252 } is_b64_patchable_at(address instruction_addr)253 inline static bool is_b64_patchable_at(address instruction_addr) { 254 return is_bxx64_patchable_at(instruction_addr, /*link=*/false); 255 } is_b64_patchable_pcrelative_at(address instruction_addr)256 inline static bool is_b64_patchable_pcrelative_at(address instruction_addr) { 257 return is_bxx64_patchable_pcrelative_at(instruction_addr, /*link=*/false); 258 } set_dest_of_b64_patchable_at(address instruction_addr,address target)259 inline static void set_dest_of_b64_patchable_at(address instruction_addr, address target) { 260 set_dest_of_bxx64_patchable_at(instruction_addr, target, /*link=*/false); 261 } get_dest_of_b64_patchable_at(address instruction_addr)262 inline static address get_dest_of_b64_patchable_at(address instruction_addr) { 263 return get_dest_of_bxx64_patchable_at(instruction_addr, /*link=*/false); 264 } 265 266 // 267 // Support for frame handling 268 // 269 270 // some ABI-related functions 271 272 // Clobbers all volatile, (non-floating-point) general-purpose registers for debugging purposes. 273 // This is especially useful for making calls to the JRT in places in which this hasn't been done before; 274 // e.g. with the introduction of LRBs (load reference barriers) for concurrent garbage collection. 275 void clobber_volatile_gprs(Register excluded_register = noreg); 276 void clobber_carg_stack_slots(Register tmp); 277 278 void save_nonvolatile_gprs( Register dst_base, int offset); 279 void restore_nonvolatile_gprs(Register src_base, int offset); 280 281 enum { 282 num_volatile_gp_regs = 11, 283 num_volatile_fp_regs = 14, 284 num_volatile_regs = num_volatile_gp_regs + num_volatile_fp_regs 285 }; 286 287 void save_volatile_gprs( Register dst_base, int offset, 288 bool include_fp_regs = true, bool include_R3_RET_reg = true); 289 void restore_volatile_gprs(Register src_base, int offset, 290 bool include_fp_regs = true, bool include_R3_RET_reg = true); 291 void save_LR_CR( Register tmp); // tmp contains LR on return. 292 void restore_LR_CR(Register tmp); 293 294 // Get current PC using bl-next-instruction trick. 295 address get_PC_trash_LR(Register result); 296 297 // Resize current frame either relatively wrt to current SP or absolute. 298 void resize_frame(Register offset, Register tmp); 299 void resize_frame(int offset, Register tmp); 300 void resize_frame_absolute(Register addr, Register tmp1, Register tmp2); 301 302 // Push a frame of size bytes. 303 void push_frame(Register bytes, Register tmp); 304 305 // Push a frame of size `bytes'. No abi space provided. 306 void push_frame(unsigned int bytes, Register tmp); 307 308 // Push a frame of size `bytes' plus abi_reg_args on top. 309 void push_frame_reg_args(unsigned int bytes, Register tmp); 310 311 // Setup up a new C frame with a spill area for non-volatile GPRs and additional 312 // space for local variables 313 void push_frame_reg_args_nonvolatiles(unsigned int bytes, Register tmp); 314 315 // pop current C frame 316 void pop_frame(); 317 318 // 319 // Calls 320 // 321 322 private: 323 address _last_calls_return_pc; 324 325 #if defined(ABI_ELFv2) 326 // Generic version of a call to C function. 327 // Updates and returns _last_calls_return_pc. 328 address branch_to(Register function_entry, bool and_link); 329 #else 330 // Generic version of a call to C function via a function descriptor 331 // with variable support for C calling conventions (TOC, ENV, etc.). 332 // updates and returns _last_calls_return_pc. 333 address branch_to(Register function_descriptor, bool and_link, bool save_toc_before_call, 334 bool restore_toc_after_call, bool load_toc_of_callee, bool load_env_of_callee); 335 #endif 336 337 public: 338 339 // Get the pc where the last call will return to. returns _last_calls_return_pc. 340 inline address last_calls_return_pc(); 341 342 #if defined(ABI_ELFv2) 343 // Call a C function via a function descriptor and use full C 344 // calling conventions. Updates and returns _last_calls_return_pc. 345 address call_c(Register function_entry); 346 // For tail calls: only branch, don't link, so callee returns to caller of this function. 347 address call_c_and_return_to_caller(Register function_entry); 348 address call_c(address function_entry, relocInfo::relocType rt); 349 #else 350 // Call a C function via a function descriptor and use full C 351 // calling conventions. Updates and returns _last_calls_return_pc. 352 address call_c(Register function_descriptor); 353 // For tail calls: only branch, don't link, so callee returns to caller of this function. 354 address call_c_and_return_to_caller(Register function_descriptor); 355 address call_c(const FunctionDescriptor* function_descriptor, relocInfo::relocType rt); 356 address call_c_using_toc(const FunctionDescriptor* function_descriptor, relocInfo::relocType rt, 357 Register toc); 358 #endif 359 360 protected: 361 362 // It is imperative that all calls into the VM are handled via the 363 // call_VM macros. They make sure that the stack linkage is setup 364 // correctly. call_VM's correspond to ENTRY/ENTRY_X entry points 365 // while call_VM_leaf's correspond to LEAF entry points. 366 // 367 // This is the base routine called by the different versions of 368 // call_VM. The interpreter may customize this version by overriding 369 // it for its purposes (e.g., to save/restore additional registers 370 // when doing a VM call). 371 // 372 // If no last_java_sp is specified (noreg) then SP will be used instead. 373 virtual void call_VM_base( 374 // where an oop-result ends up if any; use noreg otherwise 375 Register oop_result, 376 // to set up last_Java_frame in stubs; use noreg otherwise 377 Register last_java_sp, 378 // the entry point 379 address entry_point, 380 // flag which indicates if exception should be checked 381 bool check_exception = true 382 ); 383 384 // Support for VM calls. This is the base routine called by the 385 // different versions of call_VM_leaf. The interpreter may customize 386 // this version by overriding it for its purposes (e.g., to 387 // save/restore additional registers when doing a VM call). 388 void call_VM_leaf_base(address entry_point); 389 390 public: 391 // Call into the VM. 392 // Passes the thread pointer (in R3_ARG1) as a prepended argument. 393 // Makes sure oop return values are visible to the GC. 394 void call_VM(Register oop_result, address entry_point, bool check_exceptions = true); 395 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true); 396 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 397 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg3, bool check_exceptions = true); 398 void call_VM_leaf(address entry_point); 399 void call_VM_leaf(address entry_point, Register arg_1); 400 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 401 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 402 403 // Call a stub function via a function descriptor, but don't save 404 // TOC before call, don't setup TOC and ENV for call, and don't 405 // restore TOC after call. Updates and returns _last_calls_return_pc. 406 inline address call_stub(Register function_entry); 407 inline void call_stub_and_return_to(Register function_entry, Register return_pc); 408 409 // 410 // Java utilities 411 // 412 413 // Read from the polling page, its address is already in a register. 414 inline void load_from_polling_page(Register polling_page_address, int offset = 0); 415 // Check whether instruction is a read access to the polling page 416 // which was emitted by load_from_polling_page(..). 417 static bool is_load_from_polling_page(int instruction, void* ucontext/*may be NULL*/, 418 address* polling_address_ptr = NULL); 419 420 // Support for NULL-checks 421 // 422 // Generates code that causes a NULL OS exception if the content of reg is NULL. 423 // If the accessed location is M[reg + offset] and the offset is known, provide the 424 // offset. No explicit code generation is needed if the offset is within a certain 425 // range (0 <= offset <= page_size). 426 427 // Stack overflow checking 428 void bang_stack_with_offset(int offset); 429 430 // If instruction is a stack bang of the form ld, stdu, or 431 // stdux, return the banged address. Otherwise, return 0. 432 static address get_stack_bang_address(int instruction, void* ucontext); 433 434 // Check for reserved stack access in method being exited. If the reserved 435 // stack area was accessed, protect it again and throw StackOverflowError. 436 void reserved_stack_check(Register return_pc); 437 438 // Atomics 439 // CmpxchgX sets condition register to cmpX(current, compare). 440 // (flag == ne) => (dest_current_value != compare_value), (!swapped) 441 // (flag == eq) => (dest_current_value == compare_value), ( swapped) cmpxchgx_hint_acquire_lock()442 static inline bool cmpxchgx_hint_acquire_lock() { return true; } 443 // The stxcx will probably not be succeeded by a releasing store. cmpxchgx_hint_release_lock()444 static inline bool cmpxchgx_hint_release_lock() { return false; } cmpxchgx_hint_atomic_update()445 static inline bool cmpxchgx_hint_atomic_update() { return false; } 446 447 // Cmpxchg semantics 448 enum { 449 MemBarNone = 0, 450 MemBarRel = 1, 451 MemBarAcq = 2, 452 MemBarFenceAfter = 4 // use powers of 2 453 }; 454 private: 455 // Helper functions for word/sub-word atomics. 456 void atomic_get_and_modify_generic(Register dest_current_value, Register exchange_value, 457 Register addr_base, Register tmp1, Register tmp2, Register tmp3, 458 bool cmpxchgx_hint, bool is_add, int size); 459 void cmpxchg_loop_body(ConditionRegister flag, Register dest_current_value, 460 Register compare_value, Register exchange_value, 461 Register addr_base, Register tmp1, Register tmp2, 462 Label &retry, Label &failed, bool cmpxchgx_hint, int size); 463 void cmpxchg_generic(ConditionRegister flag, 464 Register dest_current_value, Register compare_value, Register exchange_value, Register addr_base, 465 Register tmp1, Register tmp2, 466 int semantics, bool cmpxchgx_hint, Register int_flag_success, bool contention_hint, bool weak, int size); 467 public: 468 // Temps and addr_base are killed if processor does not support Power 8 instructions. 469 // Result will be sign extended. getandsetb(Register dest_current_value,Register exchange_value,Register addr_base,Register tmp1,Register tmp2,Register tmp3,bool cmpxchgx_hint)470 void getandsetb(Register dest_current_value, Register exchange_value, Register addr_base, 471 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) { 472 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, false, 1); 473 } 474 // Temps and addr_base are killed if processor does not support Power 8 instructions. 475 // Result will be sign extended. getandseth(Register dest_current_value,Register exchange_value,Register addr_base,Register tmp1,Register tmp2,Register tmp3,bool cmpxchgx_hint)476 void getandseth(Register dest_current_value, Register exchange_value, Register addr_base, 477 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) { 478 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, false, 2); 479 } getandsetw(Register dest_current_value,Register exchange_value,Register addr_base,bool cmpxchgx_hint)480 void getandsetw(Register dest_current_value, Register exchange_value, Register addr_base, 481 bool cmpxchgx_hint) { 482 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, noreg, noreg, noreg, cmpxchgx_hint, false, 4); 483 } 484 void getandsetd(Register dest_current_value, Register exchange_value, Register addr_base, 485 bool cmpxchgx_hint); 486 // tmp2/3 and addr_base are killed if processor does not support Power 8 instructions (tmp1 is always needed). 487 // Result will be sign extended. getandaddb(Register dest_current_value,Register inc_value,Register addr_base,Register tmp1,Register tmp2,Register tmp3,bool cmpxchgx_hint)488 void getandaddb(Register dest_current_value, Register inc_value, Register addr_base, 489 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) { 490 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, true, 1); 491 } 492 // tmp2/3 and addr_base are killed if processor does not support Power 8 instructions (tmp1 is always needed). 493 // Result will be sign extended. getandaddh(Register dest_current_value,Register inc_value,Register addr_base,Register tmp1,Register tmp2,Register tmp3,bool cmpxchgx_hint)494 void getandaddh(Register dest_current_value, Register inc_value, Register addr_base, 495 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) { 496 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, true, 2); 497 } getandaddw(Register dest_current_value,Register inc_value,Register addr_base,Register tmp1,bool cmpxchgx_hint)498 void getandaddw(Register dest_current_value, Register inc_value, Register addr_base, 499 Register tmp1, bool cmpxchgx_hint) { 500 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, noreg, noreg, cmpxchgx_hint, true, 4); 501 } 502 void getandaddd(Register dest_current_value, Register exchange_value, Register addr_base, 503 Register tmp, bool cmpxchgx_hint); 504 // Temps, addr_base and exchange_value are killed if processor does not support Power 8 instructions. 505 // compare_value must be at least 32 bit sign extended. Result will be sign extended. cmpxchgb(ConditionRegister flag,Register dest_current_value,Register compare_value,Register exchange_value,Register addr_base,Register tmp1,Register tmp2,int semantics,bool cmpxchgx_hint=false,Register int_flag_success=noreg,bool contention_hint=false,bool weak=false)506 void cmpxchgb(ConditionRegister flag, 507 Register dest_current_value, Register compare_value, Register exchange_value, Register addr_base, 508 Register tmp1, Register tmp2, int semantics, bool cmpxchgx_hint = false, 509 Register int_flag_success = noreg, bool contention_hint = false, bool weak = false) { 510 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base, tmp1, tmp2, 511 semantics, cmpxchgx_hint, int_flag_success, contention_hint, weak, 1); 512 } 513 // Temps, addr_base and exchange_value are killed if processor does not support Power 8 instructions. 514 // compare_value must be at least 32 bit sign extended. Result will be sign extended. cmpxchgh(ConditionRegister flag,Register dest_current_value,Register compare_value,Register exchange_value,Register addr_base,Register tmp1,Register tmp2,int semantics,bool cmpxchgx_hint=false,Register int_flag_success=noreg,bool contention_hint=false,bool weak=false)515 void cmpxchgh(ConditionRegister flag, 516 Register dest_current_value, Register compare_value, Register exchange_value, Register addr_base, 517 Register tmp1, Register tmp2, int semantics, bool cmpxchgx_hint = false, 518 Register int_flag_success = noreg, bool contention_hint = false, bool weak = false) { 519 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base, tmp1, tmp2, 520 semantics, cmpxchgx_hint, int_flag_success, contention_hint, weak, 2); 521 } cmpxchgw(ConditionRegister flag,Register dest_current_value,Register compare_value,Register exchange_value,Register addr_base,int semantics,bool cmpxchgx_hint=false,Register int_flag_success=noreg,bool contention_hint=false,bool weak=false)522 void cmpxchgw(ConditionRegister flag, 523 Register dest_current_value, Register compare_value, Register exchange_value, Register addr_base, 524 int semantics, bool cmpxchgx_hint = false, 525 Register int_flag_success = noreg, bool contention_hint = false, bool weak = false) { 526 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base, noreg, noreg, 527 semantics, cmpxchgx_hint, int_flag_success, contention_hint, weak, 4); 528 } 529 void cmpxchgd(ConditionRegister flag, 530 Register dest_current_value, RegisterOrConstant compare_value, Register exchange_value, 531 Register addr_base, int semantics, bool cmpxchgx_hint = false, 532 Register int_flag_success = noreg, Label* failed = NULL, bool contention_hint = false, bool weak = false); 533 534 // interface method calling 535 void lookup_interface_method(Register recv_klass, 536 Register intf_klass, 537 RegisterOrConstant itable_index, 538 Register method_result, 539 Register temp_reg, Register temp2_reg, 540 Label& no_such_interface, 541 bool return_method = true); 542 543 // virtual method calling 544 void lookup_virtual_method(Register recv_klass, 545 RegisterOrConstant vtable_index, 546 Register method_result); 547 548 // Test sub_klass against super_klass, with fast and slow paths. 549 550 // The fast path produces a tri-state answer: yes / no / maybe-slow. 551 // One of the three labels can be NULL, meaning take the fall-through. 552 // If super_check_offset is -1, the value is loaded up from super_klass. 553 // No registers are killed, except temp_reg and temp2_reg. 554 // If super_check_offset is not -1, temp2_reg is not used and can be noreg. 555 void check_klass_subtype_fast_path(Register sub_klass, 556 Register super_klass, 557 Register temp1_reg, 558 Register temp2_reg, 559 Label* L_success, 560 Label* L_failure, 561 Label* L_slow_path = NULL, // default fall through 562 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 563 564 // The rest of the type check; must be wired to a corresponding fast path. 565 // It does not repeat the fast path logic, so don't use it standalone. 566 // The temp_reg can be noreg, if no temps are available. 567 // It can also be sub_klass or super_klass, meaning it's OK to kill that one. 568 // Updates the sub's secondary super cache as necessary. 569 void check_klass_subtype_slow_path(Register sub_klass, 570 Register super_klass, 571 Register temp1_reg, 572 Register temp2_reg, 573 Label* L_success = NULL, 574 Register result_reg = noreg); 575 576 // Simplified, combined version, good for typical uses. 577 // Falls through on failure. 578 void check_klass_subtype(Register sub_klass, 579 Register super_klass, 580 Register temp1_reg, 581 Register temp2_reg, 582 Label& L_success); 583 584 void clinit_barrier(Register klass, 585 Register thread, 586 Label* L_fast_path = NULL, 587 Label* L_slow_path = NULL); 588 589 // Method handle support (JSR 292). 590 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot, Register temp_reg, int extra_slot_offset = 0); 591 592 // Biased locking support 593 // Upon entry,obj_reg must contain the target object, and mark_reg 594 // must contain the target object's header. 595 // Destroys mark_reg if an attempt is made to bias an anonymously 596 // biased lock. In this case a failure will go either to the slow 597 // case or fall through with the notEqual condition code set with 598 // the expectation that the slow case in the runtime will be called. 599 // In the fall-through case where the CAS-based lock is done, 600 // mark_reg is not destroyed. 601 void biased_locking_enter(ConditionRegister cr_reg, Register obj_reg, Register mark_reg, Register temp_reg, 602 Register temp2_reg, Label& done, Label* slow_case = NULL); 603 // Upon entry, the base register of mark_addr must contain the oop. 604 // Destroys temp_reg. 605 // If allow_delay_slot_filling is set to true, the next instruction 606 // emitted after this one will go in an annulled delay slot if the 607 // biased locking exit case failed. 608 void biased_locking_exit(ConditionRegister cr_reg, Register mark_addr, Register temp_reg, Label& done); 609 610 // allocation (for C1) 611 void eden_allocate( 612 Register obj, // result: pointer to object after successful allocation 613 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 614 int con_size_in_bytes, // object size in bytes if known at compile time 615 Register t1, // temp register 616 Register t2, // temp register 617 Label& slow_case // continuation point if fast allocation fails 618 ); 619 void tlab_allocate( 620 Register obj, // result: pointer to object after successful allocation 621 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 622 int con_size_in_bytes, // object size in bytes if known at compile time 623 Register t1, // temp register 624 Label& slow_case // continuation point if fast allocation fails 625 ); 626 void incr_allocated_bytes(RegisterOrConstant size_in_bytes, Register t1, Register t2); 627 628 enum { trampoline_stub_size = 6 * 4 }; 629 address emit_trampoline_stub(int destination_toc_offset, int insts_call_instruction_offset, Register Rtoc = noreg); 630 631 void atomic_inc_ptr(Register addr, Register result, int simm16 = 1); 632 void atomic_ori_int(Register addr, Register result, int uimm16); 633 634 #if INCLUDE_RTM_OPT 635 void rtm_counters_update(Register abort_status, Register rtm_counters); 636 void branch_on_random_using_tb(Register tmp, int count, Label& brLabel); 637 void rtm_abort_ratio_calculation(Register rtm_counters_reg, RTMLockingCounters* rtm_counters, 638 Metadata* method_data); 639 void rtm_profiling(Register abort_status_Reg, Register temp_Reg, 640 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm); 641 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, 642 Label& retryLabel, Label* checkRetry = NULL); 643 void rtm_retry_lock_on_busy(Register retry_count, Register owner_addr, Label& retryLabel); 644 void rtm_stack_locking(ConditionRegister flag, Register obj, Register mark_word, Register tmp, 645 Register retry_on_abort_count, 646 RTMLockingCounters* stack_rtm_counters, 647 Metadata* method_data, bool profile_rtm, 648 Label& DONE_LABEL, Label& IsInflated); 649 void rtm_inflated_locking(ConditionRegister flag, Register obj, Register mark_word, Register box, 650 Register retry_on_busy_count, Register retry_on_abort_count, 651 RTMLockingCounters* rtm_counters, 652 Metadata* method_data, bool profile_rtm, 653 Label& DONE_LABEL); 654 #endif 655 656 void compiler_fast_lock_object(ConditionRegister flag, Register oop, Register box, 657 Register tmp1, Register tmp2, Register tmp3, 658 bool try_bias = UseBiasedLocking, 659 RTMLockingCounters* rtm_counters = NULL, 660 RTMLockingCounters* stack_rtm_counters = NULL, 661 Metadata* method_data = NULL, 662 bool use_rtm = false, bool profile_rtm = false); 663 664 void compiler_fast_unlock_object(ConditionRegister flag, Register oop, Register box, 665 Register tmp1, Register tmp2, Register tmp3, 666 bool try_bias = UseBiasedLocking, bool use_rtm = false); 667 668 // Check if safepoint requested and if so branch 669 void safepoint_poll(Label& slow_path, Register temp, bool at_return, bool in_nmethod); 670 671 void resolve_jobject(Register value, Register tmp1, Register tmp2, 672 MacroAssembler::PreservationLevel preservation_level); 673 674 // Support for managing the JavaThread pointer (i.e.; the reference to 675 // thread-local information). 676 677 // Support for last Java frame (but use call_VM instead where possible): 678 // access R16_thread->last_Java_sp. 679 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc); 680 void reset_last_Java_frame(void); 681 void set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1); 682 683 // Read vm result from thread: oop_result = R16_thread->result; 684 void get_vm_result (Register oop_result); 685 void get_vm_result_2(Register metadata_result); 686 687 static bool needs_explicit_null_check(intptr_t offset); 688 static bool uses_implicit_null_check(void* address); 689 690 // Trap-instruction-based checks. 691 // Range checks can be distinguished from zero checks as they check 32 bit, 692 // zero checks all 64 bits (tw, td). 693 inline void trap_null_check(Register a, trap_to_bits cmp = traptoEqual); is_trap_null_check(int x)694 static bool is_trap_null_check(int x) { 695 return is_tdi(x, traptoEqual, -1/*any reg*/, 0) || 696 is_tdi(x, traptoGreaterThanUnsigned, -1/*any reg*/, 0); 697 } 698 699 inline void trap_ic_miss_check(Register a, Register b); is_trap_ic_miss_check(int x)700 static bool is_trap_ic_miss_check(int x) { 701 return is_td(x, traptoGreaterThanUnsigned | traptoLessThanUnsigned, -1/*any reg*/, -1/*any reg*/); 702 } 703 704 // Implicit or explicit null check, jumps to static address exception_entry. 705 inline void null_check_throw(Register a, int offset, Register temp_reg, address exception_entry); 706 inline void null_check(Register a, int offset, Label *Lis_null); // implicit only if Lis_null not provided 707 708 // Access heap oop, handle encoding and GC barriers. 709 // Some GC barriers call C so use needs_frame = true if an extra frame is needed at the current call site. 710 private: 711 inline void access_store_at(BasicType type, DecoratorSet decorators, 712 Register base, RegisterOrConstant ind_or_offs, Register val, 713 Register tmp1, Register tmp2, Register tmp3, 714 MacroAssembler::PreservationLevel preservation_level); 715 inline void access_load_at(BasicType type, DecoratorSet decorators, 716 Register base, RegisterOrConstant ind_or_offs, Register dst, 717 Register tmp1, Register tmp2, 718 MacroAssembler::PreservationLevel preservation_level, Label *L_handle_null = NULL); 719 720 public: 721 // Specify tmp1 for better code in certain compressed oops cases. Specify Label to bail out on null oop. 722 // tmp1, tmp2 and needs_frame are used with decorators ON_PHANTOM_OOP_REF or ON_WEAK_OOP_REF. 723 inline void load_heap_oop(Register d, RegisterOrConstant offs, Register s1, 724 Register tmp1, Register tmp2, 725 MacroAssembler::PreservationLevel preservation_level, 726 DecoratorSet decorators = 0, Label *L_handle_null = NULL); 727 728 inline void store_heap_oop(Register d, RegisterOrConstant offs, Register s1, 729 Register tmp1, Register tmp2, Register tmp3, 730 MacroAssembler::PreservationLevel preservation_level, DecoratorSet decorators = 0); 731 732 // Encode/decode heap oop. Oop may not be null, else en/decoding goes wrong. 733 // src == d allowed. 734 inline Register encode_heap_oop_not_null(Register d, Register src = noreg); 735 inline Register decode_heap_oop_not_null(Register d, Register src = noreg); 736 737 // Null allowed. 738 inline Register encode_heap_oop(Register d, Register src); // Prefer null check in GC barrier! 739 inline void decode_heap_oop(Register d); 740 741 // Load/Store klass oop from klass field. Compress. 742 void load_klass(Register dst, Register src); 743 void store_klass(Register dst_oop, Register klass, Register tmp = R0); 744 void store_klass_gap(Register dst_oop, Register val = noreg); // Will store 0 if val not specified. 745 746 void resolve_oop_handle(Register result, Register tmp1, Register tmp2, 747 MacroAssembler::PreservationLevel preservation_level); 748 void resolve_weak_handle(Register result, Register tmp1, Register tmp2, 749 MacroAssembler::PreservationLevel preservation_level); 750 void load_method_holder(Register holder, Register method); 751 752 static int instr_size_for_decode_klass_not_null(); 753 void decode_klass_not_null(Register dst, Register src = noreg); 754 Register encode_klass_not_null(Register dst, Register src = noreg); 755 756 // SIGTRAP-based range checks for arrays. 757 inline void trap_range_check_l(Register a, Register b); 758 inline void trap_range_check_l(Register a, int si16); is_trap_range_check_l(int x)759 static bool is_trap_range_check_l(int x) { 760 return (is_tw (x, traptoLessThanUnsigned, -1/*any reg*/, -1/*any reg*/) || 761 is_twi(x, traptoLessThanUnsigned, -1/*any reg*/) ); 762 } 763 inline void trap_range_check_le(Register a, int si16); is_trap_range_check_le(int x)764 static bool is_trap_range_check_le(int x) { 765 return is_twi(x, traptoEqual | traptoLessThanUnsigned, -1/*any reg*/); 766 } 767 inline void trap_range_check_g(Register a, int si16); is_trap_range_check_g(int x)768 static bool is_trap_range_check_g(int x) { 769 return is_twi(x, traptoGreaterThanUnsigned, -1/*any reg*/); 770 } 771 inline void trap_range_check_ge(Register a, Register b); 772 inline void trap_range_check_ge(Register a, int si16); is_trap_range_check_ge(int x)773 static bool is_trap_range_check_ge(int x) { 774 return (is_tw (x, traptoEqual | traptoGreaterThanUnsigned, -1/*any reg*/, -1/*any reg*/) || 775 is_twi(x, traptoEqual | traptoGreaterThanUnsigned, -1/*any reg*/) ); 776 } is_trap_range_check(int x)777 static bool is_trap_range_check(int x) { 778 return is_trap_range_check_l(x) || is_trap_range_check_le(x) || 779 is_trap_range_check_g(x) || is_trap_range_check_ge(x); 780 } 781 782 void clear_memory_unrolled(Register base_ptr, int cnt_dwords, Register tmp = R0, int offset = 0); 783 void clear_memory_constlen(Register base_ptr, int cnt_dwords, Register tmp = R0); 784 void clear_memory_doubleword(Register base_ptr, Register cnt_dwords, Register tmp = R0, long const_cnt = -1); 785 786 // Emitters for BigInteger.multiplyToLen intrinsic. 787 inline void multiply64(Register dest_hi, Register dest_lo, 788 Register x, Register y); 789 void add2_with_carry(Register dest_hi, Register dest_lo, 790 Register src1, Register src2); 791 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 792 Register y, Register y_idx, Register z, 793 Register carry, Register product_high, Register product, 794 Register idx, Register kdx, Register tmp); 795 void multiply_add_128_x_128(Register x_xstart, Register y, Register z, 796 Register yz_idx, Register idx, Register carry, 797 Register product_high, Register product, Register tmp, 798 int offset); 799 void multiply_128_x_128_loop(Register x_xstart, 800 Register y, Register z, 801 Register yz_idx, Register idx, Register carry, 802 Register product_high, Register product, 803 Register carry2, Register tmp); 804 void muladd(Register out, Register in, Register offset, Register len, Register k, 805 Register tmp1, Register tmp2, Register carry); 806 void multiply_to_len(Register x, Register xlen, 807 Register y, Register ylen, 808 Register z, Register zlen, 809 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, 810 Register tmp6, Register tmp7, Register tmp8, Register tmp9, Register tmp10, 811 Register tmp11, Register tmp12, Register tmp13); 812 813 // Emitters for CRC32 calculation. 814 // A note on invertCRC: 815 // Unfortunately, internal representation of crc differs between CRC32 and CRC32C. 816 // CRC32 holds it's current crc value in the externally visible representation. 817 // CRC32C holds it's current crc value in internal format, ready for updating. 818 // Thus, the crc value must be bit-flipped before updating it in the CRC32 case. 819 // In the CRC32C case, it must be bit-flipped when it is given to the outside world (getValue()). 820 // The bool invertCRC parameter indicates whether bit-flipping is required before updates. 821 void load_reverse_32(Register dst, Register src); 822 int crc32_table_columns(Register table, Register tc0, Register tc1, Register tc2, Register tc3); 823 void fold_byte_crc32(Register crc, Register val, Register table, Register tmp); 824 void update_byte_crc32(Register crc, Register val, Register table); 825 void update_byteLoop_crc32(Register crc, Register buf, Register len, Register table, 826 Register data, bool loopAlignment); 827 void update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc, 828 Register t0, Register t1, Register t2, Register t3, 829 Register tc0, Register tc1, Register tc2, Register tc3); 830 void kernel_crc32_1word(Register crc, Register buf, Register len, Register table, 831 Register t0, Register t1, Register t2, Register t3, 832 Register tc0, Register tc1, Register tc2, Register tc3, 833 bool invertCRC); 834 void kernel_crc32_vpmsum(Register crc, Register buf, Register len, Register constants, 835 Register t0, Register t1, Register t2, Register t3, Register t4, 836 Register t5, Register t6, bool invertCRC); 837 void kernel_crc32_vpmsum_aligned(Register crc, Register buf, Register len, Register constants, 838 Register t0, Register t1, Register t2, Register t3, Register t4, 839 Register t5, Register t6); 840 // Version which internally decides what to use. 841 void crc32(Register crc, Register buf, Register len, Register t0, Register t1, Register t2, 842 Register t3, Register t4, Register t5, Register t6, Register t7, bool is_crc32c); 843 844 void kernel_crc32_singleByteReg(Register crc, Register val, Register table, 845 bool invertCRC); 846 847 // SHA-2 auxiliary functions and public interfaces 848 private: 849 void sha256_deque(const VectorRegister src, 850 const VectorRegister dst1, const VectorRegister dst2, const VectorRegister dst3); 851 void sha256_load_h_vec(const VectorRegister a, const VectorRegister e, const Register hptr); 852 void sha256_round(const VectorRegister* hs, const int total_hs, int& h_cnt, const VectorRegister kpw); 853 void sha256_load_w_plus_k_vec(const Register buf_in, const VectorRegister* ws, 854 const int total_ws, const Register k, const VectorRegister* kpws, 855 const int total_kpws); 856 void sha256_calc_4w(const VectorRegister w0, const VectorRegister w1, 857 const VectorRegister w2, const VectorRegister w3, const VectorRegister kpw0, 858 const VectorRegister kpw1, const VectorRegister kpw2, const VectorRegister kpw3, 859 const Register j, const Register k); 860 void sha256_update_sha_state(const VectorRegister a, const VectorRegister b, 861 const VectorRegister c, const VectorRegister d, const VectorRegister e, 862 const VectorRegister f, const VectorRegister g, const VectorRegister h, 863 const Register hptr); 864 865 void sha512_load_w_vec(const Register buf_in, const VectorRegister* ws, const int total_ws); 866 void sha512_update_sha_state(const Register state, const VectorRegister* hs, const int total_hs); 867 void sha512_round(const VectorRegister* hs, const int total_hs, int& h_cnt, const VectorRegister kpw); 868 void sha512_load_h_vec(const Register state, const VectorRegister* hs, const int total_hs); 869 void sha512_calc_2w(const VectorRegister w0, const VectorRegister w1, 870 const VectorRegister w2, const VectorRegister w3, 871 const VectorRegister w4, const VectorRegister w5, 872 const VectorRegister w6, const VectorRegister w7, 873 const VectorRegister kpw0, const VectorRegister kpw1, const Register j, 874 const VectorRegister vRb, const Register k); 875 876 public: 877 void sha256(bool multi_block); 878 void sha512(bool multi_block); 879 880 void cache_wb(Address line); 881 void cache_wbsync(bool is_presync); 882 883 // 884 // Debugging 885 // 886 887 // assert on cr0 888 void asm_assert(bool check_equal, const char* msg); asm_assert_eq(const char * msg)889 void asm_assert_eq(const char* msg) { asm_assert(true, msg); } asm_assert_ne(const char * msg)890 void asm_assert_ne(const char* msg) { asm_assert(false, msg); } 891 892 private: 893 void asm_assert_mems_zero(bool check_equal, int size, int mem_offset, Register mem_base, 894 const char* msg); 895 896 public: 897 asm_assert_mem8_is_zero(int mem_offset,Register mem_base,const char * msg)898 void asm_assert_mem8_is_zero(int mem_offset, Register mem_base, const char* msg) { 899 asm_assert_mems_zero(true, 8, mem_offset, mem_base, msg); 900 } asm_assert_mem8_isnot_zero(int mem_offset,Register mem_base,const char * msg)901 void asm_assert_mem8_isnot_zero(int mem_offset, Register mem_base, const char* msg) { 902 asm_assert_mems_zero(false, 8, mem_offset, mem_base, msg); 903 } 904 905 // Verify R16_thread contents. 906 void verify_thread(); 907 908 // Calls verify_oop. If UseCompressedOops is on, decodes the oop. 909 // Preserves reg. 910 void verify_coop(Register reg, const char*); 911 // Emit code to verify that reg contains a valid oop if +VerifyOops is set. 912 void verify_oop(Register reg, const char* s = "broken oop"); 913 void verify_oop_addr(RegisterOrConstant offs, Register base, const char* s = "contains broken oop"); 914 915 // TODO: verify method and klass metadata (compare against vptr?) _verify_method_ptr(Register reg,const char * msg,const char * file,int line)916 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} _verify_klass_ptr(Register reg,const char * msg,const char * file,int line)917 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line) {} 918 919 // Convenience method returning function entry. For the ELFv1 case 920 // creates function descriptor at the current address and returs 921 // the pointer to it. For the ELFv2 case returns the current address. 922 inline address function_entry(); 923 924 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 925 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 926 927 private: 928 void stop(int type, const char* msg); 929 930 public: 931 enum { 932 stop_stop = 0, 933 stop_untested = 1, 934 stop_unimplemented = 2, 935 stop_shouldnotreachhere = 3, 936 stop_msg_present = -0x8000 937 }; 938 939 // Prints msg, dumps registers and stops execution. stop(const char * msg=NULL)940 void stop (const char* msg = NULL) { stop(stop_stop, msg); } untested(const char * msg=NULL)941 void untested (const char* msg = NULL) { stop(stop_untested, msg); } unimplemented(const char * msg=NULL)942 void unimplemented (const char* msg = NULL) { stop(stop_unimplemented, msg); } should_not_reach_here(const char * msg=NULL)943 void should_not_reach_here(const char* msg = NULL) { stop(stop_shouldnotreachhere, msg); } 944 945 void zap_from_to(Register low, int before, Register high, int after, Register val, Register addr) PRODUCT_RETURN; 946 }; 947 948 // class SkipIfEqualZero: 949 // 950 // Instantiating this class will result in assembly code being output that will 951 // jump around any code emitted between the creation of the instance and it's 952 // automatic destruction at the end of a scope block, depending on the value of 953 // the flag passed to the constructor, which will be checked at run-time. 954 class SkipIfEqualZero : public StackObj { 955 private: 956 MacroAssembler* _masm; 957 Label _label; 958 959 public: 960 // 'Temp' is a temp register that this object can use (and trash). 961 explicit SkipIfEqualZero(MacroAssembler*, Register temp, const bool* flag_addr); 962 static void skip_to_label_if_equal_zero(MacroAssembler*, Register temp, 963 const bool* flag_addr, Label& label); 964 ~SkipIfEqualZero(); 965 }; 966 967 #endif // CPU_PPC_MACROASSEMBLER_PPC_HPP 968