1 /* $OpenBSD: qlwreg.h,v 1.7 2014/03/15 21:49:47 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2013, 2014 Jonathan Matthew <jmatthew@openbsd.org> 5 * Copyright (c) 2014 Mark Kettenis <kettenis@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* firmware loading */ 21 #define QLW_CODE_ORG 0x1000 22 23 /* interrupt types */ 24 #define QLW_INT_TYPE_MBOX 1 25 #define QLW_INT_TYPE_ASYNC 2 26 #define QLW_INT_TYPE_IO 3 27 #define QLW_INT_TYPE_OTHER 4 28 29 /* ISP registers */ 30 #define QLW_CFG0 0x04 31 #define QLW_CFG1 0x06 32 #define QLW_INT_CTRL 0x08 33 #define QLW_INT_STATUS 0x0a 34 #define QLW_SEMA 0x0c 35 #define QLW_NVRAM 0x0e 36 #define QLW_FLASH_BIOS_DATA 0x10 37 #define QLW_FLASH_BIOS_ADDR 0x12 38 #define QLW_CDMA_CFG 0x20 39 #define QLW_DDMA_CFG 0x40 40 #define QLW_MBOX_BASE_PCI 0x70 41 #define QLW_MBOX_BASE_SBUS 0x80 42 #define QLW_CDMA_CFG_1080 0x80 43 #define QLW_DDMA_CFG_1080 0xa0 44 #define QLW_HOST_CMD_CTRL_PCI 0xc0 45 #define QLW_GPIO_DATA 0xcc 46 #define QLW_GPIO_ENABLE 0xce 47 48 #define QLW_HOST_CMD_CTRL_SBUS 0x440 49 50 #define QLW_REQ_IN 0x08 51 #define QLW_REQ_OUT 0x08 52 #define QLW_RESP_IN 0x0a 53 #define QLW_RESP_OUT 0x0a 54 55 /* QLW_CFG1 */ 56 #define QLW_BURST_ENABLE 0x0004 57 #define QLW_PCI_FIFO_16 0x0010 58 #define QLW_PCI_FIFO_32 0x0020 59 #define QLW_PCI_FIFO_64 0x0030 60 #define QLW_PCI_FIFO_128 0x0040 61 #define QLW_PCI_FIFO_MASK 0x0070 62 #define QLW_SBUS_FIFO_64 0x0003 63 #define QLW_SBUS_FIFO_32 0x0002 64 #define QLW_SBUS_FIFO_16 0x0001 65 #define QLW_SBUS_FIFO_8 0x0000 66 #define QLW_SBUS_FIFO_MASK 0x0003 67 #define QLW_SBUS_BURST_8 0x0008 68 #define QLW_DMA_BANK 0x0300 69 70 /* QLW_INT_CTRL */ 71 #define QLW_RESET 0x0001 72 73 /* QLW_INT_STATUS */ 74 #define QLW_INT_REQ 0x0002 75 #define QLW_RISC_INT_REQ 0x0004 76 77 /* QLW_SEMA */ 78 #define QLW_SEMA_STATUS 0x0002 79 #define QLW_SEMA_LOCK 0x0001 80 81 /* QLW_NVRAM */ 82 #define QLW_NVRAM_DATA_IN 0x0008 83 #define QLW_NVRAM_DATA_OUT 0x0004 84 #define QLW_NVRAM_CHIP_SEL 0x0002 85 #define QLW_NVRAM_CLOCK 0x0001 86 #define QLW_NVRAM_CMD_READ 6 87 88 /* QLW_CDMA_CFG and QLW_DDMA_CFG */ 89 #define QLW_DMA_BURST_ENABLE 0x0002 90 91 /* QLW_HOST_CMD_CTRL write */ 92 #define QLW_HOST_CMD_SHIFT 12 93 #define QLW_HOST_CMD_NOP 0x0 94 #define QLW_HOST_CMD_RESET 0x1 95 #define QLW_HOST_CMD_PAUSE 0x2 96 #define QLW_HOST_CMD_RELEASE 0x3 97 #define QLW_HOST_CMD_MASK_PARITY 0x4 98 #define QLW_HOST_CMD_SET_HOST_INT 0x5 99 #define QLW_HOST_CMD_CLR_HOST_INT 0x6 100 #define QLW_HOST_CMD_CLR_RISC_INT 0x7 101 #define QLW_HOST_CMD_BIOS 0x9 102 #define QLW_HOST_CMD_ENABLE_PARITY 0xa 103 #define QLW_HOST_CMD_PARITY_ERROR 0xe 104 105 /* QLA_HOST_CMD_CTRL read */ 106 #define QLA_HOST_STATUS_HOST_INT 0x0080 107 #define QLA_HOST_STATUS_RISC_RESET 0x0040 108 #define QLA_HOST_STATUS_RISC_PAUSE 0x0020 109 #define QLA_HOST_STATUS_RISC_EXT 0x0010 110 111 /* QLW_MBIX_BASE (reg 0) read */ 112 #define QLW_MBOX_HAS_STATUS 0x4000 113 #define QLW_MBOX_COMPLETE 0x4000 114 #define QLW_MBOX_INVALID 0x4001 115 #define QLW_ASYNC_BUS_RESET 0x8001 116 #define QLW_ASYNC_SYSTEM_ERROR 0x8002 117 #define QLW_ASYNC_REQ_XFER_ERROR 0x8003 118 #define QLW_ASYNC_RSP_XFER_ERROR 0x8004 119 #define QLW_ASYNC_SCSI_CMD_COMPLETE 0x8020 120 #define QLW_ASYNC_CTIO_COMPLETE 0x8021 121 122 /* QLW_MBOX_BASE (reg 0) write */ 123 #define QLW_MBOX_NOP 0x0000 124 #define QLW_MBOX_LOAD_RAM 0x0001 125 #define QLW_MBOX_EXEC_FIRMWARE 0x0002 126 #define QLW_MBOX_WRITE_RAM_WORD 0x0004 127 #define QLW_MBOX_REGISTER_TEST 0x0006 128 #define QLW_MBOX_VERIFY_CSUM 0x0007 129 #define QLW_MBOX_ABOUT_FIRMWARE 0x0008 130 #define QLW_MBOX_INIT_REQ_QUEUE 0x0010 131 #define QLW_MBOX_INIT_RSP_QUEUE 0x0011 132 #define QLW_MBOX_BUS_RESET 0x0018 133 #define QLW_MBOX_GET_FIRMWARE_STATUS 0x001F 134 #define QLW_MBOX_SET_INITIATOR_ID 0x0030 135 #define QLW_MBOX_SET_SELECTION_TIMEOUT 0x0031 136 #define QLW_MBOX_SET_RETRY_COUNT 0x0032 137 #define QLW_MBOX_SET_TAG_AGE_LIMIT 0x0033 138 #define QLW_MBOX_SET_CLOCK_RATE 0x0034 139 #define QLW_MBOX_SET_ACTIVE_NEGATION 0x0035 140 #define QLW_MBOX_SET_ASYNC_DATA_SETUP 0x0036 141 #define QLW_MBOX_SET_PCI_CONTROL 0x0037 142 #define QLW_MBOX_SET_TARGET_PARAMETERS 0x0038 143 #define QLW_MBOX_SET_DEVICE_QUEUE 0x0039 144 #define QLW_MBOX_SET_SYSTEM_PARAMETER 0x0045 145 #define QLW_MBOX_SET_FIRMWARE_FEATURES 0x004a 146 #define QLW_MBOX_INIT_REQ_QUEUE_A64 0x0052 147 #define QLW_MBOX_INIT_RSP_QUEUE_A64 0x0053 148 #define QLW_MBOX_SET_DATA_OVERRUN_RECOVERY 0x005a 149 150 /* mailbox operation register bitfields */ 151 #define QLW_MBOX_ABOUT_FIRMWARE_IN 0x0001 152 #define QLW_MBOX_ABOUT_FIRMWARE_OUT 0x004f 153 #define QLW_MBOX_INIT_FIRMWARE_IN 0x00fd 154 155 #define QLW_FW_FEATURE_FAST_POSTING 0x0001 156 #define QLW_FW_FEATURE_LVD_NOTIFY 0x0002 157 158 /* nvram layout */ 159 struct qlw_nvram_target { 160 u_int8_t parameter; 161 u_int8_t execution_throttle; 162 u_int8_t sync_period; 163 u_int8_t flags; 164 u_int8_t reserved[2]; 165 } __packed; 166 167 struct qlw_nvram_1040 { 168 u_int8_t id[4]; 169 u_int8_t nvram_version; 170 u_int8_t config1; 171 u_int8_t reset_delay; 172 u_int8_t retry_count; 173 u_int8_t retry_delay; 174 u_int8_t config2; 175 u_int8_t tag_age_limit; 176 u_int8_t flags1; 177 u_int16_t selection_timeout; 178 u_int16_t max_queue_depth; 179 u_int8_t flags2; 180 u_int8_t reserved_0[5]; 181 u_int8_t flags3; 182 u_int8_t reserved_1[5]; 183 struct qlw_nvram_target target[16]; 184 u_int8_t reserved_2[3]; 185 u_int8_t checksum; 186 } __packed; 187 188 struct qlw_nvram_bus { 189 u_int8_t config1; 190 u_int8_t reset_delay; 191 u_int8_t retry_count; 192 u_int8_t retry_delay; 193 u_int8_t config2; 194 u_int8_t reserved_0; 195 u_int16_t selection_timeout; 196 u_int16_t max_queue_depth; 197 u_int8_t reserved_1[6]; 198 struct qlw_nvram_target target[16]; 199 } __packed; 200 201 struct qlw_nvram_1080 { 202 u_int8_t id[4]; 203 u_int8_t nvram_version; 204 u_int8_t flags1; 205 u_int16_t flags2; 206 u_int8_t reserved_0[8]; 207 u_int8_t isp_config; 208 u_int8_t termination; 209 u_int16_t isp_parameter; 210 u_int16_t fw_features; 211 u_int16_t reserved_1; 212 struct qlw_nvram_bus bus[2]; 213 u_int8_t reserved_2[2]; 214 u_int16_t subsystem_vendor_id; 215 u_int16_t subsystem_device_id; 216 u_int8_t reserved_3; 217 u_int8_t checksum; 218 } __packed; 219 220 struct qlw_nvram { 221 u_int8_t id[4]; 222 u_int8_t nvram_version; 223 u_int8_t data[251]; 224 }; 225 226 #define QLW_TARGET_PPR 0x0020 227 #define QLW_TARGET_ASYNC 0x0040 228 #define QLW_TARGET_NARROW 0x0080 229 #define QLW_TARGET_RENEG 0x0100 230 #define QLW_TARGET_QFRZ 0x0200 231 #define QLW_TARGET_ARQ 0x0400 232 #define QLW_TARGET_TAGS 0x0800 233 #define QLW_TARGET_SYNC 0x1000 234 #define QLW_TARGET_WIDE 0x2000 235 #define QLW_TARGET_PARITY 0x4000 236 #define QLW_TARGET_DISC 0x8000 237 #define QLW_TARGET_SAFE 0xc500 238 #define QLW_TARGET_DEFAULT 0xfd00 239 240 #define QLW_IOCB_CMD_HEAD_OF_QUEUE 0x0002 241 #define QLW_IOCB_CMD_ORDERED_QUEUE 0x0004 242 #define QLW_IOCB_CMD_SIMPLE_QUEUE 0x0008 243 #define QLW_IOCB_CMD_NO_DATA 0x0000 244 #define QLW_IOCB_CMD_READ_DATA 0x0020 245 #define QLW_IOCB_CMD_WRITE_DATA 0x0040 246 #define QLW_IOCB_CMD_NO_FAST_POST 0x0080 247 248 struct qlw_iocb_hdr { 249 u_int8_t entry_type; 250 u_int8_t entry_count; 251 u_int8_t seqno; 252 u_int8_t flags; 253 } __packed; 254 255 #define QLW_IOCB_SEGS_PER_CMD 4 256 #define QLW_IOCB_SEGS_PER_CONT 7 257 258 struct qlw_iocb_seg { 259 u_int32_t seg_addr; 260 u_int32_t seg_len; 261 } __packed; 262 263 /* IOCB types */ 264 #define QLW_IOCB_CMD_TYPE_0 0x01 265 #define QLW_IOCB_CONT_TYPE_0 0x02 266 #define QLW_IOCB_STATUS 0x03 267 #define QLW_IOCB_MARKER 0x04 268 269 struct qlw_iocb_req0 { 270 struct qlw_iocb_hdr hdr; /* QLW_IOCB_REQ_TYPE0 */ 271 272 u_int32_t handle; 273 u_int16_t device; 274 u_int16_t ccblen; 275 u_int16_t flags; 276 u_int16_t reserved; 277 u_int16_t timeout; 278 u_int16_t seg_count; 279 u_int8_t cdb[12]; 280 struct qlw_iocb_seg segs[4]; 281 } __packed; 282 283 struct qlw_iocb_cont0 { 284 struct qlw_iocb_hdr hdr; /* QLW_IOCB_CONT_TYPE_0 */ 285 286 u_int32_t reserved; 287 struct qlw_iocb_seg segs[7]; 288 } __packed; 289 290 struct qlw_iocb_status { 291 struct qlw_iocb_hdr hdr; 292 293 u_int32_t handle; 294 u_int16_t scsi_status; 295 u_int16_t completion; 296 u_int16_t state_flags; 297 u_int16_t status_flags; 298 u_int16_t rsp_len; 299 u_int16_t sense_len; 300 u_int32_t resid; 301 u_int8_t fcp_rsp[8]; 302 u_int8_t sense_data[32]; 303 } __packed; 304 305 /* completion */ 306 #define QLW_IOCB_STATUS_COMPLETE 0x0000 307 #define QLW_IOCB_STATUS_INCOMPLETE 0x0001 308 #define QLW_IOCB_STATUS_DMA_ERROR 0x0002 309 #define QLW_IOCB_STATUS_RESET 0x0004 310 #define QLW_IOCB_STATUS_ABORTED 0x0005 311 #define QLW_IOCB_STATUS_TIMEOUT 0x0006 312 #define QLW_IOCB_STATUS_DATA_OVERRUN 0x0007 313 #define QLW_IOCB_STATUS_DATA_UNDERRUN 0x0015 314 #define QLW_IOCB_STATUS_QUEUE_FULL 0x001c 315 #define QLW_IOCB_STATUS_WIDE_FAILED 0x001f 316 #define QLW_IOCB_STATUS_SYNCXFER_FAILED 0x0020 317 318 #define QLW_STATE_GOT_BUS 0x0100 319 #define QLW_STATE_GOT_TARGET 0x0200 320 321 #define QLW_SCSI_STATUS_SENSE_VALID 0x0200 322 323 struct qlw_iocb_marker { 324 struct qlw_iocb_hdr hdr; /* QLW_IOCB_MARKER */ 325 326 u_int32_t handle; 327 u_int16_t device; 328 u_int16_t modifier; 329 u_int8_t reserved2[52]; 330 331 } __packed; 332 333 #define QLW_IOCB_MARKER_SYNC_ALL 2 334