1 /* $NetBSD: armreg.h,v 1.111 2016/05/17 08:27:24 msaitoh Exp $ */
2
3 /*
4 * Copyright (c) 1998, 2001 Ben Harris
5 * Copyright (c) 1994-1996 Mark Brinicombe.
6 * Copyright (c) 1994 Brini.
7 * All rights reserved.
8 *
9 * This code is derived from software written for Brini by Mark Brinicombe
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by Brini.
22 * 4. The name of the company nor the name of the author may be used to
23 * endorse or promote products derived from this software without specific
24 * prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 */
38
39 #ifndef _ARM_ARMREG_H
40 #define _ARM_ARMREG_H
41
42 /*
43 * ARM Process Status Register
44 *
45 * The picture in the ARM manuals looks like this:
46 * 3 3 2 2 2 2
47 * 1 0 9 8 7 6 8 7 6 5 4 0
48 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+
49 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M|
50 * | | | | | | | | | |4 3 2 1 0|
51 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+
52 */
53
54 #define PSR_FLAGS 0xf0000000 /* flags */
55 #define PSR_N_bit (1 << 31) /* negative */
56 #define PSR_Z_bit (1 << 30) /* zero */
57 #define PSR_C_bit (1 << 29) /* carry */
58 #define PSR_V_bit (1 << 28) /* overflow */
59
60 #define PSR_Q_bit (1 << 27) /* saturation */
61 #define PSR_IT1_bit (1 << 26)
62 #define PSR_IT0_bit (1 << 25)
63 #define PSR_J_bit (1 << 24) /* Jazelle mode */
64 #define PSR_GE_bits (15 << 16) /* SIMD GE bits */
65 #define PSR_IT7_bit (1 << 15)
66 #define PSR_IT6_bit (1 << 14)
67 #define PSR_IT5_bit (1 << 13)
68 #define PSR_IT4_bit (1 << 12)
69 #define PSR_IT3_bit (1 << 11)
70 #define PSR_IT2_bit (1 << 10)
71 #define PSR_E_BIT (1 << 9) /* Endian state */
72 #define PSR_A_BIT (1 << 8) /* Async abort disable */
73
74 #define I32_bit (1 << 7) /* IRQ disable */
75 #define F32_bit (1 << 6) /* FIQ disable */
76 #define IF32_bits (3 << 6) /* IRQ/FIQ disable */
77
78 #define PSR_T_bit (1 << 5) /* Thumb state */
79
80 #define PSR_MODE 0x0000001f /* mode mask */
81 #define PSR_USR26_MODE 0x00000000
82 #define PSR_FIQ26_MODE 0x00000001
83 #define PSR_IRQ26_MODE 0x00000002
84 #define PSR_SVC26_MODE 0x00000003
85 #define PSR_USR32_MODE 0x00000010
86 #define PSR_FIQ32_MODE 0x00000011
87 #define PSR_IRQ32_MODE 0x00000012
88 #define PSR_SVC32_MODE 0x00000013
89 #define PSR_MON32_MODE 0x00000016
90 #define PSR_ABT32_MODE 0x00000017
91 #define PSR_HYP32_MODE 0x0000001a
92 #define PSR_UND32_MODE 0x0000001b
93 #define PSR_SYS32_MODE 0x0000001f
94 #define PSR_32_MODE 0x00000010
95
96 #define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */
97 #define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE)
98
99 /* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */
100
101 #define R15_MODE 0x00000003
102 #define R15_MODE_USR 0x00000000
103 #define R15_MODE_FIQ 0x00000001
104 #define R15_MODE_IRQ 0x00000002
105 #define R15_MODE_SVC 0x00000003
106
107 #define R15_PC 0x03fffffc
108
109 #define R15_FIQ_DISABLE 0x04000000
110 #define R15_IRQ_DISABLE 0x08000000
111
112 #define R15_FLAGS 0xf0000000
113 #define R15_FLAG_N 0x80000000
114 #define R15_FLAG_Z 0x40000000
115 #define R15_FLAG_C 0x20000000
116 #define R15_FLAG_V 0x10000000
117
118 /*
119 * Co-processor 15: The system control co-processor.
120 */
121
122 #define ARM_CP15_CPU_ID 0
123
124 /*
125 * The CPU ID register is theoretically structured, but the definitions of
126 * the fields keep changing.
127 */
128
129 /* The high-order byte is always the implementor */
130 #define CPU_ID_IMPLEMENTOR_MASK 0xff000000
131 #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */
132 #define CPU_ID_DEC 0x44000000 /* 'D' */
133 #define CPU_ID_INTEL 0x69000000 /* 'i' */
134 #define CPU_ID_TI 0x54000000 /* 'T' */
135 #define CPU_ID_MARVELL 0x56000000 /* 'V' */
136 #define CPU_ID_FARADAY 0x66000000 /* 'f' */
137
138 /* How to decide what format the CPUID is in. */
139 #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000)
140 #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000)
141 #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x))
142
143 /* On ARM3 and ARM6, this byte holds the foundry ID. */
144 #define CPU_ID_FOUNDRY_MASK 0x00ff0000
145 #define CPU_ID_FOUNDRY_VLSI 0x00560000
146
147 /* On ARM7 it holds the architecture and variant (sub-model) */
148 #define CPU_ID_7ARCH_MASK 0x00800000
149 #define CPU_ID_7ARCH_V3 0x00000000
150 #define CPU_ID_7ARCH_V4T 0x00800000
151 #define CPU_ID_7VARIANT_MASK 0x007f0000
152
153 /* On more recent ARMs, it does the same, but in a different format */
154 #define CPU_ID_ARCH_MASK 0x000f0000
155 #define CPU_ID_ARCH_V3 0x00000000
156 #define CPU_ID_ARCH_V4 0x00010000
157 #define CPU_ID_ARCH_V4T 0x00020000
158 #define CPU_ID_ARCH_V5 0x00030000
159 #define CPU_ID_ARCH_V5T 0x00040000
160 #define CPU_ID_ARCH_V5TE 0x00050000
161 #define CPU_ID_ARCH_V5TEJ 0x00060000
162 #define CPU_ID_ARCH_V6 0x00070000
163 #define CPU_ID_VARIANT_MASK 0x00f00000
164
165 /* Next three nybbles are part number */
166 #define CPU_ID_PARTNO_MASK 0x0000fff0
167
168 /* Intel XScale has sub fields in part number */
169 #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */
170 #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */
171 #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */
172
173 /* And finally, the revision number. */
174 #define CPU_ID_REVISION_MASK 0x0000000f
175
176 /* Individual CPUs are probably best IDed by everything but the revision. */
177 #define CPU_ID_CPU_MASK 0xfffffff0
178
179 /* Fake CPU IDs for ARMs without CP15 */
180 #define CPU_ID_ARM2 0x41560200
181 #define CPU_ID_ARM250 0x41560250
182
183 /* Pre-ARM7 CPUs -- [15:12] == 0 */
184 #define CPU_ID_ARM3 0x41560300
185 #define CPU_ID_ARM600 0x41560600
186 #define CPU_ID_ARM610 0x41560610
187 #define CPU_ID_ARM620 0x41560620
188
189 /* ARM7 CPUs -- [15:12] == 7 */
190 #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */
191 #define CPU_ID_ARM710 0x41007100
192 #define CPU_ID_ARM7500 0x41027100
193 #define CPU_ID_ARM710A 0x41067100
194 #define CPU_ID_ARM7500FE 0x41077100
195 #define CPU_ID_ARM710T 0x41807100
196 #define CPU_ID_ARM720T 0x41807200
197 #define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */
198 #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */
199
200 /* Post-ARM7 CPUs */
201 #define CPU_ID_ARM810 0x41018100
202 #define CPU_ID_ARM920T 0x41129200
203 #define CPU_ID_ARM922T 0x41029220
204 #define CPU_ID_ARM926EJS 0x41069260
205 #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */
206 #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */
207 #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */
208 #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */
209 #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */
210 #define CPU_ID_ARM1022ES 0x4105a220
211 #define CPU_ID_ARM1026EJS 0x4106a260
212 #define CPU_ID_ARM11MPCORE 0x410fb020
213 #define CPU_ID_ARM1136JS 0x4107b360
214 #define CPU_ID_ARM1136JSR1 0x4117b360
215 #define CPU_ID_ARM1156T2S 0x4107b560 /* MPU only */
216 #define CPU_ID_ARM1176JZS 0x410fb760
217 #define CPU_ID_ARM11_P(n) ((n & 0xff07f000) == 0x4107b000)
218 #define CPU_ID_CORTEXA5R0 0x410fc050
219 #define CPU_ID_CORTEXA7R0 0x410fc070
220 #define CPU_ID_CORTEXA8R1 0x411fc080
221 #define CPU_ID_CORTEXA8R2 0x412fc080
222 #define CPU_ID_CORTEXA8R3 0x413fc080
223 #define CPU_ID_CORTEXA9R1 0x411fc090
224 #define CPU_ID_CORTEXA9R2 0x412fc090
225 #define CPU_ID_CORTEXA9R3 0x413fc090
226 #define CPU_ID_CORTEXA9R4 0x414fc090
227 #define CPU_ID_CORTEXA15R2 0x412fc0f0
228 #define CPU_ID_CORTEXA15R3 0x413fc0f0
229 #define CPU_ID_CORTEXA17R1 0x411fc0e0
230 #define CPU_ID_CORTEXA53R0 0x410fd030
231 #define CPU_ID_CORTEXA57R0 0x410fd070
232 #define CPU_ID_CORTEXA57R1 0x411fd070
233 #define CPU_ID_CORTEXA72R0 0x410fd080
234
235 #define CPU_ID_CORTEX_P(n) ((n & 0xff0fe000) == 0x410fc000)
236 #define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050)
237 #define CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070)
238 #define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080)
239 #define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090)
240 #define CPU_ID_CORTEX_A15_P(n) ((n & 0xff0ff0f0) == 0x410fc0f0)
241 #define CPU_ID_CORTEX_A53_P(n) ((n & 0xff0ff0f0) == 0x410fd030)
242 #define CPU_ID_CORTEX_A57_P(n) ((n & 0xff0ff0f0) == 0x410fd070)
243 #define CPU_ID_CORTEX_A72_P(n) ((n & 0xff0ff0f0) == 0x410fd080)
244 #define CPU_ID_SA110 0x4401a100
245 #define CPU_ID_SA1100 0x4401a110
246 #define CPU_ID_TI925T 0x54029250
247 #define CPU_ID_MV88FR571_VD 0x56155710
248 #define CPU_ID_MV88SV131 0x56251310
249 #define CPU_ID_FA526 0x66015260
250 #define CPU_ID_SA1110 0x6901b110
251 #define CPU_ID_IXP1200 0x6901c120
252 #define CPU_ID_80200 0x69052000
253 #define CPU_ID_PXA250 0x69052100 /* sans core revision */
254 #define CPU_ID_PXA210 0x69052120
255 #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */
256 #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */
257 #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */
258 #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */
259 #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */
260 #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */
261 #define CPU_ID_PXA27X 0x69054110
262 #define CPU_ID_80321_400 0x69052420
263 #define CPU_ID_80321_600 0x69052430
264 #define CPU_ID_80321_400_B0 0x69052c20
265 #define CPU_ID_80321_600_B0 0x69052c30
266 #define CPU_ID_80219_400 0x69052e20
267 #define CPU_ID_80219_600 0x69052e30
268 #define CPU_ID_IXP425_533 0x690541c0
269 #define CPU_ID_IXP425_400 0x690541d0
270 #define CPU_ID_IXP425_266 0x690541f0
271 #define CPU_ID_MV88SV58XX_P(n) ((n & 0xff0fff00) == 0x560f5800)
272 #define CPU_ID_MV88SV581X_V6 0x560f5810 /* Marvell Sheeva 88SV581x v6 Core */
273 #define CPU_ID_MV88SV581X_V7 0x561f5810 /* Marvell Sheeva 88SV581x v7 Core */
274 #define CPU_ID_MV88SV584X_V6 0x561f5840 /* Marvell Sheeva 88SV584x v6 Core */
275 #define CPU_ID_MV88SV584X_V7 0x562f5840 /* Marvell Sheeva 88SV584x v7 Core */
276 /* Marvell's CPUIDs with ARM ID in implementor field */
277 #define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */
278 #define CPU_ID_ARM_88SV581X_V7 0x413fc080 /* Marvell Sheeva 88SV581x v7 Core */
279 #define CPU_ID_ARM_88SV584X_V6 0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */
280
281 /* CPUID registers */
282 #define ARM_ISA3_SYNCHPRIM_MASK 0x0000f000
283 #define ARM_ISA4_SYNCHPRIM_MASK 0x00f00000
284 #define ARM_ISA3_SYNCHPRIM_LDREX 0x10 // LDREX
285 #define ARM_ISA3_SYNCHPRIM_LDREXPLUS 0x13 // +CLREX/LDREXB/LDREXH
286 #define ARM_ISA3_SYNCHPRIM_LDREXD 0x20 // +LDREXD
287 #define ARM_PFR0_THUMBEE_MASK 0x0000f000
288 #define ARM_PFR1_GTIMER_MASK 0x000f0000
289 #define ARM_PFR1_VIRT_MASK 0x0000f000
290 #define ARM_PFR1_SEC_MASK 0x000000f0
291
292 /* Media and VFP Feature registers */
293 #define ARM_MVFR0_ROUNDING_MASK 0xf0000000
294 #define ARM_MVFR0_SHORTVEC_MASK 0x0f000000
295 #define ARM_MVFR0_SQRT_MASK 0x00f00000
296 #define ARM_MVFR0_DIVIDE_MASK 0x000f0000
297 #define ARM_MVFR0_EXCEPT_MASK 0x0000f000
298 #define ARM_MVFR0_DFLOAT_MASK 0x00000f00
299 #define ARM_MVFR0_SFLOAT_MASK 0x000000f0
300 #define ARM_MVFR0_ASIMD_MASK 0x0000000f
301 #define ARM_MVFR1_ASIMD_FMACS_MASK 0xf0000000
302 #define ARM_MVFR1_VFP_HPFP_MASK 0x0f000000
303 #define ARM_MVFR1_ASIMD_HPFP_MASK 0x00f00000
304 #define ARM_MVFR1_ASIMD_SPFP_MASK 0x000f0000
305 #define ARM_MVFR1_ASIMD_INT_MASK 0x0000f000
306 #define ARM_MVFR1_ASIMD_LDST_MASK 0x00000f00
307 #define ARM_MVFR1_D_NAN_MASK 0x000000f0
308 #define ARM_MVFR1_FTZ_MASK 0x0000000f
309
310 /* ARM3-specific coprocessor 15 registers */
311 #define ARM3_CP15_FLUSH 1
312 #define ARM3_CP15_CONTROL 2
313 #define ARM3_CP15_CACHEABLE 3
314 #define ARM3_CP15_UPDATEABLE 4
315 #define ARM3_CP15_DISRUPTIVE 5
316
317 /* ARM3 Control register bits */
318 #define ARM3_CTL_CACHE_ON 0x00000001
319 #define ARM3_CTL_SHARED 0x00000002
320 #define ARM3_CTL_MONITOR 0x00000004
321
322 /*
323 * Post-ARM3 CP15 registers:
324 *
325 * 1 Control register
326 *
327 * 2 Translation Table Base
328 *
329 * 3 Domain Access Control
330 *
331 * 4 Reserved
332 *
333 * 5 Fault Status
334 *
335 * 6 Fault Address
336 *
337 * 7 Cache/write-buffer Control
338 *
339 * 8 TLB Control
340 *
341 * 9 Cache Lockdown
342 *
343 * 10 TLB Lockdown
344 *
345 * 11 Reserved
346 *
347 * 12 Reserved
348 *
349 * 13 Process ID (for FCSE)
350 *
351 * 14 Reserved
352 *
353 * 15 Implementation Dependent
354 */
355
356 /* Some of the definitions below need cleaning up for V3/V4 architectures */
357
358 /* CPU control register (CP15 register 1) */
359 #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */
360 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
361 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */
362 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
363 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
364 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
365 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
366 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
367 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
368 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */
369 #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */
370 #define CPU_CONTROL_SWP_ENABLE 0x00000400 /* SW: SWP{B} perform normally. */
371 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
372 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */
373 #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */
374 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */
375 #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
376 #define CPU_CONTROL_HA_ENABLE 0x00020000 /* HA: Hardware Access flag enable */
377 #define CPU_CONTROL_WXN_ENABLE 0x00080000 /* WXN: Write Execute Never */
378 #define CPU_CONTROL_UWXN_ENABLE 0x00100000 /* UWXN: User Write eXecute Never */
379 #define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */
380 #define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */
381 #define CPU_CONTROL_XP_ENABLE 0x00800000 /* XP: extended page table */
382 #define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */
383 #define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */
384 #define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */
385 #define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: */
386 #define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access flag enable */
387 #define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */
388
389 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
390
391 /* ARMv6/ARMv7 Co-Processor Access Control Register (CP15, 0, c1, c0, 2) */
392 #define CPACR_V7_ASEDIS 0x80000000 /* Disable Advanced SIMD Ext. */
393 #define CPACR_V7_D32DIS 0x40000000 /* Disable VFP regs 15-31 */
394 #define CPACR_CPn(n) (3 << (2*n))
395 #define CPACR_NOACCESS 0 /* reset value */
396 #define CPACR_PRIVED 1 /* Privileged mode access */
397 #define CPACR_RESERVED 2
398 #define CPACR_ALL 3 /* Privileged and User mode access */
399
400 /* ARMv6/ARMv7 Non-Secure Access Control Register (CP15, 0, c1, c1, 2) */
401 #define NSACR_SMP 0x00040000 /* ACTRL.SMP is writeable (!A8) */
402 #define NSACR_L2ERR 0x00020000 /* L2ECTRL is writeable (!A8) */
403 #define NSACR_ASEDIS 0x00008000 /* Deny Advanced SIMD Ext. */
404 #define NSACR_D32DIS 0x00004000 /* Deny VFP regs 15-31 */
405 #define NSACR_CPn(n) (1 << (n)) /* NonSecure access allowed */
406
407 /* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */
408 #define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */
409 #define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */
410 #define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */
411 #define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */
412 #define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */
413 #define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */
414 #define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */
415 #define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */
416
417 /* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */
418 #define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */
419 /* This is an undocumented flag
420 * used to work around a cache bug
421 * in r0 steppings. See errata
422 * 364296.
423 */
424 /* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */
425 #define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */
426 #define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */
427 #define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */
428 #define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */
429
430 /* XScale Auxiliary Control Register (CP15 register 1, opcode2 1) */
431 #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */
432 #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */
433 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */
434 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */
435 #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */
436 #define XSCALE_AUXCTL_MD_MASK 0x00000030
437
438 /* ARM11 MPCore Auxiliary Control Register (CP15 register 1, opcode2 1) */
439 #define MPCORE_AUXCTL_RS 0x00000001 /* return stack */
440 #define MPCORE_AUXCTL_DB 0x00000002 /* dynamic branch prediction */
441 #define MPCORE_AUXCTL_SB 0x00000004 /* static branch prediction */
442 #define MPCORE_AUXCTL_F 0x00000008 /* instruction folding enable */
443 #define MPCORE_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */
444 #define MPCORE_AUXCTL_SA 0x00000020 /* SMP/AMP */
445
446 /* Marvell PJ4B Auxillary Control Register (CP15.0.R1.c0.1) */
447 #define PJ4B_AUXCTL_FW __BIT(0) /* Cache and TLB updates broadcast */
448 #define PJ4B_AUXCTL_SMPNAMP __BIT(6) /* 0 = AMP, 1 = SMP */
449 #define PJ4B_AUXCTL_L1PARITY __BIT(9) /* L1 parity checking */
450
451 /* Marvell PJ4B Auxialiary Function Modes Control 0 (CP15.1.R15.c2.0) */
452 #define PJ4B_AUXFMC0_L2EN __BIT(0) /* Tightly-Coupled L2 cache enable */
453 #define PJ4B_AUXFMC0_SMPNAMP __BIT(1) /* 0 = AMP, 1 = SMP */
454 #define PJ4B_AUXFMC0_L1PARITY __BIT(2) /* alias of PJ4B_AUXCTL_L1PARITY */
455 #define PJ4B_AUXFMC0_DCSLFD __BIT(2) /* Disable DC Speculative linefill */
456 #define PJ4B_AUXFMC0_FW __BIT(8) /* alias of PJ4B_AUXCTL_FW*/
457
458 /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */
459 #define CORTEXA9_AUXCTL_FW 0x00000001 /* Cache and TLB updates broadcast */
460 #define CORTEXA9_AUXCTL_L2PE 0x00000002 /* Prefetch hint enable */
461 #define CORTEXA9_AUXCTL_L1PE 0x00000004 /* Data prefetch hint enable */
462 #define CORTEXA9_AUXCTL_WR_ZERO 0x00000008 /* Ena. write full line of 0s mode */
463 #define CORTEXA9_AUXCTL_SMP 0x00000040 /* Coherency is active */
464 #define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache bit */
465 #define CORTEXA9_AUXCTL_ONEWAY 0x00000100 /* Allocate in on cache way only */
466 #define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Support parity checking */
467
468 /* Cortex-A15 Auxiliary Control Register (CP15 register 1, opcode 1) */
469 #define CORTEXA15_ACTLR_BTB __BIT(0) /* Cache and TLB updates broadcast */
470 #define CORTEXA15_ACTLR_SMP __BIT(6) /* SMP */
471 #define CORTEXA15_ACTLR_IOBEU __BIT(15) /* In order issue in Branch Exec Unit */
472
473 /* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */
474 #define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */
475 #define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */
476 #define FC_WR_ALLOC_EN 0x10000000 /* Enable Write Allocate */
477 #define FC_L2_PREF_DIS 0x01000000 /* L2 Cache Prefetch Disable */
478 #define FC_L2_INV_EVICT_LINE 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */
479 #define FC_L2CACHE_EN 0x00400000 /* L2 enable */
480 #define FC_ICACHE_REPL_LOCK 0x00080000 /* Replace ICache Lock */
481 #define FC_GLOB_HIST_REG_EN 0x00040000 /* Branch Global History Register Enable */
482 #define FC_BRANCH_TARG_BUF_DIS 0x00020000 /* Branch Target Buffer Disable */
483 #define FC_L1_PAR_ERR_EN 0x00010000 /* L1 Parity Error Enable */
484
485 /* Cache type register definitions 0 */
486 #define CPU_CT_FORMAT(x) (((x) >> 29) & 0x7) /* reg format */
487 #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */
488 #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */
489 #define CPU_CT_S (1U << 24) /* split cache */
490 #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */
491
492 #define CPU_CT_CTYPE_WT 0 /* write-through */
493 #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */
494 #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */
495 #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */
496 #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */
497 #define CPU_CT_CTYPE_WB14 14 /* w/b, cp15,7, lockdown fmt C */
498
499 #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */
500 #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */
501 #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */
502 #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */
503 #define CPU_CT_xSIZE_P (1U << 11) /* need to page-color */
504
505 /* format 4 definitions */
506 #define CPU_CT4_ILINE(x) ((x) & 0xf) /* I$ line size */
507 #define CPU_CT4_DLINE(x) (((x) >> 16) & 0xf) /* D$ line size */
508 #define CPU_CT4_L1IPOLICY(x) (((x) >> 14) & 0x3) /* I$ policy */
509 #define CPU_CT4_L1_AIVIVT 1 /* ASID tagged VIVT */
510 #define CPU_CT4_L1_VIPT 2 /* VIPT */
511 #define CPU_CT4_L1_PIPT 3 /* PIPT */
512 #define CPU_CT4_ERG(x) (((x) >> 20) & 0xf) /* Cache WriteBack Granule */
513 #define CPU_CT4_CWG(x) (((x) >> 24) & 0xf) /* Exclusive Resv. Granule */
514
515 /* Cache size identifaction register definitions 1, Rd, c0, c0, 0 */
516 #define CPU_CSID_CTYPE_WT 0x80000000 /* write-through avail */
517 #define CPU_CSID_CTYPE_WB 0x40000000 /* write-back avail */
518 #define CPU_CSID_CTYPE_RA 0x20000000 /* read-allocation avail */
519 #define CPU_CSID_CTYPE_WA 0x10000000 /* write-allocation avail */
520 #define CPU_CSID_NUMSETS(x) (((x) >> 13) & 0x7fff)
521 #define CPU_CSID_ASSOC(x) (((x) >> 3) & 0x1ff)
522 #define CPU_CSID_LEN(x) ((x) & 0x07)
523
524 /* Cache size selection register definitions 2, Rd, c0, c0, 0 */
525 #define CPU_CSSR_L2 0x00000002
526 #define CPU_CSSR_L1 0x00000000
527 #define CPU_CSSR_InD 0x00000001
528
529 /* ARMv7A CP15 Global Timer definitions */
530 #define CNTKCTL_PL0PTEN 0x00000200 /* PL0 Physical Timer Enable */
531 #define CNTKCTL_PL0VTEN 0x00000100 /* PL0 Virtual Timer Enable */
532 #define CNTKCTL_EVNTI 0x000000f0 /* CNTVCT Event Bit Select */
533 #define CNTKCTL_EVNTDIR 0x00000008 /* CNTVCT Event Dir (1->0) */
534 #define CNTKCTL_EVNTEN 0x00000004 /* CNTVCT Event Enable */
535 #define CNTKCTL_PL0PCTEN 0x00000200 /* PL0 Physical Counter Enable */
536 #define CNTKCTL_PL0VCTEN 0x00000100 /* PL0 Virtual Counter Enable */
537
538 #define CNT_CTL_ISTATUS 0x00000004 /* Timer is asserted */
539 #define CNT_CTL_IMASK 0x00000002 /* Timer output is masked */
540 #define CNT_CTL_ENABLE 0x00000001 /* Timer is enabled */
541
542 /* Fault status register definitions */
543
544 #define FAULT_TYPE_MASK 0x0f
545 #define FAULT_USER 0x10
546
547 #define FAULT_WRTBUF_0 0x00 /* Vector Exception */
548 #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */
549 #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */
550 #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */
551 #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */
552 #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */
553 #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */
554 #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */
555 #define FAULT_ALIGN_0 0x01 /* Alignment */
556 #define FAULT_ALIGN_1 0x03 /* Alignment */
557 #define FAULT_TRANS_S 0x05 /* Translation -- Section */
558 #define FAULT_TRANS_P 0x07 /* Translation -- Page */
559 #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */
560 #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */
561 #define FAULT_PERM_S 0x0d /* Permission -- Section */
562 #define FAULT_PERM_P 0x0f /* Permission -- Page */
563
564 #define FAULT_LPAE 0x0200 /* (SW) used long descriptors */
565 #define FAULT_IMPRECISE 0x0400 /* Imprecise exception (XSCALE) */
566 #define FAULT_WRITE 0x0800 /* fault was due to write (ARMv6+) */
567 #define FAULT_EXT 0x1000 /* fault was due to external abort (ARMv6+) */
568 #define FAULT_CM 0x2000 /* fault was due to cache maintenance (ARMv7+) */
569
570 /*
571 * Address of the vector page, low and high versions.
572 */
573 #define ARM_VECTORS_LOW 0x00000000U
574 #define ARM_VECTORS_HIGH 0xffff0000U
575
576 /*
577 * ARM Instructions
578 *
579 * 3 3 2 2 2
580 * 1 0 9 8 7 0
581 * +-------+-------------------------------------------------------+
582 * | cond | instruction dependent |
583 * |c c c c| |
584 * +-------+-------------------------------------------------------+
585 */
586
587 #define INSN_SIZE 4 /* Always 4 bytes */
588 #define INSN_COND_MASK 0xf0000000 /* Condition mask */
589 #define INSN_COND_EQ 0 /* Z == 1 */
590 #define INSN_COND_NE 1 /* Z == 0 */
591 #define INSN_COND_CS 2 /* C == 1 */
592 #define INSN_COND_CC 3 /* C == 0 */
593 #define INSN_COND_MI 4 /* N == 1 */
594 #define INSN_COND_PL 5 /* N == 0 */
595 #define INSN_COND_VS 6 /* V == 1 */
596 #define INSN_COND_VC 7 /* V == 0 */
597 #define INSN_COND_HI 8 /* C == 1 && Z == 0 */
598 #define INSN_COND_LS 9 /* C == 0 || Z == 1 */
599 #define INSN_COND_GE 10 /* N == V */
600 #define INSN_COND_LT 11 /* N != V */
601 #define INSN_COND_GT 12 /* Z == 0 && N == V */
602 #define INSN_COND_LE 13 /* Z == 1 || N != V */
603 #define INSN_COND_AL 14 /* Always condition */
604
605 #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */
606
607 /*
608 * Defines and such for arm11 Performance Monitor Counters (p15, c15, c12, 0)
609 */
610 #define ARM11_PMCCTL_E __BIT(0) /* enable all three counters */
611 #define ARM11_PMCCTL_P __BIT(1) /* reset both Count Registers to zero */
612 #define ARM11_PMCCTL_C __BIT(2) /* reset the Cycle Counter Register to zero */
613 #define ARM11_PMCCTL_D __BIT(3) /* cycle count divide by 64 */
614 #define ARM11_PMCCTL_EC0 __BIT(4) /* Enable Counter Register 0 interrupt */
615 #define ARM11_PMCCTL_EC1 __BIT(5) /* Enable Counter Register 1 interrupt */
616 #define ARM11_PMCCTL_ECC __BIT(6) /* Enable Cycle Counter interrupt */
617 #define ARM11_PMCCTL_SBZa __BIT(7) /* UNP/SBZ */
618 #define ARM11_PMCCTL_CR0 __BIT(8) /* Count Register 0 overflow flag */
619 #define ARM11_PMCCTL_CR1 __BIT(9) /* Count Register 1 overflow flag */
620 #define ARM11_PMCCTL_CCR __BIT(10) /* Cycle Count Register overflow flag */
621 #define ARM11_PMCCTL_X __BIT(11) /* Enable Export of the events to the event bus */
622 #define ARM11_PMCCTL_EVT1 __BITS(19,12) /* source of events for Count Register 1 */
623 #define ARM11_PMCCTL_EVT0 __BITS(27,20) /* source of events for Count Register 0 */
624 #define ARM11_PMCCTL_SBZb __BITS(31,28) /* UNP/SBZ */
625 #define ARM11_PMCCTL_SBZ \
626 (ARM11_PMCCTL_SBZa | ARM11_PMCCTL_SBZb)
627
628 #define ARM11_PMCEVT_ICACHE_MISS 0 /* Instruction Cache Miss */
629 #define ARM11_PMCEVT_ISTREAM_STALL 1 /* Instruction Stream Stall */
630 #define ARM11_PMCEVT_IUTLB_MISS 2 /* Instruction uTLB Miss */
631 #define ARM11_PMCEVT_DUTLB_MISS 3 /* Data uTLB Miss */
632 #define ARM11_PMCEVT_BRANCH 4 /* Branch Inst. Executed */
633 #define ARM11_PMCEVT_BRANCH_MISS 6 /* Branch mispredicted */
634 #define ARM11_PMCEVT_INST_EXEC 7 /* Instruction Executed */
635 #define ARM11_PMCEVT_DCACHE_ACCESS0 9 /* Data Cache Access */
636 #define ARM11_PMCEVT_DCACHE_ACCESS1 10 /* Data Cache Access */
637 #define ARM11_PMCEVT_DCACHE_MISS 11 /* Data Cache Miss */
638 #define ARM11_PMCEVT_DCACHE_WRITEBACK 12 /* Data Cache Writeback */
639 #define ARM11_PMCEVT_PC_CHANGE 13 /* Software PC change */
640 #define ARM11_PMCEVT_TLB_MISS 15 /* Main TLB Miss */
641 #define ARM11_PMCEVT_DATA_ACCESS 16 /* non-cached data access */
642 #define ARM11_PMCEVT_LSU_STALL 17 /* Load/Store Unit stall */
643 #define ARM11_PMCEVT_WBUF_DRAIN 18 /* Write buffer drained */
644 #define ARM11_PMCEVT_ETMEXTOUT0 32 /* ETMEXTOUT[0] asserted */
645 #define ARM11_PMCEVT_ETMEXTOUT1 33 /* ETMEXTOUT[1] asserted */
646 #define ARM11_PMCEVT_ETMEXTOUT 34 /* ETMEXTOUT[0 & 1] */
647 #define ARM11_PMCEVT_CALL_EXEC 35 /* Procedure call executed */
648 #define ARM11_PMCEVT_RETURN_EXEC 36 /* Return executed */
649 #define ARM11_PMCEVT_RETURN_HIT 37 /* return address predicted */
650 #define ARM11_PMCEVT_RETURN_MISS 38 /* return addr. mispredicted */
651 #define ARM11_PMCEVT_CYCLE 255 /* Increment each cycle */
652
653 /* Defines for ARM CORTEX performance counters */
654 #define CORTEX_CNTENS_C __BIT(31) /* Enables the cycle counter */
655 #define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */
656 #define CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */
657
658 /* Defines for ARM Cortex A7/A15 L2CTRL */
659 #define L2CTRL_NUMCPU __BITS(25,24) // numcpus - 1
660 #define L2CTRL_ICPRES __BIT(23) // Interrupt Controller is present
661
662 /* Translation Table Base Register */
663 #define TTBR_C __BIT(0) /* without MPE */
664 #define TTBR_S __BIT(1)
665 #define TTBR_IMP __BIT(2)
666 #define TTBR_RGN_MASK __BITS(4,3)
667 #define TTBR_RGN_NC __SHIFTIN(0, TTBR_RGN_MASK)
668 #define TTBR_RGN_WBWA __SHIFTIN(1, TTBR_RGN_MASK)
669 #define TTBR_RGN_WT __SHIFTIN(2, TTBR_RGN_MASK)
670 #define TTBR_RGN_WBNWA __SHIFTIN(3, TTBR_RGN_MASK)
671 #define TTBR_NOS __BIT(5)
672 #define TTBR_IRGN_MASK (__BIT(6) | __BIT(0))
673 #define TTBR_IRGN_NC 0
674 #define TTBR_IRGN_WBWA __BIT(6)
675 #define TTBR_IRGN_WT __BIT(0)
676 #define TTBR_IRGN_WBNWA (__BIT(0) | __BIT(6))
677
678 /* Translate Table Base Control Register */
679 #define TTBCR_S_EAE __BIT(31) // Extended Address Extension
680 #define TTBCR_S_PD1 __BIT(5) // Don't use TTBR1
681 #define TTBCR_S_PD0 __BIT(4) // Don't use TTBR0
682 #define TTBCR_S_N __BITS(2,0) // Width of base address in TTB0
683
684 #define TTBCR_L_EAE __BIT(31) // Extended Address Extension
685 #define TTBCR_L_SH1 __BITS(29,28) // TTBR1 Shareability
686 #define TTBCR_L_ORGN1 __BITS(27,26) // TTBR1 Outer cacheability
687 #define TTBCR_L_IRGN1 __BITS(25,24) // TTBR1 inner cacheability
688 #define TTBCR_L_EPD1 __BIT(23) // Don't use TTBR1
689 #define TTBCR_L_A1 __BIT(22) // ASID is in TTBR1
690 #define TTBCR_L_T1SZ __BITS(18,16) // TTBR1 size offset
691 #define TTBCR_L_SH0 __BITS(13,12) // TTBR0 Shareability
692 #define TTBCR_L_ORGN0 __BITS(11,10) // TTBR0 Outer cacheability
693 #define TTBCR_L_IRGN0 __BITS(9,8) // TTBR0 inner cacheability
694 #define TTBCR_L_EPD0 __BIT(7) // Don't use TTBR0
695 #define TTBCR_L_T0SZ __BITS(2,0) // TTBR0 size offset
696
697 #define NRRR_ORn(n) __BITS(17+2*(n),16+2*(n)) // Outer Cacheable mappings
698 #define NRRR_IRn(n) __BITS(1+2*(n),0+2*(n)) // Inner Cacheable mappings
699 #define NRRR_NC 0 // non-cacheable
700 #define NRRR_WB_WA 1 // write-back write-allocate
701 #define NRRR_WT 2 // write-through
702 #define NRRR_WB 3 // write-back
703 #define PRRR_NOSn(n) __BITS(24+2*(n))// Memory region is Inner Shareable
704 #define PRRR_NS1 __BIT(19) // Normal Shareable S=1 is Shareable
705 #define PRRR_NS0 __BIT(18) // Normal Shareable S=0 is Shareable
706 #define PRRR_DS1 __BIT(17) // Device Shareable S=1 is Shareable
707 #define PRRR_DS0 __BIT(16) // Device Shareable S=0 is Shareable
708 #define PRRR_TRn(n) __BITS(1+2*(n),0+2*(n))
709 #define PRRR_TR_STRONG 0 // Strongly Ordered
710 #define PRRR_TR_DEVICE 1 // Device
711 #define PRRR_TR_NORMAL 2 // Normal Memory
712
713 /* ARMv7 MPIDR, Multiprocessor Affinity Register generic format */
714 #define MPIDR_MP __BIT(31) /* 1 = Have MP Extention */
715 #define MPIDR_U __BIT(30) /* 1 = Uni-Processor System */
716 #define MPIDR_MT __BIT(24) /* 1 = SMT(AFF0 is logical) */
717 #define MPIDR_AFF2 __BITS(23,16) /* Affinity Level 2 */
718 #define MPIDR_AFF1 __BITS(15,8) /* Affinity Level 1 */
719 #define MPIDR_AFF0 __BITS(7,0) /* Affinity Level 0 */
720
721 /* MPIDR implementation of ARM Cortex A9: SMT and AFF2 is not used */
722 #define CORTEXA9_MPIDR_MP MPIDR_MP
723 #define CORTEXA9_MPIDR_U MPIDR_U
724 #define CORTEXA9_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */
725 #define CORTEXA9_MPIDR_CPUID __BITS(0,1) /* AFF0 = phisycal core id */
726
727 /* MPIDR implementation of Marvell PJ4B-MP: AFF2 is not used */
728 #define PJ4B_MPIDR_MP MPIDR_MP
729 #define PJ4B_MPIDR_U MPIDR_U
730 #define PJ4B_MPIDR_MT MPIDR_MT /* 1 = SMT(AFF0 is logical) */
731 #define PJ4B_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */
732 #define PJ4B_MPIDR_CPUID __BITS(0,3) /* AFF0 = core id */
733
734 /* Defines for ARM Generic Timer */
735 #define ARM_CNTCTL_ENABLE __BIT(0) // Timer Enabled
736 #define ARM_CNTCTL_IMASK __BIT(1) // Mask Interrupt
737 #define ARM_CNTCTL_ISTATUS __BIT(2) // Interrupt is pending
738
739 #define ARM_CNTKCTL_PL0PTEN __BIT(9)
740 #define ARM_CNTKCTL_PL0VTEN __BIT(8)
741 #define ARM_CNTKCTL_EVNTI __BITS(7,4)
742 #define ARM_CNTKCTL_EVNTDIR __BIT(3)
743 #define ARM_CNTKCTL_EVNTEN __BIT(2)
744 #define ARM_CNTKCTL_PL0PCTEN __BIT(1)
745 #define ARM_CNTKCTL_PL0VCTEN __BIT(0)
746
747 #define ARM_CNTHCTL_EVNTI __BITS(7,4)
748 #define ARM_CNTHCTL_EVNTDIR __BIT(3)
749 #define ARM_CNTHCTL_EVNTEN __BIT(2)
750 #define ARM_CNTHCTL_PL1PCTEN __BIT(1)
751 #define ARM_CNTHCTL_PL1VCTEN __BIT(0)
752
753 #define ARM_A5_TLBDATA_DOM __BITS(62,59)
754 #define ARM_A5_TLBDATA_AP __BITS(58,56)
755 #define ARM_A5_TLBDATA_NS_WALK __BIT(55)
756 #define ARM_A5_TLBDATA_NS_PAGE __BIT(54)
757 #define ARM_A5_TLBDATA_XN __BIT(53)
758 #define ARM_A5_TLBDATA_TEX __BITS(52,50)
759 #define ARM_A5_TLBDATA_B __BIT(49)
760 #define ARM_A5_TLBDATA_C __BIT(48)
761 #define ARM_A5_TLBDATA_S __BIT(47)
762 #define ARM_A5_TLBDATA_ASID __BITS(46,39)
763 #define ARM_A5_TLBDATA_SIZE __BITS(38,37)
764 #define ARM_A5_TLBDATA_SIZE_4KB 0
765 #define ARM_A5_TLBDATA_SIZE_16KB 1
766 #define ARM_A5_TLBDATA_SIZE_1MB 2
767 #define ARM_A5_TLBDATA_SIZE_16MB 3
768 #define ARM_A5_TLBDATA_VA __BITS(36,22)
769 #define ARM_A5_TLBDATA_PA __BITS(21,2)
770 #define ARM_A5_TLBDATA_nG __BIT(1)
771 #define ARM_A5_TLBDATA_VALID __BIT(0)
772
773 #define ARM_A7_TLBDATA2_S2_LEVEL __BITS(85-64,84-64)
774 #define ARM_A7_TLBDATA2_S1_SIZE __BITS(83-64,82-64)
775 #define ARM_A7_TLBDATA2_S1_SIZE_4KB 0
776 #define ARM_A7_TLBDATA2_S1_SIZE_64KB 1
777 #define ARM_A7_TLBDATA2_S1_SIZE_1MB 2
778 #define ARM_A7_TLBDATA2_S1_SIZE_16MB 3
779 #define ARM_A7_TLBDATA2_DOM __BITS(81-64,78-64)
780 #define ARM_A7_TLBDATA2_IS __BITS(77-64,76-64)
781 #define ARM_A7_TLBDATA2_IS_NC 0
782 #define ARM_A7_TLBDATA2_IS_WB_WA 1
783 #define ARM_A7_TLBDATA2_IS_WT 2
784 #define ARM_A7_TLBDATA2_IS_DSO 3
785 #define ARM_A7_TLBDATA2_S2OVR __BIT(75-64)
786 #define ARM_A7_TLBDATA2_SDO_MT __BITS(74-64,72-64)
787 #define ARM_A7_TLBDATA2_SDO_MT_D 2
788 #define ARM_A7_TLBDATA2_SDO_MT_SO 6
789 #define ARM_A7_TLBDATA2_OS __BITS(75-64,74-64)
790 #define ARM_A7_TLBDATA2_OS_NC 0
791 #define ARM_A7_TLBDATA2_OS_WB_WA 1
792 #define ARM_A7_TLBDATA2_OS_WT 2
793 #define ARM_A7_TLBDATA2_OS_WB 3
794 #define ARM_A7_TLBDATA2_SH __BITS(73-64,72-64)
795 #define ARM_A7_TLBDATA2_SH_NONE 0
796 #define ARM_A7_TLBDATA2_SH_UNUSED 1
797 #define ARM_A7_TLBDATA2_SH_OS 2
798 #define ARM_A7_TLBDATA2_SH_IS 3
799 #define ARM_A7_TLBDATA2_XN2 __BIT(71-64)
800 #define ARM_A7_TLBDATA2_XN1 __BIT(70-64)
801 #define ARM_A7_TLBDATA2_PXN __BIT(69-64)
802
803 #define ARM_A7_TLBDATA12_PA __BITS(68-32,41-32)
804
805 #define ARM_A7_TLBDATA1_NS __BIT(40-32)
806 #define ARM_A7_TLBDATA1_HAP __BITS(39-32,38-32)
807 #define ARM_A7_TLBDATA1_AP __BITS(37-32,35-32)
808 #define ARM_A7_TLBDATA1_nG __BIT(34-32)
809
810 #define ARM_A7_TLBDATA01_ASID __BITS(33,26)
811
812 #define ARM_A7_TLBDATA0_VMID __BITS(25,18)
813 #define ARM_A7_TLBDATA0_VA __BITS(17,5)
814 #define ARM_A7_TLBDATA0_NS_WALK __BIT(4)
815 #define ARM_A7_TLBDATA0_SIZE __BITS(3,1)
816 #define ARM_A7_TLBDATA0_SIZE_V7_4KB 0
817 #define ARM_A7_TLBDATA0_SIZE_LPAE_4KB 1
818 #define ARM_A7_TLBDATA0_SIZE_V7_64KB 2
819 #define ARM_A7_TLBDATA0_SIZE_LPAE_64KB 3
820 #define ARM_A7_TLBDATA0_SIZE_V7_1MB 4
821 #define ARM_A7_TLBDATA0_SIZE_LPAE_2MB 5
822 #define ARM_A7_TLBDATA0_SIZE_V7_16MB 6
823 #define ARM_A7_TLBDATA0_SIZE_LPAE_1GB 7
824
825 #define ARM_TLBDATA_VALID __BIT(0)
826
827 #define ARM_TLBDATAOP_WAY __BIT(31)
828 #define ARM_A5_TLBDATAOP_INDEX __BITS(5,0)
829 #define ARM_A7_TLBDATAOP_INDEX __BITS(6,0)
830
831 #if !defined(__ASSEMBLER__) && defined(_KERNEL)
832 static inline bool
arm_cond_ok_p(uint32_t insn,uint32_t psr)833 arm_cond_ok_p(uint32_t insn, uint32_t psr)
834 {
835 const uint32_t __cond = __SHIFTOUT(insn, INSN_COND_MASK);
836
837 bool __ok;
838 const bool __z = (psr & PSR_Z_bit);
839 const bool __n = (psr & PSR_N_bit);
840 const bool __c = (psr & PSR_C_bit);
841 const bool __v = (psr & PSR_V_bit);
842 switch (__cond & ~1) {
843 case INSN_COND_EQ: // Z == 1
844 __ok = __z;
845 break;
846 case INSN_COND_CS: // C == 1
847 __ok = __c;
848 break;
849 case INSN_COND_MI: // N == 1
850 __ok = __n;
851 break;
852 case INSN_COND_VS: // V == 1
853 __ok = __v;
854 break;
855 case INSN_COND_HI: // C == 1 && Z == 0
856 __ok = __c && !__z;
857 break;
858 case INSN_COND_GE: // N == V
859 __ok = __n == __v;
860 break;
861 case INSN_COND_GT: // N == V && Z == 0
862 __ok = __n == __v && !__z;
863 break;
864 default: /* INSN_COND_AL or unconditional */
865 return true;
866 }
867
868 return (__cond & 1) ? !__ok : __ok;
869 }
870 #endif /* !__ASSEMBLER && _KERNEL */
871
872 #if !defined(__ASSEMBLER__) && !defined(_RUMPKERNEL)
873 #define ARMREG_READ_INLINE(name, __insnstring) \
874 static inline uint32_t armreg_##name##_read(void) \
875 { \
876 uint32_t __rv; \
877 __asm __volatile("mrc " __insnstring : "=r"(__rv)); \
878 return __rv; \
879 }
880
881 #define ARMREG_WRITE_INLINE(name, __insnstring) \
882 static inline void armreg_##name##_write(uint32_t __val) \
883 { \
884 __asm __volatile("mcr " __insnstring :: "r"(__val)); \
885 }
886
887 #define ARMREG_READ_INLINE2(name, __insnstring) \
888 static inline uint32_t armreg_##name##_read(void) \
889 { \
890 uint32_t __rv; \
891 __asm __volatile(__insnstring : "=r"(__rv)); \
892 return __rv; \
893 }
894
895 #define ARMREG_WRITE_INLINE2(name, __insnstring) \
896 static inline void armreg_##name##_write(uint32_t __val) \
897 { \
898 __asm __volatile(__insnstring :: "r"(__val)); \
899 }
900
901 #define ARMREG_READ64_INLINE(name, __insnstring) \
902 static inline uint64_t armreg_##name##_read(void) \
903 { \
904 uint64_t __rv; \
905 __asm __volatile("mrrc " __insnstring : "=r"(__rv)); \
906 return __rv; \
907 }
908
909 #define ARMREG_WRITE64_INLINE(name, __insnstring) \
910 static inline void armreg_##name##_write(uint64_t __val) \
911 { \
912 __asm __volatile("mcrr " __insnstring :: "r"(__val)); \
913 }
914
915 /* cp10 registers */
916 ARMREG_READ_INLINE2(fpsid, "vmrs\t%0, fpsid") /* VFP System ID */
917 ARMREG_READ_INLINE2(fpscr, "vmrs\t%0, fpscr") /* VFP Status/Control Register */
918 ARMREG_WRITE_INLINE2(fpscr, "vmsr\tfpscr, %0") /* VFP Status/Control Register */
919 ARMREG_READ_INLINE2(mvfr1, "vmrs\t%0, mvfr1") /* Media and VFP Feature Register 1 */
920 ARMREG_READ_INLINE2(mvfr0, "vmrs\t%0, mvfr0") /* Media and VFP Feature Register 0 */
921 ARMREG_READ_INLINE2(fpexc, "vmrs\t%0, fpexc") /* VFP Exception Register */
922 ARMREG_WRITE_INLINE2(fpexc, "vmsr\tfpexc, %0") /* VFP Exception Register */
923 ARMREG_READ_INLINE2(fpinst, "fmrx\t%0, fpinst") /* VFP Exception Instruction */
924 ARMREG_WRITE_INLINE2(fpinst, "fmxr\tfpinst, %0") /* VFP Exception Instruction */
925 ARMREG_READ_INLINE2(fpinst2, "fmrx\t%0, fpinst2") /* VFP Exception Instruction 2 */
926 ARMREG_WRITE_INLINE2(fpinst2, "fmxr\tfpinst2, %0") /* VFP Exception Instruction 2 */
927
928 /* cp15 c0 registers */
929 ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */
930 ARMREG_READ_INLINE(ctr, "p15,0,%0,c0,c0,1") /* Cache Type Register */
931 ARMREG_READ_INLINE(tlbtr, "p15,0,%0,c0,c0,3") /* TLB Type Register */
932 ARMREG_READ_INLINE(mpidr, "p15,0,%0,c0,c0,5") /* Multiprocess Affinity Register */
933 ARMREG_READ_INLINE(revidr, "p15,0,%0,c0,c0,6") /* Revision ID Register */
934 ARMREG_READ_INLINE(pfr0, "p15,0,%0,c0,c1,0") /* Processor Feature Register 0 */
935 ARMREG_READ_INLINE(pfr1, "p15,0,%0,c0,c1,1") /* Processor Feature Register 1 */
936 ARMREG_READ_INLINE(mmfr0, "p15,0,%0,c0,c1,4") /* Memory Model Feature Register 0 */
937 ARMREG_READ_INLINE(mmfr1, "p15,0,%0,c0,c1,5") /* Memory Model Feature Register 1 */
938 ARMREG_READ_INLINE(mmfr2, "p15,0,%0,c0,c1,6") /* Memory Model Feature Register 2 */
939 ARMREG_READ_INLINE(mmfr3, "p15,0,%0,c0,c1,7") /* Memory Model Feature Register 3 */
940 ARMREG_READ_INLINE(isar0, "p15,0,%0,c0,c2,0") /* Instruction Set Attribute Register 0 */
941 ARMREG_READ_INLINE(isar1, "p15,0,%0,c0,c2,1") /* Instruction Set Attribute Register 1 */
942 ARMREG_READ_INLINE(isar2, "p15,0,%0,c0,c2,2") /* Instruction Set Attribute Register 2 */
943 ARMREG_READ_INLINE(isar3, "p15,0,%0,c0,c2,3") /* Instruction Set Attribute Register 3 */
944 ARMREG_READ_INLINE(isar4, "p15,0,%0,c0,c2,4") /* Instruction Set Attribute Register 4 */
945 ARMREG_READ_INLINE(isar5, "p15,0,%0,c0,c2,5") /* Instruction Set Attribute Register 5 */
946 ARMREG_READ_INLINE(ccsidr, "p15,1,%0,c0,c0,0") /* Cache Size ID Register */
947 ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */
948 ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
949 ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
950 /* cp15 c1 registers */
951 ARMREG_READ_INLINE(sctlr, "p15,0,%0,c1,c0,0") /* System Control Register */
952 ARMREG_WRITE_INLINE(sctlr, "p15,0,%0,c1,c0,0") /* System Control Register */
953 ARMREG_READ_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */
954 ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */
955 ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
956 ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
957 ARMREG_READ_INLINE(scr, "p15,0,%0,c1,c1,0") /* Secure Configuration Register */
958 ARMREG_READ_INLINE(nsacr, "p15,0,%0,c1,c1,2") /* Non-Secure Access Control Register */
959 /* cp15 c2 registers */
960 ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
961 ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
962 ARMREG_READ_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */
963 ARMREG_WRITE_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */
964 ARMREG_READ_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
965 ARMREG_WRITE_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
966 /* cp15 c3 registers */
967 ARMREG_READ_INLINE(dacr, "p15,0,%0,c3,c0,0") /* Domain Access Control Register */
968 ARMREG_WRITE_INLINE(dacr, "p15,0,%0,c3,c0,0") /* Domain Access Control Register */
969 /* cp15 c5 registers */
970 ARMREG_READ_INLINE(dfsr, "p15,0,%0,c5,c0,0") /* Data Fault Status Register */
971 ARMREG_READ_INLINE(ifsr, "p15,0,%0,c5,c0,1") /* Instruction Fault Status Register */
972 /* cp15 c6 registers */
973 ARMREG_READ_INLINE(dfar, "p15,0,%0,c6,c0,0") /* Data Fault Address Register */
974 ARMREG_READ_INLINE(ifar, "p15,0,%0,c6,c0,2") /* Instruction Fault Address Register */
975 /* cp15 c7 registers */
976 ARMREG_WRITE_INLINE(icialluis, "p15,0,%0,c7,c1,0") /* Instruction Inv All (IS) */
977 ARMREG_WRITE_INLINE(bpiallis, "p15,0,%0,c7,c1,6") /* Branch Predictor Invalidate All (IS) */
978 ARMREG_READ_INLINE(par, "p15,0,%0,c7,c4,0") /* Physical Address Register */
979 ARMREG_WRITE_INLINE(iciallu, "p15,0,%0,c7,c5,0") /* Instruction Invalidate All */
980 ARMREG_WRITE_INLINE(icimvau, "p15,0,%0,c7,c5,1") /* Instruction Invalidate MVA */
981 ARMREG_WRITE_INLINE(isb, "p15,0,%0,c7,c5,4") /* Instruction Synchronization Barrier */
982 ARMREG_WRITE_INLINE(bpiall, "p15,0,%0,c7,c5,6") /* Branch Predictor Invalidate All */
983 ARMREG_WRITE_INLINE(bpimva, "p15,0,%0,c7,c5,7") /* Branch Predictor invalidate by MVA */
984 ARMREG_WRITE_INLINE(dcimvac, "p15,0,%0,c7,c6,1") /* Data Invalidate MVA to PoC */
985 ARMREG_WRITE_INLINE(dcisw, "p15,0,%0,c7,c6,2") /* Data Invalidate Set/Way */
986 ARMREG_WRITE_INLINE(ats1cpr, "p15,0,%0,c7,c8,0") /* AddrTrans CurState PL1 Read */
987 ARMREG_WRITE_INLINE(ats1cpw, "p15,0,%0,c7,c8,1") /* AddrTrans CurState PL1 Write */
988 ARMREG_WRITE_INLINE(ats1cur, "p15,0,%0,c7,c8,2") /* AddrTrans CurState PL0 Read */
989 ARMREG_WRITE_INLINE(ats1cuw, "p15,0,%0,c7,c8,3") /* AddrTrans CurState PL0 Write */
990 ARMREG_WRITE_INLINE(dccmvac, "p15,0,%0,c7,c10,1") /* Data Clean MVA to PoC */
991 ARMREG_WRITE_INLINE(dccsw, "p15,0,%0,c7,c10,2") /* Data Clean Set/Way */
992 ARMREG_WRITE_INLINE(dsb, "p15,0,%0,c7,c10,4") /* Data Synchronization Barrier */
993 ARMREG_WRITE_INLINE(dmb, "p15,0,%0,c7,c10,5") /* Data Memory Barrier */
994 ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c11,1") /* Data Clean MVA to PoU */
995 ARMREG_WRITE_INLINE(dccimvac, "p15,0,%0,c7,c14,1") /* Data Clean&Inv MVA to PoC */
996 ARMREG_WRITE_INLINE(dccisw, "p15,0,%0,c7,c14,2") /* Data Clean&Inv Set/Way */
997 /* cp15 c8 registers */
998 ARMREG_WRITE_INLINE(tlbiallis, "p15,0,%0,c8,c3,0") /* Invalidate entire unified TLB, inner shareable */
999 ARMREG_WRITE_INLINE(tlbimvais, "p15,0,%0,c8,c3,1") /* Invalidate unified TLB by MVA, inner shareable */
1000 ARMREG_WRITE_INLINE(tlbiasidis, "p15,0,%0,c8,c3,2") /* Invalidate unified TLB by ASID, inner shareable */
1001 ARMREG_WRITE_INLINE(tlbimvaais, "p15,0,%0,c8,c3,3") /* Invalidate unified TLB by MVA, all ASID, inner shareable */
1002 ARMREG_WRITE_INLINE(itlbiall, "p15,0,%0,c8,c5,0") /* Invalidate entire instruction TLB */
1003 ARMREG_WRITE_INLINE(itlbimva, "p15,0,%0,c8,c5,1") /* Invalidate instruction TLB by MVA */
1004 ARMREG_WRITE_INLINE(itlbiasid, "p15,0,%0,c8,c5,2") /* Invalidate instruction TLB by ASID */
1005 ARMREG_WRITE_INLINE(dtlbiall, "p15,0,%0,c8,c6,0") /* Invalidate entire data TLB */
1006 ARMREG_WRITE_INLINE(dtlbimva, "p15,0,%0,c8,c6,1") /* Invalidate data TLB by MVA */
1007 ARMREG_WRITE_INLINE(dtlbiasid, "p15,0,%0,c8,c6,2") /* Invalidate data TLB by ASID */
1008 ARMREG_WRITE_INLINE(tlbiall, "p15,0,%0,c8,c7,0") /* Invalidate entire unified TLB */
1009 ARMREG_WRITE_INLINE(tlbimva, "p15,0,%0,c8,c7,1") /* Invalidate unified TLB by MVA */
1010 ARMREG_WRITE_INLINE(tlbiasid, "p15,0,%0,c8,c7,2") /* Invalidate unified TLB by ASID */
1011 ARMREG_WRITE_INLINE(tlbimvaa, "p15,0,%0,c8,c7,3") /* Invalidate unified TLB by MVA, all ASID */
1012 /* cp15 c9 registers */
1013 ARMREG_READ_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */
1014 ARMREG_WRITE_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */
1015 ARMREG_READ_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */
1016 ARMREG_WRITE_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */
1017 ARMREG_READ_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */
1018 ARMREG_WRITE_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */
1019 ARMREG_READ_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */
1020 ARMREG_WRITE_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */
1021 ARMREG_READ_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */
1022 ARMREG_WRITE_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */
1023 ARMREG_READ_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */
1024 ARMREG_WRITE_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */
1025 ARMREG_READ_INLINE(l2ctrl, "p15,1,%0,c9,c0,2") /* A7/A15 L2 Control Register */
1026 /* cp10 c10 registers */
1027 ARMREG_READ_INLINE(prrr, "p15,0,%0,c10,c2,0") /* Primary Region Remap Register */
1028 ARMREG_WRITE_INLINE(prrr, "p15,0,%0,c10,c2,0") /* Primary Region Remap Register */
1029 ARMREG_READ_INLINE(nrrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */
1030 ARMREG_WRITE_INLINE(nrrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */
1031 /* cp15 c13 registers */
1032 ARMREG_READ_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */
1033 ARMREG_WRITE_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */
1034 ARMREG_READ_INLINE(tpidrurw, "p15,0,%0,c13,c0,2") /* User read-write Thread ID Register */
1035 ARMREG_WRITE_INLINE(tpidrurw, "p15,0,%0,c13,c0,2") /* User read-write Thread ID Register */
1036 ARMREG_READ_INLINE(tpidruro, "p15,0,%0,c13,c0,3") /* User read-only Thread ID Register */
1037 ARMREG_WRITE_INLINE(tpidruro, "p15,0,%0,c13,c0,3") /* User read-only Thread ID Register */
1038 ARMREG_READ_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */
1039 ARMREG_WRITE_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */
1040 /* cp14 c12 registers */
1041 ARMREG_READ_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */
1042 ARMREG_WRITE_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */
1043 /* cp15 c14 registers */
1044 /* cp15 Global Timer Registers */
1045 ARMREG_READ_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */
1046 ARMREG_WRITE_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */
1047 ARMREG_READ_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */
1048 ARMREG_WRITE_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */
1049 ARMREG_READ_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */
1050 ARMREG_WRITE_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */
1051 ARMREG_READ_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */
1052 ARMREG_WRITE_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */
1053 ARMREG_READ_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */
1054 ARMREG_WRITE_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */
1055 ARMREG_READ_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */
1056 ARMREG_WRITE_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */
1057 ARMREG_READ64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */
1058 ARMREG_WRITE64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */
1059 ARMREG_READ64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */
1060 ARMREG_WRITE64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */
1061 ARMREG_READ64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */
1062 ARMREG_WRITE64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */
1063 ARMREG_READ64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */
1064 ARMREG_WRITE64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */
1065 /* cp15 c15 registers */
1066 ARMREG_READ_INLINE(cbar, "p15,4,%0,c15,c0,0") /* Configuration Base Address Register */
1067 ARMREG_READ_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */
1068 ARMREG_WRITE_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */
1069 ARMREG_READ_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */
1070 ARMREG_WRITE_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */
1071
1072 ARMREG_READ_INLINE(tlbdata0, "p15,3,%0,c15,c0,0") /* TLB Data Register 0 (cortex) */
1073 ARMREG_READ_INLINE(tlbdata1, "p15,3,%0,c15,c0,1") /* TLB Data Register 1 (cortex) */
1074 ARMREG_READ_INLINE(tlbdata2, "p15,3,%0,c15,c0,2") /* TLB Data Register 2 (cortex) */
1075 ARMREG_WRITE_INLINE(tlbdataop, "p15,3,%0,c15,c4,2") /* TLB Data Read Operation (cortex) */
1076
1077 ARMREG_READ_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */
1078 ARMREG_WRITE_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */
1079
1080 #endif /* !__ASSEMBLER__ */
1081
1082 #endif /* _ARM_ARMREG_H */
1083