1 /* Public Domain */ 2 3 4 /* 5 * Clocks Signals 6 */ 7 8 /* A10/A20 */ 9 10 #define A10_CLK_HOSC 1 11 #define A10_CLK_PLL_CORE 2 12 #define A10_CLK_PLL_PERIPH_BASE 14 13 #define A10_CLK_PLL_PERIPH 15 14 15 #define A10_CLK_CPU 20 16 #define A10_CLK_AXI 21 17 #define A10_CLK_AHB 23 18 #define A10_CLK_APB1 25 19 20 #define A10_CLK_AHB_EHCI0 27 21 #define A10_CLK_AHB_OHCI0 28 22 #define A10_CLK_AHB_EHCI1 29 23 #define A10_CLK_AHB_OHCI1 30 24 #define A10_CLK_AHB_MMC0 34 25 #define A10_CLK_AHB_MMC1 35 26 #define A10_CLK_AHB_MMC2 36 27 #define A10_CLK_AHB_MMC3 37 28 #define A10_CLK_AHB_EMAC 42 29 #define A10_CLK_AHB_SATA 49 30 #define A10_CLK_AHB_GMAC 66 31 #define A10_CLK_APB0_PIO 74 32 #define A10_CLK_APB1_I2C0 79 33 #define A10_CLK_APB1_I2C1 80 34 #define A10_CLK_APB1_I2C2 81 35 #define A10_CLK_APB1_I2C3 82 36 #define A10_CLK_APB1_I2C4 87 37 #define A10_CLK_APB1_UART0 88 38 #define A10_CLK_APB1_UART1 89 39 #define A10_CLK_APB1_UART2 90 40 #define A10_CLK_APB1_UART3 91 41 #define A10_CLK_APB1_UART4 92 42 #define A10_CLK_APB1_UART5 93 43 #define A10_CLK_APB1_UART6 94 44 #define A10_CLK_APB1_UART7 95 45 46 #define A10_CLK_MMC0 98 47 #define A10_CLK_MMC1 101 48 #define A10_CLK_MMC2 104 49 #define A10_CLK_MMC3 107 50 #define A10_CLK_SATA 122 51 #define A10_CLK_USB_OHCI0 123 52 #define A10_CLK_USB_OHCI1 124 53 #define A10_CLK_USB_PHY 125 54 55 #define A10_CLK_LOSC 254 56 57 const struct sxiccmu_ccu_bit sun4i_a10_gates[] = { 58 [A10_CLK_AHB_EHCI0] = { 0x0060, 1 }, 59 [A10_CLK_AHB_OHCI0] = { 0x0060, 2 }, 60 [A10_CLK_AHB_EHCI1] = { 0x0060, 3 }, 61 [A10_CLK_AHB_OHCI1] = { 0x0060, 4 }, 62 [A10_CLK_AHB_MMC0] = { 0x0060, 8 }, 63 [A10_CLK_AHB_MMC1] = { 0x0060, 9 }, 64 [A10_CLK_AHB_MMC2] = { 0x0060, 10 }, 65 [A10_CLK_AHB_MMC3] = { 0x0060, 11 }, 66 [A10_CLK_AHB_EMAC] = { 0x0060, 17 }, 67 [A10_CLK_AHB_SATA] = { 0x0060, 25 }, 68 [A10_CLK_AHB_GMAC] = { 0x0064, 17, A10_CLK_AHB }, 69 [A10_CLK_APB0_PIO] = { 0x0068, 5 }, 70 [A10_CLK_APB1_I2C0] = { 0x006c, 0, A10_CLK_APB1 }, 71 [A10_CLK_APB1_I2C1] = { 0x006c, 1, A10_CLK_APB1 }, 72 [A10_CLK_APB1_I2C2] = { 0x006c, 2, A10_CLK_APB1 }, 73 [A10_CLK_APB1_I2C3] = { 0x006c, 3, A10_CLK_APB1 }, 74 [A10_CLK_APB1_I2C4] = { 0x006c, 15, A10_CLK_APB1 }, 75 [A10_CLK_APB1_UART0] = { 0x006c, 16, A10_CLK_APB1 }, 76 [A10_CLK_APB1_UART1] = { 0x006c, 17, A10_CLK_APB1 }, 77 [A10_CLK_APB1_UART2] = { 0x006c, 18, A10_CLK_APB1 }, 78 [A10_CLK_APB1_UART3] = { 0x006c, 19, A10_CLK_APB1 }, 79 [A10_CLK_APB1_UART4] = { 0x006c, 20, A10_CLK_APB1 }, 80 [A10_CLK_APB1_UART5] = { 0x006c, 21, A10_CLK_APB1 }, 81 [A10_CLK_APB1_UART6] = { 0x006c, 22, A10_CLK_APB1 }, 82 [A10_CLK_APB1_UART7] = { 0x006c, 23, A10_CLK_APB1 }, 83 [A10_CLK_MMC0] = { 0x0088, 31 }, 84 [A10_CLK_MMC1] = { 0x008c, 31 }, 85 [A10_CLK_MMC2] = { 0x0090, 31 }, 86 [A10_CLK_MMC3] = { 0x0094, 31 }, 87 [A10_CLK_SATA] = { 0x00c8, 31 }, 88 [A10_CLK_USB_OHCI0] = { 0x00cc, 6 }, 89 [A10_CLK_USB_OHCI1] = { 0x00cc, 7 }, 90 [A10_CLK_USB_PHY] = { 0x00cc, 8 }, 91 }; 92 93 /* A10s */ 94 95 #define A10S_CLK_HOSC 1 96 #define A10S_CLK_PLL_CORE 2 97 #define A10S_CLK_PLL_PERIPH 14 98 99 #define A10S_CLK_CPU 17 100 #define A10S_CLK_AXI 18 101 #define A10S_CLK_AHB 19 102 #define A10S_CLK_APB1 21 103 104 #define A10S_CLK_AHB_EHCI0 24 105 #define A10S_CLK_AHB_OHCI0 25 106 #define A10S_CLK_AHB_MMC0 29 107 #define A10S_CLK_AHB_MMC1 30 108 #define A10S_CLK_AHB_MMC2 31 109 #define A10S_CLK_AHB_EMAC 34 110 #define A10S_CLK_APB0_PIO 53 111 #define A10S_CLK_APB1_I2C0 56 112 #define A10S_CLK_APB1_I2C1 57 113 #define A10S_CLK_APB1_I2C2 58 114 #define A10S_CLK_APB1_UART0 59 115 #define A10S_CLK_APB1_UART1 60 116 #define A10S_CLK_APB1_UART2 61 117 #define A10S_CLK_APB1_UART3 62 118 119 #define A10S_CLK_MMC0 64 120 #define A10S_CLK_MMC1 65 121 #define A10S_CLK_MMC2 66 122 #define A10S_CLK_USB_OHCI0 76 123 #define A10S_CLK_USB_PHY0 77 124 #define A10S_CLK_USB_PHY1 78 125 126 #define A10S_CLK_LOSC 254 127 128 const struct sxiccmu_ccu_bit sun5i_a10s_gates[] = { 129 [A10S_CLK_AHB_EHCI0] = { 0x0060, 1 }, 130 [A10S_CLK_AHB_OHCI0] = { 0x0060, 2 }, 131 [A10S_CLK_AHB_MMC0] = { 0x0060, 8 }, 132 [A10S_CLK_AHB_MMC1] = { 0x0060, 9 }, 133 [A10S_CLK_AHB_MMC2] = { 0x0060, 10 }, 134 [A10S_CLK_AHB_EMAC] = { 0x0060, 17 }, 135 [A10S_CLK_APB0_PIO] = { 0x0068, 5 }, 136 [A10S_CLK_APB1_I2C0] = { 0x006c, 0, A10S_CLK_APB1 }, 137 [A10S_CLK_APB1_I2C1] = { 0x006c, 1, A10S_CLK_APB1 }, 138 [A10S_CLK_APB1_I2C2] = { 0x006c, 2, A10S_CLK_APB1 }, 139 [A10S_CLK_APB1_UART0] = { 0x006c, 16, A10S_CLK_APB1 }, 140 [A10S_CLK_APB1_UART1] = { 0x006c, 17, A10S_CLK_APB1 }, 141 [A10S_CLK_APB1_UART2] = { 0x006c, 18, A10S_CLK_APB1 }, 142 [A10S_CLK_APB1_UART3] = { 0x006c, 19, A10S_CLK_APB1 }, 143 [A10S_CLK_MMC0] = { 0x0088, 31 }, 144 [A10S_CLK_MMC1] = { 0x008c, 31 }, 145 [A10S_CLK_MMC2] = { 0x0090, 31 }, 146 [A10S_CLK_USB_OHCI0] = { 0x00cc, 6 }, 147 [A10S_CLK_USB_PHY0] = { 0x00cc, 8 }, 148 [A10S_CLK_USB_PHY1] = { 0x00cc, 9 }, 149 }; 150 151 /* A23/A33 */ 152 153 #define A23_CLK_PLL_PERIPH 10 154 155 #define A23_CLK_AXI 19 156 #define A23_CLK_AHB1 20 157 #define A23_CLK_APB1 21 158 #define A23_CLK_APB2 22 159 160 #define A23_CLK_BUS_MMC0 26 161 #define A23_CLK_BUS_MMC1 27 162 #define A23_CLK_BUS_MMC2 28 163 #define A23_CLK_BUS_EHCI 35 164 #define A23_CLK_BUS_OHCI 36 165 #define A23_CLK_BUS_PIO 48 166 #define A23_CLK_BUS_I2C0 51 167 #define A23_CLK_BUS_I2C1 52 168 #define A23_CLK_BUS_I2C2 53 169 #define A23_CLK_BUS_UART0 54 170 #define A23_CLK_BUS_UART1 55 171 #define A23_CLK_BUS_UART2 56 172 #define A23_CLK_BUS_UART3 57 173 #define A23_CLK_BUS_UART4 58 174 175 #define A23_CLK_MMC0 60 176 #define A23_CLK_MMC1 63 177 #define A23_CLK_MMC2 66 178 #define A23_CLK_USB_OHCI 78 179 180 const struct sxiccmu_ccu_bit sun8i_a23_gates[] = { 181 [A23_CLK_BUS_MMC0] = { 0x0060, 8 }, 182 [A23_CLK_BUS_MMC1] = { 0x0060, 9 }, 183 [A23_CLK_BUS_MMC2] = { 0x0060, 10 }, 184 [A23_CLK_BUS_EHCI] = { 0x0060, 26 }, 185 [A23_CLK_BUS_OHCI] = { 0x0060, 29 }, 186 [A23_CLK_BUS_PIO] = { 0x0068, 5 }, 187 [A23_CLK_BUS_I2C0] = { 0x006c, 0, A23_CLK_APB2 }, 188 [A23_CLK_BUS_I2C1] = { 0x006c, 1, A23_CLK_APB2 }, 189 [A23_CLK_BUS_I2C2] = { 0x006c, 2, A23_CLK_APB2 }, 190 [A23_CLK_BUS_UART0] = { 0x006c, 16, A23_CLK_APB2 }, 191 [A23_CLK_BUS_UART1] = { 0x006c, 17, A23_CLK_APB2 }, 192 [A23_CLK_BUS_UART2] = { 0x006c, 18, A23_CLK_APB2 }, 193 [A23_CLK_BUS_UART3] = { 0x006c, 19, A23_CLK_APB2 }, 194 [A23_CLK_BUS_UART4] = { 0x006c, 20, A23_CLK_APB2 }, 195 [A23_CLK_MMC0] = { 0x0088, 31 }, 196 [A23_CLK_MMC1] = { 0x008c, 31 }, 197 [A23_CLK_MMC2] = { 0x0090, 31 }, 198 [A23_CLK_USB_OHCI] = { 0x00cc, 16 }, 199 }; 200 201 /* A64 */ 202 203 #define A64_CLK_PLL_CPUX 1 204 205 #define A64_CLK_PLL_PERIPH0 11 206 #define A64_CLK_PLL_PERIPH0_2X 12 207 208 #define A64_CLK_CPUX 21 209 #define A64_CLK_AXI 22 210 #define A64_CLK_APB 23 211 #define A64_CLK_AHB1 24 212 #define A64_CLK_APB1 25 213 #define A64_CLK_APB2 26 214 #define A64_CLK_AHB2 27 215 216 #define A64_CLK_BUS_MMC0 31 217 #define A64_CLK_BUS_MMC1 32 218 #define A64_CLK_BUS_MMC2 33 219 #define A64_CLK_BUS_EMAC 36 220 #define A64_CLK_BUS_EHCI0 42 221 #define A64_CLK_BUS_EHCI1 43 222 #define A64_CLK_BUS_OHCI0 44 223 #define A64_CLK_BUS_OHCI1 45 224 #define A64_CLK_BUS_PIO 58 225 #define A64_CLK_BUS_THS 59 226 #define A64_CLK_BUS_I2C0 63 227 #define A64_CLK_BUS_I2C1 64 228 #define A64_CLK_BUS_I2C2 65 229 #define A64_CLK_BUS_UART0 67 230 #define A64_CLK_BUS_UART1 68 231 #define A64_CLK_BUS_UART2 69 232 #define A64_CLK_BUS_UART3 70 233 #define A64_CLK_BUS_UART4 71 234 235 #define A64_CLK_THS 73 236 #define A64_CLK_MMC0 75 237 #define A64_CLK_MMC1 76 238 #define A64_CLK_MMC2 77 239 #define A64_CLK_USB_OHCI0 91 240 #define A64_CLK_USB_OHCI1 93 241 #define A64_CLK_USB_PHY0 86 242 #define A64_CLK_USB_PHY1 87 243 244 #define A64_CLK_LOSC 254 245 #define A64_CLK_HOSC 253 246 247 const struct sxiccmu_ccu_bit sun50i_a64_gates[] = { 248 [A64_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 249 [A64_CLK_BUS_MMC0] = { 0x0060, 8 }, 250 [A64_CLK_BUS_MMC1] = { 0x0060, 9 }, 251 [A64_CLK_BUS_MMC2] = { 0x0060, 10 }, 252 [A64_CLK_BUS_EMAC] = { 0x0060, 17, A64_CLK_AHB2 }, 253 [A64_CLK_BUS_EHCI0] = { 0x0060, 24 }, 254 [A64_CLK_BUS_EHCI1] = { 0x0060, 25 }, 255 [A64_CLK_BUS_OHCI0] = { 0x0060, 28 }, 256 [A64_CLK_BUS_OHCI1] = { 0x0060, 29 }, 257 [A64_CLK_BUS_PIO] = { 0x0068, 5 }, 258 [A64_CLK_BUS_THS] = { 0x0068, 8 }, 259 [A64_CLK_BUS_I2C0] = { 0x006c, 0, A64_CLK_APB2 }, 260 [A64_CLK_BUS_I2C1] = { 0x006c, 1, A64_CLK_APB2 }, 261 [A64_CLK_BUS_I2C2] = { 0x006c, 2, A64_CLK_APB2 }, 262 [A64_CLK_BUS_UART0] = { 0x006c, 16, A64_CLK_APB2 }, 263 [A64_CLK_BUS_UART1] = { 0x006c, 17, A64_CLK_APB2 }, 264 [A64_CLK_BUS_UART2] = { 0x006c, 18, A64_CLK_APB2 }, 265 [A64_CLK_BUS_UART3] = { 0x006c, 19, A64_CLK_APB2 }, 266 [A64_CLK_BUS_UART4] = { 0x006c, 20, A64_CLK_APB2 }, 267 [A64_CLK_THS] = { 0x0074, 31 }, 268 [A64_CLK_MMC0] = { 0x0088, 31 }, 269 [A64_CLK_MMC1] = { 0x008c, 31 }, 270 [A64_CLK_MMC2] = { 0x0090, 31 }, 271 [A64_CLK_USB_OHCI0] = { 0x00cc, 16 }, 272 [A64_CLK_USB_OHCI1] = { 0x00cc, 17 }, 273 [A64_CLK_USB_PHY0] = { 0x00cc, 8 }, 274 [A64_CLK_USB_PHY1] = { 0x00cc, 9 }, 275 }; 276 277 /* A80 */ 278 279 #define A80_CLK_PLL_PERIPH0 3 280 #define A80_CLK_PLL_PERIPH1 11 281 282 #define A80_CLK_GTBUS 18 283 #define A80_CLK_AHB1 20 284 #define A80_CLK_APB1 23 285 286 #define A80_CLK_MMC0 33 287 #define A80_CLK_MMC1 36 288 #define A80_CLK_MMC2 39 289 #define A80_CLK_MMC3 42 290 291 #define A80_CLK_BUS_MMC 84 292 #define A80_CLK_BUS_USB 96 293 #define A80_CLK_BUS_GMAC 97 294 #define A80_CLK_BUS_PIO 111 295 #define A80_CLK_BUS_I2C0 119 296 #define A80_CLK_BUS_I2C1 120 297 #define A80_CLK_BUS_I2C2 121 298 #define A80_CLK_BUS_I2C3 122 299 #define A80_CLK_BUS_I2C4 123 300 #define A80_CLK_BUS_UART0 124 301 #define A80_CLK_BUS_UART1 125 302 #define A80_CLK_BUS_UART2 126 303 #define A80_CLK_BUS_UART3 127 304 #define A80_CLK_BUS_UART4 128 305 #define A80_CLK_BUS_UART5 129 306 307 const struct sxiccmu_ccu_bit sun9i_a80_gates[] = { 308 [A80_CLK_MMC0] = { 0x0410, 31 }, 309 [A80_CLK_MMC1] = { 0x0414, 31 }, 310 [A80_CLK_MMC2] = { 0x0418, 31 }, 311 [A80_CLK_MMC3] = { 0x041c, 31 }, /* Undocumented */ 312 [A80_CLK_BUS_MMC] = { 0x0580, 8 }, 313 [A80_CLK_BUS_GMAC] = { 0x0584, 17, A80_CLK_AHB1 }, 314 [A80_CLK_BUS_USB] = { 0x0584, 1 }, 315 [A80_CLK_BUS_PIO] = { 0x0590, 5 }, 316 [A80_CLK_BUS_I2C0] = { 0x0594, 0, A80_CLK_APB1 }, 317 [A80_CLK_BUS_I2C1] = { 0x0594, 1, A80_CLK_APB1 }, 318 [A80_CLK_BUS_I2C2] = { 0x0594, 2, A80_CLK_APB1 }, 319 [A80_CLK_BUS_I2C3] = { 0x0594, 3, A80_CLK_APB1 }, 320 [A80_CLK_BUS_I2C4] = { 0x0594, 4, A80_CLK_APB1 }, 321 [A80_CLK_BUS_UART0] = { 0x0594, 16, A80_CLK_APB1 }, 322 [A80_CLK_BUS_UART1] = { 0x0594, 17, A80_CLK_APB1 }, 323 [A80_CLK_BUS_UART2] = { 0x0594, 18, A80_CLK_APB1 }, 324 [A80_CLK_BUS_UART3] = { 0x0594, 19, A80_CLK_APB1 }, 325 [A80_CLK_BUS_UART4] = { 0x0594, 20, A80_CLK_APB1 }, 326 [A80_CLK_BUS_UART5] = { 0x0594, 21, A80_CLK_APB1 }, 327 }; 328 329 #define A80_USB_CLK_HCI0 0 330 #define A80_USB_CLK_OHCI0 1 331 #define A80_USB_CLK_HCI1 2 332 #define A80_USB_CLK_HCI2 3 333 #define A80_USB_CLK_OHCI2 4 334 335 #define A80_USB_CLK_HCI0_PHY 5 336 #define A80_USB_CLK_HCI1_HSIC 6 337 #define A80_USB_CLK_HCI1_PHY 7 338 #define A80_USB_CLK_HCI2_HSIC 8 339 #define A80_USB_CLK_HCI2_UTMIPHY 9 340 #define A80_USB_CLK_HCI1_HSIC_12M 10 341 342 const struct sxiccmu_ccu_bit sun9i_a80_usb_gates[] = { 343 [A80_USB_CLK_HCI0] = { 0x0000, 1 }, 344 [A80_USB_CLK_OHCI0] = { 0x0000, 2 }, 345 [A80_USB_CLK_HCI1] = { 0x0000, 3 }, 346 [A80_USB_CLK_HCI2] = { 0x0000, 5 }, 347 [A80_USB_CLK_OHCI2] = { 0x0000, 6 }, 348 [A80_USB_CLK_HCI0_PHY] = { 0x0004, 1 }, 349 [A80_USB_CLK_HCI1_HSIC] = { 0x0004, 2 }, 350 [A80_USB_CLK_HCI1_PHY] = { 0x0004, 3 }, /* Undocumented */ 351 [A80_USB_CLK_HCI2_HSIC] = { 0x0004, 4 }, 352 [A80_USB_CLK_HCI2_UTMIPHY] = { 0x0004, 5 }, 353 [A80_USB_CLK_HCI1_HSIC_12M] = { 0x0004, 10 }, 354 }; 355 356 const struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = { 357 { 0x0000, 16 }, 358 { 0x0004, 16 }, 359 { 0x0008, 16 }, 360 { 0x000c, 16 }, 361 }; 362 363 /* D1 */ 364 365 #define D1_CLK_PLL_CPU 0 366 #define D1_CLK_PLL_PERIPH0 5 367 #define D1_CLK_PSI_AHB 23 368 #define D1_CLK_APB1 25 369 #define D1_CLK_MMC0 56 370 #define D1_CLK_MMC1 57 371 #define D1_CLK_MMC2 58 372 #define D1_CLK_BUS_MMC0 59 373 #define D1_CLK_BUS_MMC1 60 374 #define D1_CLK_BUS_MMC2 61 375 #define D1_CLK_BUS_UART0 62 376 #define D1_CLK_BUS_UART1 63 377 #define D1_CLK_BUS_UART2 64 378 #define D1_CLK_BUS_UART3 65 379 #define D1_CLK_BUS_UART4 66 380 #define D1_CLK_BUS_UART5 67 381 #define D1_CLK_BUS_EMAC 77 382 #define D1_CLK_USB_OHCI0 97 383 #define D1_CLK_USB_OHCI1 98 384 #define D1_CLK_BUS_OHCI0 99 385 #define D1_CLK_BUS_OHCI1 100 386 #define D1_CLK_BUS_EHCI0 101 387 #define D1_CLK_BUS_EHCI1 102 388 #define D1_CLK_RISCV 132 389 390 #define D1_CLK_HOSC 255 391 392 const struct sxiccmu_ccu_bit sun20i_d1_gates[] = { 393 [D1_CLK_MMC0] = { 0x0830, 31 }, 394 [D1_CLK_MMC1] = { 0x0834, 31 }, 395 [D1_CLK_MMC2] = { 0x0838, 31 }, 396 [D1_CLK_BUS_MMC0] = { 0x084c, 0 }, 397 [D1_CLK_BUS_MMC1] = { 0x084c, 1 }, 398 [D1_CLK_BUS_MMC2] = { 0x084c, 2 }, 399 [D1_CLK_BUS_UART0] = { 0x090c, 0, D1_CLK_APB1 }, 400 [D1_CLK_BUS_UART1] = { 0x090c, 1, D1_CLK_APB1 }, 401 [D1_CLK_BUS_UART2] = { 0x090c, 2, D1_CLK_APB1 }, 402 [D1_CLK_BUS_UART3] = { 0x090c, 3, D1_CLK_APB1 }, 403 [D1_CLK_BUS_UART4] = { 0x090c, 4, D1_CLK_APB1 }, 404 [D1_CLK_BUS_UART5] = { 0x090c, 5, D1_CLK_APB1 }, 405 [D1_CLK_BUS_EMAC] = { 0x097c, 0, D1_CLK_PSI_AHB }, 406 [D1_CLK_USB_OHCI0] = { 0x0a70, 31 }, 407 [D1_CLK_USB_OHCI1] = { 0x0a74, 31 }, 408 [D1_CLK_BUS_OHCI0] = { 0x0a8c, 0 }, 409 [D1_CLK_BUS_OHCI1] = { 0x0a8c, 1 }, 410 [D1_CLK_BUS_EHCI0] = { 0x0a8c, 4 }, 411 [D1_CLK_BUS_EHCI1] = { 0x0a8c, 5 }, 412 }; 413 414 /* H3/H5 */ 415 416 #define H3_CLK_PLL_CPUX 0 417 #define H3_CLK_PLL_PERIPH0 9 418 419 #define H3_CLK_CPUX 14 420 #define H3_CLK_AXI 15 421 #define H3_CLK_AHB1 16 422 #define H3_CLK_APB1 17 423 #define H3_CLK_APB2 18 424 #define H3_CLK_AHB2 19 425 426 #define H3_CLK_BUS_MMC0 22 427 #define H3_CLK_BUS_MMC1 23 428 #define H3_CLK_BUS_MMC2 24 429 #define H3_CLK_BUS_EMAC 27 430 #define H3_CLK_BUS_EHCI0 33 431 #define H3_CLK_BUS_EHCI1 34 432 #define H3_CLK_BUS_EHCI2 35 433 #define H3_CLK_BUS_EHCI3 36 434 #define H3_CLK_BUS_OHCI0 37 435 #define H3_CLK_BUS_OHCI1 38 436 #define H3_CLK_BUS_OHCI2 39 437 #define H3_CLK_BUS_OHCI3 40 438 #define H3_CLK_BUS_PIO 54 439 #define H3_CLK_BUS_THS 55 440 #define H3_CLK_BUS_I2C0 59 441 #define H3_CLK_BUS_I2C1 60 442 #define H3_CLK_BUS_I2C2 61 443 #define H3_CLK_BUS_UART0 62 444 #define H3_CLK_BUS_UART1 63 445 #define H3_CLK_BUS_UART2 64 446 #define H3_CLK_BUS_UART3 65 447 #define H3_CLK_BUS_EPHY 67 448 449 #define H3_CLK_THS 69 450 #define H3_CLK_MMC0 71 451 #define H3_CLK_MMC1 74 452 #define H3_CLK_MMC2 77 453 #define H3_CLK_USB_PHY0 88 454 #define H3_CLK_USB_PHY1 89 455 #define H3_CLK_USB_PHY2 90 456 #define H3_CLK_USB_PHY3 91 457 #define H3_CLK_USB_OHCI0 92 458 #define H3_CLK_USB_OHCI1 93 459 #define H3_CLK_USB_OHCI2 94 460 #define H3_CLK_USB_OHCI3 95 461 462 #define H3_CLK_LOSC 254 463 #define H3_CLK_HOSC 253 464 465 const struct sxiccmu_ccu_bit sun8i_h3_gates[] = { 466 [H3_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 467 [H3_CLK_BUS_MMC0] = { 0x0060, 8 }, 468 [H3_CLK_BUS_MMC1] = { 0x0060, 9 }, 469 [H3_CLK_BUS_MMC2] = { 0x0060, 10 }, 470 [H3_CLK_BUS_EMAC] = { 0x0060, 17, H3_CLK_AHB2 }, 471 [H3_CLK_BUS_EHCI0] = { 0x0060, 24 }, 472 [H3_CLK_BUS_EHCI1] = { 0x0060, 25 }, 473 [H3_CLK_BUS_EHCI2] = { 0x0060, 26 }, 474 [H3_CLK_BUS_EHCI3] = { 0x0060, 27 }, 475 [H3_CLK_BUS_OHCI0] = { 0x0060, 28 }, 476 [H3_CLK_BUS_OHCI1] = { 0x0060, 29 }, 477 [H3_CLK_BUS_OHCI2] = { 0x0060, 30 }, 478 [H3_CLK_BUS_OHCI3] = { 0x0060, 31 }, 479 [H3_CLK_BUS_PIO] = { 0x0068, 5 }, 480 [H3_CLK_BUS_THS] = { 0x0068, 8 }, 481 [H3_CLK_BUS_I2C0] = { 0x006c, 0, H3_CLK_APB2 }, 482 [H3_CLK_BUS_I2C1] = { 0x006c, 1, H3_CLK_APB2 }, 483 [H3_CLK_BUS_I2C2] = { 0x006c, 2, H3_CLK_APB2 }, 484 [H3_CLK_BUS_UART0] = { 0x006c, 16, H3_CLK_APB2 }, 485 [H3_CLK_BUS_UART1] = { 0x006c, 17, H3_CLK_APB2 }, 486 [H3_CLK_BUS_UART2] = { 0x006c, 18, H3_CLK_APB2 }, 487 [H3_CLK_BUS_UART3] = { 0x006c, 19, H3_CLK_APB2 }, 488 [H3_CLK_BUS_EPHY] = { 0x0070, 0 }, 489 [H3_CLK_THS] = { 0x0074, 31 }, 490 [H3_CLK_MMC0] = { 0x0088, 31 }, 491 [H3_CLK_MMC1] = { 0x008c, 31 }, 492 [H3_CLK_MMC2] = { 0x0090, 31 }, 493 [H3_CLK_USB_PHY0] = { 0x00cc, 8 }, 494 [H3_CLK_USB_PHY1] = { 0x00cc, 9 }, 495 [H3_CLK_USB_PHY2] = { 0x00cc, 10 }, 496 [H3_CLK_USB_PHY3] = { 0x00cc, 11 }, 497 [H3_CLK_USB_OHCI0] = { 0x00cc, 16 }, 498 [H3_CLK_USB_OHCI1] = { 0x00cc, 17 }, 499 [H3_CLK_USB_OHCI2] = { 0x00cc, 18 }, 500 [H3_CLK_USB_OHCI3] = { 0x00cc, 19 }, 501 }; 502 503 #define H3_R_CLK_AHB0 1 504 #define H3_R_CLK_APB0 2 505 506 #define H3_R_CLK_APB0_PIO 3 507 #define H3_R_CLK_APB0_RSB 6 508 #define H3_R_CLK_APB0_I2C 9 509 510 const struct sxiccmu_ccu_bit sun8i_h3_r_gates[] = { 511 [H3_R_CLK_APB0_PIO] = { 0x0028, 0 }, 512 [H3_R_CLK_APB0_RSB] = { 0x0028, 3, H3_R_CLK_APB0 }, 513 [H3_R_CLK_APB0_I2C] = { 0x0028, 6, H3_R_CLK_APB0 }, 514 }; 515 516 /* H6 */ 517 518 #define H6_CLK_PLL_PERIPH0 3 519 #define H6_CLK_PLL_PERIPH0_2X 4 520 #define H6_CLK_AHB3 25 521 #define H6_CLK_APB1 26 522 #define H6_CLK_APB2 27 523 #define H6_CLK_MMC0 64 524 #define H6_CLK_MMC1 65 525 #define H6_CLK_MMC2 66 526 #define H6_CLK_BUS_MMC0 67 527 #define H6_CLK_BUS_MMC1 68 528 #define H6_CLK_BUS_MMC2 69 529 #define H6_CLK_BUS_UART0 70 530 #define H6_CLK_BUS_UART1 71 531 #define H6_CLK_BUS_UART2 72 532 #define H6_CLK_BUS_UART3 73 533 #define H6_CLK_BUS_EMAC 84 534 #define H6_CLK_USB_OHCI0 104 535 #define H6_CLK_USB_PHY0 105 536 #define H6_CLK_USB_PHY1 106 537 #define H6_CLK_USB_OHCI3 107 538 #define H6_CLK_USB_PHY3 108 539 #define H6_CLK_BUS_OHCI0 111 540 #define H6_CLK_BUS_OHCI3 112 541 #define H6_CLK_BUS_EHCI0 113 542 #define H6_CLK_BUS_EHCI3 115 543 544 const struct sxiccmu_ccu_bit sun50i_h6_gates[] = { 545 [H6_CLK_PLL_PERIPH0] = { 0x0020, 31 }, 546 [H6_CLK_APB1] = { 0xffff, 0xff }, 547 [H6_CLK_MMC0] = { 0x0830, 31 }, 548 [H6_CLK_MMC1] = { 0x0834, 31 }, 549 [H6_CLK_MMC2] = { 0x0838, 31 }, 550 [H6_CLK_BUS_MMC0] = { 0x084c, 0 }, 551 [H6_CLK_BUS_MMC1] = { 0x084c, 1 }, 552 [H6_CLK_BUS_MMC2] = { 0x084c, 2 }, 553 [H6_CLK_BUS_UART0] = { 0x090c, 0, H6_CLK_APB2 }, 554 [H6_CLK_BUS_UART1] = { 0x090c, 1, H6_CLK_APB2 }, 555 [H6_CLK_BUS_UART2] = { 0x090c, 2, H6_CLK_APB2 }, 556 [H6_CLK_BUS_UART3] = { 0x090c, 3, H6_CLK_APB2 }, 557 [H6_CLK_BUS_EMAC] = { 0x097c, 0, H6_CLK_AHB3 }, 558 [H6_CLK_USB_OHCI0] = { 0x0a70, 31 }, 559 [H6_CLK_USB_PHY0] = { 0x0a70, 29 }, 560 [H6_CLK_USB_PHY1] = { 0x0a74, 29 }, 561 [H6_CLK_USB_OHCI3] = { 0x0a7c, 31 }, 562 [H6_CLK_USB_PHY3] = { 0x0a7c, 29 }, 563 [H6_CLK_BUS_OHCI0] = { 0x0a8c, 0 }, 564 [H6_CLK_BUS_OHCI3] = { 0x0a8c, 3 }, 565 [H6_CLK_BUS_EHCI0] = { 0x0a8c, 4 }, 566 [H6_CLK_BUS_EHCI3] = { 0x0a8c, 7 }, 567 }; 568 569 #define H6_R_CLK_APB1 2 570 #define H6_R_CLK_APB2 3 571 #define H6_R_CLK_APB2_I2C 8 572 #define H6_R_CLK_APB2_RSB 13 573 574 const struct sxiccmu_ccu_bit sun50i_h6_r_gates[] = { 575 [H6_R_CLK_APB1] = { 0xffff, 0xff }, 576 [H6_R_CLK_APB2_I2C] = { 0x019c, 0, H6_R_CLK_APB2 }, 577 [H6_R_CLK_APB2_RSB] = { 0x01bc, 0, H6_R_CLK_APB2 }, 578 }; 579 580 /* H616 */ 581 582 #define H616_CLK_PLL_PERIPH0 4 583 #define H616_CLK_PLL_PERIPH0_2X 5 584 #define H616_CLK_AHB3 25 585 #define H616_CLK_APB1 26 586 #define H616_CLK_APB2 27 587 #define H616_CLK_MMC0 60 588 #define H616_CLK_MMC1 61 589 #define H616_CLK_MMC2 62 590 #define H616_CLK_BUS_MMC0 63 591 #define H616_CLK_BUS_MMC1 64 592 #define H616_CLK_BUS_MMC2 65 593 #define H616_CLK_BUS_UART0 66 594 #define H616_CLK_BUS_UART1 67 595 #define H616_CLK_BUS_UART2 68 596 #define H616_CLK_BUS_UART3 69 597 #define H616_CLK_BUS_UART4 70 598 #define H616_CLK_BUS_UART5 71 599 #define H616_CLK_BUS_I2C0 72 600 #define H616_CLK_BUS_I2C1 73 601 #define H616_CLK_BUS_I2C2 74 602 #define H616_CLK_BUS_I2C3 75 603 #define H616_CLK_BUS_I2C4 76 604 #define H616_CLK_BUS_EMAC0 82 605 #define H616_CLK_BUS_EMAC1 83 606 #define H616_CLK_USB_OHCI0 96 607 #define H616_CLK_USB_PHY0 97 608 #define H616_CLK_USB_OHCI1 98 609 #define H616_CLK_USB_PHY1 99 610 #define H616_CLK_USB_OHCI2 100 611 #define H616_CLK_USB_PHY2 101 612 #define H616_CLK_USB_OHCI3 102 613 #define H616_CLK_USB_PHY3 103 614 #define H616_CLK_BUS_OHCI0 104 615 #define H616_CLK_BUS_OHCI1 105 616 #define H616_CLK_BUS_OHCI2 106 617 #define H616_CLK_BUS_OHCI3 107 618 #define H616_CLK_BUS_EHCI0 108 619 #define H616_CLK_BUS_EHCI1 109 620 #define H616_CLK_BUS_EHCI2 110 621 #define H616_CLK_BUS_EHCI3 111 622 623 struct sxiccmu_ccu_bit sun50i_h616_gates[] = { 624 [H616_CLK_PLL_PERIPH0] = { 0x0020, 31 }, 625 [H616_CLK_APB1] = { 0xffff, 0xff }, 626 [H616_CLK_MMC0] = { 0x0830, 31 }, 627 [H616_CLK_MMC1] = { 0x0834, 31 }, 628 [H616_CLK_MMC2] = { 0x0838, 31 }, 629 [H616_CLK_BUS_MMC0] = { 0x084c, 0 }, 630 [H616_CLK_BUS_MMC1] = { 0x084c, 1 }, 631 [H616_CLK_BUS_MMC2] = { 0x084c, 2 }, 632 [H616_CLK_BUS_UART0] = { 0x090c, 0, H616_CLK_APB2 }, 633 [H616_CLK_BUS_UART1] = { 0x090c, 1, H616_CLK_APB2 }, 634 [H616_CLK_BUS_UART2] = { 0x090c, 2, H616_CLK_APB2 }, 635 [H616_CLK_BUS_UART3] = { 0x090c, 3, H616_CLK_APB2 }, 636 [H616_CLK_BUS_UART4] = { 0x090c, 4, H616_CLK_APB2 }, 637 [H616_CLK_BUS_UART5] = { 0x090c, 5, H616_CLK_APB2 }, 638 [H616_CLK_BUS_I2C0] = { 0x091c, 0, H616_CLK_APB2 }, 639 [H616_CLK_BUS_I2C1] = { 0x091c, 1, H616_CLK_APB2 }, 640 [H616_CLK_BUS_I2C2] = { 0x091c, 2, H616_CLK_APB2 }, 641 [H616_CLK_BUS_I2C3] = { 0x091c, 3, H616_CLK_APB2 }, 642 [H616_CLK_BUS_I2C4] = { 0x091c, 4, H616_CLK_APB2 }, 643 [H616_CLK_BUS_EMAC0] = { 0x097c, 0, H616_CLK_AHB3 }, 644 [H616_CLK_BUS_EMAC1] = { 0x097c, 1, H616_CLK_AHB3 }, 645 [H616_CLK_USB_OHCI0] = { 0x0a70, 31 }, 646 [H616_CLK_USB_PHY0] = { 0x0a70, 29 }, 647 [H616_CLK_USB_OHCI1] = { 0x0a74, 31 }, 648 [H616_CLK_USB_PHY1] = { 0x0a74, 29 }, 649 [H616_CLK_USB_OHCI2] = { 0x0a78, 31 }, 650 [H616_CLK_USB_PHY2] = { 0x0a78, 29 }, 651 [H616_CLK_USB_OHCI3] = { 0x0a7c, 31 }, 652 [H616_CLK_USB_PHY3] = { 0x0a7c, 29 }, 653 [H616_CLK_BUS_OHCI0] = { 0x0a8c, 0 }, 654 [H616_CLK_BUS_OHCI1] = { 0x0a8c, 1 }, 655 [H616_CLK_BUS_OHCI2] = { 0x0a8c, 2 }, 656 [H616_CLK_BUS_OHCI3] = { 0x0a8c, 3 }, 657 [H616_CLK_BUS_EHCI0] = { 0x0a8c, 4 }, 658 [H616_CLK_BUS_EHCI1] = { 0x0a8c, 5 }, 659 [H616_CLK_BUS_EHCI2] = { 0x0a8c, 6 }, 660 [H616_CLK_BUS_EHCI3] = { 0x0a8c, 7 }, 661 }; 662 663 #define H616_R_CLK_APB1 2 664 #define H616_R_CLK_APB2 3 665 #define H616_R_CLK_APB2_I2C 8 666 #define H616_R_CLK_APB2_RSB 13 667 668 struct sxiccmu_ccu_bit sun50i_h616_r_gates[] = { 669 [H616_R_CLK_APB1] = { 0xffff, 0xff }, 670 [H616_R_CLK_APB2_I2C] = { 0x019c, 0, H616_R_CLK_APB2 }, 671 [H616_R_CLK_APB2_RSB] = { 0x01bc, 0, H616_R_CLK_APB2 }, 672 }; 673 674 /* R40 */ 675 676 #define R40_CLK_PLL_PERIPH0 11 677 #define R40_CLK_PLL_PERIPH0_2X 13 678 679 #define R40_CLK_AXI 25 680 #define R40_CLK_AHB1 26 681 #define R40_CLK_APB2 28 682 683 #define R40_CLK_BUS_MMC0 32 684 #define R40_CLK_BUS_MMC1 33 685 #define R40_CLK_BUS_MMC2 34 686 #define R40_CLK_BUS_MMC3 35 687 #define R40_CLK_BUS_SATA 45 688 #define R40_CLK_BUS_EHCI0 47 689 #define R40_CLK_BUS_EHCI1 48 690 #define R40_CLK_BUS_EHCI2 49 691 #define R40_CLK_BUS_OHCI0 50 692 #define R40_CLK_BUS_OHCI1 51 693 #define R40_CLK_BUS_OHCI2 52 694 #define R40_CLK_BUS_GMAC 64 695 #define R40_CLK_BUS_PIO 79 696 #define R40_CLK_BUS_THS 82 697 #define R40_CLK_BUS_I2C0 87 698 #define R40_CLK_BUS_I2C1 88 699 #define R40_CLK_BUS_I2C2 89 700 #define R40_CLK_BUS_I2C3 90 701 #define R40_CLK_BUS_I2C4 95 702 #define R40_CLK_BUS_UART0 96 703 #define R40_CLK_BUS_UART1 97 704 #define R40_CLK_BUS_UART2 98 705 #define R40_CLK_BUS_UART3 99 706 #define R40_CLK_BUS_UART4 100 707 #define R40_CLK_BUS_UART5 101 708 #define R40_CLK_BUS_UART6 102 709 #define R40_CLK_BUS_UART7 103 710 711 #define R40_CLK_THS 105 712 #define R40_CLK_MMC0 107 713 #define R40_CLK_MMC1 108 714 #define R40_CLK_MMC2 109 715 #define R40_CLK_MMC3 110 716 #define R40_CLK_SATA 123 717 #define R40_CLK_USB_PHY0 124 718 #define R40_CLK_USB_PHY1 125 719 #define R40_CLK_USB_PHY2 126 720 #define R40_CLK_USB_OHCI0 127 721 #define R40_CLK_USB_OHCI1 128 722 #define R40_CLK_USB_OHCI2 129 723 724 #define R40_CLK_HOSC 253 725 #define R40_CLK_LOSC 254 726 727 const struct sxiccmu_ccu_bit sun8i_r40_gates[] = { 728 [R40_CLK_BUS_MMC0] = { 0x0060, 8 }, 729 [R40_CLK_BUS_MMC1] = { 0x0060, 9 }, 730 [R40_CLK_BUS_MMC2] = { 0x0060, 10 }, 731 [R40_CLK_BUS_MMC3] = { 0x0060, 11 }, 732 [R40_CLK_BUS_SATA] = { 0x0060, 24 }, 733 [R40_CLK_BUS_EHCI0] = { 0x0060, 26 }, 734 [R40_CLK_BUS_EHCI1] = { 0x0060, 27 }, 735 [R40_CLK_BUS_EHCI2] = { 0x0060, 28 }, 736 [R40_CLK_BUS_OHCI0] = { 0x0060, 29 }, 737 [R40_CLK_BUS_OHCI1] = { 0x0060, 30 }, 738 [R40_CLK_BUS_OHCI2] = { 0x0060, 31 }, 739 [R40_CLK_BUS_GMAC] = { 0x0064, 17, R40_CLK_AHB1 }, 740 [R40_CLK_BUS_PIO] = { 0x0068, 5 }, 741 [R40_CLK_BUS_THS] = { 0x0068, 8 }, 742 [R40_CLK_BUS_I2C0] = { 0x006c, 0, R40_CLK_APB2 }, 743 [R40_CLK_BUS_I2C1] = { 0x006c, 1, R40_CLK_APB2 }, 744 [R40_CLK_BUS_I2C2] = { 0x006c, 2, R40_CLK_APB2 }, 745 [R40_CLK_BUS_I2C3] = { 0x006c, 3, R40_CLK_APB2 }, 746 [R40_CLK_BUS_I2C4] = { 0x006c, 15, R40_CLK_APB2 }, 747 [R40_CLK_BUS_UART0] = { 0x006c, 16, R40_CLK_APB2 }, 748 [R40_CLK_BUS_UART1] = { 0x006c, 17, R40_CLK_APB2 }, 749 [R40_CLK_BUS_UART2] = { 0x006c, 18, R40_CLK_APB2 }, 750 [R40_CLK_BUS_UART3] = { 0x006c, 19, R40_CLK_APB2 }, 751 [R40_CLK_BUS_UART4] = { 0x006c, 20, R40_CLK_APB2 }, 752 [R40_CLK_BUS_UART5] = { 0x006c, 21, R40_CLK_APB2 }, 753 [R40_CLK_BUS_UART6] = { 0x006c, 22, R40_CLK_APB2 }, 754 [R40_CLK_BUS_UART7] = { 0x006c, 23, R40_CLK_APB2 }, 755 [R40_CLK_THS] = { 0x0074, 31 }, 756 [R40_CLK_MMC0] = { 0x0088, 31 }, 757 [R40_CLK_MMC1] = { 0x008c, 31 }, 758 [R40_CLK_MMC2] = { 0x0090, 31 }, 759 [R40_CLK_MMC3] = { 0x0094, 31 }, 760 [R40_CLK_SATA] = { 0x00c8, 31 }, 761 [R40_CLK_USB_PHY0] = { 0x00cc, 8 }, 762 [R40_CLK_USB_PHY1] = { 0x00cc, 9 }, 763 [R40_CLK_USB_PHY2] = { 0x00cc, 10 }, 764 [R40_CLK_USB_OHCI0] = { 0x00cc, 16 }, 765 [R40_CLK_USB_OHCI1] = { 0x00cc, 17 }, 766 [R40_CLK_USB_OHCI2] = { 0x00cc, 18 }, 767 }; 768 769 /* V3s */ 770 771 #define V3S_CLK_PLL_PERIPH0 9 772 #define V3S_CLK_AXI 15 773 #define V3S_CLK_AHB1 16 774 #define V3S_CLK_APB2 18 775 #define V3S_CLK_AHB2 19 776 777 #define V3S_CLK_BUS_MMC0 22 778 #define V3S_CLK_BUS_MMC1 23 779 #define V3S_CLK_BUS_MMC2 24 780 #define V3S_CLK_BUS_EMAC 26 781 #define V3S_CLK_BUS_EHCI0 30 782 #define V3S_CLK_BUS_OHCI0 31 783 #define V3S_CLK_BUS_PIO 37 784 #define V3S_CLK_BUS_I2C0 38 785 #define V3S_CLK_BUS_I2C1 39 786 #define V3S_CLK_BUS_UART0 40 787 #define V3S_CLK_BUS_UART1 41 788 #define V3S_CLK_BUS_UART2 42 789 #define V3S_CLK_BUS_EPHY 43 790 791 #define V3S_CLK_MMC0 45 792 #define V3S_CLK_MMC1 48 793 #define V3S_CLK_MMC2 51 794 #define V3S_CLK_USB_PHY0 56 795 #define V3S_CLK_USB_OHCI0 57 796 797 #define V3S_CLK_LOSC 254 798 #define V3S_CLK_HOSC 253 799 800 const struct sxiccmu_ccu_bit sun8i_v3s_gates[] = { 801 [V3S_CLK_BUS_OHCI0] = { 0x0060, 29 }, 802 [V3S_CLK_BUS_EHCI0] = { 0x0060, 26 }, 803 [V3S_CLK_BUS_EMAC] = { 0x0060, 17, V3S_CLK_AHB2 }, 804 [V3S_CLK_BUS_MMC2] = { 0x0060, 10 }, 805 [V3S_CLK_BUS_MMC1] = { 0x0060, 9 }, 806 [V3S_CLK_BUS_MMC0] = { 0x0060, 8 }, 807 [V3S_CLK_BUS_PIO] = { 0x0068, 5 }, 808 [V3S_CLK_BUS_UART2] = { 0x006c, 18, V3S_CLK_APB2 }, 809 [V3S_CLK_BUS_UART1] = { 0x006c, 17, V3S_CLK_APB2 }, 810 [V3S_CLK_BUS_UART0] = { 0x006c, 16, V3S_CLK_APB2 }, 811 [V3S_CLK_BUS_I2C1] = { 0x006c, 1, V3S_CLK_APB2 }, 812 [V3S_CLK_BUS_I2C0] = { 0x006c, 0, V3S_CLK_APB2 }, 813 [V3S_CLK_BUS_EPHY] = { 0x0070, 0 }, 814 [V3S_CLK_MMC0] = { 0x0088, 31 }, 815 [V3S_CLK_MMC1] = { 0x008c, 31 }, 816 [V3S_CLK_MMC2] = { 0x0090, 31 }, 817 [V3S_CLK_USB_OHCI0] = { 0x00cc, 16 }, 818 [V3S_CLK_USB_PHY0] = { 0x00cc, 8 }, 819 }; 820 821 /* 822 * Reset Signals 823 */ 824 825 /* A10 */ 826 827 #define A10_RST_USB_PHY0 1 828 #define A10_RST_USB_PHY1 2 829 #define A10_RST_USB_PHY2 3 830 831 const struct sxiccmu_ccu_bit sun4i_a10_resets[] = { 832 [A10_RST_USB_PHY0] = { 0x00cc, 0 }, 833 [A10_RST_USB_PHY1] = { 0x00cc, 1 }, 834 [A10_RST_USB_PHY2] = { 0x00cc, 2 }, 835 }; 836 837 /* A10s */ 838 839 #define A10S_RST_USB_PHY0 0 840 #define A10S_RST_USB_PHY1 1 841 842 const struct sxiccmu_ccu_bit sun5i_a10s_resets[] = { 843 [A10S_RST_USB_PHY0] = { 0x00cc, 0 }, 844 [A10S_RST_USB_PHY1] = { 0x00cc, 1 }, 845 }; 846 847 /* A23/A33 */ 848 849 #define A23_RST_USB_PHY0 0 850 #define A23_RST_USB_PHY1 1 851 852 #define A23_RST_BUS_MMC0 7 853 #define A23_RST_BUS_MMC1 8 854 #define A23_RST_BUS_MMC2 9 855 856 #define A23_RST_BUS_EHCI 16 857 #define A23_RST_BUS_OHCI 17 858 859 #define A23_RST_BUS_I2C0 32 860 #define A23_RST_BUS_I2C1 33 861 #define A23_RST_BUS_I2C2 34 862 863 #define A23_CLK_HOSC 253 864 #define A23_CLK_LOSC 254 865 866 const struct sxiccmu_ccu_bit sun8i_a23_resets[] = { 867 [A23_RST_USB_PHY0] = { 0x00cc, 0 }, 868 [A23_RST_USB_PHY1] = { 0x00cc, 1 }, 869 [A23_RST_BUS_MMC0] = { 0x02c0, 8 }, 870 [A23_RST_BUS_MMC1] = { 0x02c0, 9 }, 871 [A23_RST_BUS_MMC2] = { 0x02c0, 10 }, 872 [A23_RST_BUS_EHCI] = { 0x02c0, 26 }, 873 [A23_RST_BUS_OHCI] = { 0x02c0, 29 }, 874 [A23_RST_BUS_I2C0] = { 0x02d8, 0 }, 875 [A23_RST_BUS_I2C1] = { 0x02d8, 1 }, 876 [A23_RST_BUS_I2C2] = { 0x02d8, 2 }, 877 }; 878 879 /* A64 */ 880 881 #define A64_RST_USB_PHY0 0 882 #define A64_RST_USB_PHY1 1 883 884 #define A64_RST_BUS_MMC0 8 885 #define A64_RST_BUS_MMC1 9 886 #define A64_RST_BUS_MMC2 10 887 #define A64_RST_BUS_EMAC 13 888 #define A64_RST_BUS_EHCI0 19 889 #define A64_RST_BUS_EHCI1 20 890 #define A64_RST_BUS_OHCI0 21 891 #define A64_RST_BUS_OHCI1 22 892 #define A64_RST_BUS_THS 38 893 #define A64_RST_BUS_I2C0 42 894 #define A64_RST_BUS_I2C1 43 895 #define A64_RST_BUS_I2C2 44 896 #define A64_RST_BUS_UART0 46 897 #define A64_RST_BUS_UART1 47 898 #define A64_RST_BUS_UART2 48 899 #define A64_RST_BUS_UART3 49 900 #define A64_RST_BUS_UART4 50 901 902 const struct sxiccmu_ccu_bit sun50i_a64_resets[] = { 903 [A64_RST_USB_PHY0] = { 0x00cc, 0 }, 904 [A64_RST_USB_PHY1] = { 0x00cc, 1 }, 905 [A64_RST_BUS_MMC0] = { 0x02c0, 8 }, 906 [A64_RST_BUS_MMC1] = { 0x02c0, 9 }, 907 [A64_RST_BUS_MMC2] = { 0x02c0, 10 }, 908 [A64_RST_BUS_EMAC] = { 0x02c0, 17 }, 909 [A64_RST_BUS_EHCI0] = { 0x02c0, 24 }, 910 [A64_RST_BUS_EHCI1] = { 0x02c0, 25 }, 911 [A64_RST_BUS_OHCI0] = { 0x02c0, 28 }, 912 [A64_RST_BUS_OHCI1] = { 0x02c0, 29 }, 913 [A64_RST_BUS_THS] = { 0x02d0, 8 }, 914 [A64_RST_BUS_I2C0] = { 0x02d8, 0 }, 915 [A64_RST_BUS_I2C1] = { 0x02d8, 1 }, 916 [A64_RST_BUS_I2C2] = { 0x02d8, 2 }, 917 [A64_RST_BUS_UART0] = { 0x02d8, 16 }, 918 [A64_RST_BUS_UART1] = { 0x02d8, 17 }, 919 [A64_RST_BUS_UART2] = { 0x02d8, 18 }, 920 [A64_RST_BUS_UART3] = { 0x02d8, 19 }, 921 [A64_RST_BUS_UART4] = { 0x02d8, 20 }, 922 }; 923 924 /* A80 */ 925 926 #define A80_RST_BUS_MMC 4 927 #define A80_RST_BUS_GMAC 17 928 #define A80_RST_BUS_I2C0 40 929 #define A80_RST_BUS_I2C1 41 930 #define A80_RST_BUS_I2C2 42 931 #define A80_RST_BUS_I2C3 43 932 #define A80_RST_BUS_I2C4 44 933 #define A80_RST_BUS_UART0 45 934 #define A80_RST_BUS_UART1 46 935 #define A80_RST_BUS_UART2 47 936 #define A80_RST_BUS_UART3 48 937 #define A80_RST_BUS_UART4 49 938 #define A80_RST_BUS_UART5 50 939 940 const struct sxiccmu_ccu_bit sun9i_a80_resets[] = { 941 [A80_RST_BUS_MMC] = { 0x05a0, 8 }, 942 [A80_RST_BUS_GMAC] = { 0x05a4, 17 }, 943 [A80_RST_BUS_I2C0] = { 0x05b4, 0 }, 944 [A80_RST_BUS_I2C1] = { 0x05b4, 1 }, 945 [A80_RST_BUS_I2C2] = { 0x05b4, 2 }, 946 [A80_RST_BUS_I2C3] = { 0x05b4, 3 }, 947 [A80_RST_BUS_I2C4] = { 0x05b4, 4 }, 948 [A80_RST_BUS_UART0] = { 0x05b4, 16 }, 949 [A80_RST_BUS_UART1] = { 0x05b4, 17 }, 950 [A80_RST_BUS_UART2] = { 0x05b4, 18 }, 951 [A80_RST_BUS_UART3] = { 0x05b4, 19 }, 952 [A80_RST_BUS_UART4] = { 0x05b4, 20 }, 953 [A80_RST_BUS_UART5] = { 0x05b4, 21 }, 954 }; 955 956 #define A80_USB_RST_HCI0 0 957 #define A80_USB_RST_HCI1 1 958 #define A80_USB_RST_HCI2 2 959 960 #define A80_USB_RST_HCI0_PHY 3 961 #define A80_USB_RST_HCI1_HSIC 4 962 #define A80_USB_RST_HCI1_PHY 5 963 #define A80_USB_RST_HCI2_HSIC 6 964 #define A80_USB_RST_HCI2_UTMIPHY 7 965 966 const struct sxiccmu_ccu_bit sun9i_a80_usb_resets[] = { 967 [A80_USB_RST_HCI0] = { 0x0000, 17 }, 968 [A80_USB_RST_HCI1] = { 0x0000, 18 }, 969 [A80_USB_RST_HCI2] = { 0x0000, 19 }, 970 [A80_USB_RST_HCI0_PHY] = { 0x0004, 17 }, 971 [A80_USB_RST_HCI1_HSIC]= { 0x0004, 18 }, 972 [A80_USB_RST_HCI1_PHY]= { 0x0004, 19 }, /* Undocumented */ 973 [A80_USB_RST_HCI2_HSIC]= { 0x0004, 20 }, /* Undocumented */ 974 [A80_USB_RST_HCI2_UTMIPHY] = { 0x0004, 21 }, 975 }; 976 977 const struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = { 978 { 0x0000, 18 }, 979 { 0x0004, 18 }, 980 { 0x0008, 18 }, 981 { 0x000c, 18 }, 982 }; 983 984 /* D1 */ 985 986 #define D1_RST_BUS_MMC0 15 987 #define D1_RST_BUS_MMC1 16 988 #define D1_RST_BUS_MMC2 17 989 #define D1_RST_BUS_UART0 18 990 #define D1_RST_BUS_UART1 19 991 #define D1_RST_BUS_UART2 20 992 #define D1_RST_BUS_UART3 21 993 #define D1_RST_BUS_UART4 22 994 #define D1_RST_BUS_UART5 23 995 #define D1_RST_BUS_EMAC 30 996 #define D1_RST_USB_PHY0 40 997 #define D1_RST_USB_PHY1 41 998 #define D1_RST_BUS_OHCI0 42 999 #define D1_RST_BUS_OHCI1 43 1000 #define D1_RST_BUS_EHCI0 44 1001 #define D1_RST_BUS_EHCI1 45 1002 1003 const struct sxiccmu_ccu_bit sun20i_d1_resets[] = { 1004 [D1_RST_BUS_MMC0] = { 0x084c, 16 }, 1005 [D1_RST_BUS_MMC1] = { 0x084c, 17 }, 1006 [D1_RST_BUS_MMC2] = { 0x084c, 18 }, 1007 [D1_RST_BUS_UART0] = { 0x090c, 16 }, 1008 [D1_RST_BUS_UART1] = { 0x090c, 17 }, 1009 [D1_RST_BUS_UART2] = { 0x090c, 18 }, 1010 [D1_RST_BUS_UART3] = { 0x090c, 19 }, 1011 [D1_RST_BUS_UART4] = { 0x090c, 20 }, 1012 [D1_RST_BUS_UART5] = { 0x090c, 21 }, 1013 [D1_RST_BUS_EMAC] = { 0x097c, 16 }, 1014 [D1_RST_USB_PHY0] = { 0x0a70, 30 }, 1015 [D1_RST_USB_PHY1] = { 0x0a74, 30 }, 1016 [D1_RST_BUS_OHCI0] = { 0x0a8c, 16 }, 1017 [D1_RST_BUS_OHCI1] = { 0x0a8c, 17 }, 1018 [D1_RST_BUS_EHCI0] = { 0x0a8c, 20 }, 1019 [D1_RST_BUS_EHCI1] = { 0x0a8c, 21 }, 1020 }; 1021 1022 /* H3/H5 */ 1023 1024 #define H3_RST_USB_PHY0 0 1025 #define H3_RST_USB_PHY1 1 1026 #define H3_RST_USB_PHY2 2 1027 #define H3_RST_USB_PHY3 3 1028 1029 #define H3_RST_BUS_MMC0 7 1030 #define H3_RST_BUS_MMC1 8 1031 #define H3_RST_BUS_MMC2 9 1032 1033 #define H3_RST_BUS_EMAC 12 1034 1035 #define H3_RST_BUS_EHCI0 18 1036 #define H3_RST_BUS_EHCI1 19 1037 #define H3_RST_BUS_EHCI2 20 1038 #define H3_RST_BUS_EHCI3 21 1039 #define H3_RST_BUS_OHCI0 22 1040 #define H3_RST_BUS_OHCI1 23 1041 #define H3_RST_BUS_OHCI2 24 1042 #define H3_RST_BUS_OHCI3 25 1043 #define H3_RST_BUS_EPHY 39 1044 #define H3_RST_BUS_THS 42 1045 #define H3_RST_BUS_I2C0 46 1046 #define H3_RST_BUS_I2C1 47 1047 #define H3_RST_BUS_I2C2 48 1048 #define H3_RST_BUS_UART0 49 1049 #define H3_RST_BUS_UART1 50 1050 #define H3_RST_BUS_UART2 51 1051 #define H3_RST_BUS_UART3 52 1052 1053 const struct sxiccmu_ccu_bit sun8i_h3_resets[] = { 1054 [H3_RST_USB_PHY0] = { 0x00cc, 0 }, 1055 [H3_RST_USB_PHY1] = { 0x00cc, 1 }, 1056 [H3_RST_USB_PHY2] = { 0x00cc, 2 }, 1057 [H3_RST_USB_PHY3] = { 0x00cc, 3 }, 1058 [H3_RST_BUS_MMC0] = { 0x02c0, 8 }, 1059 [H3_RST_BUS_MMC1] = { 0x02c0, 9 }, 1060 [H3_RST_BUS_MMC2] = { 0x02c0, 10 }, 1061 [H3_RST_BUS_EMAC] = { 0x02c0, 17 }, 1062 [H3_RST_BUS_EHCI0] = { 0x02c0, 24 }, 1063 [H3_RST_BUS_EHCI1] = { 0x02c0, 25 }, 1064 [H3_RST_BUS_EHCI2] = { 0x02c0, 26 }, 1065 [H3_RST_BUS_EHCI3] = { 0x02c0, 27 }, 1066 [H3_RST_BUS_OHCI0] = { 0x02c0, 28 }, 1067 [H3_RST_BUS_OHCI1] = { 0x02c0, 29 }, 1068 [H3_RST_BUS_OHCI2] = { 0x02c0, 30 }, 1069 [H3_RST_BUS_OHCI3] = { 0x02c0, 31 }, 1070 [H3_RST_BUS_EPHY] = { 0x02c8, 2 }, 1071 [H3_RST_BUS_THS] = { 0x02d0, 8 }, 1072 [H3_RST_BUS_I2C0] = { 0x02d8, 0 }, 1073 [H3_RST_BUS_I2C1] = { 0x02d8, 1 }, 1074 [H3_RST_BUS_I2C2] = { 0x02d8, 2 }, 1075 [H3_RST_BUS_UART0] = { 0x02d8, 16 }, 1076 [H3_RST_BUS_UART1] = { 0x02d8, 17 }, 1077 [H3_RST_BUS_UART2] = { 0x02d8, 18 }, 1078 [H3_RST_BUS_UART3] = { 0x02d8, 19 }, 1079 }; 1080 1081 #define H3_R_RST_APB0_RSB 2 1082 #define H3_R_RST_APB0_I2C 5 1083 1084 const struct sxiccmu_ccu_bit sun8i_h3_r_resets[] = { 1085 [H3_R_RST_APB0_RSB] = { 0x00b0, 3 }, 1086 [H3_R_RST_APB0_I2C] = { 0x00b0, 6 }, 1087 }; 1088 1089 /* H6 */ 1090 1091 #define H6_RST_BUS_MMC0 18 1092 #define H6_RST_BUS_MMC1 19 1093 #define H6_RST_BUS_MMC2 20 1094 #define H6_RST_BUS_UART0 21 1095 #define H6_RST_BUS_UART1 22 1096 #define H6_RST_BUS_UART2 23 1097 #define H6_RST_BUS_UART3 24 1098 #define H6_RST_BUS_EMAC 33 1099 #define H6_RST_USB_PHY0 44 1100 #define H6_RST_USB_PHY1 45 1101 #define H6_RST_USB_PHY3 46 1102 #define H6_RST_BUS_OHCI0 48 1103 #define H6_RST_BUS_OHCI3 49 1104 #define H6_RST_BUS_EHCI0 50 1105 #define H6_RST_BUS_EHCI3 52 1106 1107 const struct sxiccmu_ccu_bit sun50i_h6_resets[] = { 1108 [H6_RST_BUS_MMC0] = { 0x084c, 16 }, 1109 [H6_RST_BUS_MMC1] = { 0x084c, 17 }, 1110 [H6_RST_BUS_MMC2] = { 0x084c, 18 }, 1111 [H6_RST_BUS_UART0] = { 0x090c, 16 }, 1112 [H6_RST_BUS_UART1] = { 0x090c, 17 }, 1113 [H6_RST_BUS_UART2] = { 0x090c, 18 }, 1114 [H6_RST_BUS_UART3] = { 0x090c, 19 }, 1115 [H6_RST_BUS_EMAC] = { 0x097c, 16 }, 1116 [H6_RST_USB_PHY0] = { 0x0a70, 30 }, 1117 [H6_RST_USB_PHY1] = { 0x0a74, 30 }, 1118 [H6_RST_USB_PHY3] = { 0x0a7c, 30 }, 1119 [H6_RST_BUS_OHCI0] = { 0x0a8c, 16 }, 1120 [H6_RST_BUS_OHCI3] = { 0x0a8c, 19 }, 1121 [H6_RST_BUS_EHCI0] = { 0x0a8c, 20 }, 1122 [H6_RST_BUS_EHCI3] = { 0x0a8c, 23 }, 1123 }; 1124 1125 #define H6_R_RST_APB2_I2C 4 1126 #define H6_R_RST_APB2_RSB 7 1127 1128 const struct sxiccmu_ccu_bit sun50i_h6_r_resets[] = { 1129 [H6_R_RST_APB2_I2C] = { 0x019c, 16 }, 1130 [H6_R_RST_APB2_RSB] = { 0x01bc, 16 }, 1131 }; 1132 1133 /* H616 */ 1134 1135 #define H616_RST_BUS_MMC0 14 1136 #define H616_RST_BUS_MMC1 15 1137 #define H616_RST_BUS_MMC2 16 1138 #define H616_RST_BUS_UART0 17 1139 #define H616_RST_BUS_UART1 18 1140 #define H616_RST_BUS_UART2 19 1141 #define H616_RST_BUS_UART3 20 1142 #define H616_RST_BUS_UART4 21 1143 #define H616_RST_BUS_UART5 22 1144 #define H616_RST_BUS_I2C0 23 1145 #define H616_RST_BUS_I2C1 24 1146 #define H616_RST_BUS_I2C2 25 1147 #define H616_RST_BUS_I2C3 26 1148 #define H616_RST_BUS_I2C4 27 1149 #define H616_RST_BUS_EMAC0 30 1150 #define H616_RST_BUS_EMAC1 31 1151 #define H616_RST_USB_PHY0 38 1152 #define H616_RST_USB_PHY1 39 1153 #define H616_RST_USB_PHY2 40 1154 #define H616_RST_USB_PHY3 41 1155 #define H616_RST_BUS_OHCI0 42 1156 #define H616_RST_BUS_OHCI1 43 1157 #define H616_RST_BUS_OHCI2 44 1158 #define H616_RST_BUS_OHCI3 45 1159 #define H616_RST_BUS_EHCI0 46 1160 #define H616_RST_BUS_EHCI1 47 1161 #define H616_RST_BUS_EHCI2 48 1162 #define H616_RST_BUS_EHCI3 49 1163 1164 struct sxiccmu_ccu_bit sun50i_h616_resets[] = { 1165 [H616_RST_BUS_MMC0] = { 0x084c, 16 }, 1166 [H616_RST_BUS_MMC1] = { 0x084c, 17 }, 1167 [H616_RST_BUS_MMC2] = { 0x084c, 18 }, 1168 [H616_RST_BUS_UART0] = { 0x090c, 16 }, 1169 [H616_RST_BUS_UART1] = { 0x090c, 17 }, 1170 [H616_RST_BUS_UART2] = { 0x090c, 18 }, 1171 [H616_RST_BUS_UART3] = { 0x090c, 19 }, 1172 [H616_RST_BUS_UART4] = { 0x090c, 20 }, 1173 [H616_RST_BUS_UART5] = { 0x090c, 21 }, 1174 [H616_RST_BUS_I2C0] = { 0x091c, 16 }, 1175 [H616_RST_BUS_I2C1] = { 0x091c, 17 }, 1176 [H616_RST_BUS_I2C2] = { 0x091c, 18 }, 1177 [H616_RST_BUS_I2C3] = { 0x091c, 19 }, 1178 [H616_RST_BUS_I2C4] = { 0x091c, 20 }, 1179 [H616_RST_BUS_EMAC0] = { 0x097c, 16 }, 1180 [H616_RST_BUS_EMAC1] = { 0x097c, 17 }, 1181 [H616_RST_USB_PHY0] = { 0x0a70, 30 }, 1182 [H616_RST_USB_PHY1] = { 0x0a74, 30 }, 1183 [H616_RST_USB_PHY2] = { 0x0a78, 30 }, 1184 [H616_RST_USB_PHY3] = { 0x0a7c, 30 }, 1185 [H616_RST_BUS_OHCI0] = { 0x0a8c, 16 }, 1186 [H616_RST_BUS_OHCI1] = { 0x0a8c, 17 }, 1187 [H616_RST_BUS_OHCI2] = { 0x0a8c, 18 }, 1188 [H616_RST_BUS_OHCI3] = { 0x0a8c, 19 }, 1189 [H616_RST_BUS_EHCI0] = { 0x0a8c, 20 }, 1190 [H616_RST_BUS_EHCI1] = { 0x0a8c, 21 }, 1191 [H616_RST_BUS_EHCI2] = { 0x0a8c, 22 }, 1192 [H616_RST_BUS_EHCI3] = { 0x0a8c, 23 }, 1193 }; 1194 1195 #define H616_R_RST_APB2_I2C 4 1196 #define H616_R_RST_APB2_RSB 7 1197 1198 struct sxiccmu_ccu_bit sun50i_h616_r_resets[] = { 1199 [H616_R_RST_APB2_I2C] = { 0x019c, 16 }, 1200 [H616_R_RST_APB2_RSB] = { 0x01bc, 16 }, 1201 }; 1202 1203 /* R40 */ 1204 1205 #define R40_RST_USB_PHY0 0 1206 #define R40_RST_USB_PHY1 1 1207 #define R40_RST_USB_PHY2 2 1208 1209 #define R40_RST_BUS_MMC0 8 1210 #define R40_RST_BUS_MMC1 9 1211 #define R40_RST_BUS_MMC2 10 1212 #define R40_RST_BUS_MMC3 11 1213 #define R40_RST_BUS_SATA 21 1214 #define R40_RST_BUS_EHCI0 23 1215 #define R40_RST_BUS_EHCI1 24 1216 #define R40_RST_BUS_EHCI2 25 1217 #define R40_RST_BUS_OHCI0 26 1218 #define R40_RST_BUS_OHCI1 27 1219 #define R40_RST_BUS_OHCI2 28 1220 #define R40_RST_BUS_GMAC 40 1221 #define R40_RST_BUS_THS 59 1222 #define R40_RST_BUS_I2C0 64 1223 #define R40_RST_BUS_I2C1 65 1224 #define R40_RST_BUS_I2C2 66 1225 #define R40_RST_BUS_I2C3 67 1226 #define R40_RST_BUS_I2C4 72 1227 #define R40_RST_BUS_UART0 73 1228 #define R40_RST_BUS_UART1 74 1229 #define R40_RST_BUS_UART2 75 1230 #define R40_RST_BUS_UART3 76 1231 #define R40_RST_BUS_UART4 77 1232 #define R40_RST_BUS_UART5 78 1233 #define R40_RST_BUS_UART6 79 1234 #define R40_RST_BUS_UART7 80 1235 1236 const struct sxiccmu_ccu_bit sun8i_r40_resets[] = { 1237 [R40_RST_USB_PHY0] = { 0x00cc, 0 }, 1238 [R40_RST_USB_PHY1] = { 0x00cc, 1 }, 1239 [R40_RST_USB_PHY2] = { 0x00cc, 2 }, 1240 [R40_RST_BUS_MMC0] = { 0x02c0, 8 }, 1241 [R40_RST_BUS_MMC1] = { 0x02c0, 9 }, 1242 [R40_RST_BUS_MMC2] = { 0x02c0, 10 }, 1243 [R40_RST_BUS_MMC3] = { 0x02c0, 11 }, 1244 [R40_RST_BUS_SATA] = { 0x02c0, 24 }, 1245 [R40_RST_BUS_EHCI0] = { 0x02c0, 26 }, 1246 [R40_RST_BUS_EHCI1] = { 0x02c0, 27 }, 1247 [R40_RST_BUS_EHCI2] = { 0x02c0, 28 }, 1248 [R40_RST_BUS_OHCI0] = { 0x02c0, 29 }, 1249 [R40_RST_BUS_OHCI1] = { 0x02c0, 30 }, 1250 [R40_RST_BUS_OHCI2] = { 0x02c0, 31 }, 1251 [R40_RST_BUS_GMAC] = { 0x02c4, 17 }, 1252 [R40_RST_BUS_THS] = { 0x02d0, 8 }, 1253 [R40_RST_BUS_I2C0] = { 0x02d8, 0 }, 1254 [R40_RST_BUS_I2C1] = { 0x02d8, 1 }, 1255 [R40_RST_BUS_I2C2] = { 0x02d8, 2 }, 1256 [R40_RST_BUS_I2C3] = { 0x02d8, 3 }, 1257 [R40_RST_BUS_I2C4] = { 0x02d8, 15 }, 1258 [R40_RST_BUS_UART0] = { 0x02d8, 16 }, 1259 [R40_RST_BUS_UART1] = { 0x02d8, 17 }, 1260 [R40_RST_BUS_UART2] = { 0x02d8, 18 }, 1261 [R40_RST_BUS_UART3] = { 0x02d8, 19 }, 1262 [R40_RST_BUS_UART4] = { 0x02d8, 20 }, 1263 [R40_RST_BUS_UART5] = { 0x02d8, 21 }, 1264 [R40_RST_BUS_UART6] = { 0x02d8, 22 }, 1265 [R40_RST_BUS_UART7] = { 0x02d8, 23 }, 1266 }; 1267 1268 /* V3s */ 1269 1270 #define V3S_RST_USB_PHY0 0 1271 1272 #define V3S_RST_BUS_MMC0 7 1273 #define V3S_RST_BUS_MMC1 8 1274 #define V3S_RST_BUS_MMC2 9 1275 #define V3S_RST_BUS_EMAC 12 1276 #define V3S_RST_BUS_EHCI0 18 1277 #define V3S_RST_BUS_OHCI0 22 1278 #define V3S_RST_BUS_EPHY 39 1279 #define V3S_RST_BUS_I2C0 46 1280 #define V3S_RST_BUS_I2C1 47 1281 #define V3S_RST_BUS_UART0 49 1282 #define V3S_RST_BUS_UART1 50 1283 #define V3S_RST_BUS_UART2 51 1284 1285 const struct sxiccmu_ccu_bit sun8i_v3s_resets[] = { 1286 [V3S_RST_USB_PHY0] = { 0x00cc, 0 }, 1287 [V3S_RST_BUS_OHCI0] = { 0x02c0, 29 }, 1288 [V3S_RST_BUS_EHCI0] = { 0x02c0, 26 }, 1289 [V3S_RST_BUS_EMAC] = { 0x02c0, 17 }, 1290 [V3S_RST_BUS_MMC2] = { 0x02c0, 10 }, 1291 [V3S_RST_BUS_MMC1] = { 0x02c0, 9 }, 1292 [V3S_RST_BUS_MMC0] = { 0x02c0, 8 }, 1293 [V3S_RST_BUS_EPHY] = { 0x02c8, 2 }, 1294 [V3S_RST_BUS_UART2] = { 0x02d8, 18 }, 1295 [V3S_RST_BUS_UART1] = { 0x02d8, 17 }, 1296 [V3S_RST_BUS_UART0] = { 0x02d8, 16 }, 1297 [V3S_RST_BUS_I2C1] = { 0x02d8, 1 }, 1298 [V3S_RST_BUS_I2C0] = { 0x02d8, 0 }, 1299 }; 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