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Searched defs:RC (Results 1 – 25 of 289) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp289 -> BT::RegisterCell { in evaluate()
404 RegisterCell RC = eADD(rc(1), lo(M, W0)); in evaluate() local
409 RegisterCell RC = eADD(rc(1), lo(M, W0)); in evaluate() local
414 RegisterCell RC = eADD(rc(1), lo(M, W0)); in evaluate() local
483 RegisterCell RC = eADD(rc(1), lo(M, W0)); in evaluate() local
684 RegisterCell RC = rc(1); in evaluate() local
689 RegisterCell RC = rc(1); in evaluate() local
694 RegisterCell RC = rc(1); in evaluate() local
798 RegisterCell RC(WR); in evaluate() local
894 RegisterCell RC(W0); in evaluate() local
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H A DHexagonConstPropagation.cpp1081 LatticeCell &RC) { in getCell()
1391 LatticeCell RC; in evaluateANDrr() local
1407 LatticeCell RC; in evaluateANDri() local
1458 LatticeCell RC; in evaluateORrr() local
1474 LatticeCell RC; in evaluateORri() local
1523 LatticeCell RC; in evaluateXORrr() local
1942 LatticeCell RC; in evaluate() local
1964 LatticeCell RC; in evaluate() local
2637 LatticeCell RC; in evaluateHexLogical() local
2694 LatticeCell RC = Outputs.get(DefR.Reg); in evaluateHexCondMove() local
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H A DHexagonBitSimplify.cpp358 bool HexagonBitSimplify::isZero(const BitTracker::RegisterCell &RC, in isZero()
437 const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg); in getSubregMask() local
929 auto *RC = MRI.getRegClass(RR.Reg); in getFinalVRegClass() local
1586 const BitTracker::RegisterCell &RC = BT.lookup(R); in findMatch() local
1721 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg); in propagateRegCopy() local
1731 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg); in propagateRegCopy() local
1958 const BitTracker::RegisterCell &RC = BT.lookup(RS.Reg); in genStoreUpperHalf() local
2003 const BitTracker::RegisterCell &RC = BT.lookup(RS.Reg); in genStoreImmediate() local
2765 const BitTracker::RegisterCell &RC = BT.lookup(RD.Reg); in processBlock() local
3005 const BitTracker::RegisterCell &RC = BTP->lookup(Reg); in isConst() local
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/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h186 static bool isSGPRClass(const TargetRegisterClass *RC) { in isSGPRClass()
198 static bool isVGPRClass(const TargetRegisterClass *RC) { in isVGPRClass()
203 static bool isAGPRClass(const TargetRegisterClass *RC) { in isAGPRClass()
208 bool isVectorSuperClass(const TargetRegisterClass *RC) const { in isVectorSuperClass()
213 bool isVSSuperClass(const TargetRegisterClass *RC) const { in isVSSuperClass()
218 static bool hasVGPRs(const TargetRegisterClass *RC) { in hasVGPRs()
223 static bool hasAGPRs(const TargetRegisterClass *RC) { in hasAGPRs()
228 static bool hasSGPRs(const TargetRegisterClass *RC) { in hasSGPRs()
233 static bool hasVectorRegisters(const TargetRegisterClass *RC) { in hasVectorRegisters()
289 bool isDivergentRegClass(const TargetRegisterClass *RC) const override { in isDivergentRegClass()
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h78 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
94 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
101 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
111 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
127 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost()
135 unsigned getLastCostChange(const TargetRegisterClass *RC) const { in getLastCostChange()
H A DTargetRegisterInfo.h124 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
129 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
136 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
141 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
279 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
285 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
291 Align getSpillAlign(const TargetRegisterClass &RC) const { in getSpillAlign()
807 getCrossCopyRegClass(const TargetRegisterClass *RC) const { in getCrossCopyRegClass()
816 getLargestLegalSuperClass(const TargetRegisterClass *RC, in getLargestLegalSuperClass()
829 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, in getRegPressureLimit()
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/openbsd/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExplicitLocals.cpp88 static unsigned getDropOpcode(const TargetRegisterClass *RC) { in getDropOpcode()
107 static unsigned getLocalGetOpcode(const TargetRegisterClass *RC) { in getLocalGetOpcode()
126 static unsigned getLocalSetOpcode(const TargetRegisterClass *RC) { in getLocalSetOpcode()
145 static unsigned getLocalTeeOpcode(const TargetRegisterClass *RC) { in getLocalTeeOpcode()
164 static MVT typeForRegClass(const TargetRegisterClass *RC) { in typeForRegClass()
274 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
307 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
379 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
/openbsd/gnu/llvm/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp72 void addRegisterClass(const CodeGenRegisterClass *RC) { in addRegisterClass()
170 const CodeGenRegisterClass *RC, const Twine &Kind, in visitRegisterBankClasses()
221 for (const auto &RC : Bank.register_classes()) in emitBaseClassImplementation() local
228 for (const auto &RC : RCs) { in emitBaseClassImplementation() local
244 const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegsSize(); in emitBaseClassImplementation() local
285 for (const CodeGenRegisterClass *RC : in run() local
289 [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) { in run()
H A DRegisterInfoEmitter.cpp146 for (const auto &RC : RegisterClasses) in runEnums() local
1047 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1083 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1211 for (const auto &RC : RegisterClasses) { in runTargetHeader() local
1248 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1261 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1349 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1377 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1392 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1457 for (const auto &RC : RegisterClasses) in runTargetDesc() local
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H A DCodeGenRegisters.cpp982 CodeGenRegisterClass &RC = *I; in computeSubClasses() local
1006 for (auto &RC : RegClasses) { in computeSubClasses() local
1022 for (auto &RC : RegClasses) in computeSubClasses() local
1050 for (auto &RC : RegClasses) in getMatchingSubClassWithSubRegs() local
1060 for (auto &RC: RegClasses) { in getMatchingSubClassWithSubRegs() local
1261 for (auto &RC : RegClasses) in CodeGenRegBank() local
1950 for (auto &RC : RegClasses) { in computeRegUnitSets() local
2054 for (auto &RC : RegClasses) { in computeRegUnitSets() local
2368 CodeGenRegisterClass *RC = &*I; in computeInferredRegisterClasses() local
2406 for (const auto &RC : getRegClasses()) { in getRegClassForRegister() local
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/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp606 const TargetRegisterClass *RC = in SelectLoad() local
987 auto RC = MRI.getRegClass(SrcReg); in SelectFPTrunc() local
1174 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1225 auto RC = MRI.getRegClass(SrcReg); in SelectFPToI() local
1280 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1442 const TargetRegisterClass *RC = in processCallArgs() local
1454 const TargetRegisterClass *RC = in processCallArgs() local
1768 const TargetRegisterClass *RC = in SelectRet() local
1925 const TargetRegisterClass *RC = in SelectIntExt() local
2000 const TargetRegisterClass *RC; in PPCMaterializeFP() local
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/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
188 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
264 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
317 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
383 const TargetRegisterClass *RC = in expandExtractElementF64() local
421 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? in emitPrologue() local
719 const TargetRegisterClass *RC = in emitEpilogue() local
895 const TargetRegisterClass &RC = STI.isGP64bit() ? in determineCalleeSaves() local
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H A DMipsMachineFunction.cpp78 const TargetRegisterClass *RC; in initGlobalBaseReg() local
159 const TargetRegisterClass &RC = in createEhDataRegsFI() local
174 const TargetRegisterClass &RC = Mips::GPR32RegClass; in createISRRegFI() local
201 const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI()
H A DMipsInstrInfo.h139 const TargetRegisterClass *RC, in storeRegToStackSlot()
147 int FrameIndex, const TargetRegisterClass *RC, in loadRegFromStackSlot()
/openbsd/gnu/llvm/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp45 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createLRSpillSlot() local
63 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createFPSpillSlot() local
76 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createEHSpillSlot() local
/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DSwiftErrorValueTracking.cpp36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVReg() local
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVRegDefAt() local
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in createEntriesInEntryBlock() local
240 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in propagateVRegs() local
H A DLiveStacks.cpp54 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
79 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
H A DRegisterBank.cpp35 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify() local
105 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print() local
H A DRegAllocBase.cpp127 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg()); in allocatePhysRegs() local
184 const TargetRegisterClass &RC = *MRI->getRegClass(Reg); in enqueue() local
H A DTargetRegisterInfo.cpp219 for (const TargetRegisterClass* RC : regclasses()) { in getMinimalPhysRegClass() local
237 for (const TargetRegisterClass *RC : regclasses()) { in getMinimalPhysRegClassLLT() local
249 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
353 const TargetRegisterClass *RC = in getCommonSuperRegClass() local
504 const TargetRegisterClass *RC{}; in getRegSizeInBits() local
525 const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, in getCoveringSubRegIndexes()
/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp59 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue() local
359 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta() local
363 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta() local
477 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
488 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
/openbsd/gnu/llvm/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName()
73 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { in getNVPTXRegClassStr()
/openbsd/gnu/llvm/llvm/include/llvm/IR/
H A DConstantFolder.h46 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
58 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
71 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
100 auto *RC = dyn_cast<Constant>(RHS); in FoldICmp() local
/openbsd/gnu/llvm/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp151 wasm::ValType WebAssembly::regClassToValType(unsigned RC) { in regClassToValType()
172 wasm::ValType WebAssembly::regClassToValType(const TargetRegisterClass *RC) { in regClassToValType()
/openbsd/gnu/llvm/llvm/include/llvm/Analysis/
H A DTargetFolder.h57 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
69 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
82 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
104 auto *RC = dyn_cast<Constant>(RHS); in FoldICmp() local

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