1 /*
2  * STM32L4X5 RCC (Reset and clock control)
3  *
4  * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5  * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
10  * See the COPYING file in the top-level directory.
11  *
12  * The reference used is the STMicroElectronics RM0351 Reference manual
13  * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
14  *
15  * Inspired by the BCM2835 CPRMAN clock manager implementation by Luc Michel.
16  */
17 
18 #ifndef HW_STM32L4X5_RCC_INTERNALS_H
19 #define HW_STM32L4X5_RCC_INTERNALS_H
20 
21 #include "hw/registerfields.h"
22 #include "hw/misc/stm32l4x5_rcc.h"
23 
24 #define TYPE_RCC_CLOCK_MUX "stm32l4x5-rcc-clock-mux"
25 #define TYPE_RCC_PLL "stm32l4x5-rcc-pll"
26 
27 OBJECT_DECLARE_SIMPLE_TYPE(RccClockMuxState, RCC_CLOCK_MUX)
28 OBJECT_DECLARE_SIMPLE_TYPE(RccPllState, RCC_PLL)
29 
30 /* Register map */
31 REG32(CR, 0x00)
32     FIELD(CR, PLLSAI2RDY, 29, 1)
33     FIELD(CR, PLLSAI2ON, 28, 1)
34     FIELD(CR, PLLSAI1RDY, 27, 1)
35     FIELD(CR, PLLSAI1ON, 26, 1)
36     FIELD(CR, PLLRDY, 25, 1)
37     FIELD(CR, PLLON, 24, 1)
38     FIELD(CR, CSSON, 19, 1)
39     FIELD(CR, HSEBYP, 18, 1)
40     FIELD(CR, HSERDY, 17, 1)
41     FIELD(CR, HSEON, 16, 1)
42     FIELD(CR, HSIASFS, 11, 1)
43     FIELD(CR, HSIRDY, 10, 1)
44     FIELD(CR, HSIKERON, 9, 1)
45     FIELD(CR, HSION, 8, 1)
46     FIELD(CR, MSIRANGE, 4, 4)
47     FIELD(CR, MSIRGSEL, 3, 1)
48     FIELD(CR, MSIPLLEN, 2, 1)
49     FIELD(CR, MSIRDY, 1, 1)
50     FIELD(CR, MSION, 0, 1)
51 REG32(ICSCR, 0x04)
52     FIELD(ICSCR, HSITRIM, 24, 7)
53     FIELD(ICSCR, HSICAL, 16, 8)
54     FIELD(ICSCR, MSITRIM, 8, 8)
55     FIELD(ICSCR, MSICAL, 0, 8)
56 REG32(CFGR, 0x08)
57     FIELD(CFGR, MCOPRE, 28, 3)
58     /* MCOSEL[2:0] only for STM32L475xx/476xx/486xx devices */
59     FIELD(CFGR, MCOSEL, 24, 3)
60     FIELD(CFGR, STOPWUCK, 15, 1)
61     FIELD(CFGR, PPRE2, 11, 3)
62     FIELD(CFGR, PPRE1, 8, 3)
63     FIELD(CFGR, HPRE, 4, 4)
64     FIELD(CFGR, SWS, 2, 2)
65     FIELD(CFGR, SW, 0, 2)
66 REG32(PLLCFGR, 0x0C)
67     FIELD(PLLCFGR, PLLPDIV, 27, 5)
68     FIELD(PLLCFGR, PLLR, 25, 2)
69     FIELD(PLLCFGR, PLLREN, 24, 1)
70     FIELD(PLLCFGR, PLLQ, 21, 2)
71     FIELD(PLLCFGR, PLLQEN, 20, 1)
72     FIELD(PLLCFGR, PLLP, 17, 1)
73     FIELD(PLLCFGR, PLLPEN, 16, 1)
74     FIELD(PLLCFGR, PLLN, 8, 7)
75     FIELD(PLLCFGR, PLLM, 4, 3)
76     FIELD(PLLCFGR, PLLSRC, 0, 2)
77 REG32(PLLSAI1CFGR, 0x10)
78     FIELD(PLLSAI1CFGR, PLLSAI1PDIV, 27, 5)
79     FIELD(PLLSAI1CFGR, PLLSAI1R, 25, 2)
80     FIELD(PLLSAI1CFGR, PLLSAI1REN, 24, 1)
81     FIELD(PLLSAI1CFGR, PLLSAI1Q, 21, 2)
82     FIELD(PLLSAI1CFGR, PLLSAI1QEN, 20, 1)
83     FIELD(PLLSAI1CFGR, PLLSAI1P, 17, 1)
84     FIELD(PLLSAI1CFGR, PLLSAI1PEN, 16, 1)
85     FIELD(PLLSAI1CFGR, PLLSAI1N, 8, 7)
86 REG32(PLLSAI2CFGR, 0x14)
87     FIELD(PLLSAI2CFGR, PLLSAI2PDIV, 27, 5)
88     FIELD(PLLSAI2CFGR, PLLSAI2R, 25, 2)
89     FIELD(PLLSAI2CFGR, PLLSAI2REN, 24, 1)
90     FIELD(PLLSAI2CFGR, PLLSAI2Q, 21, 2)
91     FIELD(PLLSAI2CFGR, PLLSAI2QEN, 20, 1)
92     FIELD(PLLSAI2CFGR, PLLSAI2P, 17, 1)
93     FIELD(PLLSAI2CFGR, PLLSAI2PEN, 16, 1)
94     FIELD(PLLSAI2CFGR, PLLSAI2N, 8, 7)
95 REG32(CIER, 0x18)
96     /* HSI48RDYIE: only on STM32L496xx/4A6xx devices */
97     FIELD(CIER, LSECSSIE, 9, 1)
98     FIELD(CIER, PLLSAI2RDYIE, 7, 1)
99     FIELD(CIER, PLLSAI1RDYIE, 6, 1)
100     FIELD(CIER, PLLRDYIE, 5, 1)
101     FIELD(CIER, HSERDYIE, 4, 1)
102     FIELD(CIER, HSIRDYIE, 3, 1)
103     FIELD(CIER, MSIRDYIE, 2, 1)
104     FIELD(CIER, LSERDYIE, 1, 1)
105     FIELD(CIER, LSIRDYIE, 0, 1)
106 REG32(CIFR, 0x1C)
107     /* HSI48RDYF: only on STM32L496xx/4A6xx devices */
108     FIELD(CIFR, LSECSSF, 9, 1)
109     FIELD(CIFR, CSSF, 8, 1)
110     FIELD(CIFR, PLLSAI2RDYF, 7, 1)
111     FIELD(CIFR, PLLSAI1RDYF, 6, 1)
112     FIELD(CIFR, PLLRDYF, 5, 1)
113     FIELD(CIFR, HSERDYF, 4, 1)
114     FIELD(CIFR, HSIRDYF, 3, 1)
115     FIELD(CIFR, MSIRDYF, 2, 1)
116     FIELD(CIFR, LSERDYF, 1, 1)
117     FIELD(CIFR, LSIRDYF, 0, 1)
118 REG32(CICR, 0x20)
119     /* HSI48RDYC: only on STM32L496xx/4A6xx devices */
120     FIELD(CICR, LSECSSC, 9, 1)
121     FIELD(CICR, CSSC, 8, 1)
122     FIELD(CICR, PLLSAI2RDYC, 7, 1)
123     FIELD(CICR, PLLSAI1RDYC, 6, 1)
124     FIELD(CICR, PLLRDYC, 5, 1)
125     FIELD(CICR, HSERDYC, 4, 1)
126     FIELD(CICR, HSIRDYC, 3, 1)
127     FIELD(CICR, MSIRDYC, 2, 1)
128     FIELD(CICR, LSERDYC, 1, 1)
129     FIELD(CICR, LSIRDYC, 0, 1)
130 REG32(AHB1RSTR, 0x28)
131 REG32(AHB2RSTR, 0x2C)
132 REG32(AHB3RSTR, 0x30)
133 REG32(APB1RSTR1, 0x38)
134 REG32(APB1RSTR2, 0x3C)
135 REG32(APB2RSTR, 0x40)
136 REG32(AHB1ENR, 0x48)
137     /* DMA2DEN: reserved for STM32L475xx */
138     FIELD(AHB1ENR, TSCEN, 16, 1)
139     FIELD(AHB1ENR, CRCEN, 12, 1)
140     FIELD(AHB1ENR, FLASHEN, 8, 1)
141     FIELD(AHB1ENR, DMA2EN, 1, 1)
142     FIELD(AHB1ENR, DMA1EN, 0, 1)
143 REG32(AHB2ENR, 0x4C)
144     FIELD(AHB2ENR, RNGEN, 18, 1)
145     /* HASHEN: reserved for STM32L475xx */
146     FIELD(AHB2ENR, AESEN, 16, 1)
147     /* DCMIEN: reserved for STM32L475xx */
148     FIELD(AHB2ENR, ADCEN, 13, 1)
149     FIELD(AHB2ENR, OTGFSEN, 12, 1)
150     /* GPIOIEN: reserved for STM32L475xx */
151     FIELD(AHB2ENR, GPIOHEN, 7, 1)
152     FIELD(AHB2ENR, GPIOGEN, 6, 1)
153     FIELD(AHB2ENR, GPIOFEN, 5, 1)
154     FIELD(AHB2ENR, GPIOEEN, 4, 1)
155     FIELD(AHB2ENR, GPIODEN, 3, 1)
156     FIELD(AHB2ENR, GPIOCEN, 2, 1)
157     FIELD(AHB2ENR, GPIOBEN, 1, 1)
158     FIELD(AHB2ENR, GPIOAEN, 0, 1)
159 REG32(AHB3ENR, 0x50)
160     FIELD(AHB3ENR, QSPIEN, 8, 1)
161     FIELD(AHB3ENR, FMCEN, 0, 1)
162 REG32(APB1ENR1, 0x58)
163     FIELD(APB1ENR1, LPTIM1EN, 31, 1)
164     FIELD(APB1ENR1, OPAMPEN, 30, 1)
165     FIELD(APB1ENR1, DAC1EN, 29, 1)
166     FIELD(APB1ENR1, PWREN, 28, 1)
167     FIELD(APB1ENR1, CAN2EN, 26, 1)
168     FIELD(APB1ENR1, CAN1EN, 25, 1)
169     /* CRSEN: reserved for STM32L475xx */
170     FIELD(APB1ENR1, I2C3EN, 23, 1)
171     FIELD(APB1ENR1, I2C2EN, 22, 1)
172     FIELD(APB1ENR1, I2C1EN, 21, 1)
173     FIELD(APB1ENR1, UART5EN, 20, 1)
174     FIELD(APB1ENR1, UART4EN, 19, 1)
175     FIELD(APB1ENR1, USART3EN, 18, 1)
176     FIELD(APB1ENR1, USART2EN, 17, 1)
177     FIELD(APB1ENR1, SPI3EN, 15, 1)
178     FIELD(APB1ENR1, SPI2EN, 14, 1)
179     FIELD(APB1ENR1, WWDGEN, 11, 1)
180     /* RTCAPBEN: reserved for STM32L475xx */
181     FIELD(APB1ENR1, LCDEN, 9, 1)
182     FIELD(APB1ENR1, TIM7EN, 5, 1)
183     FIELD(APB1ENR1, TIM6EN, 4, 1)
184     FIELD(APB1ENR1, TIM5EN, 3, 1)
185     FIELD(APB1ENR1, TIM4EN, 2, 1)
186     FIELD(APB1ENR1, TIM3EN, 1, 1)
187     FIELD(APB1ENR1, TIM2EN, 0, 1)
188 REG32(APB1ENR2, 0x5C)
189     FIELD(APB1ENR2, LPTIM2EN, 5, 1)
190     FIELD(APB1ENR2, SWPMI1EN, 2, 1)
191     /* I2C4EN: reserved for STM32L475xx */
192     FIELD(APB1ENR2, LPUART1EN, 0, 1)
193 REG32(APB2ENR, 0x60)
194     FIELD(APB2ENR, DFSDM1EN, 24, 1)
195     FIELD(APB2ENR, SAI2EN, 22, 1)
196     FIELD(APB2ENR, SAI1EN, 21, 1)
197     FIELD(APB2ENR, TIM17EN, 18, 1)
198     FIELD(APB2ENR, TIM16EN, 17, 1)
199     FIELD(APB2ENR, TIM15EN, 16, 1)
200     FIELD(APB2ENR, USART1EN, 14, 1)
201     FIELD(APB2ENR, TIM8EN, 13, 1)
202     FIELD(APB2ENR, SPI1EN, 12, 1)
203     FIELD(APB2ENR, TIM1EN, 11, 1)
204     FIELD(APB2ENR, SDMMC1EN, 10, 1)
205     FIELD(APB2ENR, FWEN, 7, 1)
206     FIELD(APB2ENR, SYSCFGEN, 0, 1)
207 REG32(AHB1SMENR, 0x68)
208 REG32(AHB2SMENR, 0x6C)
209 REG32(AHB3SMENR, 0x70)
210 REG32(APB1SMENR1, 0x78)
211 REG32(APB1SMENR2, 0x7C)
212 REG32(APB2SMENR, 0x80)
213 REG32(CCIPR, 0x88)
214     FIELD(CCIPR, DFSDM1SEL, 31, 1)
215     FIELD(CCIPR, SWPMI1SEL, 30, 1)
216     FIELD(CCIPR, ADCSEL, 28, 2)
217     FIELD(CCIPR, CLK48SEL, 26, 2)
218     FIELD(CCIPR, SAI2SEL, 24, 2)
219     FIELD(CCIPR, SAI1SEL, 22, 2)
220     FIELD(CCIPR, LPTIM2SEL, 20, 2)
221     FIELD(CCIPR, LPTIM1SEL, 18, 2)
222     FIELD(CCIPR, I2C3SEL, 16, 2)
223     FIELD(CCIPR, I2C2SEL, 14, 2)
224     FIELD(CCIPR, I2C1SEL, 12, 2)
225     FIELD(CCIPR, LPUART1SEL, 10, 2)
226     FIELD(CCIPR, UART5SEL, 8, 2)
227     FIELD(CCIPR, UART4SEL, 6, 2)
228     FIELD(CCIPR, USART3SEL, 4, 2)
229     FIELD(CCIPR, USART2SEL, 2, 2)
230     FIELD(CCIPR, USART1SEL, 0, 2)
231 REG32(BDCR, 0x90)
232     FIELD(BDCR, LSCOSEL, 25, 1)
233     FIELD(BDCR, LSCOEN, 24, 1)
234     FIELD(BDCR, BDRST, 16, 1)
235     FIELD(BDCR, RTCEN, 15, 1)
236     FIELD(BDCR, RTCSEL, 8, 2)
237     FIELD(BDCR, LSECSSD, 6, 1)
238     FIELD(BDCR, LSECSSON, 5, 1)
239     FIELD(BDCR, LSEDRV, 3, 2)
240     FIELD(BDCR, LSEBYP, 2, 1)
241     FIELD(BDCR, LSERDY, 1, 1)
242     FIELD(BDCR, LSEON, 0, 1)
243 REG32(CSR, 0x94)
244     FIELD(CSR, LPWRRSTF, 31, 1)
245     FIELD(CSR, WWDGRSTF, 30, 1)
246     FIELD(CSR, IWWGRSTF, 29, 1)
247     FIELD(CSR, SFTRSTF, 28, 1)
248     FIELD(CSR, BORRSTF, 27, 1)
249     FIELD(CSR, PINRSTF, 26, 1)
250     FIELD(CSR, OBLRSTF, 25, 1)
251     FIELD(CSR, FWRSTF, 24, 1)
252     FIELD(CSR, RMVF, 23, 1)
253     FIELD(CSR, MSISRANGE, 8, 4)
254     FIELD(CSR, LSIRDY, 1, 1)
255     FIELD(CSR, LSION, 0, 1)
256 /* CRRCR and CCIPR2 registers are present on L496/L4A6 devices only. */
257 
258 /* Read Only masks to prevent writes in unauthorized bits */
259 #define CR_READ_ONLY_MASK (R_CR_PLLSAI2RDY_MASK | \
260                            R_CR_PLLSAI1RDY_MASK | \
261                            R_CR_PLLRDY_MASK     | \
262                            R_CR_HSERDY_MASK     | \
263                            R_CR_HSIRDY_MASK     | \
264                            R_CR_MSIRDY_MASK)
265 #define CR_READ_SET_MASK (R_CR_CSSON_MASK | R_CR_MSIRGSEL_MASK)
266 #define ICSCR_READ_ONLY_MASK (R_ICSCR_HSICAL_MASK | R_ICSCR_MSICAL_MASK)
267 #define CFGR_READ_ONLY_MASK (R_CFGR_SWS_MASK)
268 #define CIFR_READ_ONLY_MASK (R_CIFR_LSECSSF_MASK     | \
269                              R_CIFR_CSSF_MASK        | \
270                              R_CIFR_PLLSAI2RDYF_MASK | \
271                              R_CIFR_PLLSAI1RDYF_MASK | \
272                              R_CIFR_PLLRDYF_MASK     | \
273                              R_CIFR_HSERDYF_MASK     | \
274                              R_CIFR_HSIRDYF_MASK     | \
275                              R_CIFR_MSIRDYF_MASK     | \
276                              R_CIFR_LSERDYF_MASK     | \
277                              R_CIFR_LSIRDYF_MASK)
278 #define CIFR_IRQ_MASK CIFR_READ_ONLY_MASK
279 #define APB2ENR_READ_SET_MASK (R_APB2ENR_FWEN_MASK)
280 #define BDCR_READ_ONLY_MASK (R_BDCR_LSECSSD_MASK | R_BDCR_LSERDY_MASK)
281 #define CSR_READ_ONLY_MASK (R_CSR_LPWRRSTF_MASK | \
282                             R_CSR_WWDGRSTF_MASK | \
283                             R_CSR_IWWGRSTF_MASK | \
284                             R_CSR_SFTRSTF_MASK  | \
285                             R_CSR_BORRSTF_MASK  | \
286                             R_CSR_PINRSTF_MASK  | \
287                             R_CSR_OBLRSTF_MASK  | \
288                             R_CSR_FWRSTF_MASK   | \
289                             R_CSR_LSIRDY_MASK)
290 
291 /* Pll Channels */
292 enum PllChannels {
293     RCC_PLL_CHANNEL_PLLSAI3CLK = 0,
294     RCC_PLL_CHANNEL_PLL48M1CLK = 1,
295     RCC_PLL_CHANNEL_PLLCLK = 2,
296 };
297 
298 enum PllSai1Channels {
299     RCC_PLLSAI1_CHANNEL_PLLSAI1CLK = 0,
300     RCC_PLLSAI1_CHANNEL_PLL48M2CLK = 1,
301     RCC_PLLSAI1_CHANNEL_PLLADC1CLK = 2,
302 };
303 
304 enum PllSai2Channels {
305     RCC_PLLSAI2_CHANNEL_PLLSAI2CLK = 0,
306     /* No Q channel */
307     RCC_PLLSAI2_CHANNEL_PLLADC2CLK = 2,
308 };
309 
310 typedef enum RccClockMuxSource {
311     RCC_CLOCK_MUX_SRC_GND = 0,
312     RCC_CLOCK_MUX_SRC_HSI,
313     RCC_CLOCK_MUX_SRC_HSE,
314     RCC_CLOCK_MUX_SRC_MSI,
315     RCC_CLOCK_MUX_SRC_LSI,
316     RCC_CLOCK_MUX_SRC_LSE,
317     RCC_CLOCK_MUX_SRC_SAI1_EXTCLK,
318     RCC_CLOCK_MUX_SRC_SAI2_EXTCLK,
319     RCC_CLOCK_MUX_SRC_PLL,
320     RCC_CLOCK_MUX_SRC_PLLSAI1,
321     RCC_CLOCK_MUX_SRC_PLLSAI2,
322     RCC_CLOCK_MUX_SRC_PLLSAI3,
323     RCC_CLOCK_MUX_SRC_PLL48M1,
324     RCC_CLOCK_MUX_SRC_PLL48M2,
325     RCC_CLOCK_MUX_SRC_PLLADC1,
326     RCC_CLOCK_MUX_SRC_PLLADC2,
327     RCC_CLOCK_MUX_SRC_SYSCLK,
328     RCC_CLOCK_MUX_SRC_HCLK,
329     RCC_CLOCK_MUX_SRC_PCLK1,
330     RCC_CLOCK_MUX_SRC_PCLK2,
331     RCC_CLOCK_MUX_SRC_HSE_OVER_32,
332     RCC_CLOCK_MUX_SRC_LCD_AND_RTC_COMMON,
333 
334     RCC_CLOCK_MUX_SRC_NUMBER,
335 } RccClockMuxSource;
336 
337 /* PLL init info */
338 typedef struct PllInitInfo {
339     const char *name;
340 
341     const char *channel_name[RCC_NUM_CHANNEL_PLL_OUT];
342     bool channel_exists[RCC_NUM_CHANNEL_PLL_OUT];
343     uint32_t default_channel_divider[RCC_NUM_CHANNEL_PLL_OUT];
344 
345     RccClockMuxSource src_mapping[RCC_NUM_CLOCK_MUX_SRC];
346 } PllInitInfo;
347 
348 static const PllInitInfo PLL_INIT_INFO[] = {
349     [RCC_PLL_PLL] = {
350         .name = "pll",
351         .channel_name = {
352             "pllsai3clk",
353             "pll48m1clk",
354             "pllclk"
355         },
356         .channel_exists = {
357             true, true, true
358         },
359         /* From PLLCFGR register documentation */
360         .default_channel_divider = {
361             7, 2, 2
362         }
363     },
364     [RCC_PLL_PLLSAI1] = {
365         .name = "pllsai1",
366         .channel_name = {
367             "pllsai1clk",
368             "pll48m2clk",
369             "plladc1clk"
370         },
371         .channel_exists = {
372             true, true, true
373         },
374         /* From PLLSAI1CFGR register documentation */
375         .default_channel_divider = {
376             7, 2, 2
377         }
378     },
379     [RCC_PLL_PLLSAI2] = {
380         .name = "pllsai2",
381         .channel_name = {
382             "pllsai2clk",
383             NULL,
384             "plladc2clk"
385         },
386         .channel_exists = {
387             true, false, true
388         },
389         /* From PLLSAI2CFGR register documentation */
390         .default_channel_divider = {
391             7, 0, 2
392         }
393     }
394 };
395 
set_pll_init_info(RccPllState * pll,RccPll id)396 static inline void set_pll_init_info(RccPllState *pll,
397                                      RccPll id)
398 {
399     int i;
400 
401     pll->id = id;
402     pll->vco_multiplier = 1;
403     for (i = 0; i < RCC_NUM_CHANNEL_PLL_OUT; i++) {
404         pll->channel_enabled[i] = false;
405         pll->channel_exists[i] = PLL_INIT_INFO[id].channel_exists[i];
406         pll->channel_divider[i] = PLL_INIT_INFO[id].default_channel_divider[i];
407     }
408 }
409 
410 /* Clock mux init info */
411 typedef struct ClockMuxInitInfo {
412     const char *name;
413 
414     uint32_t multiplier;
415     uint32_t divider;
416     bool enabled;
417     /* If this is true, the clock will not be exposed outside of the device */
418     bool hidden;
419 
420     RccClockMuxSource src_mapping[RCC_NUM_CLOCK_MUX_SRC];
421 } ClockMuxInitInfo;
422 
423 #define FILL_DEFAULT_FACTOR \
424     .multiplier = 1, \
425     .divider =  1
426 
427 #define FILL_DEFAULT_INIT_ENABLED \
428     FILL_DEFAULT_FACTOR, \
429     .enabled = true
430 
431 #define FILL_DEFAULT_INIT_DISABLED \
432     FILL_DEFAULT_FACTOR, \
433     .enabled = false
434 
435 
436 static const ClockMuxInitInfo CLOCK_MUX_INIT_INFO[] = {
437     [RCC_CLOCK_MUX_SYSCLK] = {
438         .name = "sysclk",
439         /* Same mapping as: CFGR_SW */
440         .src_mapping = {
441             RCC_CLOCK_MUX_SRC_MSI,
442             RCC_CLOCK_MUX_SRC_HSI,
443             RCC_CLOCK_MUX_SRC_HSE,
444             RCC_CLOCK_MUX_SRC_PLL,
445         },
446         .hidden = true,
447         FILL_DEFAULT_INIT_ENABLED,
448     },
449     [RCC_CLOCK_MUX_PLL_INPUT] = {
450         .name = "pll-input",
451         /* Same mapping as: PLLCFGR_PLLSRC */
452         .src_mapping = {
453             RCC_CLOCK_MUX_SRC_MSI,
454             RCC_CLOCK_MUX_SRC_HSI,
455             RCC_CLOCK_MUX_SRC_HSE,
456         },
457         .hidden = true,
458         FILL_DEFAULT_INIT_ENABLED,
459     },
460     [RCC_CLOCK_MUX_HCLK] = {
461         .name = "hclk",
462         .src_mapping = {
463             RCC_CLOCK_MUX_SRC_SYSCLK,
464         },
465         .hidden = true,
466         FILL_DEFAULT_INIT_ENABLED,
467     },
468     [RCC_CLOCK_MUX_PCLK1] = {
469         .name = "pclk1",
470         .src_mapping = {
471             RCC_CLOCK_MUX_SRC_HCLK,
472         },
473         .hidden = true,
474         FILL_DEFAULT_INIT_ENABLED,
475     },
476     [RCC_CLOCK_MUX_PCLK2] = {
477         .name = "pclk2",
478         .src_mapping = {
479             RCC_CLOCK_MUX_SRC_HCLK,
480         },
481         .hidden = true,
482         FILL_DEFAULT_INIT_ENABLED,
483     },
484     [RCC_CLOCK_MUX_HSE_OVER_32] = {
485         .name = "hse-divided-by-32",
486         .multiplier = 1,
487         .divider = 32,
488         .enabled = true,
489         .src_mapping = {
490             RCC_CLOCK_MUX_SRC_HSE,
491         },
492         .hidden = true,
493     },
494     [RCC_CLOCK_MUX_LCD_AND_RTC_COMMON] = {
495         .name = "lcd-and-rtc-common-mux",
496         /* Same mapping as: BDCR_RTCSEL */
497         .src_mapping = {
498             RCC_CLOCK_MUX_SRC_GND,
499             RCC_CLOCK_MUX_SRC_LSE,
500             RCC_CLOCK_MUX_SRC_LSI,
501             RCC_CLOCK_MUX_SRC_HSE_OVER_32,
502         },
503         .hidden = true,
504         FILL_DEFAULT_INIT_ENABLED,
505     },
506     /* From now on, muxes with a publicly available output */
507     [RCC_CLOCK_MUX_CORTEX_REFCLK] = {
508         .name = "cortex-refclk",
509         .multiplier = 1,
510         /* REFCLK is always HCLK/8 */
511         .divider = 8,
512         .enabled = true,
513         .src_mapping = {
514             RCC_CLOCK_MUX_SRC_HCLK,
515         }
516     },
517     [RCC_CLOCK_MUX_USART1] = {
518         .name = "usart1",
519         /* Same mapping as: CCIPR_USART1SEL */
520         .src_mapping = {
521             RCC_CLOCK_MUX_SRC_PCLK2,
522             RCC_CLOCK_MUX_SRC_SYSCLK,
523             RCC_CLOCK_MUX_SRC_HSI,
524             RCC_CLOCK_MUX_SRC_LSE,
525         },
526         FILL_DEFAULT_INIT_DISABLED,
527     },
528     [RCC_CLOCK_MUX_USART2] = {
529         .name = "usart2",
530         /* Same mapping as: CCIPR_USART2SEL */
531         .src_mapping = {
532             RCC_CLOCK_MUX_SRC_PCLK1,
533             RCC_CLOCK_MUX_SRC_SYSCLK,
534             RCC_CLOCK_MUX_SRC_HSI,
535             RCC_CLOCK_MUX_SRC_LSE,
536         },
537         FILL_DEFAULT_INIT_DISABLED,
538     },
539     [RCC_CLOCK_MUX_USART3] = {
540         .name = "usart3",
541         /* Same mapping as: CCIPR_USART3SEL */
542         .src_mapping = {
543             RCC_CLOCK_MUX_SRC_PCLK1,
544             RCC_CLOCK_MUX_SRC_SYSCLK,
545             RCC_CLOCK_MUX_SRC_HSI,
546             RCC_CLOCK_MUX_SRC_LSE,
547         },
548         FILL_DEFAULT_INIT_DISABLED,
549     },
550     [RCC_CLOCK_MUX_UART4] = {
551         .name = "uart4",
552         /* Same mapping as: CCIPR_UART4SEL */
553         .src_mapping = {
554             RCC_CLOCK_MUX_SRC_PCLK1,
555             RCC_CLOCK_MUX_SRC_SYSCLK,
556             RCC_CLOCK_MUX_SRC_HSI,
557             RCC_CLOCK_MUX_SRC_LSE,
558         },
559         FILL_DEFAULT_INIT_DISABLED,
560     },
561     [RCC_CLOCK_MUX_UART5] = {
562         .name = "uart5",
563         /* Same mapping as: CCIPR_UART5SEL */
564         .src_mapping = {
565             RCC_CLOCK_MUX_SRC_PCLK1,
566             RCC_CLOCK_MUX_SRC_SYSCLK,
567             RCC_CLOCK_MUX_SRC_HSI,
568             RCC_CLOCK_MUX_SRC_LSE,
569         },
570         FILL_DEFAULT_INIT_DISABLED,
571     },
572     [RCC_CLOCK_MUX_LPUART1] = {
573         .name = "lpuart1",
574         /* Same mapping as: CCIPR_LPUART1SEL */
575         .src_mapping = {
576             RCC_CLOCK_MUX_SRC_PCLK1,
577             RCC_CLOCK_MUX_SRC_SYSCLK,
578             RCC_CLOCK_MUX_SRC_HSI,
579             RCC_CLOCK_MUX_SRC_LSE,
580         },
581         FILL_DEFAULT_INIT_DISABLED,
582     },
583     [RCC_CLOCK_MUX_I2C1] = {
584         .name = "i2c1",
585         /* Same mapping as: CCIPR_I2C1SEL */
586         .src_mapping = {
587             RCC_CLOCK_MUX_SRC_PCLK1,
588             RCC_CLOCK_MUX_SRC_SYSCLK,
589             RCC_CLOCK_MUX_SRC_HSI,
590         },
591         FILL_DEFAULT_INIT_DISABLED,
592     },
593     [RCC_CLOCK_MUX_I2C2] = {
594         .name = "i2c2",
595         /* Same mapping as: CCIPR_I2C2SEL */
596         .src_mapping = {
597             RCC_CLOCK_MUX_SRC_PCLK1,
598             RCC_CLOCK_MUX_SRC_SYSCLK,
599             RCC_CLOCK_MUX_SRC_HSI,
600         },
601         FILL_DEFAULT_INIT_DISABLED,
602     },
603     [RCC_CLOCK_MUX_I2C3] = {
604         .name = "i2c3",
605         /* Same mapping as: CCIPR_I2C3SEL */
606         .src_mapping = {
607             RCC_CLOCK_MUX_SRC_PCLK1,
608             RCC_CLOCK_MUX_SRC_SYSCLK,
609             RCC_CLOCK_MUX_SRC_HSI,
610         },
611         FILL_DEFAULT_INIT_DISABLED,
612     },
613     [RCC_CLOCK_MUX_LPTIM1] = {
614         .name = "lptim1",
615         /* Same mapping as: CCIPR_LPTIM1SEL */
616         .src_mapping = {
617             RCC_CLOCK_MUX_SRC_PCLK1,
618             RCC_CLOCK_MUX_SRC_LSI,
619             RCC_CLOCK_MUX_SRC_HSI,
620             RCC_CLOCK_MUX_SRC_LSE,
621         },
622         FILL_DEFAULT_INIT_DISABLED,
623     },
624     [RCC_CLOCK_MUX_LPTIM2] = {
625         .name = "lptim2",
626         /* Same mapping as: CCIPR_LPTIM2SEL */
627         .src_mapping = {
628             RCC_CLOCK_MUX_SRC_PCLK1,
629             RCC_CLOCK_MUX_SRC_LSI,
630             RCC_CLOCK_MUX_SRC_HSI,
631             RCC_CLOCK_MUX_SRC_LSE,
632         },
633         FILL_DEFAULT_INIT_DISABLED,
634     },
635     [RCC_CLOCK_MUX_SWPMI1] = {
636         .name = "swpmi1",
637         /* Same mapping as: CCIPR_SWPMI1SEL */
638         .src_mapping = {
639             RCC_CLOCK_MUX_SRC_PCLK1,
640             RCC_CLOCK_MUX_SRC_HSI,
641         },
642         FILL_DEFAULT_INIT_DISABLED,
643     },
644     [RCC_CLOCK_MUX_MCO] = {
645         .name = "mco",
646         /* Same mapping as: CFGR_MCOSEL */
647         .src_mapping = {
648             RCC_CLOCK_MUX_SRC_SYSCLK,
649             RCC_CLOCK_MUX_SRC_MSI,
650             RCC_CLOCK_MUX_SRC_HSI,
651             RCC_CLOCK_MUX_SRC_HSE,
652             RCC_CLOCK_MUX_SRC_PLL,
653             RCC_CLOCK_MUX_SRC_LSI,
654             RCC_CLOCK_MUX_SRC_LSE,
655         },
656         FILL_DEFAULT_INIT_DISABLED,
657     },
658     [RCC_CLOCK_MUX_LSCO] = {
659         .name = "lsco",
660         /* Same mapping as: BDCR_LSCOSEL */
661         .src_mapping = {
662             RCC_CLOCK_MUX_SRC_LSI,
663             RCC_CLOCK_MUX_SRC_LSE,
664         },
665         FILL_DEFAULT_INIT_DISABLED,
666     },
667     [RCC_CLOCK_MUX_DFSDM1] = {
668         .name = "dfsdm1",
669         /* Same mapping as: CCIPR_DFSDM1SEL */
670         .src_mapping = {
671             RCC_CLOCK_MUX_SRC_PCLK2,
672             RCC_CLOCK_MUX_SRC_SYSCLK,
673         },
674         FILL_DEFAULT_INIT_DISABLED,
675     },
676     [RCC_CLOCK_MUX_ADC] = {
677         .name = "adc",
678         /* Same mapping as: CCIPR_ADCSEL */
679         .src_mapping = {
680             RCC_CLOCK_MUX_SRC_GND,
681             RCC_CLOCK_MUX_SRC_PLLADC1,
682             RCC_CLOCK_MUX_SRC_PLLADC2,
683             RCC_CLOCK_MUX_SRC_SYSCLK,
684         },
685         FILL_DEFAULT_INIT_DISABLED,
686     },
687     [RCC_CLOCK_MUX_CLK48] = {
688         .name = "clk48",
689         /* Same mapping as: CCIPR_CLK48SEL */
690         .src_mapping = {
691             RCC_CLOCK_MUX_SRC_GND,
692             RCC_CLOCK_MUX_SRC_PLL48M2,
693             RCC_CLOCK_MUX_SRC_PLL48M1,
694             RCC_CLOCK_MUX_SRC_MSI,
695         },
696         FILL_DEFAULT_INIT_DISABLED,
697     },
698     [RCC_CLOCK_MUX_SAI2] = {
699         .name = "sai2",
700         /* Same mapping as: CCIPR_SAI2SEL */
701         .src_mapping = {
702             RCC_CLOCK_MUX_SRC_PLLSAI1,
703             RCC_CLOCK_MUX_SRC_PLLSAI2,
704             RCC_CLOCK_MUX_SRC_PLLSAI3,
705             RCC_CLOCK_MUX_SRC_SAI2_EXTCLK,
706         },
707         FILL_DEFAULT_INIT_DISABLED,
708     },
709     [RCC_CLOCK_MUX_SAI1] = {
710         .name = "sai1",
711         /* Same mapping as: CCIPR_SAI1SEL */
712         .src_mapping = {
713             RCC_CLOCK_MUX_SRC_PLLSAI1,
714             RCC_CLOCK_MUX_SRC_PLLSAI2,
715             RCC_CLOCK_MUX_SRC_PLLSAI3,
716             RCC_CLOCK_MUX_SRC_SAI1_EXTCLK,
717         },
718         FILL_DEFAULT_INIT_DISABLED,
719     },
720     /* From now on, these muxes only have one valid source */
721     [RCC_CLOCK_MUX_TSC] = {
722         .name = "tsc",
723         .src_mapping = {
724             RCC_CLOCK_MUX_SRC_SYSCLK,
725         },
726         FILL_DEFAULT_INIT_DISABLED,
727     },
728     [RCC_CLOCK_MUX_CRC] = {
729         .name = "crc",
730         .src_mapping = {
731             RCC_CLOCK_MUX_SRC_SYSCLK,
732         },
733         FILL_DEFAULT_INIT_DISABLED,
734     },
735     [RCC_CLOCK_MUX_FLASH] = {
736         .name = "flash",
737         .src_mapping = {
738             RCC_CLOCK_MUX_SRC_SYSCLK,
739         },
740         FILL_DEFAULT_INIT_DISABLED,
741     },
742     [RCC_CLOCK_MUX_DMA2] = {
743         .name = "dma2",
744         .src_mapping = {
745             RCC_CLOCK_MUX_SRC_SYSCLK,
746         },
747         FILL_DEFAULT_INIT_DISABLED,
748     },
749     [RCC_CLOCK_MUX_DMA1] = {
750         .name = "dma1",
751         .src_mapping = {
752             RCC_CLOCK_MUX_SRC_SYSCLK,
753         },
754         FILL_DEFAULT_INIT_DISABLED,
755     },
756     [RCC_CLOCK_MUX_RNG] = {
757         .name = "rng",
758         .src_mapping = {
759             RCC_CLOCK_MUX_SRC_SYSCLK,
760         },
761         FILL_DEFAULT_INIT_DISABLED,
762     },
763     [RCC_CLOCK_MUX_AES] = {
764         .name = "aes",
765         .src_mapping = {
766             RCC_CLOCK_MUX_SRC_SYSCLK,
767         },
768         FILL_DEFAULT_INIT_DISABLED,
769     },
770     [RCC_CLOCK_MUX_OTGFS] = {
771         .name = "otgfs",
772         .src_mapping = {
773             RCC_CLOCK_MUX_SRC_SYSCLK,
774         },
775         FILL_DEFAULT_INIT_DISABLED,
776     },
777     [RCC_CLOCK_MUX_GPIOA] = {
778         .name = "gpioa",
779         .src_mapping = {
780             RCC_CLOCK_MUX_SRC_SYSCLK,
781         },
782         FILL_DEFAULT_INIT_DISABLED,
783     },
784     [RCC_CLOCK_MUX_GPIOB] = {
785         .name = "gpiob",
786         .src_mapping = {
787             RCC_CLOCK_MUX_SRC_SYSCLK,
788         },
789         FILL_DEFAULT_INIT_DISABLED,
790     },
791     [RCC_CLOCK_MUX_GPIOC] = {
792         .name = "gpioc",
793         .src_mapping = {
794             RCC_CLOCK_MUX_SRC_SYSCLK,
795         },
796         FILL_DEFAULT_INIT_DISABLED,
797     },
798     [RCC_CLOCK_MUX_GPIOD] = {
799         .name = "gpiod",
800         .src_mapping = {
801             RCC_CLOCK_MUX_SRC_SYSCLK,
802         },
803         FILL_DEFAULT_INIT_DISABLED,
804     },
805     [RCC_CLOCK_MUX_GPIOE] = {
806         .name = "gpioe",
807         .src_mapping = {
808             RCC_CLOCK_MUX_SRC_SYSCLK,
809         },
810         FILL_DEFAULT_INIT_DISABLED,
811     },
812     [RCC_CLOCK_MUX_GPIOF] = {
813         .name = "gpiof",
814         .src_mapping = {
815             RCC_CLOCK_MUX_SRC_SYSCLK,
816         },
817         FILL_DEFAULT_INIT_DISABLED,
818     },
819     [RCC_CLOCK_MUX_GPIOG] = {
820         .name = "gpiog",
821         .src_mapping = {
822             RCC_CLOCK_MUX_SRC_SYSCLK,
823         },
824         FILL_DEFAULT_INIT_DISABLED,
825     },
826     [RCC_CLOCK_MUX_GPIOH] = {
827         .name = "gpioh",
828         .src_mapping = {
829             RCC_CLOCK_MUX_SRC_SYSCLK,
830         },
831         FILL_DEFAULT_INIT_DISABLED,
832     },
833     [RCC_CLOCK_MUX_QSPI] = {
834         .name = "qspi",
835         .src_mapping = {
836             RCC_CLOCK_MUX_SRC_SYSCLK,
837         },
838         FILL_DEFAULT_INIT_DISABLED,
839     },
840     [RCC_CLOCK_MUX_FMC] = {
841         .name = "fmc",
842         .src_mapping = {
843             RCC_CLOCK_MUX_SRC_SYSCLK,
844         },
845         FILL_DEFAULT_INIT_DISABLED,
846     },
847     [RCC_CLOCK_MUX_OPAMP] = {
848         .name = "opamp",
849         .src_mapping = {
850             RCC_CLOCK_MUX_SRC_PCLK1,
851         },
852         FILL_DEFAULT_INIT_DISABLED,
853     },
854     [RCC_CLOCK_MUX_DAC1] = {
855         .name = "dac1",
856         .src_mapping = {
857             RCC_CLOCK_MUX_SRC_PCLK1,
858         },
859         FILL_DEFAULT_INIT_DISABLED,
860     },
861     [RCC_CLOCK_MUX_PWR] = {
862         .name = "pwr",
863         /*
864          * PWREN is in the APB1ENR1 register,
865          * but PWR uses SYSCLK according to the clock tree.
866          */
867         .src_mapping = {
868             RCC_CLOCK_MUX_SRC_SYSCLK,
869         },
870         FILL_DEFAULT_INIT_DISABLED,
871     },
872     [RCC_CLOCK_MUX_CAN1] = {
873         .name = "can1",
874         .src_mapping = {
875             RCC_CLOCK_MUX_SRC_PCLK1,
876         },
877         FILL_DEFAULT_INIT_DISABLED,
878     },
879     [RCC_CLOCK_MUX_SPI3] = {
880         .name = "spi3",
881         .src_mapping = {
882             RCC_CLOCK_MUX_SRC_PCLK1,
883         },
884         FILL_DEFAULT_INIT_DISABLED,
885     },
886     [RCC_CLOCK_MUX_SPI2] = {
887         .name = "spi2",
888         .src_mapping = {
889             RCC_CLOCK_MUX_SRC_PCLK1,
890         },
891         FILL_DEFAULT_INIT_DISABLED,
892     },
893     [RCC_CLOCK_MUX_WWDG] = {
894         .name = "wwdg",
895         .src_mapping = {
896             RCC_CLOCK_MUX_SRC_PCLK1,
897         },
898         FILL_DEFAULT_INIT_DISABLED,
899     },
900     [RCC_CLOCK_MUX_LCD] = {
901         .name = "lcd",
902         .src_mapping = {
903             RCC_CLOCK_MUX_SRC_LCD_AND_RTC_COMMON,
904         },
905         FILL_DEFAULT_INIT_DISABLED,
906     },
907     [RCC_CLOCK_MUX_TIM7] = {
908         .name = "tim7",
909         .src_mapping = {
910             RCC_CLOCK_MUX_SRC_PCLK1,
911         },
912         FILL_DEFAULT_INIT_DISABLED,
913     },
914     [RCC_CLOCK_MUX_TIM6] = {
915         .name = "tim6",
916         .src_mapping = {
917             RCC_CLOCK_MUX_SRC_PCLK1,
918         },
919         FILL_DEFAULT_INIT_DISABLED,
920     },
921     [RCC_CLOCK_MUX_TIM5] = {
922         .name = "tim5",
923         .src_mapping = {
924             RCC_CLOCK_MUX_SRC_PCLK1,
925         },
926         FILL_DEFAULT_INIT_DISABLED,
927     },
928     [RCC_CLOCK_MUX_TIM4] = {
929         .name = "tim4",
930         .src_mapping = {
931             RCC_CLOCK_MUX_SRC_PCLK1,
932         },
933         FILL_DEFAULT_INIT_DISABLED,
934     },
935     [RCC_CLOCK_MUX_TIM3] = {
936         .name = "tim3",
937         .src_mapping = {
938             RCC_CLOCK_MUX_SRC_PCLK1,
939         },
940         FILL_DEFAULT_INIT_DISABLED,
941     },
942     [RCC_CLOCK_MUX_TIM2] = {
943         .name = "tim2",
944         .src_mapping = {
945             RCC_CLOCK_MUX_SRC_PCLK1,
946         },
947         FILL_DEFAULT_INIT_DISABLED,
948     },
949     [RCC_CLOCK_MUX_TIM17] = {
950         .name = "tim17",
951         .src_mapping = {
952             RCC_CLOCK_MUX_SRC_PCLK2,
953         },
954         FILL_DEFAULT_INIT_DISABLED,
955     },
956     [RCC_CLOCK_MUX_TIM16] = {
957         .name = "tim16",
958         .src_mapping = {
959             RCC_CLOCK_MUX_SRC_PCLK2,
960         },
961         FILL_DEFAULT_INIT_DISABLED,
962     },
963     [RCC_CLOCK_MUX_TIM15] = {
964         .name = "tim15",
965         .src_mapping = {
966             RCC_CLOCK_MUX_SRC_PCLK2,
967         },
968         FILL_DEFAULT_INIT_DISABLED,
969     },
970     [RCC_CLOCK_MUX_TIM8] = {
971         .name = "tim8",
972         .src_mapping = {
973             RCC_CLOCK_MUX_SRC_PCLK2,
974         },
975         FILL_DEFAULT_INIT_DISABLED,
976     },
977     [RCC_CLOCK_MUX_SPI1] = {
978         .name = "spi1",
979         .src_mapping = {
980             RCC_CLOCK_MUX_SRC_PCLK2,
981         },
982         FILL_DEFAULT_INIT_DISABLED,
983     },
984     [RCC_CLOCK_MUX_TIM1] = {
985         .name = "tim1",
986         .src_mapping = {
987             RCC_CLOCK_MUX_SRC_PCLK2,
988         },
989         FILL_DEFAULT_INIT_DISABLED,
990     },
991     [RCC_CLOCK_MUX_SDMMC1] = {
992         .name = "sdmmc1",
993         .src_mapping = {
994             RCC_CLOCK_MUX_SRC_PCLK2,
995         },
996         FILL_DEFAULT_INIT_DISABLED,
997     },
998     [RCC_CLOCK_MUX_FW] = {
999         .name = "fw",
1000         .src_mapping = {
1001             RCC_CLOCK_MUX_SRC_PCLK2,
1002         },
1003         FILL_DEFAULT_INIT_DISABLED,
1004     },
1005     [RCC_CLOCK_MUX_SYSCFG] = {
1006         .name = "syscfg",
1007         .src_mapping = {
1008             RCC_CLOCK_MUX_SRC_PCLK2,
1009         },
1010         FILL_DEFAULT_INIT_DISABLED,
1011     },
1012     [RCC_CLOCK_MUX_RTC] = {
1013         .name = "rtc",
1014         .src_mapping = {
1015             RCC_CLOCK_MUX_SRC_LCD_AND_RTC_COMMON,
1016         },
1017         FILL_DEFAULT_INIT_DISABLED,
1018     },
1019     [RCC_CLOCK_MUX_CORTEX_FCLK] = {
1020         .name = "cortex-fclk",
1021         .src_mapping = {
1022             RCC_CLOCK_MUX_SRC_HCLK,
1023         },
1024         FILL_DEFAULT_INIT_ENABLED,
1025     },
1026 };
1027 
set_clock_mux_init_info(RccClockMuxState * mux,RccClockMux id)1028 static inline void set_clock_mux_init_info(RccClockMuxState *mux,
1029                                            RccClockMux id)
1030 {
1031     mux->id = id;
1032     mux->multiplier = CLOCK_MUX_INIT_INFO[id].multiplier;
1033     mux->divider = CLOCK_MUX_INIT_INFO[id].divider;
1034     mux->enabled = CLOCK_MUX_INIT_INFO[id].enabled;
1035     /*
1036      * Every peripheral has the first source of their source list as
1037      * as their default source.
1038      */
1039     mux->src = 0;
1040 }
1041 
1042 #endif /* HW_STM32L4X5_RCC_INTERNALS_H */
1043