1 /* 2 * ArmCpuMemoryAccess.h 3 * 4 * Implementaion for access of CPU registers. 5 * 6 * Copyright (C) 2007 - 2011 Texas Instruments Incorporated - http://www.ti.com/ 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 16 * Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the 19 * distribution. 20 * 21 * Neither the name of Texas Instruments Incorporated nor the names of 22 * its contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #pragma once 39 40 #include "CpuRegisters.h" 41 #include "DeviceInfo.h" 42 43 namespace TI 44 { 45 namespace DLL430 46 { 47 class IDeviceHandle; 48 class ArmCpuMemoryAccess : public CpuRegisters 49 { 50 public: 51 ArmCpuMemoryAccess (MemoryArea::Name name, IDeviceHandle* devHandle, 52 uint32_t start, 53 uint32_t size, 54 uint32_t seg, 55 uint32_t banks, 56 bool mapped, 57 uint8_t bits); 58 59 bool read (uint32_t Register, uint32_t* buffer, size_t count) OVERRIDE; 60 bool write (uint32_t Register, const uint32_t* buffer, size_t count) OVERRIDE; 61 bool write (uint32_t Register, uint32_t value) OVERRIDE; 62 size_t getSize() const OVERRIDE; 63 64 bool flushCache() OVERRIDE; 65 bool fillCache(uint32_t Register, size_t count) OVERRIDE; 66 void clearCache(uint32_t Register, size_t count) OVERRIDE; 67 68 void pushCache() OVERRIDE; 69 void popCache() OVERRIDE; 70 bool switchContext(uint32_t pc, uint32_t sp) OVERRIDE; 71 bool disableInterrupts() OVERRIDE; 72 73 private: postSync(const HalExecCommand &)74 virtual bool postSync(const HalExecCommand&) { return true; } 75 76 size_t size; 77 std::vector<uint32_t> localCache; 78 std::vector<uint32_t> backupCache; 79 IDeviceHandle* devHandle; 80 static const uint32_t REGISTER_SP = 0x0d; 81 static const uint32_t REGISTER_LR = 0x0e; 82 static const uint32_t REGISTER_PC = 0x0f; 83 static const uint32_t REGISTER_XPSR = 0x10; 84 static const uint32_t REGISTER_SPECIAL = 0x11; 85 }; 86 87 } 88 } 89