1 /************************************************************************** 2 * 3 * Copyright 2017 Advanced Micro Devices, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #ifndef _RADEON_VCN_ENC_H 29 #define _RADEON_VCN_ENC_H 30 31 #include "radeon_video.h" 32 33 #define RENCODE_IB_OP_INITIALIZE 0x01000001 34 #define RENCODE_IB_OP_CLOSE_SESSION 0x01000002 35 #define RENCODE_IB_OP_ENCODE 0x01000003 36 #define RENCODE_IB_OP_INIT_RC 0x01000004 37 #define RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x01000005 38 #define RENCODE_IB_OP_SET_SPEED_ENCODING_MODE 0x01000006 39 #define RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE 0x01000007 40 #define RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE 0x01000008 41 42 #define RENCODE_IF_MAJOR_VERSION_MASK 0xFFFF0000 43 #define RENCODE_IF_MAJOR_VERSION_SHIFT 16 44 #define RENCODE_IF_MINOR_VERSION_MASK 0x0000FFFF 45 #define RENCODE_IF_MINOR_VERSION_SHIFT 0 46 47 #define RENCODE_ENGINE_TYPE_ENCODE 1 48 49 #define RENCODE_ENCODE_STANDARD_HEVC 0 50 #define RENCODE_ENCODE_STANDARD_H264 1 51 52 #define RENCODE_PREENCODE_MODE_NONE 0x00000000 53 #define RENCODE_PREENCODE_MODE_1X 0x00000001 54 #define RENCODE_PREENCODE_MODE_2X 0x00000002 55 #define RENCODE_PREENCODE_MODE_4X 0x00000004 56 57 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS 0x00000000 58 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001 59 60 #define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS 0x00000000 61 #define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001 62 63 #define RENCODE_RATE_CONTROL_METHOD_NONE 0x00000000 64 #define RENCODE_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR 0x00000001 65 #define RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR 0x00000002 66 #define RENCODE_RATE_CONTROL_METHOD_CBR 0x00000003 67 68 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD 0x00000000 69 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS 0x00000001 70 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS 0x00000002 71 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS 0x00000003 72 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PREFIX 0x00000004 73 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_END_OF_SEQUENCE 0x00000005 74 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_SEI 0x00000006 75 76 #define RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS 16 77 #define RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS 16 78 79 #define RENCODE_HEADER_INSTRUCTION_END 0x00000000 80 #define RENCODE_HEADER_INSTRUCTION_COPY 0x00000001 81 82 #define RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END 0x00010000 83 #define RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE 0x00010001 84 #define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT 0x00010002 85 #define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00010003 86 #define RENCODE_HEVC_HEADER_INSTRUCTION_SAO_ENABLE 0x00010004 87 #define RENCODE_HEVC_HEADER_INSTRUCTION_LOOP_FILTER_ACROSS_SLICES_ENABLE 0x00010005 88 89 #define RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB 0x00020000 90 #define RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00020001 91 92 #define RENCODE_PICTURE_TYPE_B 0 93 #define RENCODE_PICTURE_TYPE_P 1 94 #define RENCODE_PICTURE_TYPE_I 2 95 #define RENCODE_PICTURE_TYPE_P_SKIP 3 96 97 #define RENCODE_INPUT_SWIZZLE_MODE_LINEAR 0 98 #define RENCODE_INPUT_SWIZZLE_MODE_256B_S 1 99 #define RENCODE_INPUT_SWIZZLE_MODE_4kB_S 5 100 #define RENCODE_INPUT_SWIZZLE_MODE_64kB_S 9 101 102 #define RENCODE_H264_PICTURE_STRUCTURE_FRAME 0 103 #define RENCODE_H264_PICTURE_STRUCTURE_TOP_FIELD 1 104 #define RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD 2 105 106 #define RENCODE_H264_INTERLACING_MODE_PROGRESSIVE 0 107 #define RENCODE_H264_INTERLACING_MODE_INTERLACED_STACKED 1 108 #define RENCODE_H264_INTERLACING_MODE_INTERLACED_INTERLEAVED 2 109 110 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_ENABLE 0 111 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISABLE 1 112 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISALBE_ACROSS_SLICE_BOUNDARY 2 113 114 #define RENCODE_INTRA_REFRESH_MODE_NONE 0 115 #define RENCODE_INTRA_REFRESH_MODE_CTB_MB_ROWS 1 116 #define RENCODE_INTRA_REFRESH_MODE_CTB_MB_COLUMNS 2 117 118 #define RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES 34 119 120 #define RENCODE_REC_SWIZZLE_MODE_LINEAR 0 121 #define RENCODE_REC_SWIZZLE_MODE_256B_S 1 122 123 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_LINEAR 0 124 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_CIRCULAR 1 125 126 #define RENCODE_FEEDBACK_BUFFER_MODE_LINEAR 0 127 #define RENCODE_FEEDBACK_BUFFER_MODE_CIRCULAR 1 128 129 #define RENCODE_MAX_NUM_TEMPORAL_LAYERS 4 130 131 typedef enum { 132 RENCODE_COLOR_SPACE_YUV, 133 RENCODE_COLOR_SPACE_RGB 134 } RENCODE_COLOR_SPACE; 135 136 typedef enum { 137 RENCODE_CHROMA_SUBSAMPLING_4_2_0, 138 RENCODE_CHROMA_SUBSAMPLING_4_4_4 139 } RENCODE_CHROMA_SUBSAMPLING; 140 141 typedef enum { 142 RENCODE_COLOR_BIT_DEPTH_8_BIT, 143 RENCODE_COLOR_BIT_DEPTH_10_BIT 144 } RENCODE_COLOR_BIT_DEPTH; 145 146 typedef enum { 147 RENCODE_COLOR_PACKING_FORMAT_NV12, 148 RENCODE_COLOR_PACKING_FORMAT_P010, 149 RENCODE_COLOR_PACKING_FORMAT_A8R8G8B8 = 4, 150 RENCODE_COLOR_PACKING_FORMAT_A8B8G8R8 = 7, 151 } RENCODE_COLOR_PACKING_FORMAT; 152 153 154 #define RADEON_ENC_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value)) 155 #define RADEON_ENC_BEGIN(cmd) \ 156 { \ 157 uint32_t *begin = &enc->cs.current.buf[enc->cs.current.cdw++]; \ 158 RADEON_ENC_CS(cmd) 159 #define RADEON_ENC_READ(buf, domain, off) \ 160 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off)) 161 #define RADEON_ENC_WRITE(buf, domain, off) \ 162 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off)) 163 #define RADEON_ENC_READWRITE(buf, domain, off) \ 164 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off)) 165 #define RADEON_ENC_END() \ 166 *begin = (&enc->cs.current.buf[enc->cs.current.cdw] - begin) * 4; \ 167 enc->total_task_size += *begin; \ 168 } 169 170 typedef struct rvcn_enc_session_info_s { 171 uint32_t interface_version; 172 uint32_t sw_context_address_hi; 173 uint32_t sw_context_address_lo; 174 } rvcn_enc_session_info_t; 175 176 typedef struct rvcn_enc_task_info_s { 177 uint32_t total_size_of_all_packages; 178 uint32_t task_id; 179 uint32_t allowed_max_num_feedbacks; 180 } rvcn_enc_task_info_t; 181 182 typedef struct rvcn_enc_session_init_s { 183 uint32_t encode_standard; 184 uint32_t aligned_picture_width; 185 uint32_t aligned_picture_height; 186 uint32_t padding_width; 187 uint32_t padding_height; 188 uint32_t pre_encode_mode; 189 uint32_t pre_encode_chroma_enabled; 190 uint32_t display_remote; 191 } rvcn_enc_session_init_t; 192 193 typedef struct rvcn_enc_layer_control_s { 194 uint32_t max_num_temporal_layers; 195 uint32_t num_temporal_layers; 196 } rvcn_enc_layer_control_t; 197 198 typedef struct rvcn_enc_layer_select_s { 199 uint32_t temporal_layer_index; 200 } rvcn_enc_layer_select_t; 201 202 typedef struct rvcn_enc_h264_slice_control_s { 203 uint32_t slice_control_mode; 204 union { 205 uint32_t num_mbs_per_slice; 206 uint32_t num_bits_per_slice; 207 }; 208 } rvcn_enc_h264_slice_control_t; 209 210 typedef struct rvcn_enc_hevc_slice_control_s { 211 uint32_t slice_control_mode; 212 union { 213 struct { 214 uint32_t num_ctbs_per_slice; 215 uint32_t num_ctbs_per_slice_segment; 216 } fixed_ctbs_per_slice; 217 218 struct { 219 uint32_t num_bits_per_slice; 220 uint32_t num_bits_per_slice_segment; 221 } fixed_bits_per_slice; 222 }; 223 } rvcn_enc_hevc_slice_control_t; 224 225 typedef struct rvcn_enc_h264_spec_misc_s { 226 uint32_t constrained_intra_pred_flag; 227 uint32_t cabac_enable; 228 uint32_t cabac_init_idc; 229 uint32_t half_pel_enabled; 230 uint32_t quarter_pel_enabled; 231 uint32_t profile_idc; 232 uint32_t level_idc; 233 uint32_t b_picture_enabled; 234 uint32_t weighted_bipred_idc; 235 } rvcn_enc_h264_spec_misc_t; 236 237 typedef struct rvcn_enc_hevc_spec_misc_s { 238 uint32_t log2_min_luma_coding_block_size_minus3; 239 uint32_t amp_disabled; 240 uint32_t strong_intra_smoothing_enabled; 241 uint32_t constrained_intra_pred_flag; 242 uint32_t cabac_init_flag; 243 uint32_t half_pel_enabled; 244 uint32_t quarter_pel_enabled; 245 } rvcn_enc_hevc_spec_misc_t; 246 247 typedef struct rvcn_enc_rate_ctl_session_init_s { 248 uint32_t rate_control_method; 249 uint32_t vbv_buffer_level; 250 } rvcn_enc_rate_ctl_session_init_t; 251 252 typedef struct rvcn_enc_rate_ctl_layer_init_s { 253 uint32_t target_bit_rate; 254 uint32_t peak_bit_rate; 255 uint32_t frame_rate_num; 256 uint32_t frame_rate_den; 257 uint32_t vbv_buffer_size; 258 uint32_t avg_target_bits_per_picture; 259 uint32_t peak_bits_per_picture_integer; 260 uint32_t peak_bits_per_picture_fractional; 261 } rvcn_enc_rate_ctl_layer_init_t; 262 263 typedef struct rvcn_enc_rate_ctl_per_picture_s { 264 uint32_t qp; 265 uint32_t min_qp_app; 266 uint32_t max_qp_app; 267 uint32_t max_au_size; 268 uint32_t enabled_filler_data; 269 uint32_t skip_frame_enable; 270 uint32_t enforce_hrd; 271 } rvcn_enc_rate_ctl_per_picture_t; 272 273 typedef struct rvcn_enc_quality_params_s { 274 uint32_t vbaq_mode; 275 uint32_t scene_change_sensitivity; 276 uint32_t scene_change_min_idr_interval; 277 uint32_t two_pass_search_center_map_mode; 278 } rvcn_enc_quality_params_t; 279 280 typedef struct rvcn_enc_direct_output_nalu_s { 281 uint32_t type; 282 uint32_t size; 283 uint32_t data[1]; 284 } rvcn_enc_direct_output_nalu_t; 285 286 typedef struct rvcn_enc_slice_header_s { 287 uint32_t bitstream_template[RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS]; 288 struct { 289 uint32_t instruction; 290 uint32_t num_bits; 291 } instructions[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS]; 292 } rvcn_enc_slice_header_t; 293 294 typedef struct rvcn_enc_h264_reference_picture_info_s { 295 unsigned int pic_type; 296 unsigned int is_long_term; 297 unsigned int picture_structure; 298 unsigned int pic_order_cnt; 299 } rvcn_enc_h264_reference_picture_info_t; 300 301 typedef struct rvcn_enc_encode_params_s { 302 uint32_t pic_type; 303 uint32_t allowed_max_bitstream_size; 304 uint32_t input_picture_luma_address_hi; 305 uint32_t input_picture_luma_address_lo; 306 uint32_t input_picture_chroma_address_hi; 307 uint32_t input_picture_chroma_address_lo; 308 uint32_t input_pic_luma_pitch; 309 uint32_t input_pic_chroma_pitch; 310 uint8_t input_pic_swizzle_mode; 311 uint32_t reference_picture_index; 312 uint32_t reconstructed_picture_index; 313 } rvcn_enc_encode_params_t; 314 315 typedef struct rvcn_enc_h264_encode_params_s { 316 uint32_t input_picture_structure; 317 uint32_t input_pic_order_cnt; 318 uint32_t interlaced_mode; 319 uint32_t reference_picture_structure; 320 uint32_t reference_picture1_index; 321 rvcn_enc_h264_reference_picture_info_t picture_info_l0_reference_picture0; 322 uint32_t l0_reference_picture1_index; 323 rvcn_enc_h264_reference_picture_info_t picture_info_l0_reference_picture1; 324 uint32_t l1_reference_picture0_index; 325 rvcn_enc_h264_reference_picture_info_t picture_info_l1_reference_picture0; 326 } rvcn_enc_h264_encode_params_t; 327 328 typedef struct rvcn_enc_h264_deblocking_filter_s { 329 uint32_t disable_deblocking_filter_idc; 330 int32_t alpha_c0_offset_div2; 331 int32_t beta_offset_div2; 332 int32_t cb_qp_offset; 333 int32_t cr_qp_offset; 334 } rvcn_enc_h264_deblocking_filter_t; 335 336 typedef struct rvcn_enc_hevc_deblocking_filter_s { 337 uint32_t loop_filter_across_slices_enabled; 338 int32_t deblocking_filter_disabled; 339 int32_t beta_offset_div2; 340 int32_t tc_offset_div2; 341 int32_t cb_qp_offset; 342 int32_t cr_qp_offset; 343 } rvcn_enc_hevc_deblocking_filter_t; 344 345 typedef struct rvcn_enc_intra_refresh_s { 346 uint32_t intra_refresh_mode; 347 uint32_t offset; 348 uint32_t region_size; 349 } rvcn_enc_intra_refresh_t; 350 351 typedef struct rvcn_enc_reconstructed_picture_s { 352 uint32_t luma_offset; 353 uint32_t chroma_offset; 354 } rvcn_enc_reconstructed_picture_t; 355 356 typedef struct rvcn_enc_picture_info_s 357 { 358 bool in_use; 359 uint32_t frame_num; 360 } rvcn_enc_picture_info_t; 361 362 typedef struct rvcn_enc_pre_encode_input_picture_s { 363 union { 364 struct { 365 uint32_t luma_offset; 366 uint32_t chroma_offset; 367 } yuv; 368 struct { 369 uint32_t red_offset; 370 uint32_t green_offset; 371 uint32_t blue_offset; 372 } rgb; 373 }; 374 } rvcn_enc_pre_encode_input_picture_t; 375 376 typedef struct rvcn_enc_encode_context_buffer_s { 377 uint32_t encode_context_address_hi; 378 uint32_t encode_context_address_lo; 379 uint32_t swizzle_mode; 380 uint32_t rec_luma_pitch; 381 uint32_t rec_chroma_pitch; 382 uint32_t num_reconstructed_pictures; 383 rvcn_enc_reconstructed_picture_t reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES]; 384 uint32_t pre_encode_picture_luma_pitch; 385 uint32_t pre_encode_picture_chroma_pitch; 386 rvcn_enc_reconstructed_picture_t 387 pre_encode_reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES]; 388 rvcn_enc_pre_encode_input_picture_t pre_encode_input_picture; 389 uint32_t two_pass_search_center_map_offset; 390 } rvcn_enc_encode_context_buffer_t; 391 392 typedef struct rvcn_enc_video_bitstream_buffer_s { 393 uint32_t mode; 394 uint32_t video_bitstream_buffer_address_hi; 395 uint32_t video_bitstream_buffer_address_lo; 396 uint32_t video_bitstream_buffer_size; 397 uint32_t video_bitstream_data_offset; 398 } rvcn_enc_video_bitstream_buffer_t; 399 400 typedef struct rvcn_enc_feedback_buffer_s { 401 uint32_t mode; 402 uint32_t feedback_buffer_address_hi; 403 uint32_t feedback_buffer_address_lo; 404 uint32_t feedback_buffer_size; 405 uint32_t feedback_data_size; 406 } rvcn_enc_feedback_buffer_t; 407 408 typedef struct rvcn_enc_cmd_s { 409 uint32_t session_info; 410 uint32_t task_info; 411 uint32_t session_init; 412 uint32_t layer_control; 413 uint32_t layer_select; 414 uint32_t rc_session_init; 415 uint32_t rc_layer_init; 416 uint32_t rc_per_pic; 417 uint32_t quality_params; 418 uint32_t slice_header; 419 uint32_t enc_params; 420 uint32_t intra_refresh; 421 uint32_t ctx; 422 uint32_t bitstream; 423 uint32_t feedback; 424 uint32_t nalu; 425 uint32_t slice_control_hevc; 426 uint32_t spec_misc_hevc; 427 uint32_t enc_params_hevc; 428 uint32_t deblocking_filter_hevc; 429 uint32_t slice_control_h264; 430 uint32_t spec_misc_h264; 431 uint32_t enc_params_h264; 432 uint32_t deblocking_filter_h264; 433 uint32_t input_format; 434 uint32_t output_format; 435 uint32_t efc_params; 436 } rvcn_enc_cmd_t; 437 438 typedef struct rvcn_enc_efc_config_s 439 { 440 uint32_t coef_buffer_address_hi; 441 uint32_t coef_buffer_address_lo; 442 uint32_t coef_buffer_size; 443 uint32_t cm_program_register_data_size; 444 } rvcn_enc_efc_config_t; 445 446 447 typedef struct rvcn_enc_input_format_s 448 { 449 uint32_t input_color_volume; 450 RENCODE_COLOR_SPACE input_color_space; 451 uint32_t input_color_range; 452 RENCODE_CHROMA_SUBSAMPLING input_chroma_subsampling; 453 uint32_t input_chroma_location; 454 RENCODE_COLOR_BIT_DEPTH input_color_bit_depth; 455 RENCODE_COLOR_PACKING_FORMAT input_color_packing_format; 456 } rvcn_enc_input_format_t; 457 458 typedef struct rvcn_enc_output_format_s 459 { 460 uint32_t output_color_volume; 461 uint32_t output_color_range; 462 uint32_t output_chroma_location; 463 RENCODE_COLOR_BIT_DEPTH output_color_bit_depth; 464 } rvcn_enc_output_format_t; 465 466 typedef void (*radeon_enc_get_buffer)(struct pipe_resource *resource, struct pb_buffer **handle, 467 struct radeon_surf **surface); 468 469 struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context, 470 const struct pipe_video_codec *templat, 471 struct radeon_winsys *ws, 472 radeon_enc_get_buffer get_buffer); 473 474 struct radeon_enc_pic { 475 enum pipe_h2645_enc_picture_type picture_type; 476 477 unsigned frame_num; 478 unsigned pic_order_cnt; 479 unsigned pic_order_cnt_type; 480 unsigned ref_idx_l0; 481 unsigned ref_idx_l1; 482 unsigned crop_left; 483 unsigned crop_right; 484 unsigned crop_top; 485 unsigned crop_bottom; 486 unsigned general_tier_flag; 487 unsigned general_profile_idc; 488 unsigned general_level_idc; 489 unsigned max_poc; 490 unsigned log2_max_poc; 491 unsigned chroma_format_idc; 492 unsigned pic_width_in_luma_samples; 493 unsigned pic_height_in_luma_samples; 494 unsigned log2_diff_max_min_luma_coding_block_size; 495 unsigned log2_min_transform_block_size_minus2; 496 unsigned log2_diff_max_min_transform_block_size; 497 unsigned max_transform_hierarchy_depth_inter; 498 unsigned max_transform_hierarchy_depth_intra; 499 unsigned log2_parallel_merge_level_minus2; 500 unsigned bit_depth_luma_minus8; 501 unsigned bit_depth_chroma_minus8; 502 unsigned nal_unit_type; 503 unsigned max_num_merge_cand; 504 unsigned temporal_id; 505 unsigned num_temporal_layers; 506 unsigned temporal_layer_pattern_index; 507 508 bool not_referenced; 509 bool is_idr; 510 bool is_even_frame; 511 bool sample_adaptive_offset_enabled_flag; 512 bool pcm_enabled_flag; 513 bool sps_temporal_mvp_enabled_flag; 514 515 rvcn_enc_session_info_t session_info; 516 rvcn_enc_task_info_t task_info; 517 rvcn_enc_session_init_t session_init; 518 rvcn_enc_layer_control_t layer_ctrl; 519 rvcn_enc_layer_select_t layer_sel; 520 rvcn_enc_h264_slice_control_t slice_ctrl; 521 rvcn_enc_hevc_slice_control_t hevc_slice_ctrl; 522 rvcn_enc_h264_spec_misc_t spec_misc; 523 rvcn_enc_hevc_spec_misc_t hevc_spec_misc; 524 rvcn_enc_rate_ctl_session_init_t rc_session_init; 525 rvcn_enc_rate_ctl_layer_init_t rc_layer_init[RENCODE_MAX_NUM_TEMPORAL_LAYERS]; 526 rvcn_enc_h264_encode_params_t h264_enc_params; 527 rvcn_enc_h264_deblocking_filter_t h264_deblock; 528 rvcn_enc_hevc_deblocking_filter_t hevc_deblock; 529 rvcn_enc_rate_ctl_per_picture_t rc_per_pic; 530 rvcn_enc_quality_params_t quality_params; 531 rvcn_enc_encode_context_buffer_t ctx_buf; 532 rvcn_enc_video_bitstream_buffer_t bit_buf; 533 rvcn_enc_feedback_buffer_t fb_buf; 534 rvcn_enc_intra_refresh_t intra_ref; 535 rvcn_enc_encode_params_t enc_params; 536 rvcn_enc_efc_config_t efc_params; 537 rvcn_enc_input_format_t input_format; 538 rvcn_enc_output_format_t output_format; 539 }; 540 541 struct radeon_encoder { 542 struct pipe_video_codec base; 543 544 void (*begin)(struct radeon_encoder *enc); 545 void (*before_encode)(struct radeon_encoder *enc); 546 void (*encode)(struct radeon_encoder *enc); 547 void (*destroy)(struct radeon_encoder *enc); 548 void (*session_info)(struct radeon_encoder *enc); 549 void (*task_info)(struct radeon_encoder *enc, bool need_feedback); 550 void (*session_init)(struct radeon_encoder *enc); 551 void (*layer_control)(struct radeon_encoder *enc); 552 void (*layer_select)(struct radeon_encoder *enc); 553 void (*slice_control)(struct radeon_encoder *enc); 554 void (*spec_misc)(struct radeon_encoder *enc); 555 void (*rc_session_init)(struct radeon_encoder *enc); 556 void (*rc_layer_init)(struct radeon_encoder *enc); 557 void (*deblocking_filter)(struct radeon_encoder *enc); 558 void (*quality_params)(struct radeon_encoder *enc); 559 void (*nalu_sps)(struct radeon_encoder *enc); 560 void (*nalu_pps)(struct radeon_encoder *enc); 561 void (*nalu_vps)(struct radeon_encoder *enc); 562 void (*nalu_aud)(struct radeon_encoder *enc); 563 void (*nalu_sei)(struct radeon_encoder *enc); 564 void (*nalu_prefix)(struct radeon_encoder *enc); 565 void (*slice_header)(struct radeon_encoder *enc); 566 void (*ctx)(struct radeon_encoder *enc); 567 void (*bitstream)(struct radeon_encoder *enc); 568 void (*feedback)(struct radeon_encoder *enc); 569 void (*intra_refresh)(struct radeon_encoder *enc); 570 void (*rc_per_pic)(struct radeon_encoder *enc); 571 void (*encode_params)(struct radeon_encoder *enc); 572 void (*encode_params_codec_spec)(struct radeon_encoder *enc); 573 void (*op_init)(struct radeon_encoder *enc); 574 void (*op_close)(struct radeon_encoder *enc); 575 void (*op_enc)(struct radeon_encoder *enc); 576 void (*op_init_rc)(struct radeon_encoder *enc); 577 void (*op_init_rc_vbv)(struct radeon_encoder *enc); 578 void (*op_preset)(struct radeon_encoder *enc); 579 void (*encode_headers)(struct radeon_encoder *enc); 580 void (*input_format)(struct radeon_encoder *enc); 581 void (*output_format)(struct radeon_encoder *enc); 582 void (*efc_params)(struct radeon_encoder *enc); 583 584 unsigned stream_handle; 585 586 struct pipe_screen *screen; 587 struct radeon_winsys *ws; 588 struct radeon_cmdbuf cs; 589 590 radeon_enc_get_buffer get_buffer; 591 592 struct pb_buffer *handle; 593 struct radeon_surf *luma; 594 struct radeon_surf *chroma; 595 596 struct pb_buffer *bs_handle; 597 unsigned bs_size; 598 599 unsigned cpb_num; 600 601 struct rvid_buffer *si; 602 struct rvid_buffer *fb; 603 struct rvid_buffer cpb; 604 struct radeon_enc_pic enc_pic; 605 rvcn_enc_cmd_t cmd; 606 607 unsigned alignment; 608 unsigned shifter; 609 unsigned bits_in_shifter; 610 unsigned num_zeros; 611 unsigned byte_index; 612 unsigned bits_output; 613 unsigned bits_size; 614 uint32_t total_task_size; 615 uint32_t *p_task_size; 616 617 bool emulation_prevention; 618 bool need_feedback; 619 unsigned dpb_size; 620 rvcn_enc_picture_info_t dpb[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES]; 621 struct rvid_buffer *efc; 622 }; 623 624 void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf, 625 unsigned usage, enum radeon_bo_domain domain, signed offset); 626 627 void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set); 628 629 void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte); 630 631 void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte); 632 633 void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value, 634 unsigned int num_bits); 635 636 void radeon_enc_reset(struct radeon_encoder *enc); 637 638 void radeon_enc_byte_align(struct radeon_encoder *enc); 639 640 void radeon_enc_flush_headers(struct radeon_encoder *enc); 641 642 void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value); 643 644 void radeon_enc_code_se(struct radeon_encoder *enc, int value); 645 646 void radeon_enc_1_2_init(struct radeon_encoder *enc); 647 648 void radeon_enc_2_0_init(struct radeon_encoder *enc); 649 650 void radeon_enc_3_0_init(struct radeon_encoder *enc); 651 652 #endif // _RADEON_VCN_ENC_H 653