1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #ifndef DMUB_CMD_H
27 #define DMUB_CMD_H
28
29 #include <asm/byteorder.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
32 #include <linux/delay.h>
33
34 #include "atomfirmware.h"
35
36 //<DMUB_TYPES>==================================================================
37 /* Basic type definitions. */
38
39 #define __forceinline inline
40
41 /**
42 * Flag from driver to indicate that ABM should be disabled gradually
43 * by slowly reversing all backlight programming and pixel compensation.
44 */
45 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0
46
47 /**
48 * Flag from driver to indicate that ABM should be disabled immediately
49 * and undo all backlight programming and pixel compensation.
50 */
51 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
52
53 /**
54 * Flag from driver to indicate that ABM should be disabled immediately
55 * and keep the current backlight programming and pixel compensation.
56 */
57 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
58
59 /**
60 * Flag from driver to set the current ABM pipe index or ABM operating level.
61 */
62 #define SET_ABM_PIPE_NORMAL 1
63
64 /**
65 * Number of ambient light levels in ABM algorithm.
66 */
67 #define NUM_AMBI_LEVEL 5
68
69 /**
70 * Number of operating/aggression levels in ABM algorithm.
71 */
72 #define NUM_AGGR_LEVEL 4
73
74 /**
75 * Number of segments in the gamma curve.
76 */
77 #define NUM_POWER_FN_SEGS 8
78
79 /**
80 * Number of segments in the backlight curve.
81 */
82 #define NUM_BL_CURVE_SEGS 16
83
84 /**
85 * Maximum number of segments in ABM ACE curve.
86 */
87 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64
88
89 /**
90 * Maximum number of bins in ABM histogram.
91 */
92 #define ABM_MAX_NUM_OF_HG_BINS 64
93
94 /* Maximum number of SubVP streams */
95 #define DMUB_MAX_SUBVP_STREAMS 2
96
97 /* Define max FPO streams as 4 for now. Current implementation today
98 * only supports 1, but could be more in the future. Reduce array
99 * size to ensure the command size remains less than 64 bytes if
100 * adding new fields.
101 */
102 #define DMUB_MAX_FPO_STREAMS 4
103
104 /* Maximum number of streams on any ASIC. */
105 #define DMUB_MAX_STREAMS 6
106
107 /* Maximum number of planes on any ASIC. */
108 #define DMUB_MAX_PLANES 6
109
110 /* Maximum number of phantom planes on any ASIC */
111 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2)
112
113 /* Trace buffer offset for entry */
114 #define TRACE_BUFFER_ENTRY_OFFSET 16
115
116 /**
117 * Maximum number of dirty rects supported by FW.
118 */
119 #define DMUB_MAX_DIRTY_RECTS 3
120
121 /**
122 *
123 * PSR control version legacy
124 */
125 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
126 /**
127 * PSR control version with multi edp support
128 */
129 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
130
131
132 /**
133 * ABM control version legacy
134 */
135 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
136
137 /**
138 * ABM control version with multi edp support
139 */
140 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
141
142 /**
143 * Physical framebuffer address location, 64-bit.
144 */
145 #ifndef PHYSICAL_ADDRESS_LOC
146 #define PHYSICAL_ADDRESS_LOC union large_integer
147 #endif
148
149 /**
150 * OS/FW agnostic memcpy
151 */
152 #ifndef dmub_memcpy
153 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
154 #endif
155
156 /**
157 * OS/FW agnostic memset
158 */
159 #ifndef dmub_memset
160 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
161 #endif
162
163 /**
164 * OS/FW agnostic udelay
165 */
166 #ifndef dmub_udelay
167 #define dmub_udelay(microseconds) udelay(microseconds)
168 #endif
169
170 #pragma pack(push, 1)
171 #define ABM_NUM_OF_ACE_SEGMENTS 5
172
173 union abm_flags {
174 struct {
175 /**
176 * @abm_enabled: Indicates if ABM is enabled.
177 */
178 unsigned int abm_enabled : 1;
179
180 /**
181 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled.
182 */
183 unsigned int disable_abm_requested : 1;
184
185 /**
186 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately.
187 */
188 unsigned int disable_abm_immediately : 1;
189
190 /**
191 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM
192 * to be disabled immediately and keep gain.
193 */
194 unsigned int disable_abm_immediate_keep_gain : 1;
195
196 /**
197 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled.
198 */
199 unsigned int fractional_pwm : 1;
200
201 /**
202 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment
203 * of user backlight level.
204 */
205 unsigned int abm_gradual_bl_change : 1;
206
207 /**
208 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady
209 */
210 unsigned int abm_new_frame : 1;
211
212 /**
213 * @vb_scaling_enabled: Indicates variBright Scaling Enable
214 */
215 unsigned int vb_scaling_enabled : 1;
216 } bitfields;
217
218 unsigned int u32All;
219 };
220
221 struct abm_save_restore {
222 /**
223 * @flags: Misc. ABM flags.
224 */
225 union abm_flags flags;
226
227 /**
228 * @pause: true: pause ABM and get state
229 * false: unpause ABM after setting state
230 */
231 uint32_t pause;
232
233 /**
234 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13)
235 */
236 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS];
237
238 /**
239 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6)
240 */
241 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS];
242
243 /**
244 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6)
245 */
246 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS];
247
248
249 /**
250 * @knee_threshold: Current x-position of ACE knee (u0.16).
251 */
252 uint32_t knee_threshold;
253 /**
254 * @current_gain: Current backlight reduction (u16.16).
255 */
256 uint32_t current_gain;
257 /**
258 * @curr_bl_level: Current actual backlight level converging to target backlight level.
259 */
260 uint16_t curr_bl_level;
261
262 /**
263 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user.
264 */
265 uint16_t curr_user_bl_level;
266
267 };
268
269 /**
270 * union dmub_addr - DMUB physical/virtual 64-bit address.
271 */
272 union dmub_addr {
273 struct {
274 uint32_t low_part; /**< Lower 32 bits */
275 uint32_t high_part; /**< Upper 32 bits */
276 } u; /*<< Low/high bit access */
277 uint64_t quad_part; /*<< 64 bit address */
278 };
279 #pragma pack(pop)
280
281 /**
282 * Dirty rect definition.
283 */
284 struct dmub_rect {
285 /**
286 * Dirty rect x offset.
287 */
288 uint32_t x;
289
290 /**
291 * Dirty rect y offset.
292 */
293 uint32_t y;
294
295 /**
296 * Dirty rect width.
297 */
298 uint32_t width;
299
300 /**
301 * Dirty rect height.
302 */
303 uint32_t height;
304 };
305
306 /**
307 * Flags that can be set by driver to change some PSR behaviour.
308 */
309 union dmub_psr_debug_flags {
310 /**
311 * Debug flags.
312 */
313 struct {
314 /**
315 * Enable visual confirm in FW.
316 */
317 uint32_t visual_confirm : 1;
318
319 /**
320 * Force all selective updates to bw full frame updates.
321 */
322 uint32_t force_full_frame_update : 1;
323
324 /**
325 * Use HW Lock Mgr object to do HW locking in FW.
326 */
327 uint32_t use_hw_lock_mgr : 1;
328
329 /**
330 * Use TPS3 signal when restore main link.
331 */
332 uint32_t force_wakeup_by_tps3 : 1;
333
334 /**
335 * Back to back flip, therefore cannot power down PHY
336 */
337 uint32_t back_to_back_flip : 1;
338
339 /**
340 * Enable visual confirm for IPS
341 */
342 uint32_t enable_ips_visual_confirm : 1;
343 } bitfields;
344
345 /**
346 * Union for debug flags.
347 */
348 uint32_t u32All;
349 };
350
351 /**
352 * Flags that can be set by driver to change some Replay behaviour.
353 */
354 union replay_debug_flags {
355 struct {
356 /**
357 * 0x1 (bit 0)
358 * Enable visual confirm in FW.
359 */
360 uint32_t visual_confirm : 1;
361
362 /**
363 * 0x2 (bit 1)
364 * @skip_crc: Set if need to skip CRC.
365 */
366 uint32_t skip_crc : 1;
367
368 /**
369 * 0x4 (bit 2)
370 * @force_link_power_on: Force disable ALPM control
371 */
372 uint32_t force_link_power_on : 1;
373
374 /**
375 * 0x8 (bit 3)
376 * @force_phy_power_on: Force phy power on
377 */
378 uint32_t force_phy_power_on : 1;
379
380 /**
381 * 0x10 (bit 4)
382 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync
383 */
384 uint32_t timing_resync_disabled : 1;
385
386 /**
387 * 0x20 (bit 5)
388 * @skip_crtc_disabled: CRTC disable skipped
389 */
390 uint32_t skip_crtc_disabled : 1;
391
392 /**
393 * 0x40 (bit 6)
394 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode
395 */
396 uint32_t force_defer_one_frame_update : 1;
397
398 /**
399 * 0x80 (bit 7)
400 * @disable_delay_alpm_on: Force disable delay alpm on
401 */
402 uint32_t disable_delay_alpm_on : 1;
403
404 /**
405 * 0x100 (bit 8)
406 * @disable_desync_error_check: Force disable desync error check
407 */
408 uint32_t disable_desync_error_check : 1;
409
410 /**
411 * 0x200 (bit 9)
412 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady
413 */
414 uint32_t force_self_update_when_abm_non_steady : 1;
415
416 /**
417 * 0x400 (bit 10)
418 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS
419 * If we enter IPS2, the Visual confirm bar will change to yellow
420 */
421 uint32_t enable_ips_visual_confirm : 1;
422
423 /**
424 * 0x800 (bit 11)
425 * @enable_ips_residency_profiling: Enable IPS residency profiling
426 */
427 uint32_t enable_ips_residency_profiling : 1;
428
429 uint32_t reserved : 20;
430 } bitfields;
431
432 uint32_t u32All;
433 };
434
435 union replay_hw_flags {
436 struct {
437 /**
438 * @allow_alpm_fw_standby_mode: To indicate whether the
439 * ALPM FW standby mode is allowed
440 */
441 uint32_t allow_alpm_fw_standby_mode : 1;
442
443 /*
444 * @dsc_enable_status: DSC enable status in driver
445 */
446 uint32_t dsc_enable_status : 1;
447
448 /**
449 * @fec_enable_status: receive fec enable/disable status from driver
450 */
451 uint32_t fec_enable_status : 1;
452
453 /*
454 * @smu_optimizations_en: SMU power optimization.
455 * Only when active display is Replay capable and display enters Replay.
456 * Trigger interrupt to SMU to powerup/down.
457 */
458 uint32_t smu_optimizations_en : 1;
459
460 /**
461 * @phy_power_state: Indicates current phy power state
462 */
463 uint32_t phy_power_state : 1;
464
465 /**
466 * @link_power_state: Indicates current link power state
467 */
468 uint32_t link_power_state : 1;
469 /**
470 * Use TPS3 signal when restore main link.
471 */
472 uint32_t force_wakeup_by_tps3 : 1;
473 } bitfields;
474
475 uint32_t u32All;
476 };
477
478 /**
479 * DMUB feature capabilities.
480 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
481 */
482 struct dmub_feature_caps {
483 /**
484 * Max PSR version supported by FW.
485 */
486 uint8_t psr;
487 uint8_t fw_assisted_mclk_switch_ver;
488 uint8_t reserved[4];
489 uint8_t subvp_psr_support;
490 uint8_t gecc_enable;
491 uint8_t replay_supported;
492 uint8_t replay_reserved[3];
493 };
494
495 struct dmub_visual_confirm_color {
496 /**
497 * Maximum 10 bits color value
498 */
499 uint16_t color_r_cr;
500 uint16_t color_g_y;
501 uint16_t color_b_cb;
502 uint16_t panel_inst;
503 };
504
505 //==============================================================================
506 //</DMUB_TYPES>=================================================================
507 //==============================================================================
508 //< DMUB_META>==================================================================
509 //==============================================================================
510 #pragma pack(push, 1)
511
512 /* Magic value for identifying dmub_fw_meta_info */
513 #define DMUB_FW_META_MAGIC 0x444D5542
514
515 /* Offset from the end of the file to the dmub_fw_meta_info */
516 #define DMUB_FW_META_OFFSET 0x24
517
518 /**
519 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization
520 */
521 union dmub_fw_meta_feature_bits {
522 struct {
523 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */
524 uint32_t reserved : 31;
525 } bits; /**< status bits */
526 uint32_t all; /**< 32-bit access to status bits */
527 };
528
529 /**
530 * struct dmub_fw_meta_info - metadata associated with fw binary
531 *
532 * NOTE: This should be considered a stable API. Fields should
533 * not be repurposed or reordered. New fields should be
534 * added instead to extend the structure.
535 *
536 * @magic_value: magic value identifying DMUB firmware meta info
537 * @fw_region_size: size of the firmware state region
538 * @trace_buffer_size: size of the tracebuffer region
539 * @fw_version: the firmware version information
540 * @dal_fw: 1 if the firmware is DAL
541 * @shared_state_size: size of the shared state region in bytes
542 * @shared_state_features: number of shared state features
543 */
544 struct dmub_fw_meta_info {
545 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
546 uint32_t fw_region_size; /**< size of the firmware state region */
547 uint32_t trace_buffer_size; /**< size of the tracebuffer region */
548 uint32_t fw_version; /**< the firmware version information */
549 uint8_t dal_fw; /**< 1 if the firmware is DAL */
550 uint8_t reserved[3]; /**< padding bits */
551 uint32_t shared_state_size; /**< size of the shared state region in bytes */
552 uint16_t shared_state_features; /**< number of shared state features */
553 uint16_t reserved2; /**< padding bytes */
554 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */
555 };
556
557 /**
558 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
559 */
560 union dmub_fw_meta {
561 struct dmub_fw_meta_info info; /**< metadata info */
562 uint8_t reserved[64]; /**< padding bits */
563 };
564
565 #pragma pack(pop)
566
567 //==============================================================================
568 //< DMUB Trace Buffer>================================================================
569 //==============================================================================
570 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED)
571 /**
572 * dmub_trace_code_t - firmware trace code, 32-bits
573 */
574 typedef uint32_t dmub_trace_code_t;
575
576 /**
577 * struct dmcub_trace_buf_entry - Firmware trace entry
578 */
579 struct dmcub_trace_buf_entry {
580 dmub_trace_code_t trace_code; /**< trace code for the event */
581 uint32_t tick_count; /**< the tick count at time of trace */
582 uint32_t param0; /**< trace defined parameter 0 */
583 uint32_t param1; /**< trace defined parameter 1 */
584 };
585 #endif
586
587 //==============================================================================
588 //< DMUB_STATUS>================================================================
589 //==============================================================================
590
591 /**
592 * DMCUB scratch registers can be used to determine firmware status.
593 * Current scratch register usage is as follows:
594 *
595 * SCRATCH0: FW Boot Status register
596 * SCRATCH5: LVTMA Status Register
597 * SCRATCH15: FW Boot Options register
598 */
599
600 /**
601 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
602 */
603 union dmub_fw_boot_status {
604 struct {
605 uint32_t dal_fw : 1; /**< 1 if DAL FW */
606 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
607 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
608 uint32_t restore_required : 1; /**< 1 if driver should call restore */
609 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
610 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */
611 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */
612 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */
613 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */
614 } bits; /**< status bits */
615 uint32_t all; /**< 32-bit access to status bits */
616 };
617
618 /**
619 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
620 */
621 enum dmub_fw_boot_status_bit {
622 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
623 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
624 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
625 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
626 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
627 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/
628 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
629 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */
630 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */
631 };
632
633 /* Register bit definition for SCRATCH5 */
634 union dmub_lvtma_status {
635 struct {
636 uint32_t psp_ok : 1;
637 uint32_t edp_on : 1;
638 uint32_t reserved : 30;
639 } bits;
640 uint32_t all;
641 };
642
643 enum dmub_lvtma_status_bit {
644 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
645 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
646 };
647
648 enum dmub_ips_disable_type {
649 DMUB_IPS_ENABLE = 0,
650 DMUB_IPS_DISABLE_ALL = 1,
651 DMUB_IPS_DISABLE_IPS1 = 2,
652 DMUB_IPS_DISABLE_IPS2 = 3,
653 DMUB_IPS_DISABLE_IPS2_Z10 = 4,
654 DMUB_IPS_DISABLE_DYNAMIC = 5,
655 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6,
656 };
657
658 #define DMUB_IPS1_ALLOW_MASK 0x00000001
659 #define DMUB_IPS2_ALLOW_MASK 0x00000002
660 #define DMUB_IPS1_COMMIT_MASK 0x00000004
661 #define DMUB_IPS2_COMMIT_MASK 0x00000008
662
663 /**
664 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14
665 */
666 union dmub_fw_boot_options {
667 struct {
668 uint32_t pemu_env : 1; /**< 1 if PEMU */
669 uint32_t fpga_env : 1; /**< 1 if FPGA */
670 uint32_t optimized_init : 1; /**< 1 if optimized init */
671 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
672 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
673 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
674 uint32_t z10_disable: 1; /**< 1 to disable z10 */
675 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */
676 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
677 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */
678 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */
679 /**< 1 if all root clock gating is enabled and low power memory is enabled*/
680 uint32_t power_optimization: 1;
681 uint32_t diag_env: 1; /* 1 if diagnostic environment */
682 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/
683 uint32_t usb4_cm_version: 1; /**< 1 CM support */
684 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */
685 uint32_t reserved0: 1;
686 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/
687 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */
688 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/
689 uint32_t ips_disable: 3; /* options to disable ips support*/
690 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */
691 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */
692 uint32_t reserved : 7; /**< reserved */
693 } bits; /**< boot bits */
694 uint32_t all; /**< 32-bit access to bits */
695 };
696
697 enum dmub_fw_boot_options_bit {
698 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
699 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
700 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
701 };
702
703 //==============================================================================
704 //< DMUB_SHARED_STATE>==========================================================
705 //==============================================================================
706
707 /**
708 * Shared firmware state between driver and firmware for lockless communication
709 * in situations where the inbox/outbox may be unavailable.
710 *
711 * Each structure *must* be at most 256-bytes in size. The layout allocation is
712 * described below:
713 *
714 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]...
715 */
716
717 /**
718 * enum dmub_shared_state_feature_id - List of shared state features.
719 */
720 enum dmub_shared_state_feature_id {
721 DMUB_SHARED_SHARE_FEATURE__INVALID = 0,
722 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1,
723 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2,
724 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */
725 };
726
727 /**
728 * struct dmub_shared_state_ips_fw - Firmware signals for IPS.
729 */
730 union dmub_shared_state_ips_fw_signals {
731 struct {
732 uint32_t ips1_commit : 1; /**< 1 if in IPS1 */
733 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */
734 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */
735 uint32_t detection_required : 1; /**< 1 if detection is required */
736 uint32_t reserved_bits : 28; /**< Reversed */
737 } bits;
738 uint32_t all;
739 };
740
741 /**
742 * struct dmub_shared_state_ips_signals - Firmware signals for IPS.
743 */
744 union dmub_shared_state_ips_driver_signals {
745 struct {
746 uint32_t allow_pg : 1; /**< 1 if PG is allowed */
747 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */
748 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */
749 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */
750 uint32_t reserved_bits : 28; /**< Reversed bits */
751 } bits;
752 uint32_t all;
753 };
754
755 /**
756 * IPS FW Version
757 */
758 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1
759
760 /**
761 * struct dmub_shared_state_ips_fw - Firmware state for IPS.
762 */
763 struct dmub_shared_state_ips_fw {
764 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */
765 uint32_t rcg_entry_count; /**< Entry counter for RCG */
766 uint32_t rcg_exit_count; /**< Exit counter for RCG */
767 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */
768 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */
769 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */
770 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */
771 uint32_t reserved[55]; /**< Reversed, to be updated when adding new fields. */
772 }; /* 248-bytes, fixed */
773
774 /**
775 * IPS Driver Version
776 */
777 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1
778
779 /**
780 * struct dmub_shared_state_ips_driver - Driver state for IPS.
781 */
782 struct dmub_shared_state_ips_driver {
783 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */
784 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */
785 }; /* 248-bytes, fixed */
786
787 /**
788 * enum dmub_shared_state_feature_common - Generic payload.
789 */
790 struct dmub_shared_state_feature_common {
791 uint32_t padding[62];
792 }; /* 248-bytes, fixed */
793
794 /**
795 * enum dmub_shared_state_feature_header - Feature description.
796 */
797 struct dmub_shared_state_feature_header {
798 uint16_t id; /**< Feature ID */
799 uint16_t version; /**< Feature version */
800 uint32_t reserved; /**< Reserved bytes. */
801 }; /* 8 bytes, fixed */
802
803 /**
804 * struct dmub_shared_state_feature_block - Feature block.
805 */
806 struct dmub_shared_state_feature_block {
807 struct dmub_shared_state_feature_header header; /**< Shared state header. */
808 union dmub_shared_feature_state_union {
809 struct dmub_shared_state_feature_common common; /**< Generic data */
810 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */
811 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */
812 } data; /**< Shared state data. */
813 }; /* 256-bytes, fixed */
814
815 /**
816 * Shared state size in bytes.
817 */
818 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \
819 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block))
820
821 //==============================================================================
822 //</DMUB_STATUS>================================================================
823 //==============================================================================
824 //< DMUB_VBIOS>=================================================================
825 //==============================================================================
826
827 /*
828 * enum dmub_cmd_vbios_type - VBIOS commands.
829 *
830 * Command IDs should be treated as stable ABI.
831 * Do not reuse or modify IDs.
832 */
833 enum dmub_cmd_vbios_type {
834 /**
835 * Configures the DIG encoder.
836 */
837 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
838 /**
839 * Controls the PHY.
840 */
841 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
842 /**
843 * Sets the pixel clock/symbol clock.
844 */
845 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
846 /**
847 * Enables or disables power gating.
848 */
849 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
850 /**
851 * Controls embedded panels.
852 */
853 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
854 /**
855 * Query DP alt status on a transmitter.
856 */
857 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26,
858 /**
859 * Control PHY FSM
860 */
861 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29,
862 /**
863 * Controls domain power gating
864 */
865 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28,
866 };
867
868 //==============================================================================
869 //</DMUB_VBIOS>=================================================================
870 //==============================================================================
871 //< DMUB_GPINT>=================================================================
872 //==============================================================================
873
874 /**
875 * The shifts and masks below may alternatively be used to format and read
876 * the command register bits.
877 */
878
879 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
880 #define DMUB_GPINT_DATA_PARAM_SHIFT 0
881
882 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
883 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
884
885 #define DMUB_GPINT_DATA_STATUS_MASK 0xF
886 #define DMUB_GPINT_DATA_STATUS_SHIFT 28
887
888 /**
889 * Command responses.
890 */
891
892 /**
893 * Return response for DMUB_GPINT__STOP_FW command.
894 */
895 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
896
897 /**
898 * union dmub_gpint_data_register - Format for sending a command via the GPINT.
899 */
900 union dmub_gpint_data_register {
901 struct {
902 uint32_t param : 16; /**< 16-bit parameter */
903 uint32_t command_code : 12; /**< GPINT command */
904 uint32_t status : 4; /**< Command status bit */
905 } bits; /**< GPINT bit access */
906 uint32_t all; /**< GPINT 32-bit access */
907 };
908
909 /*
910 * enum dmub_gpint_command - GPINT command to DMCUB FW
911 *
912 * Command IDs should be treated as stable ABI.
913 * Do not reuse or modify IDs.
914 */
915 enum dmub_gpint_command {
916 /**
917 * Invalid command, ignored.
918 */
919 DMUB_GPINT__INVALID_COMMAND = 0,
920 /**
921 * DESC: Queries the firmware version.
922 * RETURN: Firmware version.
923 */
924 DMUB_GPINT__GET_FW_VERSION = 1,
925 /**
926 * DESC: Halts the firmware.
927 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
928 */
929 DMUB_GPINT__STOP_FW = 2,
930 /**
931 * DESC: Get PSR state from FW.
932 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
933 */
934 DMUB_GPINT__GET_PSR_STATE = 7,
935 /**
936 * DESC: Notifies DMCUB of the currently active streams.
937 * ARGS: Stream mask, 1 bit per active stream index.
938 */
939 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
940 /**
941 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
942 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
943 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
944 * RETURN: PSR residency in milli-percent.
945 */
946 DMUB_GPINT__PSR_RESIDENCY = 9,
947
948 /**
949 * DESC: Notifies DMCUB detection is done so detection required can be cleared.
950 */
951 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
952
953 /**
954 * DESC: Get REPLAY state from FW.
955 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value.
956 */
957 DMUB_GPINT__GET_REPLAY_STATE = 13,
958
959 /**
960 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value.
961 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
962 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
963 * RETURN: REPLAY residency in milli-percent.
964 */
965 DMUB_GPINT__REPLAY_RESIDENCY = 14,
966
967 /**
968 * DESC: Copy bounding box to the host.
969 * ARGS: Version of bounding box to copy
970 * RETURN: Result of copying bounding box
971 */
972 DMUB_GPINT__BB_COPY = 96,
973
974 /**
975 * DESC: Updates the host addresses bit48~bit63 for bounding box.
976 * ARGS: The word3 for the 64 bit address
977 */
978 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97,
979
980 /**
981 * DESC: Updates the host addresses bit32~bit47 for bounding box.
982 * ARGS: The word2 for the 64 bit address
983 */
984 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98,
985
986 /**
987 * DESC: Updates the host addresses bit16~bit31 for bounding box.
988 * ARGS: The word1 for the 64 bit address
989 */
990 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99,
991
992 /**
993 * DESC: Updates the host addresses bit0~bit15 for bounding box.
994 * ARGS: The word0 for the 64 bit address
995 */
996 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100,
997
998 /**
999 * DESC: Updates the trace buffer lower 32-bit mask.
1000 * ARGS: The new mask
1001 * RETURN: Lower 32-bit mask.
1002 */
1003 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101,
1004
1005 /**
1006 * DESC: Updates the trace buffer mask bit0~bit15.
1007 * ARGS: The new mask
1008 * RETURN: Lower 32-bit mask.
1009 */
1010 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102,
1011
1012 /**
1013 * DESC: Updates the trace buffer mask bit16~bit31.
1014 * ARGS: The new mask
1015 * RETURN: Lower 32-bit mask.
1016 */
1017 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103,
1018
1019 /**
1020 * DESC: Updates the trace buffer mask bit32~bit47.
1021 * ARGS: The new mask
1022 * RETURN: Lower 32-bit mask.
1023 */
1024 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114,
1025
1026 /**
1027 * DESC: Updates the trace buffer mask bit48~bit63.
1028 * ARGS: The new mask
1029 * RETURN: Lower 32-bit mask.
1030 */
1031 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115,
1032
1033 /**
1034 * DESC: Read the trace buffer mask bi0~bit15.
1035 */
1036 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116,
1037
1038 /**
1039 * DESC: Read the trace buffer mask bit16~bit31.
1040 */
1041 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117,
1042
1043 /**
1044 * DESC: Read the trace buffer mask bi32~bit47.
1045 */
1046 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118,
1047
1048 /**
1049 * DESC: Updates the trace buffer mask bit32~bit63.
1050 */
1051 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119,
1052
1053 /**
1054 * DESC: Enable measurements for various task duration
1055 * ARGS: 0 - Disable measurement
1056 * 1 - Enable measurement
1057 */
1058 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123,
1059 };
1060
1061 /**
1062 * INBOX0 generic command definition
1063 */
1064 union dmub_inbox0_cmd_common {
1065 struct {
1066 uint32_t command_code: 8; /**< INBOX0 command code */
1067 uint32_t param: 24; /**< 24-bit parameter */
1068 } bits;
1069 uint32_t all;
1070 };
1071
1072 /**
1073 * INBOX0 hw_lock command definition
1074 */
1075 union dmub_inbox0_cmd_lock_hw {
1076 struct {
1077 uint32_t command_code: 8;
1078
1079 /* NOTE: Must be have enough bits to match: enum hw_lock_client */
1080 uint32_t hw_lock_client: 2;
1081
1082 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
1083 uint32_t otg_inst: 3;
1084 uint32_t opp_inst: 3;
1085 uint32_t dig_inst: 3;
1086
1087 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */
1088 uint32_t lock_pipe: 1;
1089 uint32_t lock_cursor: 1;
1090 uint32_t lock_dig: 1;
1091 uint32_t triple_buffer_lock: 1;
1092
1093 uint32_t lock: 1; /**< Lock */
1094 uint32_t should_release: 1; /**< Release */
1095 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */
1096 } bits;
1097 uint32_t all;
1098 };
1099
1100 union dmub_inbox0_data_register {
1101 union dmub_inbox0_cmd_common inbox0_cmd_common;
1102 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
1103 };
1104
1105 enum dmub_inbox0_command {
1106 /**
1107 * DESC: Invalid command, ignored.
1108 */
1109 DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
1110 /**
1111 * DESC: Notification to acquire/release HW lock
1112 * ARGS:
1113 */
1114 DMUB_INBOX0_CMD__HW_LOCK = 1,
1115 };
1116 //==============================================================================
1117 //</DMUB_GPINT>=================================================================
1118 //==============================================================================
1119 //< DMUB_CMD>===================================================================
1120 //==============================================================================
1121
1122 /**
1123 * Size in bytes of each DMUB command.
1124 */
1125 #define DMUB_RB_CMD_SIZE 64
1126
1127 /**
1128 * Maximum number of items in the DMUB ringbuffer.
1129 */
1130 #define DMUB_RB_MAX_ENTRY 128
1131
1132 /**
1133 * Ringbuffer size in bytes.
1134 */
1135 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
1136
1137 /**
1138 * REG_SET mask for reg offload.
1139 */
1140 #define REG_SET_MASK 0xFFFF
1141
1142 /*
1143 * enum dmub_cmd_type - DMUB inbox command.
1144 *
1145 * Command IDs should be treated as stable ABI.
1146 * Do not reuse or modify IDs.
1147 */
1148 enum dmub_cmd_type {
1149 /**
1150 * Invalid command.
1151 */
1152 DMUB_CMD__NULL = 0,
1153 /**
1154 * Read modify write register sequence offload.
1155 */
1156 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
1157 /**
1158 * Field update register sequence offload.
1159 */
1160 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
1161 /**
1162 * Burst write sequence offload.
1163 */
1164 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
1165 /**
1166 * Reg wait sequence offload.
1167 */
1168 DMUB_CMD__REG_REG_WAIT = 4,
1169 /**
1170 * Workaround to avoid HUBP underflow during NV12 playback.
1171 */
1172 DMUB_CMD__PLAT_54186_WA = 5,
1173 /**
1174 * Command type used to query FW feature caps.
1175 */
1176 DMUB_CMD__QUERY_FEATURE_CAPS = 6,
1177 /**
1178 * Command type used to get visual confirm color.
1179 */
1180 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8,
1181 /**
1182 * Command type used for all PSR commands.
1183 */
1184 DMUB_CMD__PSR = 64,
1185 /**
1186 * Command type used for all MALL commands.
1187 */
1188 DMUB_CMD__MALL = 65,
1189 /**
1190 * Command type used for all ABM commands.
1191 */
1192 DMUB_CMD__ABM = 66,
1193 /**
1194 * Command type used to update dirty rects in FW.
1195 */
1196 DMUB_CMD__UPDATE_DIRTY_RECT = 67,
1197 /**
1198 * Command type used to update cursor info in FW.
1199 */
1200 DMUB_CMD__UPDATE_CURSOR_INFO = 68,
1201 /**
1202 * Command type used for HW locking in FW.
1203 */
1204 DMUB_CMD__HW_LOCK = 69,
1205 /**
1206 * Command type used to access DP AUX.
1207 */
1208 DMUB_CMD__DP_AUX_ACCESS = 70,
1209 /**
1210 * Command type used for OUTBOX1 notification enable
1211 */
1212 DMUB_CMD__OUTBOX1_ENABLE = 71,
1213
1214 /**
1215 * Command type used for all idle optimization commands.
1216 */
1217 DMUB_CMD__IDLE_OPT = 72,
1218 /**
1219 * Command type used for all clock manager commands.
1220 */
1221 DMUB_CMD__CLK_MGR = 73,
1222 /**
1223 * Command type used for all panel control commands.
1224 */
1225 DMUB_CMD__PANEL_CNTL = 74,
1226
1227 /**
1228 * Command type used for all CAB commands.
1229 */
1230 DMUB_CMD__CAB_FOR_SS = 75,
1231
1232 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76,
1233
1234 /**
1235 * Command type used for interfacing with DPIA.
1236 */
1237 DMUB_CMD__DPIA = 77,
1238 /**
1239 * Command type used for EDID CEA parsing
1240 */
1241 DMUB_CMD__EDID_CEA = 79,
1242 /**
1243 * Command type used for getting usbc cable ID
1244 */
1245 DMUB_CMD_GET_USBC_CABLE_ID = 81,
1246 /**
1247 * Command type used to query HPD state.
1248 */
1249 DMUB_CMD__QUERY_HPD_STATE = 82,
1250 /**
1251 * Command type used for all VBIOS interface commands.
1252 */
1253 /**
1254 * Command type used for all REPLAY commands.
1255 */
1256 DMUB_CMD__REPLAY = 83,
1257
1258 /**
1259 * Command type used for all SECURE_DISPLAY commands.
1260 */
1261 DMUB_CMD__SECURE_DISPLAY = 85,
1262
1263 /**
1264 * Command type used to set DPIA HPD interrupt state
1265 */
1266 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86,
1267
1268 /**
1269 * Command type used for all PSP commands.
1270 */
1271 DMUB_CMD__PSP = 88,
1272
1273 DMUB_CMD__VBIOS = 128,
1274 };
1275
1276 /**
1277 * enum dmub_out_cmd_type - DMUB outbox commands.
1278 */
1279 enum dmub_out_cmd_type {
1280 /**
1281 * Invalid outbox command, ignored.
1282 */
1283 DMUB_OUT_CMD__NULL = 0,
1284 /**
1285 * Command type used for DP AUX Reply data notification
1286 */
1287 DMUB_OUT_CMD__DP_AUX_REPLY = 1,
1288 /**
1289 * Command type used for DP HPD event notification
1290 */
1291 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
1292 /**
1293 * Command type used for SET_CONFIG Reply notification
1294 */
1295 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3,
1296 /**
1297 * Command type used for USB4 DPIA notification
1298 */
1299 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5,
1300 /**
1301 * Command type used for HPD redetect notification
1302 */
1303 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6,
1304 };
1305
1306 /* DMUB_CMD__DPIA command sub-types. */
1307 enum dmub_cmd_dpia_type {
1308 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0,
1309 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1,
1310 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2,
1311 };
1312
1313 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */
1314 enum dmub_cmd_dpia_notification_type {
1315 DPIA_NOTIFY__BW_ALLOCATION = 0,
1316 };
1317
1318 #pragma pack(push, 1)
1319
1320 /**
1321 * struct dmub_cmd_header - Common command header fields.
1322 */
1323 struct dmub_cmd_header {
1324 unsigned int type : 8; /**< command type */
1325 unsigned int sub_type : 8; /**< command sub type */
1326 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
1327 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
1328 unsigned int reserved0 : 6; /**< reserved bits */
1329 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */
1330 unsigned int reserved1 : 2; /**< reserved bits */
1331 };
1332
1333 /*
1334 * struct dmub_cmd_read_modify_write_sequence - Read modify write
1335 *
1336 * 60 payload bytes can hold up to 5 sets of read modify writes,
1337 * each take 3 dwords.
1338 *
1339 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
1340 *
1341 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
1342 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
1343 */
1344 struct dmub_cmd_read_modify_write_sequence {
1345 uint32_t addr; /**< register address */
1346 uint32_t modify_mask; /**< modify mask */
1347 uint32_t modify_value; /**< modify value */
1348 };
1349
1350 /**
1351 * Maximum number of ops in read modify write sequence.
1352 */
1353 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
1354
1355 /**
1356 * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
1357 */
1358 struct dmub_rb_cmd_read_modify_write {
1359 struct dmub_cmd_header header; /**< command header */
1360 /**
1361 * Read modify write sequence.
1362 */
1363 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
1364 };
1365
1366 /*
1367 * Update a register with specified masks and values sequeunce
1368 *
1369 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
1370 *
1371 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
1372 *
1373 *
1374 * USE CASE:
1375 * 1. auto-increment register where additional read would update pointer and produce wrong result
1376 * 2. toggle a bit without read in the middle
1377 */
1378
1379 struct dmub_cmd_reg_field_update_sequence {
1380 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
1381 uint32_t modify_value; /**< value to update with */
1382 };
1383
1384 /**
1385 * Maximum number of ops in field update sequence.
1386 */
1387 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
1388
1389 /**
1390 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
1391 */
1392 struct dmub_rb_cmd_reg_field_update_sequence {
1393 struct dmub_cmd_header header; /**< command header */
1394 uint32_t addr; /**< register address */
1395 /**
1396 * Field update sequence.
1397 */
1398 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
1399 };
1400
1401
1402 /**
1403 * Maximum number of burst write values.
1404 */
1405 #define DMUB_BURST_WRITE_VALUES__MAX 14
1406
1407 /*
1408 * struct dmub_rb_cmd_burst_write - Burst write
1409 *
1410 * support use case such as writing out LUTs.
1411 *
1412 * 60 payload bytes can hold up to 14 values to write to given address
1413 *
1414 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
1415 */
1416 struct dmub_rb_cmd_burst_write {
1417 struct dmub_cmd_header header; /**< command header */
1418 uint32_t addr; /**< register start address */
1419 /**
1420 * Burst write register values.
1421 */
1422 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
1423 };
1424
1425 /**
1426 * struct dmub_rb_cmd_common - Common command header
1427 */
1428 struct dmub_rb_cmd_common {
1429 struct dmub_cmd_header header; /**< command header */
1430 /**
1431 * Padding to RB_CMD_SIZE
1432 */
1433 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
1434 };
1435
1436 /**
1437 * struct dmub_cmd_reg_wait_data - Register wait data
1438 */
1439 struct dmub_cmd_reg_wait_data {
1440 uint32_t addr; /**< Register address */
1441 uint32_t mask; /**< Mask for register bits */
1442 uint32_t condition_field_value; /**< Value to wait for */
1443 uint32_t time_out_us; /**< Time out for reg wait in microseconds */
1444 };
1445
1446 /**
1447 * struct dmub_rb_cmd_reg_wait - Register wait command
1448 */
1449 struct dmub_rb_cmd_reg_wait {
1450 struct dmub_cmd_header header; /**< Command header */
1451 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
1452 };
1453
1454 /**
1455 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
1456 *
1457 * Reprograms surface parameters to avoid underflow.
1458 */
1459 struct dmub_cmd_PLAT_54186_wa {
1460 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
1461 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
1462 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
1463 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
1464 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
1465 struct {
1466 uint32_t hubp_inst : 4; /**< HUBP instance */
1467 uint32_t tmz_surface : 1; /**< TMZ enable or disable */
1468 uint32_t immediate :1; /**< Immediate flip */
1469 uint32_t vmid : 4; /**< VMID */
1470 uint32_t grph_stereo : 1; /**< 1 if stereo */
1471 uint32_t reserved : 21; /**< Reserved */
1472 } flip_params; /**< Pageflip parameters */
1473 uint32_t reserved[9]; /**< Reserved bits */
1474 };
1475
1476 /**
1477 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
1478 */
1479 struct dmub_rb_cmd_PLAT_54186_wa {
1480 struct dmub_cmd_header header; /**< Command header */
1481 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
1482 };
1483
1484 /**
1485 * enum dmub_cmd_mall_type - MALL commands
1486 */
1487 enum dmub_cmd_mall_type {
1488 /**
1489 * Allows display refresh from MALL.
1490 */
1491 DMUB_CMD__MALL_ACTION_ALLOW = 0,
1492 /**
1493 * Disallows display refresh from MALL.
1494 */
1495 DMUB_CMD__MALL_ACTION_DISALLOW = 1,
1496 /**
1497 * Cursor copy for MALL.
1498 */
1499 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
1500 /**
1501 * Controls DF requests.
1502 */
1503 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
1504 };
1505
1506 /**
1507 * struct dmub_rb_cmd_mall - MALL command data.
1508 */
1509 struct dmub_rb_cmd_mall {
1510 struct dmub_cmd_header header; /**< Common command header */
1511 union dmub_addr cursor_copy_src; /**< Cursor copy address */
1512 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
1513 uint32_t tmr_delay; /**< Timer delay */
1514 uint32_t tmr_scale; /**< Timer scale */
1515 uint16_t cursor_width; /**< Cursor width in pixels */
1516 uint16_t cursor_pitch; /**< Cursor pitch in pixels */
1517 uint16_t cursor_height; /**< Cursor height in pixels */
1518 uint8_t cursor_bpp; /**< Cursor bits per pixel */
1519 uint8_t debug_bits; /**< Debug bits */
1520
1521 uint8_t reserved1; /**< Reserved bits */
1522 uint8_t reserved2; /**< Reserved bits */
1523 };
1524
1525 /**
1526 * enum dmub_cmd_cab_type - CAB command data.
1527 */
1528 enum dmub_cmd_cab_type {
1529 /**
1530 * No idle optimizations (i.e. no CAB)
1531 */
1532 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0,
1533 /**
1534 * No DCN requests for memory
1535 */
1536 DMUB_CMD__CAB_NO_DCN_REQ = 1,
1537 /**
1538 * Fit surfaces in CAB (i.e. CAB enable)
1539 */
1540 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,
1541 /**
1542 * Do not fit surfaces in CAB (i.e. no CAB)
1543 */
1544 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3,
1545 };
1546
1547 /**
1548 * struct dmub_rb_cmd_cab - CAB command data.
1549 */
1550 struct dmub_rb_cmd_cab_for_ss {
1551 struct dmub_cmd_header header;
1552 uint8_t cab_alloc_ways; /* total number of ways */
1553 uint8_t debug_bits; /* debug bits */
1554 };
1555
1556 /**
1557 * Enum for indicating which MCLK switch mode per pipe
1558 */
1559 enum mclk_switch_mode {
1560 NONE = 0,
1561 FPO = 1,
1562 SUBVP = 2,
1563 VBLANK = 3,
1564 };
1565
1566 /* Per pipe struct which stores the MCLK switch mode
1567 * data to be sent to DMUB.
1568 * Named "v2" for now -- once FPO and SUBVP are fully merged
1569 * the type name can be updated
1570 */
1571 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 {
1572 union {
1573 struct {
1574 uint32_t pix_clk_100hz;
1575 uint16_t main_vblank_start;
1576 uint16_t main_vblank_end;
1577 uint16_t mall_region_lines;
1578 uint16_t prefetch_lines;
1579 uint16_t prefetch_to_mall_start_lines;
1580 uint16_t processing_delay_lines;
1581 uint16_t htotal; // required to calculate line time for multi-display cases
1582 uint16_t vtotal;
1583 uint8_t main_pipe_index;
1584 uint8_t phantom_pipe_index;
1585 /* Since the microschedule is calculated in terms of OTG lines,
1586 * include any scaling factors to make sure when we get accurate
1587 * conversion when programming MALL_START_LINE (which is in terms
1588 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor
1589 * is 1/2 (numerator = 1, denominator = 2).
1590 */
1591 uint8_t scale_factor_numerator;
1592 uint8_t scale_factor_denominator;
1593 uint8_t is_drr;
1594 uint8_t main_split_pipe_index;
1595 uint8_t phantom_split_pipe_index;
1596 } subvp_data;
1597
1598 struct {
1599 uint32_t pix_clk_100hz;
1600 uint16_t vblank_start;
1601 uint16_t vblank_end;
1602 uint16_t vstartup_start;
1603 uint16_t vtotal;
1604 uint16_t htotal;
1605 uint8_t vblank_pipe_index;
1606 uint8_t padding[1];
1607 struct {
1608 uint8_t drr_in_use;
1609 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame
1610 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK
1611 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling
1612 uint8_t use_ramping; // Use ramping or not
1613 uint8_t drr_vblank_start_margin;
1614 } drr_info; // DRR considered as part of SubVP + VBLANK case
1615 } vblank_data;
1616 } pipe_config;
1617
1618 /* - subvp_data in the union (pipe_config) takes up 27 bytes.
1619 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only
1620 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state).
1621 */
1622 uint8_t mode; // enum mclk_switch_mode
1623 };
1624
1625 /**
1626 * Config data for Sub-VP and FPO
1627 * Named "v2" for now -- once FPO and SUBVP are fully merged
1628 * the type name can be updated
1629 */
1630 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 {
1631 uint16_t watermark_a_cache;
1632 uint8_t vertical_int_margin_us;
1633 uint8_t pstate_allow_width_us;
1634 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS];
1635 };
1636
1637 /**
1638 * DMUB rb command definition for Sub-VP and FPO
1639 * Named "v2" for now -- once FPO and SUBVP are fully merged
1640 * the type name can be updated
1641 */
1642 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 {
1643 struct dmub_cmd_header header;
1644 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data;
1645 };
1646
1647 struct dmub_flip_addr_info {
1648 uint32_t surf_addr_lo;
1649 uint32_t surf_addr_c_lo;
1650 uint32_t meta_addr_lo;
1651 uint32_t meta_addr_c_lo;
1652 uint16_t surf_addr_hi;
1653 uint16_t surf_addr_c_hi;
1654 uint16_t meta_addr_hi;
1655 uint16_t meta_addr_c_hi;
1656 };
1657
1658 struct dmub_fams2_flip_info {
1659 union {
1660 struct {
1661 uint8_t is_immediate: 1;
1662 } bits;
1663 uint8_t all;
1664 } config;
1665 uint8_t otg_inst;
1666 uint8_t pipe_mask;
1667 uint8_t pad;
1668 struct dmub_flip_addr_info addr_info;
1669 };
1670
1671 struct dmub_rb_cmd_fams2_flip {
1672 struct dmub_cmd_header header;
1673 struct dmub_fams2_flip_info flip_info;
1674 };
1675
1676 struct dmub_optc_state_v2 {
1677 uint32_t v_total_min;
1678 uint32_t v_total_max;
1679 uint32_t v_total_mid;
1680 uint32_t v_total_mid_frame_num;
1681 uint8_t program_manual_trigger;
1682 uint8_t tg_inst;
1683 uint8_t pad[2];
1684 };
1685
1686 struct dmub_optc_position {
1687 uint32_t vpos;
1688 uint32_t hpos;
1689 uint32_t frame;
1690 };
1691
1692 struct dmub_rb_cmd_fams2_drr_update {
1693 struct dmub_cmd_header header;
1694 struct dmub_optc_state_v2 dmub_optc_state_req;
1695 };
1696
1697 /* HW and FW global configuration data for FAMS2 */
1698 /* FAMS2 types and structs */
1699 enum fams2_stream_type {
1700 FAMS2_STREAM_TYPE_NONE = 0,
1701 FAMS2_STREAM_TYPE_VBLANK = 1,
1702 FAMS2_STREAM_TYPE_VACTIVE = 2,
1703 FAMS2_STREAM_TYPE_DRR = 3,
1704 FAMS2_STREAM_TYPE_SUBVP = 4,
1705 };
1706
1707 /* dynamic stream state */
1708 struct dmub_fams2_legacy_stream_dynamic_state {
1709 uint8_t force_allow_at_vblank;
1710 uint8_t pad[3];
1711 };
1712
1713 struct dmub_fams2_subvp_stream_dynamic_state {
1714 uint16_t viewport_start_hubp_vline;
1715 uint16_t viewport_height_hubp_vlines;
1716 uint16_t viewport_start_c_hubp_vline;
1717 uint16_t viewport_height_c_hubp_vlines;
1718 uint16_t phantom_viewport_height_hubp_vlines;
1719 uint16_t phantom_viewport_height_c_hubp_vlines;
1720 uint16_t microschedule_start_otg_vline;
1721 uint16_t mall_start_otg_vline;
1722 uint16_t mall_start_hubp_vline;
1723 uint16_t mall_start_c_hubp_vline;
1724 uint8_t force_allow_at_vblank_only;
1725 uint8_t pad[3];
1726 };
1727
1728 struct dmub_fams2_drr_stream_dynamic_state {
1729 uint16_t stretched_vtotal;
1730 uint8_t use_cur_vtotal;
1731 uint8_t pad;
1732 };
1733
1734 struct dmub_fams2_stream_dynamic_state {
1735 uint64_t ref_tick;
1736 uint32_t cur_vtotal;
1737 uint16_t adjusted_allow_end_otg_vline;
1738 uint8_t pad[2];
1739 struct dmub_optc_position ref_otg_pos;
1740 struct dmub_optc_position target_otg_pos;
1741 union {
1742 struct dmub_fams2_legacy_stream_dynamic_state legacy;
1743 struct dmub_fams2_subvp_stream_dynamic_state subvp;
1744 struct dmub_fams2_drr_stream_dynamic_state drr;
1745 } sub_state;
1746 };
1747
1748 /* static stream state */
1749 struct dmub_fams2_legacy_stream_static_state {
1750 uint8_t vactive_det_fill_delay_otg_vlines;
1751 uint8_t programming_delay_otg_vlines;
1752 };
1753
1754 struct dmub_fams2_subvp_stream_static_state {
1755 uint16_t vratio_numerator;
1756 uint16_t vratio_denominator;
1757 uint16_t phantom_vtotal;
1758 uint16_t phantom_vactive;
1759 union {
1760 struct {
1761 uint8_t is_multi_planar : 1;
1762 uint8_t is_yuv420 : 1;
1763 } bits;
1764 uint8_t all;
1765 } config;
1766 uint8_t programming_delay_otg_vlines;
1767 uint8_t prefetch_to_mall_otg_vlines;
1768 uint8_t phantom_otg_inst;
1769 uint8_t phantom_pipe_mask;
1770 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)
1771 };
1772
1773 struct dmub_fams2_drr_stream_static_state {
1774 uint16_t nom_stretched_vtotal;
1775 uint8_t programming_delay_otg_vlines;
1776 uint8_t only_stretch_if_required;
1777 uint8_t pad[2];
1778 };
1779
1780 struct dmub_fams2_stream_static_state {
1781 enum fams2_stream_type type;
1782 uint32_t otg_vline_time_ns;
1783 uint32_t otg_vline_time_ticks;
1784 uint16_t htotal;
1785 uint16_t vtotal; // nominal vtotal
1786 uint16_t vblank_start;
1787 uint16_t vblank_end;
1788 uint16_t max_vtotal;
1789 uint16_t allow_start_otg_vline;
1790 uint16_t allow_end_otg_vline;
1791 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed
1792 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start
1793 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution
1794 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing
1795 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline
1796 union {
1797 struct {
1798 uint8_t is_drr: 1; // stream is DRR enabled
1799 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal
1800 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank
1801 } bits;
1802 uint8_t all;
1803 } config;
1804 uint8_t otg_inst;
1805 uint8_t pipe_mask; // pipe mask for the whole config
1806 uint8_t num_planes;
1807 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)
1808 uint8_t pad[DMUB_MAX_PLANES % 4];
1809 union {
1810 struct dmub_fams2_legacy_stream_static_state legacy;
1811 struct dmub_fams2_subvp_stream_static_state subvp;
1812 struct dmub_fams2_drr_stream_static_state drr;
1813 } sub_state;
1814 };
1815
1816 /**
1817 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive
1818 * p-state request to allow latency
1819 */
1820 enum dmub_fams2_allow_delay_check_mode {
1821 /* No check for request to allow delay */
1822 FAMS2_ALLOW_DELAY_CHECK_NONE = 0,
1823 /* Check for request to allow delay */
1824 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1,
1825 /* Check for prepare to allow delay */
1826 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2,
1827 };
1828
1829 union dmub_fams2_global_feature_config {
1830 struct {
1831 uint32_t enable: 1;
1832 uint32_t enable_ppt_check: 1;
1833 uint32_t enable_stall_recovery: 1;
1834 uint32_t enable_debug: 1;
1835 uint32_t enable_offload_flip: 1;
1836 uint32_t enable_visual_confirm: 1;
1837 uint32_t allow_delay_check_mode: 2;
1838 uint32_t reserved: 24;
1839 } bits;
1840 uint32_t all;
1841 };
1842
1843 struct dmub_cmd_fams2_global_config {
1844 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin
1845 uint32_t lock_wait_time_us; // time to forecast acquisition of lock
1846 uint32_t num_streams;
1847 union dmub_fams2_global_feature_config features;
1848 uint32_t recovery_timeout_us;
1849 uint32_t hwfq_flip_programming_delay_us;
1850 };
1851
1852 union dmub_cmd_fams2_config {
1853 struct dmub_cmd_fams2_global_config global;
1854 struct dmub_fams2_stream_static_state stream;
1855 };
1856
1857 /**
1858 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy)
1859 */
1860 struct dmub_rb_cmd_fams2 {
1861 struct dmub_cmd_header header;
1862 union dmub_cmd_fams2_config config;
1863 };
1864
1865 /**
1866 * enum dmub_cmd_idle_opt_type - Idle optimization command type.
1867 */
1868 enum dmub_cmd_idle_opt_type {
1869 /**
1870 * DCN hardware restore.
1871 */
1872 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
1873
1874 /**
1875 * DCN hardware save.
1876 */
1877 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1,
1878
1879 /**
1880 * DCN hardware notify idle.
1881 */
1882 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2,
1883
1884 /**
1885 * DCN hardware notify power state.
1886 */
1887 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3,
1888 };
1889
1890 /**
1891 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
1892 */
1893 struct dmub_rb_cmd_idle_opt_dcn_restore {
1894 struct dmub_cmd_header header; /**< header */
1895 };
1896
1897 /**
1898 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
1899 */
1900 struct dmub_dcn_notify_idle_cntl_data {
1901 uint8_t driver_idle;
1902 uint8_t skip_otg_disable;
1903 uint8_t reserved[58];
1904 };
1905
1906 /**
1907 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
1908 */
1909 struct dmub_rb_cmd_idle_opt_dcn_notify_idle {
1910 struct dmub_cmd_header header; /**< header */
1911 struct dmub_dcn_notify_idle_cntl_data cntl_data;
1912 };
1913
1914 /**
1915 * enum dmub_idle_opt_dc_power_state - DC power states.
1916 */
1917 enum dmub_idle_opt_dc_power_state {
1918 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0,
1919 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1,
1920 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2,
1921 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4,
1922 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8,
1923 };
1924
1925 /**
1926 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.
1927 */
1928 struct dmub_idle_opt_set_dc_power_state_data {
1929 uint8_t power_state; /**< power state */
1930 uint8_t pad[3]; /**< padding */
1931 };
1932
1933 /**
1934 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.
1935 */
1936 struct dmub_rb_cmd_idle_opt_set_dc_power_state {
1937 struct dmub_cmd_header header; /**< header */
1938 struct dmub_idle_opt_set_dc_power_state_data data;
1939 };
1940
1941 /**
1942 * struct dmub_clocks - Clock update notification.
1943 */
1944 struct dmub_clocks {
1945 uint32_t dispclk_khz; /**< dispclk kHz */
1946 uint32_t dppclk_khz; /**< dppclk kHz */
1947 uint32_t dcfclk_khz; /**< dcfclk kHz */
1948 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
1949 };
1950
1951 /**
1952 * enum dmub_cmd_clk_mgr_type - Clock manager commands.
1953 */
1954 enum dmub_cmd_clk_mgr_type {
1955 /**
1956 * Notify DMCUB of clock update.
1957 */
1958 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
1959 };
1960
1961 /**
1962 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
1963 */
1964 struct dmub_rb_cmd_clk_mgr_notify_clocks {
1965 struct dmub_cmd_header header; /**< header */
1966 struct dmub_clocks clocks; /**< clock data */
1967 };
1968
1969 /**
1970 * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
1971 */
1972 struct dmub_cmd_digx_encoder_control_data {
1973 union dig_encoder_control_parameters_v1_5 dig; /**< payload */
1974 };
1975
1976 /**
1977 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
1978 */
1979 struct dmub_rb_cmd_digx_encoder_control {
1980 struct dmub_cmd_header header; /**< header */
1981 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
1982 };
1983
1984 /**
1985 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
1986 */
1987 struct dmub_cmd_set_pixel_clock_data {
1988 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
1989 };
1990
1991 /**
1992 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
1993 */
1994 struct dmub_rb_cmd_set_pixel_clock {
1995 struct dmub_cmd_header header; /**< header */
1996 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
1997 };
1998
1999 /**
2000 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
2001 */
2002 struct dmub_cmd_enable_disp_power_gating_data {
2003 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
2004 };
2005
2006 /**
2007 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
2008 */
2009 struct dmub_rb_cmd_enable_disp_power_gating {
2010 struct dmub_cmd_header header; /**< header */
2011 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */
2012 };
2013
2014 /**
2015 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
2016 */
2017 struct dmub_dig_transmitter_control_data_v1_7 {
2018 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
2019 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
2020 union {
2021 uint8_t digmode; /**< enum atom_encode_mode_def */
2022 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
2023 } mode_laneset;
2024 uint8_t lanenum; /**< Number of lanes */
2025 union {
2026 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
2027 } symclk_units;
2028 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
2029 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
2030 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
2031 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */
2032 uint8_t reserved1; /**< For future use */
2033 uint8_t reserved2[3]; /**< For future use */
2034 uint32_t reserved3[11]; /**< For future use */
2035 };
2036
2037 /**
2038 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
2039 */
2040 union dmub_cmd_dig1_transmitter_control_data {
2041 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
2042 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */
2043 };
2044
2045 /**
2046 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
2047 */
2048 struct dmub_rb_cmd_dig1_transmitter_control {
2049 struct dmub_cmd_header header; /**< header */
2050 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
2051 };
2052
2053 /**
2054 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control
2055 */
2056 struct dmub_rb_cmd_domain_control_data {
2057 uint8_t inst : 6; /**< DOMAIN instance to control */
2058 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */
2059 uint8_t reserved[3]; /**< Reserved for future use */
2060 };
2061
2062 /**
2063 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating
2064 */
2065 struct dmub_rb_cmd_domain_control {
2066 struct dmub_cmd_header header; /**< header */
2067 struct dmub_rb_cmd_domain_control_data data; /**< payload */
2068 };
2069
2070 /**
2071 * DPIA tunnel command parameters.
2072 */
2073 struct dmub_cmd_dig_dpia_control_data {
2074 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */
2075 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */
2076 union {
2077 uint8_t digmode; /** enum atom_encode_mode_def */
2078 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */
2079 } mode_laneset;
2080 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */
2081 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */
2082 uint8_t hpdsel; /** =0: HPD is not assigned */
2083 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */
2084 uint8_t dpia_id; /** Index of DPIA */
2085 uint8_t fec_rdy : 1;
2086 uint8_t reserved : 7;
2087 uint32_t reserved1;
2088 };
2089
2090 /**
2091 * DMUB command for DPIA tunnel control.
2092 */
2093 struct dmub_rb_cmd_dig1_dpia_control {
2094 struct dmub_cmd_header header;
2095 struct dmub_cmd_dig_dpia_control_data dpia_control;
2096 };
2097
2098 /**
2099 * SET_CONFIG Command Payload
2100 */
2101 struct set_config_cmd_payload {
2102 uint8_t msg_type; /* set config message type */
2103 uint8_t msg_data; /* set config message data */
2104 };
2105
2106 /**
2107 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
2108 */
2109 struct dmub_cmd_set_config_control_data {
2110 struct set_config_cmd_payload cmd_pkt;
2111 uint8_t instance; /* DPIA instance */
2112 uint8_t immed_status; /* Immediate status returned in case of error */
2113 };
2114
2115 /**
2116 * DMUB command structure for SET_CONFIG command.
2117 */
2118 struct dmub_rb_cmd_set_config_access {
2119 struct dmub_cmd_header header; /* header */
2120 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */
2121 };
2122
2123 /**
2124 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
2125 */
2126 struct dmub_cmd_mst_alloc_slots_control_data {
2127 uint8_t mst_alloc_slots; /* mst slots to be allotted */
2128 uint8_t instance; /* DPIA instance */
2129 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */
2130 uint8_t mst_slots_in_use; /* returns slots in use for error cases */
2131 };
2132
2133 /**
2134 * DMUB command structure for SET_ command.
2135 */
2136 struct dmub_rb_cmd_set_mst_alloc_slots {
2137 struct dmub_cmd_header header; /* header */
2138 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */
2139 };
2140
2141 /**
2142 * DMUB command structure for DPIA HPD int enable control.
2143 */
2144 struct dmub_rb_cmd_dpia_hpd_int_enable {
2145 struct dmub_cmd_header header; /* header */
2146 uint32_t enable; /* dpia hpd interrupt enable */
2147 };
2148
2149 /**
2150 * struct dmub_rb_cmd_dpphy_init - DPPHY init.
2151 */
2152 struct dmub_rb_cmd_dpphy_init {
2153 struct dmub_cmd_header header; /**< header */
2154 uint8_t reserved[60]; /**< reserved bits */
2155 };
2156
2157 /**
2158 * enum dp_aux_request_action - DP AUX request command listing.
2159 *
2160 * 4 AUX request command bits are shifted to high nibble.
2161 */
2162 enum dp_aux_request_action {
2163 /** I2C-over-AUX write request */
2164 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,
2165 /** I2C-over-AUX read request */
2166 DP_AUX_REQ_ACTION_I2C_READ = 0x10,
2167 /** I2C-over-AUX write status request */
2168 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20,
2169 /** I2C-over-AUX write request with MOT=1 */
2170 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,
2171 /** I2C-over-AUX read request with MOT=1 */
2172 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,
2173 /** I2C-over-AUX write status request with MOT=1 */
2174 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60,
2175 /** Native AUX write request */
2176 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80,
2177 /** Native AUX read request */
2178 DP_AUX_REQ_ACTION_DPCD_READ = 0x90
2179 };
2180
2181 /**
2182 * enum aux_return_code_type - DP AUX process return code listing.
2183 */
2184 enum aux_return_code_type {
2185 /** AUX process succeeded */
2186 AUX_RET_SUCCESS = 0,
2187 /** AUX process failed with unknown reason */
2188 AUX_RET_ERROR_UNKNOWN,
2189 /** AUX process completed with invalid reply */
2190 AUX_RET_ERROR_INVALID_REPLY,
2191 /** AUX process timed out */
2192 AUX_RET_ERROR_TIMEOUT,
2193 /** HPD was low during AUX process */
2194 AUX_RET_ERROR_HPD_DISCON,
2195 /** Failed to acquire AUX engine */
2196 AUX_RET_ERROR_ENGINE_ACQUIRE,
2197 /** AUX request not supported */
2198 AUX_RET_ERROR_INVALID_OPERATION,
2199 /** AUX process not available */
2200 AUX_RET_ERROR_PROTOCOL_ERROR,
2201 };
2202
2203 /**
2204 * enum aux_channel_type - DP AUX channel type listing.
2205 */
2206 enum aux_channel_type {
2207 /** AUX thru Legacy DP AUX */
2208 AUX_CHANNEL_LEGACY_DDC,
2209 /** AUX thru DPIA DP tunneling */
2210 AUX_CHANNEL_DPIA
2211 };
2212
2213 /**
2214 * struct aux_transaction_parameters - DP AUX request transaction data
2215 */
2216 struct aux_transaction_parameters {
2217 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
2218 uint8_t action; /**< enum dp_aux_request_action */
2219 uint8_t length; /**< DP AUX request data length */
2220 uint8_t reserved; /**< For future use */
2221 uint32_t address; /**< DP AUX address */
2222 uint8_t data[16]; /**< DP AUX write data */
2223 };
2224
2225 /**
2226 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
2227 */
2228 struct dmub_cmd_dp_aux_control_data {
2229 uint8_t instance; /**< AUX instance or DPIA instance */
2230 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
2231 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
2232 uint8_t reserved0; /**< For future use */
2233 uint16_t timeout; /**< timeout time in us */
2234 uint16_t reserved1; /**< For future use */
2235 enum aux_channel_type type; /**< enum aux_channel_type */
2236 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
2237 };
2238
2239 /**
2240 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
2241 */
2242 struct dmub_rb_cmd_dp_aux_access {
2243 /**
2244 * Command header.
2245 */
2246 struct dmub_cmd_header header;
2247 /**
2248 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
2249 */
2250 struct dmub_cmd_dp_aux_control_data aux_control;
2251 };
2252
2253 /**
2254 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
2255 */
2256 struct dmub_rb_cmd_outbox1_enable {
2257 /**
2258 * Command header.
2259 */
2260 struct dmub_cmd_header header;
2261 /**
2262 * enable: 0x0 -> disable outbox1 notification (default value)
2263 * 0x1 -> enable outbox1 notification
2264 */
2265 uint32_t enable;
2266 };
2267
2268 /* DP AUX Reply command - OutBox Cmd */
2269 /**
2270 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
2271 */
2272 struct aux_reply_data {
2273 /**
2274 * Aux cmd
2275 */
2276 uint8_t command;
2277 /**
2278 * Aux reply data length (max: 16 bytes)
2279 */
2280 uint8_t length;
2281 /**
2282 * Alignment only
2283 */
2284 uint8_t pad[2];
2285 /**
2286 * Aux reply data
2287 */
2288 uint8_t data[16];
2289 };
2290
2291 /**
2292 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
2293 */
2294 struct aux_reply_control_data {
2295 /**
2296 * Reserved for future use
2297 */
2298 uint32_t handle;
2299 /**
2300 * Aux Instance
2301 */
2302 uint8_t instance;
2303 /**
2304 * Aux transaction result: definition in enum aux_return_code_type
2305 */
2306 uint8_t result;
2307 /**
2308 * Alignment only
2309 */
2310 uint16_t pad;
2311 };
2312
2313 /**
2314 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
2315 */
2316 struct dmub_rb_cmd_dp_aux_reply {
2317 /**
2318 * Command header.
2319 */
2320 struct dmub_cmd_header header;
2321 /**
2322 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
2323 */
2324 struct aux_reply_control_data control;
2325 /**
2326 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
2327 */
2328 struct aux_reply_data reply_data;
2329 };
2330
2331 /* DP HPD Notify command - OutBox Cmd */
2332 /**
2333 * DP HPD Type
2334 */
2335 enum dp_hpd_type {
2336 /**
2337 * Normal DP HPD
2338 */
2339 DP_HPD = 0,
2340 /**
2341 * DP HPD short pulse
2342 */
2343 DP_IRQ
2344 };
2345
2346 /**
2347 * DP HPD Status
2348 */
2349 enum dp_hpd_status {
2350 /**
2351 * DP_HPD status low
2352 */
2353 DP_HPD_UNPLUG = 0,
2354 /**
2355 * DP_HPD status high
2356 */
2357 DP_HPD_PLUG
2358 };
2359
2360 /**
2361 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
2362 */
2363 struct dp_hpd_data {
2364 /**
2365 * DP HPD instance
2366 */
2367 uint8_t instance;
2368 /**
2369 * HPD type
2370 */
2371 uint8_t hpd_type;
2372 /**
2373 * HPD status: only for type: DP_HPD to indicate status
2374 */
2375 uint8_t hpd_status;
2376 /**
2377 * Alignment only
2378 */
2379 uint8_t pad;
2380 };
2381
2382 /**
2383 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
2384 */
2385 struct dmub_rb_cmd_dp_hpd_notify {
2386 /**
2387 * Command header.
2388 */
2389 struct dmub_cmd_header header;
2390 /**
2391 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
2392 */
2393 struct dp_hpd_data hpd_data;
2394 };
2395
2396 /**
2397 * Definition of a SET_CONFIG reply from DPOA.
2398 */
2399 enum set_config_status {
2400 SET_CONFIG_PENDING = 0,
2401 SET_CONFIG_ACK_RECEIVED,
2402 SET_CONFIG_RX_TIMEOUT,
2403 SET_CONFIG_UNKNOWN_ERROR,
2404 };
2405
2406 /**
2407 * Definition of a set_config reply
2408 */
2409 struct set_config_reply_control_data {
2410 uint8_t instance; /* DPIA Instance */
2411 uint8_t status; /* Set Config reply */
2412 uint16_t pad; /* Alignment */
2413 };
2414
2415 /**
2416 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command.
2417 */
2418 struct dmub_rb_cmd_dp_set_config_reply {
2419 struct dmub_cmd_header header;
2420 struct set_config_reply_control_data set_config_reply_control;
2421 };
2422
2423 /**
2424 * Definition of a DPIA notification header
2425 */
2426 struct dpia_notification_header {
2427 uint8_t instance; /**< DPIA Instance */
2428 uint8_t reserved[3];
2429 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */
2430 };
2431
2432 /**
2433 * Definition of the common data struct of DPIA notification
2434 */
2435 struct dpia_notification_common {
2436 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)
2437 - sizeof(struct dpia_notification_header)];
2438 };
2439
2440 /**
2441 * Definition of a DPIA notification data
2442 */
2443 struct dpia_bw_allocation_notify_data {
2444 union {
2445 struct {
2446 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */
2447 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */
2448 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */
2449 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */
2450 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */
2451 uint16_t reserved: 11; /**< Reserved */
2452 } bits;
2453
2454 uint16_t flags;
2455 };
2456
2457 uint8_t cm_id; /**< CM ID */
2458 uint8_t group_id; /**< Group ID */
2459 uint8_t granularity; /**< BW Allocation Granularity */
2460 uint8_t estimated_bw; /**< Estimated_BW */
2461 uint8_t allocated_bw; /**< Allocated_BW */
2462 uint8_t reserved;
2463 };
2464
2465 /**
2466 * union dpia_notify_data_type - DPIA Notification in Outbox command
2467 */
2468 union dpia_notification_data {
2469 /**
2470 * DPIA Notification for common data struct
2471 */
2472 struct dpia_notification_common common_data;
2473
2474 /**
2475 * DPIA Notification for DP BW Allocation support
2476 */
2477 struct dpia_bw_allocation_notify_data dpia_bw_alloc;
2478 };
2479
2480 /**
2481 * Definition of a DPIA notification payload
2482 */
2483 struct dpia_notification_payload {
2484 struct dpia_notification_header header;
2485 union dpia_notification_data data; /**< DPIA notification payload data */
2486 };
2487
2488 /**
2489 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command.
2490 */
2491 struct dmub_rb_cmd_dpia_notification {
2492 struct dmub_cmd_header header; /**< DPIA notification header */
2493 struct dpia_notification_payload payload; /**< DPIA notification payload */
2494 };
2495
2496 /**
2497 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
2498 */
2499 struct dmub_cmd_hpd_state_query_data {
2500 uint8_t instance; /**< HPD instance or DPIA instance */
2501 uint8_t result; /**< For returning HPD state */
2502 uint16_t pad; /** < Alignment */
2503 enum aux_channel_type ch_type; /**< enum aux_channel_type */
2504 enum aux_return_code_type status; /**< for returning the status of command */
2505 };
2506
2507 /**
2508 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
2509 */
2510 struct dmub_rb_cmd_query_hpd_state {
2511 /**
2512 * Command header.
2513 */
2514 struct dmub_cmd_header header;
2515 /**
2516 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
2517 */
2518 struct dmub_cmd_hpd_state_query_data data;
2519 };
2520
2521 /**
2522 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data.
2523 */
2524 struct dmub_rb_cmd_hpd_sense_notify_data {
2525 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */
2526 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */
2527 };
2528
2529 /**
2530 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command.
2531 */
2532 struct dmub_rb_cmd_hpd_sense_notify {
2533 struct dmub_cmd_header header; /**< header */
2534 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */
2535 };
2536
2537 /*
2538 * Command IDs should be treated as stable ABI.
2539 * Do not reuse or modify IDs.
2540 */
2541
2542 /**
2543 * PSR command sub-types.
2544 */
2545 enum dmub_cmd_psr_type {
2546 /**
2547 * Set PSR version support.
2548 */
2549 DMUB_CMD__PSR_SET_VERSION = 0,
2550 /**
2551 * Copy driver-calculated parameters to PSR state.
2552 */
2553 DMUB_CMD__PSR_COPY_SETTINGS = 1,
2554 /**
2555 * Enable PSR.
2556 */
2557 DMUB_CMD__PSR_ENABLE = 2,
2558
2559 /**
2560 * Disable PSR.
2561 */
2562 DMUB_CMD__PSR_DISABLE = 3,
2563
2564 /**
2565 * Set PSR level.
2566 * PSR level is a 16-bit value dicated by driver that
2567 * will enable/disable different functionality.
2568 */
2569 DMUB_CMD__PSR_SET_LEVEL = 4,
2570
2571 /**
2572 * Forces PSR enabled until an explicit PSR disable call.
2573 */
2574 DMUB_CMD__PSR_FORCE_STATIC = 5,
2575 /**
2576 * Set vtotal in psr active for FreeSync PSR.
2577 */
2578 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6,
2579 /**
2580 * Set PSR power option
2581 */
2582 DMUB_CMD__SET_PSR_POWER_OPT = 7,
2583 };
2584
2585 /**
2586 * Different PSR residency modes.
2587 * Different modes change the definition of PSR residency.
2588 */
2589 enum psr_residency_mode {
2590 PSR_RESIDENCY_MODE_PHY = 0,
2591 PSR_RESIDENCY_MODE_ALPM,
2592 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD,
2593 /* Do not add below. */
2594 PSR_RESIDENCY_MODE_LAST_ELEMENT,
2595 };
2596
2597 enum dmub_cmd_fams_type {
2598 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0,
2599 DMUB_CMD__FAMS_DRR_UPDATE = 1,
2600 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd
2601 /**
2602 * For SubVP set manual trigger in FW because it
2603 * triggers DRR_UPDATE_PENDING which SubVP relies
2604 * on (for any SubVP cases that use a DRR display)
2605 */
2606 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3,
2607 DMUB_CMD__FAMS2_CONFIG = 4,
2608 DMUB_CMD__FAMS2_DRR_UPDATE = 5,
2609 DMUB_CMD__FAMS2_FLIP = 6,
2610 };
2611
2612 /**
2613 * PSR versions.
2614 */
2615 enum psr_version {
2616 /**
2617 * PSR version 1.
2618 */
2619 PSR_VERSION_1 = 0,
2620 /**
2621 * Freesync PSR SU.
2622 */
2623 PSR_VERSION_SU_1 = 1,
2624 /**
2625 * PSR not supported.
2626 */
2627 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide
2628 };
2629
2630 /**
2631 * PHY Link rate for DP.
2632 */
2633 enum phy_link_rate {
2634 /**
2635 * not supported.
2636 */
2637 PHY_RATE_UNKNOWN = 0,
2638 /**
2639 * Rate_1 (RBR) - 1.62 Gbps/Lane
2640 */
2641 PHY_RATE_162 = 1,
2642 /**
2643 * Rate_2 - 2.16 Gbps/Lane
2644 */
2645 PHY_RATE_216 = 2,
2646 /**
2647 * Rate_3 - 2.43 Gbps/Lane
2648 */
2649 PHY_RATE_243 = 3,
2650 /**
2651 * Rate_4 (HBR) - 2.70 Gbps/Lane
2652 */
2653 PHY_RATE_270 = 4,
2654 /**
2655 * Rate_5 (RBR2)- 3.24 Gbps/Lane
2656 */
2657 PHY_RATE_324 = 5,
2658 /**
2659 * Rate_6 - 4.32 Gbps/Lane
2660 */
2661 PHY_RATE_432 = 6,
2662 /**
2663 * Rate_7 (HBR2)- 5.40 Gbps/Lane
2664 */
2665 PHY_RATE_540 = 7,
2666 /**
2667 * Rate_8 (HBR3)- 8.10 Gbps/Lane
2668 */
2669 PHY_RATE_810 = 8,
2670 /**
2671 * UHBR10 - 10.0 Gbps/Lane
2672 */
2673 PHY_RATE_1000 = 9,
2674 /**
2675 * UHBR13.5 - 13.5 Gbps/Lane
2676 */
2677 PHY_RATE_1350 = 10,
2678 /**
2679 * UHBR10 - 20.0 Gbps/Lane
2680 */
2681 PHY_RATE_2000 = 11,
2682
2683 PHY_RATE_675 = 12,
2684 /**
2685 * Rate 12 - 6.75 Gbps/Lane
2686 */
2687 };
2688
2689 /**
2690 * enum dmub_phy_fsm_state - PHY FSM states.
2691 * PHY FSM state to transit to during PSR enable/disable.
2692 */
2693 enum dmub_phy_fsm_state {
2694 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0,
2695 DMUB_PHY_FSM_RESET,
2696 DMUB_PHY_FSM_RESET_RELEASED,
2697 DMUB_PHY_FSM_SRAM_LOAD_DONE,
2698 DMUB_PHY_FSM_INITIALIZED,
2699 DMUB_PHY_FSM_CALIBRATED,
2700 DMUB_PHY_FSM_CALIBRATED_LP,
2701 DMUB_PHY_FSM_CALIBRATED_PG,
2702 DMUB_PHY_FSM_POWER_DOWN,
2703 DMUB_PHY_FSM_PLL_EN,
2704 DMUB_PHY_FSM_TX_EN,
2705 DMUB_PHY_FSM_TX_EN_TEST_MODE,
2706 DMUB_PHY_FSM_FAST_LP,
2707 DMUB_PHY_FSM_P2_PLL_OFF_CPM,
2708 DMUB_PHY_FSM_P2_PLL_OFF_PG,
2709 DMUB_PHY_FSM_P2_PLL_OFF,
2710 DMUB_PHY_FSM_P2_PLL_ON,
2711 };
2712
2713 /**
2714 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
2715 */
2716 struct dmub_cmd_psr_copy_settings_data {
2717 /**
2718 * Flags that can be set by driver to change some PSR behaviour.
2719 */
2720 union dmub_psr_debug_flags debug;
2721 /**
2722 * 16-bit value dicated by driver that will enable/disable different functionality.
2723 */
2724 uint16_t psr_level;
2725 /**
2726 * DPP HW instance.
2727 */
2728 uint8_t dpp_inst;
2729 /**
2730 * MPCC HW instance.
2731 * Not used in dmub fw,
2732 * dmub fw will get active opp by reading odm registers.
2733 */
2734 uint8_t mpcc_inst;
2735 /**
2736 * OPP HW instance.
2737 * Not used in dmub fw,
2738 * dmub fw will get active opp by reading odm registers.
2739 */
2740 uint8_t opp_inst;
2741 /**
2742 * OTG HW instance.
2743 */
2744 uint8_t otg_inst;
2745 /**
2746 * DIG FE HW instance.
2747 */
2748 uint8_t digfe_inst;
2749 /**
2750 * DIG BE HW instance.
2751 */
2752 uint8_t digbe_inst;
2753 /**
2754 * DP PHY HW instance.
2755 */
2756 uint8_t dpphy_inst;
2757 /**
2758 * AUX HW instance.
2759 */
2760 uint8_t aux_inst;
2761 /**
2762 * Determines if SMU optimzations are enabled/disabled.
2763 */
2764 uint8_t smu_optimizations_en;
2765 /**
2766 * Unused.
2767 * TODO: Remove.
2768 */
2769 uint8_t frame_delay;
2770 /**
2771 * If RFB setup time is greater than the total VBLANK time,
2772 * it is not possible for the sink to capture the video frame
2773 * in the same frame the SDP is sent. In this case,
2774 * the frame capture indication bit should be set and an extra
2775 * static frame should be transmitted to the sink.
2776 */
2777 uint8_t frame_cap_ind;
2778 /**
2779 * Granularity of Y offset supported by sink.
2780 */
2781 uint8_t su_y_granularity;
2782 /**
2783 * Indicates whether sink should start capturing
2784 * immediately following active scan line,
2785 * or starting with the 2nd active scan line.
2786 */
2787 uint8_t line_capture_indication;
2788 /**
2789 * Multi-display optimizations are implemented on certain ASICs.
2790 */
2791 uint8_t multi_disp_optimizations_en;
2792 /**
2793 * The last possible line SDP may be transmitted without violating
2794 * the RFB setup time or entering the active video frame.
2795 */
2796 uint16_t init_sdp_deadline;
2797 /**
2798 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities
2799 */
2800 uint8_t rate_control_caps ;
2801 /*
2802 * Force PSRSU always doing full frame update
2803 */
2804 uint8_t force_ffu_mode;
2805 /**
2806 * Length of each horizontal line in us.
2807 */
2808 uint32_t line_time_in_us;
2809 /**
2810 * FEC enable status in driver
2811 */
2812 uint8_t fec_enable_status;
2813 /**
2814 * FEC re-enable delay when PSR exit.
2815 * unit is 100us, range form 0~255(0xFF).
2816 */
2817 uint8_t fec_enable_delay_in100us;
2818 /**
2819 * PSR control version.
2820 */
2821 uint8_t cmd_version;
2822 /**
2823 * Panel Instance.
2824 * Panel instance to identify which psr_state to use
2825 * Currently the support is only for 0 or 1
2826 */
2827 uint8_t panel_inst;
2828 /*
2829 * DSC enable status in driver
2830 */
2831 uint8_t dsc_enable_status;
2832 /*
2833 * Use FSM state for PSR power up/down
2834 */
2835 uint8_t use_phy_fsm;
2836 /**
2837 * frame delay for frame re-lock
2838 */
2839 uint8_t relock_delay_frame_cnt;
2840 /**
2841 * esd recovery indicate.
2842 */
2843 uint8_t esd_recovery;
2844 /**
2845 * DSC Slice height.
2846 */
2847 uint16_t dsc_slice_height;
2848 /**
2849 * Some panels request main link off before xth vertical line
2850 */
2851 uint16_t poweroff_before_vertical_line;
2852 };
2853
2854 /**
2855 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
2856 */
2857 struct dmub_rb_cmd_psr_copy_settings {
2858 /**
2859 * Command header.
2860 */
2861 struct dmub_cmd_header header;
2862 /**
2863 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
2864 */
2865 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
2866 };
2867
2868 /**
2869 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
2870 */
2871 struct dmub_cmd_psr_set_level_data {
2872 /**
2873 * 16-bit value dicated by driver that will enable/disable different functionality.
2874 */
2875 uint16_t psr_level;
2876 /**
2877 * PSR control version.
2878 */
2879 uint8_t cmd_version;
2880 /**
2881 * Panel Instance.
2882 * Panel instance to identify which psr_state to use
2883 * Currently the support is only for 0 or 1
2884 */
2885 uint8_t panel_inst;
2886 };
2887
2888 /**
2889 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
2890 */
2891 struct dmub_rb_cmd_psr_set_level {
2892 /**
2893 * Command header.
2894 */
2895 struct dmub_cmd_header header;
2896 /**
2897 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
2898 */
2899 struct dmub_cmd_psr_set_level_data psr_set_level_data;
2900 };
2901
2902 struct dmub_rb_cmd_psr_enable_data {
2903 /**
2904 * PSR control version.
2905 */
2906 uint8_t cmd_version;
2907 /**
2908 * Panel Instance.
2909 * Panel instance to identify which psr_state to use
2910 * Currently the support is only for 0 or 1
2911 */
2912 uint8_t panel_inst;
2913 /**
2914 * Phy state to enter.
2915 * Values to use are defined in dmub_phy_fsm_state
2916 */
2917 uint8_t phy_fsm_state;
2918 /**
2919 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
2920 * Set this using enum phy_link_rate.
2921 * This does not support HDMI/DP2 for now.
2922 */
2923 uint8_t phy_rate;
2924 };
2925
2926 /**
2927 * Definition of a DMUB_CMD__PSR_ENABLE command.
2928 * PSR enable/disable is controlled using the sub_type.
2929 */
2930 struct dmub_rb_cmd_psr_enable {
2931 /**
2932 * Command header.
2933 */
2934 struct dmub_cmd_header header;
2935
2936 struct dmub_rb_cmd_psr_enable_data data;
2937 };
2938
2939 /**
2940 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
2941 */
2942 struct dmub_cmd_psr_set_version_data {
2943 /**
2944 * PSR version that FW should implement.
2945 */
2946 enum psr_version version;
2947 /**
2948 * PSR control version.
2949 */
2950 uint8_t cmd_version;
2951 /**
2952 * Panel Instance.
2953 * Panel instance to identify which psr_state to use
2954 * Currently the support is only for 0 or 1
2955 */
2956 uint8_t panel_inst;
2957 /**
2958 * Explicit padding to 4 byte boundary.
2959 */
2960 uint8_t pad[2];
2961 };
2962
2963 /**
2964 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
2965 */
2966 struct dmub_rb_cmd_psr_set_version {
2967 /**
2968 * Command header.
2969 */
2970 struct dmub_cmd_header header;
2971 /**
2972 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
2973 */
2974 struct dmub_cmd_psr_set_version_data psr_set_version_data;
2975 };
2976
2977 struct dmub_cmd_psr_force_static_data {
2978 /**
2979 * PSR control version.
2980 */
2981 uint8_t cmd_version;
2982 /**
2983 * Panel Instance.
2984 * Panel instance to identify which psr_state to use
2985 * Currently the support is only for 0 or 1
2986 */
2987 uint8_t panel_inst;
2988 /**
2989 * Explicit padding to 4 byte boundary.
2990 */
2991 uint8_t pad[2];
2992 };
2993
2994 /**
2995 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
2996 */
2997 struct dmub_rb_cmd_psr_force_static {
2998 /**
2999 * Command header.
3000 */
3001 struct dmub_cmd_header header;
3002 /**
3003 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
3004 */
3005 struct dmub_cmd_psr_force_static_data psr_force_static_data;
3006 };
3007
3008 /**
3009 * PSR SU debug flags.
3010 */
3011 union dmub_psr_su_debug_flags {
3012 /**
3013 * PSR SU debug flags.
3014 */
3015 struct {
3016 /**
3017 * Update dirty rect in SW only.
3018 */
3019 uint8_t update_dirty_rect_only : 1;
3020 /**
3021 * Reset the cursor/plane state before processing the call.
3022 */
3023 uint8_t reset_state : 1;
3024 } bitfields;
3025
3026 /**
3027 * Union for debug flags.
3028 */
3029 uint32_t u32All;
3030 };
3031
3032 /**
3033 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
3034 * This triggers a selective update for PSR SU.
3035 */
3036 struct dmub_cmd_update_dirty_rect_data {
3037 /**
3038 * Dirty rects from OS.
3039 */
3040 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS];
3041 /**
3042 * PSR SU debug flags.
3043 */
3044 union dmub_psr_su_debug_flags debug_flags;
3045 /**
3046 * OTG HW instance.
3047 */
3048 uint8_t pipe_idx;
3049 /**
3050 * Number of dirty rects.
3051 */
3052 uint8_t dirty_rect_count;
3053 /**
3054 * PSR control version.
3055 */
3056 uint8_t cmd_version;
3057 /**
3058 * Panel Instance.
3059 * Panel instance to identify which psr_state to use
3060 * Currently the support is only for 0 or 1
3061 */
3062 uint8_t panel_inst;
3063 };
3064
3065 /**
3066 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
3067 */
3068 struct dmub_rb_cmd_update_dirty_rect {
3069 /**
3070 * Command header.
3071 */
3072 struct dmub_cmd_header header;
3073 /**
3074 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
3075 */
3076 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data;
3077 };
3078
3079 /**
3080 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
3081 */
3082 union dmub_reg_cursor_control_cfg {
3083 struct {
3084 uint32_t cur_enable: 1;
3085 uint32_t reser0: 3;
3086 uint32_t cur_2x_magnify: 1;
3087 uint32_t reser1: 3;
3088 uint32_t mode: 3;
3089 uint32_t reser2: 5;
3090 uint32_t pitch: 2;
3091 uint32_t reser3: 6;
3092 uint32_t line_per_chunk: 5;
3093 uint32_t reser4: 3;
3094 } bits;
3095 uint32_t raw;
3096 };
3097 struct dmub_cursor_position_cache_hubp {
3098 union dmub_reg_cursor_control_cfg cur_ctl;
3099 union dmub_reg_position_cfg {
3100 struct {
3101 uint32_t cur_x_pos: 16;
3102 uint32_t cur_y_pos: 16;
3103 } bits;
3104 uint32_t raw;
3105 } position;
3106 union dmub_reg_hot_spot_cfg {
3107 struct {
3108 uint32_t hot_x: 16;
3109 uint32_t hot_y: 16;
3110 } bits;
3111 uint32_t raw;
3112 } hot_spot;
3113 union dmub_reg_dst_offset_cfg {
3114 struct {
3115 uint32_t dst_x_offset: 13;
3116 uint32_t reserved: 19;
3117 } bits;
3118 uint32_t raw;
3119 } dst_offset;
3120 };
3121
3122 union dmub_reg_cur0_control_cfg {
3123 struct {
3124 uint32_t cur0_enable: 1;
3125 uint32_t expansion_mode: 1;
3126 uint32_t reser0: 1;
3127 uint32_t cur0_rom_en: 1;
3128 uint32_t mode: 3;
3129 uint32_t reserved: 25;
3130 } bits;
3131 uint32_t raw;
3132 };
3133 struct dmub_cursor_position_cache_dpp {
3134 union dmub_reg_cur0_control_cfg cur0_ctl;
3135 };
3136 struct dmub_cursor_position_cfg {
3137 struct dmub_cursor_position_cache_hubp pHubp;
3138 struct dmub_cursor_position_cache_dpp pDpp;
3139 uint8_t pipe_idx;
3140 /*
3141 * Padding is required. To be 4 Bytes Aligned.
3142 */
3143 uint8_t padding[3];
3144 };
3145
3146 struct dmub_cursor_attribute_cache_hubp {
3147 uint32_t SURFACE_ADDR_HIGH;
3148 uint32_t SURFACE_ADDR;
3149 union dmub_reg_cursor_control_cfg cur_ctl;
3150 union dmub_reg_cursor_size_cfg {
3151 struct {
3152 uint32_t width: 16;
3153 uint32_t height: 16;
3154 } bits;
3155 uint32_t raw;
3156 } size;
3157 union dmub_reg_cursor_settings_cfg {
3158 struct {
3159 uint32_t dst_y_offset: 8;
3160 uint32_t chunk_hdl_adjust: 2;
3161 uint32_t reserved: 22;
3162 } bits;
3163 uint32_t raw;
3164 } settings;
3165 };
3166 struct dmub_cursor_attribute_cache_dpp {
3167 union dmub_reg_cur0_control_cfg cur0_ctl;
3168 };
3169 struct dmub_cursor_attributes_cfg {
3170 struct dmub_cursor_attribute_cache_hubp aHubp;
3171 struct dmub_cursor_attribute_cache_dpp aDpp;
3172 };
3173
3174 struct dmub_cmd_update_cursor_payload0 {
3175 /**
3176 * Cursor dirty rects.
3177 */
3178 struct dmub_rect cursor_rect;
3179 /**
3180 * PSR SU debug flags.
3181 */
3182 union dmub_psr_su_debug_flags debug_flags;
3183 /**
3184 * Cursor enable/disable.
3185 */
3186 uint8_t enable;
3187 /**
3188 * OTG HW instance.
3189 */
3190 uint8_t pipe_idx;
3191 /**
3192 * PSR control version.
3193 */
3194 uint8_t cmd_version;
3195 /**
3196 * Panel Instance.
3197 * Panel instance to identify which psr_state to use
3198 * Currently the support is only for 0 or 1
3199 */
3200 uint8_t panel_inst;
3201 /**
3202 * Cursor Position Register.
3203 * Registers contains Hubp & Dpp modules
3204 */
3205 struct dmub_cursor_position_cfg position_cfg;
3206 };
3207
3208 struct dmub_cmd_update_cursor_payload1 {
3209 struct dmub_cursor_attributes_cfg attribute_cfg;
3210 };
3211
3212 union dmub_cmd_update_cursor_info_data {
3213 struct dmub_cmd_update_cursor_payload0 payload0;
3214 struct dmub_cmd_update_cursor_payload1 payload1;
3215 };
3216 /**
3217 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
3218 */
3219 struct dmub_rb_cmd_update_cursor_info {
3220 /**
3221 * Command header.
3222 */
3223 struct dmub_cmd_header header;
3224 /**
3225 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
3226 */
3227 union dmub_cmd_update_cursor_info_data update_cursor_info_data;
3228 };
3229
3230 /**
3231 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
3232 */
3233 struct dmub_cmd_psr_set_vtotal_data {
3234 /**
3235 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle..
3236 */
3237 uint16_t psr_vtotal_idle;
3238 /**
3239 * PSR control version.
3240 */
3241 uint8_t cmd_version;
3242 /**
3243 * Panel Instance.
3244 * Panel instance to identify which psr_state to use
3245 * Currently the support is only for 0 or 1
3246 */
3247 uint8_t panel_inst;
3248 /*
3249 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU.
3250 */
3251 uint16_t psr_vtotal_su;
3252 /**
3253 * Explicit padding to 4 byte boundary.
3254 */
3255 uint8_t pad2[2];
3256 };
3257
3258 /**
3259 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
3260 */
3261 struct dmub_rb_cmd_psr_set_vtotal {
3262 /**
3263 * Command header.
3264 */
3265 struct dmub_cmd_header header;
3266 /**
3267 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
3268 */
3269 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data;
3270 };
3271
3272 /**
3273 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command.
3274 */
3275 struct dmub_cmd_psr_set_power_opt_data {
3276 /**
3277 * PSR control version.
3278 */
3279 uint8_t cmd_version;
3280 /**
3281 * Panel Instance.
3282 * Panel instance to identify which psr_state to use
3283 * Currently the support is only for 0 or 1
3284 */
3285 uint8_t panel_inst;
3286 /**
3287 * Explicit padding to 4 byte boundary.
3288 */
3289 uint8_t pad[2];
3290 /**
3291 * PSR power option
3292 */
3293 uint32_t power_opt;
3294 };
3295
3296 /**
3297 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3298 */
3299 struct dmub_rb_cmd_psr_set_power_opt {
3300 /**
3301 * Command header.
3302 */
3303 struct dmub_cmd_header header;
3304 /**
3305 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3306 */
3307 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
3308 };
3309
3310 /**
3311 * Definition of Replay Residency GPINT command.
3312 * Bit[0] - Residency mode for Revision 0
3313 * Bit[1] - Enable/Disable state
3314 * Bit[2-3] - Revision number
3315 * Bit[4-7] - Residency mode for Revision 1
3316 * Bit[8] - Panel instance
3317 * Bit[9-15] - Reserved
3318 */
3319
3320 enum pr_residency_mode {
3321 PR_RESIDENCY_MODE_PHY = 0x0,
3322 PR_RESIDENCY_MODE_ALPM,
3323 PR_RESIDENCY_MODE_IPS2,
3324 PR_RESIDENCY_MODE_FRAME_CNT,
3325 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD,
3326 };
3327
3328 #define REPLAY_RESIDENCY_MODE_SHIFT (0)
3329 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1)
3330 #define REPLAY_RESIDENCY_REVISION_SHIFT (2)
3331 #define REPLAY_RESIDENCY_MODE2_SHIFT (4)
3332
3333 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
3334 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT)
3335 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
3336
3337 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT)
3338 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT)
3339 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT)
3340 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT)
3341
3342 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
3343 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT)
3344 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
3345
3346 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT)
3347 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT)
3348 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT)
3349
3350 /**
3351 * Definition of a replay_state.
3352 */
3353 enum replay_state {
3354 REPLAY_STATE_0 = 0x0,
3355 REPLAY_STATE_1 = 0x10,
3356 REPLAY_STATE_1A = 0x11,
3357 REPLAY_STATE_2 = 0x20,
3358 REPLAY_STATE_2A = 0x21,
3359 REPLAY_STATE_3 = 0x30,
3360 REPLAY_STATE_3INIT = 0x31,
3361 REPLAY_STATE_4 = 0x40,
3362 REPLAY_STATE_4A = 0x41,
3363 REPLAY_STATE_4B = 0x42,
3364 REPLAY_STATE_4C = 0x43,
3365 REPLAY_STATE_4D = 0x44,
3366 REPLAY_STATE_4E = 0x45,
3367 REPLAY_STATE_4B_LOCKED = 0x4A,
3368 REPLAY_STATE_4C_UNLOCKED = 0x4B,
3369 REPLAY_STATE_5 = 0x50,
3370 REPLAY_STATE_5A = 0x51,
3371 REPLAY_STATE_5B = 0x52,
3372 REPLAY_STATE_5A_LOCKED = 0x5A,
3373 REPLAY_STATE_5B_UNLOCKED = 0x5B,
3374 REPLAY_STATE_6 = 0x60,
3375 REPLAY_STATE_6A = 0x61,
3376 REPLAY_STATE_6B = 0x62,
3377 REPLAY_STATE_INVALID = 0xFF,
3378 };
3379
3380 /**
3381 * Replay command sub-types.
3382 */
3383 enum dmub_cmd_replay_type {
3384 /**
3385 * Copy driver-calculated parameters to REPLAY state.
3386 */
3387 DMUB_CMD__REPLAY_COPY_SETTINGS = 0,
3388 /**
3389 * Enable REPLAY.
3390 */
3391 DMUB_CMD__REPLAY_ENABLE = 1,
3392 /**
3393 * Set Replay power option.
3394 */
3395 DMUB_CMD__SET_REPLAY_POWER_OPT = 2,
3396 /**
3397 * Set coasting vtotal.
3398 */
3399 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3,
3400 /**
3401 * Set power opt and coasting vtotal.
3402 */
3403 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4,
3404 /**
3405 * Set disabled iiming sync.
3406 */
3407 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5,
3408 /**
3409 * Set Residency Frameupdate Timer.
3410 */
3411 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6,
3412 /**
3413 * Set pseudo vtotal
3414 */
3415 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7,
3416 /**
3417 * Set adaptive sync sdp enabled
3418 */
3419 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8,
3420 /**
3421 * Set Replay General command.
3422 */
3423 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16,
3424 };
3425
3426 /**
3427 * Replay general command sub-types.
3428 */
3429 enum dmub_cmd_replay_general_subtype {
3430 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1,
3431 /**
3432 * TODO: For backward compatible, allow new command only.
3433 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED,
3434 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER,
3435 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL,
3436 */
3437 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP,
3438 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION,
3439 };
3440
3441 /**
3442 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
3443 */
3444 struct dmub_cmd_replay_copy_settings_data {
3445 /**
3446 * Flags that can be set by driver to change some replay behaviour.
3447 */
3448 union replay_debug_flags debug;
3449
3450 /**
3451 * @flags: Flags used to determine feature functionality.
3452 */
3453 union replay_hw_flags flags;
3454
3455 /**
3456 * DPP HW instance.
3457 */
3458 uint8_t dpp_inst;
3459 /**
3460 * OTG HW instance.
3461 */
3462 uint8_t otg_inst;
3463 /**
3464 * DIG FE HW instance.
3465 */
3466 uint8_t digfe_inst;
3467 /**
3468 * DIG BE HW instance.
3469 */
3470 uint8_t digbe_inst;
3471 /**
3472 * AUX HW instance.
3473 */
3474 uint8_t aux_inst;
3475 /**
3476 * Panel Instance.
3477 * Panel isntance to identify which psr_state to use
3478 * Currently the support is only for 0 or 1
3479 */
3480 uint8_t panel_inst;
3481 /**
3482 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare
3483 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode
3484 */
3485 uint8_t pixel_deviation_per_line;
3486 /**
3487 * @max_deviation_line: The max number of deviation line that can keep the timing
3488 * synchronized between the Source and Sink during Replay normal sleep mode.
3489 */
3490 uint8_t max_deviation_line;
3491 /**
3492 * Length of each horizontal line in ns.
3493 */
3494 uint32_t line_time_in_ns;
3495 /**
3496 * PHY instance.
3497 */
3498 uint8_t dpphy_inst;
3499 /**
3500 * Determines if SMU optimzations are enabled/disabled.
3501 */
3502 uint8_t smu_optimizations_en;
3503 /**
3504 * Determines if timing sync are enabled/disabled.
3505 */
3506 uint8_t replay_timing_sync_supported;
3507 /*
3508 * Use FSM state for Replay power up/down
3509 */
3510 uint8_t use_phy_fsm;
3511 };
3512
3513 /**
3514 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
3515 */
3516 struct dmub_rb_cmd_replay_copy_settings {
3517 /**
3518 * Command header.
3519 */
3520 struct dmub_cmd_header header;
3521 /**
3522 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
3523 */
3524 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data;
3525 };
3526
3527 /**
3528 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable
3529 */
3530 enum replay_enable {
3531 /**
3532 * Disable REPLAY.
3533 */
3534 REPLAY_DISABLE = 0,
3535 /**
3536 * Enable REPLAY.
3537 */
3538 REPLAY_ENABLE = 1,
3539 };
3540
3541 /**
3542 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command.
3543 */
3544 struct dmub_rb_cmd_replay_enable_data {
3545 /**
3546 * Replay enable or disable.
3547 */
3548 uint8_t enable;
3549 /**
3550 * Panel Instance.
3551 * Panel isntance to identify which replay_state to use
3552 * Currently the support is only for 0 or 1
3553 */
3554 uint8_t panel_inst;
3555 /**
3556 * Phy state to enter.
3557 * Values to use are defined in dmub_phy_fsm_state
3558 */
3559 uint8_t phy_fsm_state;
3560 /**
3561 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
3562 * Set this using enum phy_link_rate.
3563 * This does not support HDMI/DP2 for now.
3564 */
3565 uint8_t phy_rate;
3566 };
3567
3568 /**
3569 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
3570 * Replay enable/disable is controlled using action in data.
3571 */
3572 struct dmub_rb_cmd_replay_enable {
3573 /**
3574 * Command header.
3575 */
3576 struct dmub_cmd_header header;
3577
3578 struct dmub_rb_cmd_replay_enable_data data;
3579 };
3580
3581 /**
3582 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3583 */
3584 struct dmub_cmd_replay_set_power_opt_data {
3585 /**
3586 * Panel Instance.
3587 * Panel isntance to identify which replay_state to use
3588 * Currently the support is only for 0 or 1
3589 */
3590 uint8_t panel_inst;
3591 /**
3592 * Explicit padding to 4 byte boundary.
3593 */
3594 uint8_t pad[3];
3595 /**
3596 * REPLAY power option
3597 */
3598 uint32_t power_opt;
3599 };
3600
3601 /**
3602 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
3603 */
3604 struct dmub_cmd_replay_set_timing_sync_data {
3605 /**
3606 * Panel Instance.
3607 * Panel isntance to identify which replay_state to use
3608 * Currently the support is only for 0 or 1
3609 */
3610 uint8_t panel_inst;
3611 /**
3612 * REPLAY set_timing_sync
3613 */
3614 uint8_t timing_sync_supported;
3615 /**
3616 * Explicit padding to 4 byte boundary.
3617 */
3618 uint8_t pad[2];
3619 };
3620
3621 /**
3622 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
3623 */
3624 struct dmub_cmd_replay_set_pseudo_vtotal {
3625 /**
3626 * Panel Instance.
3627 * Panel isntance to identify which replay_state to use
3628 * Currently the support is only for 0 or 1
3629 */
3630 uint8_t panel_inst;
3631 /**
3632 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal
3633 */
3634 uint16_t vtotal;
3635 /**
3636 * Explicit padding to 4 byte boundary.
3637 */
3638 uint8_t pad;
3639 };
3640 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data {
3641 /**
3642 * Panel Instance.
3643 * Panel isntance to identify which replay_state to use
3644 * Currently the support is only for 0 or 1
3645 */
3646 uint8_t panel_inst;
3647 /**
3648 * enabled: set adaptive sync sdp enabled
3649 */
3650 uint8_t force_disabled;
3651
3652 uint8_t pad[2];
3653 };
3654 struct dmub_cmd_replay_set_general_cmd_data {
3655 /**
3656 * Panel Instance.
3657 * Panel isntance to identify which replay_state to use
3658 * Currently the support is only for 0 or 1
3659 */
3660 uint8_t panel_inst;
3661 /**
3662 * subtype: replay general cmd sub type
3663 */
3664 uint8_t subtype;
3665
3666 uint8_t pad[2];
3667 /**
3668 * config data with param1 and param2
3669 */
3670 uint32_t param1;
3671
3672 uint32_t param2;
3673 };
3674
3675 /**
3676 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3677 */
3678 struct dmub_rb_cmd_replay_set_power_opt {
3679 /**
3680 * Command header.
3681 */
3682 struct dmub_cmd_header header;
3683 /**
3684 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3685 */
3686 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;
3687 };
3688
3689 /**
3690 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
3691 */
3692 struct dmub_cmd_replay_set_coasting_vtotal_data {
3693 /**
3694 * 16-bit value dicated by driver that indicates the coasting vtotal.
3695 */
3696 uint16_t coasting_vtotal;
3697 /**
3698 * REPLAY control version.
3699 */
3700 uint8_t cmd_version;
3701 /**
3702 * Panel Instance.
3703 * Panel isntance to identify which replay_state to use
3704 * Currently the support is only for 0 or 1
3705 */
3706 uint8_t panel_inst;
3707 /**
3708 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part.
3709 */
3710 uint16_t coasting_vtotal_high;
3711 /**
3712 * Explicit padding to 4 byte boundary.
3713 */
3714 uint8_t pad[2];
3715 };
3716
3717 /**
3718 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
3719 */
3720 struct dmub_rb_cmd_replay_set_coasting_vtotal {
3721 /**
3722 * Command header.
3723 */
3724 struct dmub_cmd_header header;
3725 /**
3726 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
3727 */
3728 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
3729 };
3730
3731 /**
3732 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command.
3733 */
3734 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal {
3735 /**
3736 * Command header.
3737 */
3738 struct dmub_cmd_header header;
3739 /**
3740 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3741 */
3742 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;
3743 /**
3744 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
3745 */
3746 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
3747 };
3748
3749 /**
3750 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
3751 */
3752 struct dmub_rb_cmd_replay_set_timing_sync {
3753 /**
3754 * Command header.
3755 */
3756 struct dmub_cmd_header header;
3757 /**
3758 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
3759 */
3760 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data;
3761 };
3762
3763 /**
3764 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
3765 */
3766 struct dmub_rb_cmd_replay_set_pseudo_vtotal {
3767 /**
3768 * Command header.
3769 */
3770 struct dmub_cmd_header header;
3771 /**
3772 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
3773 */
3774 struct dmub_cmd_replay_set_pseudo_vtotal data;
3775 };
3776
3777 /**
3778 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
3779 */
3780 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp {
3781 /**
3782 * Command header.
3783 */
3784 struct dmub_cmd_header header;
3785 /**
3786 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
3787 */
3788 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data;
3789 };
3790
3791 /**
3792 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
3793 */
3794 struct dmub_rb_cmd_replay_set_general_cmd {
3795 /**
3796 * Command header.
3797 */
3798 struct dmub_cmd_header header;
3799 /**
3800 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
3801 */
3802 struct dmub_cmd_replay_set_general_cmd_data data;
3803 };
3804
3805 /**
3806 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.
3807 */
3808 struct dmub_cmd_replay_frameupdate_timer_data {
3809 /**
3810 * Panel Instance.
3811 * Panel isntance to identify which replay_state to use
3812 * Currently the support is only for 0 or 1
3813 */
3814 uint8_t panel_inst;
3815 /**
3816 * Replay Frameupdate Timer Enable or not
3817 */
3818 uint8_t enable;
3819 /**
3820 * REPLAY force reflash frame update number
3821 */
3822 uint16_t frameupdate_count;
3823 };
3824 /**
3825 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER
3826 */
3827 struct dmub_rb_cmd_replay_set_frameupdate_timer {
3828 /**
3829 * Command header.
3830 */
3831 struct dmub_cmd_header header;
3832 /**
3833 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3834 */
3835 struct dmub_cmd_replay_frameupdate_timer_data data;
3836 };
3837
3838 /**
3839 * Definition union of replay command set
3840 */
3841 union dmub_replay_cmd_set {
3842 /**
3843 * Panel Instance.
3844 * Panel isntance to identify which replay_state to use
3845 * Currently the support is only for 0 or 1
3846 */
3847 uint8_t panel_inst;
3848 /**
3849 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data.
3850 */
3851 struct dmub_cmd_replay_set_timing_sync_data sync_data;
3852 /**
3853 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data.
3854 */
3855 struct dmub_cmd_replay_frameupdate_timer_data timer_data;
3856 /**
3857 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data.
3858 */
3859 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data;
3860 /**
3861 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data.
3862 */
3863 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data;
3864 /**
3865 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data.
3866 */
3867 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data;
3868 };
3869
3870 /**
3871 * Set of HW components that can be locked.
3872 *
3873 * Note: If updating with more HW components, fields
3874 * in dmub_inbox0_cmd_lock_hw must be updated to match.
3875 */
3876 union dmub_hw_lock_flags {
3877 /**
3878 * Set of HW components that can be locked.
3879 */
3880 struct {
3881 /**
3882 * Lock/unlock OTG master update lock.
3883 */
3884 uint8_t lock_pipe : 1;
3885 /**
3886 * Lock/unlock cursor.
3887 */
3888 uint8_t lock_cursor : 1;
3889 /**
3890 * Lock/unlock global update lock.
3891 */
3892 uint8_t lock_dig : 1;
3893 /**
3894 * Triple buffer lock requires additional hw programming to usual OTG master lock.
3895 */
3896 uint8_t triple_buffer_lock : 1;
3897 } bits;
3898
3899 /**
3900 * Union for HW Lock flags.
3901 */
3902 uint8_t u8All;
3903 };
3904
3905 /**
3906 * Instances of HW to be locked.
3907 *
3908 * Note: If updating with more HW components, fields
3909 * in dmub_inbox0_cmd_lock_hw must be updated to match.
3910 */
3911 struct dmub_hw_lock_inst_flags {
3912 /**
3913 * OTG HW instance for OTG master update lock.
3914 */
3915 uint8_t otg_inst;
3916 /**
3917 * OPP instance for cursor lock.
3918 */
3919 uint8_t opp_inst;
3920 /**
3921 * OTG HW instance for global update lock.
3922 * TODO: Remove, and re-use otg_inst.
3923 */
3924 uint8_t dig_inst;
3925 /**
3926 * Explicit pad to 4 byte boundary.
3927 */
3928 uint8_t pad;
3929 };
3930
3931 /**
3932 * Clients that can acquire the HW Lock Manager.
3933 *
3934 * Note: If updating with more clients, fields in
3935 * dmub_inbox0_cmd_lock_hw must be updated to match.
3936 */
3937 enum hw_lock_client {
3938 /**
3939 * Driver is the client of HW Lock Manager.
3940 */
3941 HW_LOCK_CLIENT_DRIVER = 0,
3942 /**
3943 * PSR SU is the client of HW Lock Manager.
3944 */
3945 HW_LOCK_CLIENT_PSR_SU = 1,
3946 HW_LOCK_CLIENT_SUBVP = 3,
3947 /**
3948 * Replay is the client of HW Lock Manager.
3949 */
3950 HW_LOCK_CLIENT_REPLAY = 4,
3951 HW_LOCK_CLIENT_FAMS2 = 5,
3952 /**
3953 * Invalid client.
3954 */
3955 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
3956 };
3957
3958 /**
3959 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
3960 */
3961 struct dmub_cmd_lock_hw_data {
3962 /**
3963 * Specifies the client accessing HW Lock Manager.
3964 */
3965 enum hw_lock_client client;
3966 /**
3967 * HW instances to be locked.
3968 */
3969 struct dmub_hw_lock_inst_flags inst_flags;
3970 /**
3971 * Which components to be locked.
3972 */
3973 union dmub_hw_lock_flags hw_locks;
3974 /**
3975 * Specifies lock/unlock.
3976 */
3977 uint8_t lock;
3978 /**
3979 * HW can be unlocked separately from releasing the HW Lock Mgr.
3980 * This flag is set if the client wishes to release the object.
3981 */
3982 uint8_t should_release;
3983 /**
3984 * Explicit padding to 4 byte boundary.
3985 */
3986 uint8_t pad;
3987 };
3988
3989 /**
3990 * Definition of a DMUB_CMD__HW_LOCK command.
3991 * Command is used by driver and FW.
3992 */
3993 struct dmub_rb_cmd_lock_hw {
3994 /**
3995 * Command header.
3996 */
3997 struct dmub_cmd_header header;
3998 /**
3999 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
4000 */
4001 struct dmub_cmd_lock_hw_data lock_hw_data;
4002 };
4003
4004 /**
4005 * ABM command sub-types.
4006 */
4007 enum dmub_cmd_abm_type {
4008 /**
4009 * Initialize parameters for ABM algorithm.
4010 * Data is passed through an indirect buffer.
4011 */
4012 DMUB_CMD__ABM_INIT_CONFIG = 0,
4013 /**
4014 * Set OTG and panel HW instance.
4015 */
4016 DMUB_CMD__ABM_SET_PIPE = 1,
4017 /**
4018 * Set user requested backklight level.
4019 */
4020 DMUB_CMD__ABM_SET_BACKLIGHT = 2,
4021 /**
4022 * Set ABM operating/aggression level.
4023 */
4024 DMUB_CMD__ABM_SET_LEVEL = 3,
4025 /**
4026 * Set ambient light level.
4027 */
4028 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4,
4029 /**
4030 * Enable/disable fractional duty cycle for backlight PWM.
4031 */
4032 DMUB_CMD__ABM_SET_PWM_FRAC = 5,
4033
4034 /**
4035 * unregister vertical interrupt after steady state is reached
4036 */
4037 DMUB_CMD__ABM_PAUSE = 6,
4038
4039 /**
4040 * Save and Restore ABM state. On save we save parameters, and
4041 * on restore we update state with passed in data.
4042 */
4043 DMUB_CMD__ABM_SAVE_RESTORE = 7,
4044
4045 /**
4046 * Query ABM caps.
4047 */
4048 DMUB_CMD__ABM_QUERY_CAPS = 8,
4049
4050 /**
4051 * Set ABM Events
4052 */
4053 DMUB_CMD__ABM_SET_EVENT = 9,
4054
4055 /**
4056 * Get the current ACE curve.
4057 */
4058 DMUB_CMD__ABM_GET_ACE_CURVE = 10,
4059 };
4060
4061 struct abm_ace_curve {
4062 /**
4063 * @offsets: ACE curve offsets.
4064 */
4065 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS];
4066
4067 /**
4068 * @thresholds: ACE curve thresholds.
4069 */
4070 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS];
4071
4072 /**
4073 * @slopes: ACE curve slopes.
4074 */
4075 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS];
4076 };
4077
4078 struct fixed_pt_format {
4079 /**
4080 * @sign_bit: Indicates whether one bit is reserved for the sign.
4081 */
4082 bool sign_bit;
4083
4084 /**
4085 * @num_int_bits: Number of bits used for integer part.
4086 */
4087 uint8_t num_int_bits;
4088
4089 /**
4090 * @num_frac_bits: Number of bits used for fractional part.
4091 */
4092 uint8_t num_frac_bits;
4093
4094 /**
4095 * @pad: Explicit padding to 4 byte boundary.
4096 */
4097 uint8_t pad;
4098 };
4099
4100 struct abm_caps {
4101 /**
4102 * @num_hg_bins: Number of histogram bins.
4103 */
4104 uint8_t num_hg_bins;
4105
4106 /**
4107 * @num_ace_segments: Number of ACE curve segments.
4108 */
4109 uint8_t num_ace_segments;
4110
4111 /**
4112 * @pad: Explicit padding to 4 byte boundary.
4113 */
4114 uint8_t pad[2];
4115
4116 /**
4117 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0.
4118 */
4119 struct fixed_pt_format ace_thresholds_format;
4120
4121 /**
4122 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0.
4123 */
4124 struct fixed_pt_format ace_offsets_format;
4125
4126 /**
4127 * @ace_slopes_format: Format of the ACE slopes.
4128 */
4129 struct fixed_pt_format ace_slopes_format;
4130 };
4131
4132 /**
4133 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
4134 * Requirements:
4135 * - Padded explicitly to 32-bit boundary.
4136 * - Must ensure this structure matches the one on driver-side,
4137 * otherwise it won't be aligned.
4138 */
4139 struct abm_config_table {
4140 /**
4141 * Gamma curve thresholds, used for crgb conversion.
4142 */
4143 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B
4144 /**
4145 * Gamma curve offsets, used for crgb conversion.
4146 */
4147 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B
4148 /**
4149 * Gamma curve slopes, used for crgb conversion.
4150 */
4151 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B
4152 /**
4153 * Custom backlight curve thresholds.
4154 */
4155 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B
4156 /**
4157 * Custom backlight curve offsets.
4158 */
4159 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B
4160 /**
4161 * Ambient light thresholds.
4162 */
4163 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B
4164 /**
4165 * Minimum programmable backlight.
4166 */
4167 uint16_t min_abm_backlight; // 122B
4168 /**
4169 * Minimum reduction values.
4170 */
4171 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B
4172 /**
4173 * Maximum reduction values.
4174 */
4175 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B
4176 /**
4177 * Bright positive gain.
4178 */
4179 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
4180 /**
4181 * Dark negative gain.
4182 */
4183 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B
4184 /**
4185 * Hybrid factor.
4186 */
4187 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B
4188 /**
4189 * Contrast factor.
4190 */
4191 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B
4192 /**
4193 * Deviation gain.
4194 */
4195 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B
4196 /**
4197 * Minimum knee.
4198 */
4199 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B
4200 /**
4201 * Maximum knee.
4202 */
4203 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B
4204 /**
4205 * Unused.
4206 */
4207 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B
4208 /**
4209 * Explicit padding to 4 byte boundary.
4210 */
4211 uint8_t pad3[3]; // 229B
4212 /**
4213 * Backlight ramp reduction.
4214 */
4215 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B
4216 /**
4217 * Backlight ramp start.
4218 */
4219 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B
4220 };
4221
4222 /**
4223 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
4224 */
4225 struct dmub_cmd_abm_set_pipe_data {
4226 /**
4227 * OTG HW instance.
4228 */
4229 uint8_t otg_inst;
4230
4231 /**
4232 * Panel Control HW instance.
4233 */
4234 uint8_t panel_inst;
4235
4236 /**
4237 * Controls how ABM will interpret a set pipe or set level command.
4238 */
4239 uint8_t set_pipe_option;
4240
4241 /**
4242 * Unused.
4243 * TODO: Remove.
4244 */
4245 uint8_t ramping_boundary;
4246
4247 /**
4248 * PwrSeq HW Instance.
4249 */
4250 uint8_t pwrseq_inst;
4251
4252 /**
4253 * Explicit padding to 4 byte boundary.
4254 */
4255 uint8_t pad[3];
4256 };
4257
4258 /**
4259 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
4260 */
4261 struct dmub_rb_cmd_abm_set_pipe {
4262 /**
4263 * Command header.
4264 */
4265 struct dmub_cmd_header header;
4266
4267 /**
4268 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
4269 */
4270 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
4271 };
4272
4273 /**
4274 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
4275 */
4276 struct dmub_cmd_abm_set_backlight_data {
4277 /**
4278 * Number of frames to ramp to backlight user level.
4279 */
4280 uint32_t frame_ramp;
4281
4282 /**
4283 * Requested backlight level from user.
4284 */
4285 uint32_t backlight_user_level;
4286
4287 /**
4288 * ABM control version.
4289 */
4290 uint8_t version;
4291
4292 /**
4293 * Panel Control HW instance mask.
4294 * Bit 0 is Panel Control HW instance 0.
4295 * Bit 1 is Panel Control HW instance 1.
4296 */
4297 uint8_t panel_mask;
4298
4299 /**
4300 * Explicit padding to 4 byte boundary.
4301 */
4302 uint8_t pad[2];
4303 };
4304
4305 /**
4306 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
4307 */
4308 struct dmub_rb_cmd_abm_set_backlight {
4309 /**
4310 * Command header.
4311 */
4312 struct dmub_cmd_header header;
4313
4314 /**
4315 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
4316 */
4317 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
4318 };
4319
4320 /**
4321 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
4322 */
4323 struct dmub_cmd_abm_set_level_data {
4324 /**
4325 * Set current ABM operating/aggression level.
4326 */
4327 uint32_t level;
4328
4329 /**
4330 * ABM control version.
4331 */
4332 uint8_t version;
4333
4334 /**
4335 * Panel Control HW instance mask.
4336 * Bit 0 is Panel Control HW instance 0.
4337 * Bit 1 is Panel Control HW instance 1.
4338 */
4339 uint8_t panel_mask;
4340
4341 /**
4342 * Explicit padding to 4 byte boundary.
4343 */
4344 uint8_t pad[2];
4345 };
4346
4347 /**
4348 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
4349 */
4350 struct dmub_rb_cmd_abm_set_level {
4351 /**
4352 * Command header.
4353 */
4354 struct dmub_cmd_header header;
4355
4356 /**
4357 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
4358 */
4359 struct dmub_cmd_abm_set_level_data abm_set_level_data;
4360 };
4361
4362 /**
4363 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
4364 */
4365 struct dmub_cmd_abm_set_ambient_level_data {
4366 /**
4367 * Ambient light sensor reading from OS.
4368 */
4369 uint32_t ambient_lux;
4370
4371 /**
4372 * ABM control version.
4373 */
4374 uint8_t version;
4375
4376 /**
4377 * Panel Control HW instance mask.
4378 * Bit 0 is Panel Control HW instance 0.
4379 * Bit 1 is Panel Control HW instance 1.
4380 */
4381 uint8_t panel_mask;
4382
4383 /**
4384 * Explicit padding to 4 byte boundary.
4385 */
4386 uint8_t pad[2];
4387 };
4388
4389 /**
4390 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
4391 */
4392 struct dmub_rb_cmd_abm_set_ambient_level {
4393 /**
4394 * Command header.
4395 */
4396 struct dmub_cmd_header header;
4397
4398 /**
4399 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
4400 */
4401 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
4402 };
4403
4404 /**
4405 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
4406 */
4407 struct dmub_cmd_abm_set_pwm_frac_data {
4408 /**
4409 * Enable/disable fractional duty cycle for backlight PWM.
4410 * TODO: Convert to uint8_t.
4411 */
4412 uint32_t fractional_pwm;
4413
4414 /**
4415 * ABM control version.
4416 */
4417 uint8_t version;
4418
4419 /**
4420 * Panel Control HW instance mask.
4421 * Bit 0 is Panel Control HW instance 0.
4422 * Bit 1 is Panel Control HW instance 1.
4423 */
4424 uint8_t panel_mask;
4425
4426 /**
4427 * Explicit padding to 4 byte boundary.
4428 */
4429 uint8_t pad[2];
4430 };
4431
4432 /**
4433 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
4434 */
4435 struct dmub_rb_cmd_abm_set_pwm_frac {
4436 /**
4437 * Command header.
4438 */
4439 struct dmub_cmd_header header;
4440
4441 /**
4442 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
4443 */
4444 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
4445 };
4446
4447 /**
4448 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
4449 */
4450 struct dmub_cmd_abm_init_config_data {
4451 /**
4452 * Location of indirect buffer used to pass init data to ABM.
4453 */
4454 union dmub_addr src;
4455
4456 /**
4457 * Indirect buffer length.
4458 */
4459 uint16_t bytes;
4460
4461
4462 /**
4463 * ABM control version.
4464 */
4465 uint8_t version;
4466
4467 /**
4468 * Panel Control HW instance mask.
4469 * Bit 0 is Panel Control HW instance 0.
4470 * Bit 1 is Panel Control HW instance 1.
4471 */
4472 uint8_t panel_mask;
4473
4474 /**
4475 * Explicit padding to 4 byte boundary.
4476 */
4477 uint8_t pad[2];
4478 };
4479
4480 /**
4481 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
4482 */
4483 struct dmub_rb_cmd_abm_init_config {
4484 /**
4485 * Command header.
4486 */
4487 struct dmub_cmd_header header;
4488
4489 /**
4490 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
4491 */
4492 struct dmub_cmd_abm_init_config_data abm_init_config_data;
4493 };
4494
4495 /**
4496 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
4497 */
4498
4499 struct dmub_cmd_abm_pause_data {
4500
4501 /**
4502 * Panel Control HW instance mask.
4503 * Bit 0 is Panel Control HW instance 0.
4504 * Bit 1 is Panel Control HW instance 1.
4505 */
4506 uint8_t panel_mask;
4507
4508 /**
4509 * OTG hw instance
4510 */
4511 uint8_t otg_inst;
4512
4513 /**
4514 * Enable or disable ABM pause
4515 */
4516 uint8_t enable;
4517
4518 /**
4519 * Explicit padding to 4 byte boundary.
4520 */
4521 uint8_t pad[1];
4522 };
4523
4524 /**
4525 * Definition of a DMUB_CMD__ABM_PAUSE command.
4526 */
4527 struct dmub_rb_cmd_abm_pause {
4528 /**
4529 * Command header.
4530 */
4531 struct dmub_cmd_header header;
4532
4533 /**
4534 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
4535 */
4536 struct dmub_cmd_abm_pause_data abm_pause_data;
4537 };
4538
4539 /**
4540 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command.
4541 */
4542 struct dmub_cmd_abm_query_caps_in {
4543 /**
4544 * Panel instance.
4545 */
4546 uint8_t panel_inst;
4547
4548 /**
4549 * Explicit padding to 4 byte boundary.
4550 */
4551 uint8_t pad[3];
4552 };
4553
4554 /**
4555 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command.
4556 */
4557 struct dmub_cmd_abm_query_caps_out {
4558 /**
4559 * SW Algorithm caps.
4560 */
4561 struct abm_caps sw_caps;
4562
4563 /**
4564 * ABM HW caps.
4565 */
4566 struct abm_caps hw_caps;
4567 };
4568
4569 /**
4570 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command.
4571 */
4572 struct dmub_rb_cmd_abm_query_caps {
4573 /**
4574 * Command header.
4575 */
4576 struct dmub_cmd_header header;
4577
4578 /**
4579 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command.
4580 */
4581 union {
4582 struct dmub_cmd_abm_query_caps_in abm_query_caps_in;
4583 struct dmub_cmd_abm_query_caps_out abm_query_caps_out;
4584 } data;
4585 };
4586
4587 /**
4588 * enum dmub_abm_ace_curve_type - ACE curve type.
4589 */
4590 enum dmub_abm_ace_curve_type {
4591 /**
4592 * ACE curve as defined by the SW layer.
4593 */
4594 ABM_ACE_CURVE_TYPE__SW = 0,
4595 /**
4596 * ACE curve as defined by the SW to HW translation interface layer.
4597 */
4598 ABM_ACE_CURVE_TYPE__SW_IF = 1,
4599 };
4600
4601 /**
4602 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command.
4603 */
4604 struct dmub_rb_cmd_abm_get_ace_curve {
4605 /**
4606 * Command header.
4607 */
4608 struct dmub_cmd_header header;
4609
4610 /**
4611 * Address where ACE curve should be copied.
4612 */
4613 union dmub_addr dest;
4614
4615 /**
4616 * Type of ACE curve being queried.
4617 */
4618 enum dmub_abm_ace_curve_type ace_type;
4619
4620 /**
4621 * Indirect buffer length.
4622 */
4623 uint16_t bytes;
4624
4625 /**
4626 * eDP panel instance.
4627 */
4628 uint8_t panel_inst;
4629
4630 /**
4631 * Explicit padding to 4 byte boundary.
4632 */
4633 uint8_t pad;
4634 };
4635
4636 /**
4637 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
4638 */
4639 struct dmub_rb_cmd_abm_save_restore {
4640 /**
4641 * Command header.
4642 */
4643 struct dmub_cmd_header header;
4644
4645 /**
4646 * OTG hw instance
4647 */
4648 uint8_t otg_inst;
4649
4650 /**
4651 * Enable or disable ABM pause
4652 */
4653 uint8_t freeze;
4654
4655 /**
4656 * Explicit padding to 4 byte boundary.
4657 */
4658 uint8_t debug;
4659
4660 /**
4661 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
4662 */
4663 struct dmub_cmd_abm_init_config_data abm_init_config_data;
4664 };
4665
4666 /**
4667 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command.
4668 */
4669
4670 struct dmub_cmd_abm_set_event_data {
4671
4672 /**
4673 * VB Scaling Init. Strength Mapping
4674 * Byte 0: 0~255 for VB level 0
4675 * Byte 1: 0~255 for VB level 1
4676 * Byte 2: 0~255 for VB level 2
4677 * Byte 3: 0~255 for VB level 3
4678 */
4679 uint32_t vb_scaling_strength_mapping;
4680 /**
4681 * VariBright Scaling Enable
4682 */
4683 uint8_t vb_scaling_enable;
4684 /**
4685 * Panel Control HW instance mask.
4686 * Bit 0 is Panel Control HW instance 0.
4687 * Bit 1 is Panel Control HW instance 1.
4688 */
4689 uint8_t panel_mask;
4690
4691 /**
4692 * Explicit padding to 4 byte boundary.
4693 */
4694 uint8_t pad[2];
4695 };
4696
4697 /**
4698 * Definition of a DMUB_CMD__ABM_SET_EVENT command.
4699 */
4700 struct dmub_rb_cmd_abm_set_event {
4701 /**
4702 * Command header.
4703 */
4704 struct dmub_cmd_header header;
4705
4706 /**
4707 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command.
4708 */
4709 struct dmub_cmd_abm_set_event_data abm_set_event_data;
4710 };
4711
4712 /**
4713 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
4714 */
4715 struct dmub_cmd_query_feature_caps_data {
4716 /**
4717 * DMUB feature capabilities.
4718 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
4719 */
4720 struct dmub_feature_caps feature_caps;
4721 };
4722
4723 /**
4724 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
4725 */
4726 struct dmub_rb_cmd_query_feature_caps {
4727 /**
4728 * Command header.
4729 */
4730 struct dmub_cmd_header header;
4731 /**
4732 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
4733 */
4734 struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
4735 };
4736
4737 /**
4738 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
4739 */
4740 struct dmub_cmd_visual_confirm_color_data {
4741 /**
4742 * DMUB visual confirm color
4743 */
4744 struct dmub_visual_confirm_color visual_confirm_color;
4745 };
4746
4747 /**
4748 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
4749 */
4750 struct dmub_rb_cmd_get_visual_confirm_color {
4751 /**
4752 * Command header.
4753 */
4754 struct dmub_cmd_header header;
4755 /**
4756 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
4757 */
4758 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
4759 };
4760
4761 /**
4762 * enum dmub_cmd_panel_cntl_type - Panel control command.
4763 */
4764 enum dmub_cmd_panel_cntl_type {
4765 /**
4766 * Initializes embedded panel hardware blocks.
4767 */
4768 DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
4769 /**
4770 * Queries backlight info for the embedded panel.
4771 */
4772 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
4773 /**
4774 * Sets the PWM Freq as per user's requirement.
4775 */
4776 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2,
4777 };
4778
4779 /**
4780 * struct dmub_cmd_panel_cntl_data - Panel control data.
4781 */
4782 struct dmub_cmd_panel_cntl_data {
4783 uint32_t pwrseq_inst; /**< pwrseq instance */
4784 uint32_t current_backlight; /* in/out */
4785 uint32_t bl_pwm_cntl; /* in/out */
4786 uint32_t bl_pwm_period_cntl; /* in/out */
4787 uint32_t bl_pwm_ref_div1; /* in/out */
4788 uint8_t is_backlight_on : 1; /* in/out */
4789 uint8_t is_powered_on : 1; /* in/out */
4790 uint8_t padding[3];
4791 uint32_t bl_pwm_ref_div2; /* in/out */
4792 uint8_t reserved[4];
4793 };
4794
4795 /**
4796 * struct dmub_rb_cmd_panel_cntl - Panel control command.
4797 */
4798 struct dmub_rb_cmd_panel_cntl {
4799 struct dmub_cmd_header header; /**< header */
4800 struct dmub_cmd_panel_cntl_data data; /**< payload */
4801 };
4802
4803 struct dmub_optc_state {
4804 uint32_t v_total_max;
4805 uint32_t v_total_min;
4806 uint32_t tg_inst;
4807 };
4808
4809 struct dmub_rb_cmd_drr_update {
4810 struct dmub_cmd_header header;
4811 struct dmub_optc_state dmub_optc_state_req;
4812 };
4813
4814 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
4815 uint32_t pix_clk_100hz;
4816 uint8_t max_ramp_step;
4817 uint8_t pipes;
4818 uint8_t min_refresh_in_hz;
4819 uint8_t pipe_count;
4820 uint8_t pipe_index[4];
4821 };
4822
4823 struct dmub_cmd_fw_assisted_mclk_switch_config {
4824 uint8_t fams_enabled;
4825 uint8_t visual_confirm_enabled;
4826 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive
4827 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS];
4828 };
4829
4830 struct dmub_rb_cmd_fw_assisted_mclk_switch {
4831 struct dmub_cmd_header header;
4832 struct dmub_cmd_fw_assisted_mclk_switch_config config_data;
4833 };
4834
4835 /**
4836 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
4837 */
4838 struct dmub_cmd_lvtma_control_data {
4839 uint8_t uc_pwr_action; /**< LVTMA_ACTION */
4840 uint8_t bypass_panel_control_wait;
4841 uint8_t reserved_0[2]; /**< For future use */
4842 uint8_t pwrseq_inst; /**< LVTMA control instance */
4843 uint8_t reserved_1[3]; /**< For future use */
4844 };
4845
4846 /**
4847 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
4848 */
4849 struct dmub_rb_cmd_lvtma_control {
4850 /**
4851 * Command header.
4852 */
4853 struct dmub_cmd_header header;
4854 /**
4855 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
4856 */
4857 struct dmub_cmd_lvtma_control_data data;
4858 };
4859
4860 /**
4861 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
4862 */
4863 struct dmub_rb_cmd_transmitter_query_dp_alt_data {
4864 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
4865 uint8_t is_usb; /**< is phy is usb */
4866 uint8_t is_dp_alt_disable; /**< is dp alt disable */
4867 uint8_t is_dp4; /**< is dp in 4 lane */
4868 };
4869
4870 /**
4871 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
4872 */
4873 struct dmub_rb_cmd_transmitter_query_dp_alt {
4874 struct dmub_cmd_header header; /**< header */
4875 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */
4876 };
4877
4878 struct phy_test_mode {
4879 uint8_t mode;
4880 uint8_t pat0;
4881 uint8_t pad[2];
4882 };
4883
4884 /**
4885 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.
4886 */
4887 struct dmub_rb_cmd_transmitter_set_phy_fsm_data {
4888 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
4889 uint8_t mode; /**< HDMI/DP/DP2 etc */
4890 uint8_t lane_num; /**< Number of lanes */
4891 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */
4892 struct phy_test_mode test_mode;
4893 enum dmub_phy_fsm_state state;
4894 uint32_t status;
4895 uint8_t pad;
4896 };
4897
4898 /**
4899 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.
4900 */
4901 struct dmub_rb_cmd_transmitter_set_phy_fsm {
4902 struct dmub_cmd_header header; /**< header */
4903 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */
4904 };
4905
4906 /**
4907 * Maximum number of bytes a chunk sent to DMUB for parsing
4908 */
4909 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
4910
4911 /**
4912 * Represent a chunk of CEA blocks sent to DMUB for parsing
4913 */
4914 struct dmub_cmd_send_edid_cea {
4915 uint16_t offset; /**< offset into the CEA block */
4916 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */
4917 uint16_t cea_total_length; /**< total length of the CEA block */
4918 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
4919 uint8_t pad[3]; /**< padding and for future expansion */
4920 };
4921
4922 /**
4923 * Result of VSDB parsing from CEA block
4924 */
4925 struct dmub_cmd_edid_cea_amd_vsdb {
4926 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */
4927 uint8_t freesync_supported; /**< 1 if Freesync is supported */
4928 uint16_t amd_vsdb_version; /**< AMD VSDB version */
4929 uint16_t min_frame_rate; /**< Maximum frame rate */
4930 uint16_t max_frame_rate; /**< Minimum frame rate */
4931 };
4932
4933 /**
4934 * Result of sending a CEA chunk
4935 */
4936 struct dmub_cmd_edid_cea_ack {
4937 uint16_t offset; /**< offset of the chunk into the CEA block */
4938 uint8_t success; /**< 1 if this sending of chunk succeeded */
4939 uint8_t pad; /**< padding and for future expansion */
4940 };
4941
4942 /**
4943 * Specify whether the result is an ACK/NACK or the parsing has finished
4944 */
4945 enum dmub_cmd_edid_cea_reply_type {
4946 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */
4947 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */
4948 };
4949
4950 /**
4951 * Definition of a DMUB_CMD__EDID_CEA command.
4952 */
4953 struct dmub_rb_cmd_edid_cea {
4954 struct dmub_cmd_header header; /**< Command header */
4955 union dmub_cmd_edid_cea_data {
4956 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
4957 struct dmub_cmd_edid_cea_output { /**< output with results */
4958 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */
4959 union {
4960 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
4961 struct dmub_cmd_edid_cea_ack ack;
4962 };
4963 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */
4964 } data; /**< Command data */
4965
4966 };
4967
4968 /**
4969 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command.
4970 */
4971 struct dmub_cmd_cable_id_input {
4972 uint8_t phy_inst; /**< phy inst for cable id data */
4973 };
4974
4975 /**
4976 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command.
4977 */
4978 struct dmub_cmd_cable_id_output {
4979 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */
4980 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */
4981 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */
4982 uint8_t RESERVED :2; /**< reserved means not defined */
4983 };
4984
4985 /**
4986 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command
4987 */
4988 struct dmub_rb_cmd_get_usbc_cable_id {
4989 struct dmub_cmd_header header; /**< Command header */
4990 /**
4991 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command.
4992 */
4993 union dmub_cmd_cable_id_data {
4994 struct dmub_cmd_cable_id_input input; /**< Input */
4995 struct dmub_cmd_cable_id_output output; /**< Output */
4996 uint8_t output_raw; /**< Raw data output */
4997 } data;
4998 };
4999
5000 /**
5001 * Command type of a DMUB_CMD__SECURE_DISPLAY command
5002 */
5003 enum dmub_cmd_secure_display_type {
5004 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */
5005 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE,
5006 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY
5007 };
5008
5009 /**
5010 * Definition of a DMUB_CMD__SECURE_DISPLAY command
5011 */
5012 struct dmub_rb_cmd_secure_display {
5013 struct dmub_cmd_header header;
5014 /**
5015 * Data passed from driver to dmub firmware.
5016 */
5017 struct dmub_cmd_roi_info {
5018 uint16_t x_start;
5019 uint16_t x_end;
5020 uint16_t y_start;
5021 uint16_t y_end;
5022 uint8_t otg_id;
5023 uint8_t phy_id;
5024 } roi_info;
5025 };
5026
5027 /**
5028 * Command type of a DMUB_CMD__PSP command
5029 */
5030 enum dmub_cmd_psp_type {
5031 DMUB_CMD__PSP_ASSR_ENABLE = 0
5032 };
5033
5034 /**
5035 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command.
5036 */
5037 struct dmub_cmd_assr_enable_data {
5038 /**
5039 * ASSR enable or disable.
5040 */
5041 uint8_t enable;
5042 /**
5043 * PHY port type.
5044 * Indicates eDP / non-eDP port type
5045 */
5046 uint8_t phy_port_type;
5047 /**
5048 * PHY port ID.
5049 */
5050 uint8_t phy_port_id;
5051 /**
5052 * Link encoder index.
5053 */
5054 uint8_t link_enc_index;
5055 /**
5056 * HPO mode.
5057 */
5058 uint8_t hpo_mode;
5059
5060 /**
5061 * Reserved field.
5062 */
5063 uint8_t reserved[7];
5064 };
5065
5066 /**
5067 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.
5068 */
5069 struct dmub_rb_cmd_assr_enable {
5070 /**
5071 * Command header.
5072 */
5073 struct dmub_cmd_header header;
5074
5075 /**
5076 * Assr data.
5077 */
5078 struct dmub_cmd_assr_enable_data assr_data;
5079
5080 /**
5081 * Reserved field.
5082 */
5083 uint32_t reserved[3];
5084 };
5085
5086 /**
5087 * union dmub_rb_cmd - DMUB inbox command.
5088 */
5089 union dmub_rb_cmd {
5090 /**
5091 * Elements shared with all commands.
5092 */
5093 struct dmub_rb_cmd_common cmd_common;
5094 /**
5095 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
5096 */
5097 struct dmub_rb_cmd_read_modify_write read_modify_write;
5098 /**
5099 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
5100 */
5101 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
5102 /**
5103 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
5104 */
5105 struct dmub_rb_cmd_burst_write burst_write;
5106 /**
5107 * Definition of a DMUB_CMD__REG_REG_WAIT command.
5108 */
5109 struct dmub_rb_cmd_reg_wait reg_wait;
5110 /**
5111 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
5112 */
5113 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
5114 /**
5115 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
5116 */
5117 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
5118 /**
5119 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
5120 */
5121 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
5122 /**
5123 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
5124 */
5125 struct dmub_rb_cmd_dpphy_init dpphy_init;
5126 /**
5127 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
5128 */
5129 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
5130 /**
5131 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command.
5132 */
5133 struct dmub_rb_cmd_domain_control domain_control;
5134 /**
5135 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
5136 */
5137 struct dmub_rb_cmd_psr_set_version psr_set_version;
5138 /**
5139 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
5140 */
5141 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
5142 /**
5143 * Definition of a DMUB_CMD__PSR_ENABLE command.
5144 */
5145 struct dmub_rb_cmd_psr_enable psr_enable;
5146 /**
5147 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
5148 */
5149 struct dmub_rb_cmd_psr_set_level psr_set_level;
5150 /**
5151 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
5152 */
5153 struct dmub_rb_cmd_psr_force_static psr_force_static;
5154 /**
5155 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
5156 */
5157 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect;
5158 /**
5159 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
5160 */
5161 struct dmub_rb_cmd_update_cursor_info update_cursor_info;
5162 /**
5163 * Definition of a DMUB_CMD__HW_LOCK command.
5164 * Command is used by driver and FW.
5165 */
5166 struct dmub_rb_cmd_lock_hw lock_hw;
5167 /**
5168 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
5169 */
5170 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal;
5171 /**
5172 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
5173 */
5174 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt;
5175 /**
5176 * Definition of a DMUB_CMD__PLAT_54186_WA command.
5177 */
5178 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
5179 /**
5180 * Definition of a DMUB_CMD__MALL command.
5181 */
5182 struct dmub_rb_cmd_mall mall;
5183
5184 /**
5185 * Definition of a DMUB_CMD__CAB command.
5186 */
5187 struct dmub_rb_cmd_cab_for_ss cab;
5188
5189 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2;
5190
5191 /**
5192 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
5193 */
5194 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
5195
5196 /**
5197 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
5198 */
5199 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
5200
5201 /**
5202 * Definition of DMUB_CMD__PANEL_CNTL commands.
5203 */
5204 struct dmub_rb_cmd_panel_cntl panel_cntl;
5205
5206 /**
5207 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
5208 */
5209 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
5210
5211 /**
5212 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
5213 */
5214 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
5215
5216 /**
5217 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
5218 */
5219 struct dmub_rb_cmd_abm_set_level abm_set_level;
5220
5221 /**
5222 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
5223 */
5224 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
5225
5226 /**
5227 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
5228 */
5229 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
5230
5231 /**
5232 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
5233 */
5234 struct dmub_rb_cmd_abm_init_config abm_init_config;
5235
5236 /**
5237 * Definition of a DMUB_CMD__ABM_PAUSE command.
5238 */
5239 struct dmub_rb_cmd_abm_pause abm_pause;
5240
5241 /**
5242 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
5243 */
5244 struct dmub_rb_cmd_abm_save_restore abm_save_restore;
5245
5246 /**
5247 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command.
5248 */
5249 struct dmub_rb_cmd_abm_query_caps abm_query_caps;
5250
5251 /**
5252 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command.
5253 */
5254 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve;
5255
5256 /**
5257 * Definition of a DMUB_CMD__ABM_SET_EVENT command.
5258 */
5259 struct dmub_rb_cmd_abm_set_event abm_set_event;
5260
5261 /**
5262 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
5263 */
5264 struct dmub_rb_cmd_dp_aux_access dp_aux_access;
5265
5266 /**
5267 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
5268 */
5269 struct dmub_rb_cmd_outbox1_enable outbox1_enable;
5270
5271 /**
5272 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
5273 */
5274 struct dmub_rb_cmd_query_feature_caps query_feature_caps;
5275
5276 /**
5277 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
5278 */
5279 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color;
5280 struct dmub_rb_cmd_drr_update drr_update;
5281 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch;
5282
5283 /**
5284 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
5285 */
5286 struct dmub_rb_cmd_lvtma_control lvtma_control;
5287 /**
5288 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
5289 */
5290 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt;
5291 /**
5292 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.
5293 */
5294 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm;
5295 /**
5296 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command.
5297 */
5298 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control;
5299 /**
5300 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
5301 */
5302 struct dmub_rb_cmd_set_config_access set_config_access;
5303 /**
5304 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
5305 */
5306 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots;
5307 /**
5308 * Definition of a DMUB_CMD__EDID_CEA command.
5309 */
5310 struct dmub_rb_cmd_edid_cea edid_cea;
5311 /**
5312 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command.
5313 */
5314 struct dmub_rb_cmd_get_usbc_cable_id cable_id;
5315
5316 /**
5317 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
5318 */
5319 struct dmub_rb_cmd_query_hpd_state query_hpd;
5320 /**
5321 * Definition of a DMUB_CMD__SECURE_DISPLAY command.
5322 */
5323 struct dmub_rb_cmd_secure_display secure_display;
5324
5325 /**
5326 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command.
5327 */
5328 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable;
5329 /**
5330 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
5331 */
5332 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle;
5333 /**
5334 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.
5335 */
5336 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state;
5337 /*
5338 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
5339 */
5340 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings;
5341 /**
5342 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
5343 */
5344 struct dmub_rb_cmd_replay_enable replay_enable;
5345 /**
5346 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
5347 */
5348 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt;
5349 /**
5350 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
5351 */
5352 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal;
5353 /**
5354 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command.
5355 */
5356 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal;
5357
5358 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync;
5359 /**
5360 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.
5361 */
5362 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer;
5363 /**
5364 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
5365 */
5366 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal;
5367 /**
5368 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
5369 */
5370 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp;
5371 /**
5372 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
5373 */
5374 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd;
5375 /**
5376 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.
5377 */
5378 struct dmub_rb_cmd_assr_enable assr_enable;
5379 struct dmub_rb_cmd_fams2 fams2_config;
5380
5381 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update;
5382
5383 struct dmub_rb_cmd_fams2_flip fams2_flip;
5384 };
5385
5386 /**
5387 * union dmub_rb_out_cmd - Outbox command
5388 */
5389 union dmub_rb_out_cmd {
5390 /**
5391 * Parameters common to every command.
5392 */
5393 struct dmub_rb_cmd_common cmd_common;
5394 /**
5395 * AUX reply command.
5396 */
5397 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
5398 /**
5399 * HPD notify command.
5400 */
5401 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
5402 /**
5403 * SET_CONFIG reply command.
5404 */
5405 struct dmub_rb_cmd_dp_set_config_reply set_config_reply;
5406 /**
5407 * DPIA notification command.
5408 */
5409 struct dmub_rb_cmd_dpia_notification dpia_notification;
5410 /**
5411 * HPD sense notification command.
5412 */
5413 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify;
5414 };
5415 #pragma pack(pop)
5416
5417
5418 //==============================================================================
5419 //</DMUB_CMD>===================================================================
5420 //==============================================================================
5421 //< DMUB_RB>====================================================================
5422 //==============================================================================
5423
5424 /**
5425 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
5426 */
5427 struct dmub_rb_init_params {
5428 void *ctx; /**< Caller provided context pointer */
5429 void *base_address; /**< CPU base address for ring's data */
5430 uint32_t capacity; /**< Ringbuffer capacity in bytes */
5431 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
5432 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
5433 };
5434
5435 /**
5436 * struct dmub_rb - Inbox or outbox DMUB ringbuffer
5437 */
5438 struct dmub_rb {
5439 void *base_address; /**< CPU address for the ring's data */
5440 uint32_t rptr; /**< Read pointer for consumer in bytes */
5441 uint32_t wrpt; /**< Write pointer for producer in bytes */
5442 uint32_t capacity; /**< Ringbuffer capacity in bytes */
5443
5444 void *ctx; /**< Caller provided context pointer */
5445 void *dmub; /**< Pointer to the DMUB interface */
5446 };
5447
5448 /**
5449 * @brief Checks if the ringbuffer is empty.
5450 *
5451 * @param rb DMUB Ringbuffer
5452 * @return true if empty
5453 * @return false otherwise
5454 */
dmub_rb_empty(struct dmub_rb * rb)5455 static inline bool dmub_rb_empty(struct dmub_rb *rb)
5456 {
5457 return (rb->wrpt == rb->rptr);
5458 }
5459
5460 /**
5461 * @brief Checks if the ringbuffer is full
5462 *
5463 * @param rb DMUB Ringbuffer
5464 * @return true if full
5465 * @return false otherwise
5466 */
dmub_rb_full(struct dmub_rb * rb)5467 static inline bool dmub_rb_full(struct dmub_rb *rb)
5468 {
5469 uint32_t data_count;
5470
5471 if (rb->wrpt >= rb->rptr)
5472 data_count = rb->wrpt - rb->rptr;
5473 else
5474 data_count = rb->capacity - (rb->rptr - rb->wrpt);
5475
5476 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
5477 }
5478
5479 /**
5480 * @brief Pushes a command into the ringbuffer
5481 *
5482 * @param rb DMUB ringbuffer
5483 * @param cmd The command to push
5484 * @return true if the ringbuffer was not full
5485 * @return false otherwise
5486 */
dmub_rb_push_front(struct dmub_rb * rb,const union dmub_rb_cmd * cmd)5487 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
5488 const union dmub_rb_cmd *cmd)
5489 {
5490 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt);
5491 const uint64_t *src = (const uint64_t *)cmd;
5492 uint8_t i;
5493
5494 if (dmub_rb_full(rb))
5495 return false;
5496
5497 // copying data
5498 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
5499 *dst++ = *src++;
5500
5501 rb->wrpt += DMUB_RB_CMD_SIZE;
5502
5503 if (rb->wrpt >= rb->capacity)
5504 rb->wrpt %= rb->capacity;
5505
5506 return true;
5507 }
5508
5509 /**
5510 * @brief Pushes a command into the DMUB outbox ringbuffer
5511 *
5512 * @param rb DMUB outbox ringbuffer
5513 * @param cmd Outbox command
5514 * @return true if not full
5515 * @return false otherwise
5516 */
dmub_rb_out_push_front(struct dmub_rb * rb,const union dmub_rb_out_cmd * cmd)5517 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
5518 const union dmub_rb_out_cmd *cmd)
5519 {
5520 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
5521 const uint8_t *src = (const uint8_t *)cmd;
5522
5523 if (dmub_rb_full(rb))
5524 return false;
5525
5526 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
5527
5528 rb->wrpt += DMUB_RB_CMD_SIZE;
5529
5530 if (rb->wrpt >= rb->capacity)
5531 rb->wrpt %= rb->capacity;
5532
5533 return true;
5534 }
5535
5536 /**
5537 * @brief Returns the next unprocessed command in the ringbuffer.
5538 *
5539 * @param rb DMUB ringbuffer
5540 * @param cmd The command to return
5541 * @return true if not empty
5542 * @return false otherwise
5543 */
dmub_rb_front(struct dmub_rb * rb,union dmub_rb_cmd ** cmd)5544 static inline bool dmub_rb_front(struct dmub_rb *rb,
5545 union dmub_rb_cmd **cmd)
5546 {
5547 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
5548
5549 if (dmub_rb_empty(rb))
5550 return false;
5551
5552 *cmd = (union dmub_rb_cmd *)rb_cmd;
5553
5554 return true;
5555 }
5556
5557 /**
5558 * @brief Determines the next ringbuffer offset.
5559 *
5560 * @param rb DMUB inbox ringbuffer
5561 * @param num_cmds Number of commands
5562 * @param next_rptr The next offset in the ringbuffer
5563 */
dmub_rb_get_rptr_with_offset(struct dmub_rb * rb,uint32_t num_cmds,uint32_t * next_rptr)5564 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
5565 uint32_t num_cmds,
5566 uint32_t *next_rptr)
5567 {
5568 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
5569
5570 if (*next_rptr >= rb->capacity)
5571 *next_rptr %= rb->capacity;
5572 }
5573
5574 /**
5575 * @brief Returns a pointer to a command in the inbox.
5576 *
5577 * @param rb DMUB inbox ringbuffer
5578 * @param cmd The inbox command to return
5579 * @param rptr The ringbuffer offset
5580 * @return true if not empty
5581 * @return false otherwise
5582 */
dmub_rb_peek_offset(struct dmub_rb * rb,union dmub_rb_cmd ** cmd,uint32_t rptr)5583 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
5584 union dmub_rb_cmd **cmd,
5585 uint32_t rptr)
5586 {
5587 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
5588
5589 if (dmub_rb_empty(rb))
5590 return false;
5591
5592 *cmd = (union dmub_rb_cmd *)rb_cmd;
5593
5594 return true;
5595 }
5596
5597 /**
5598 * @brief Returns the next unprocessed command in the outbox.
5599 *
5600 * @param rb DMUB outbox ringbuffer
5601 * @param cmd The outbox command to return
5602 * @return true if not empty
5603 * @return false otherwise
5604 */
dmub_rb_out_front(struct dmub_rb * rb,union dmub_rb_out_cmd * cmd)5605 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
5606 union dmub_rb_out_cmd *cmd)
5607 {
5608 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr);
5609 uint64_t *dst = (uint64_t *)cmd;
5610 uint8_t i;
5611
5612 if (dmub_rb_empty(rb))
5613 return false;
5614
5615 // copying data
5616 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
5617 *dst++ = *src++;
5618
5619 return true;
5620 }
5621
5622 /**
5623 * @brief Removes the front entry in the ringbuffer.
5624 *
5625 * @param rb DMUB ringbuffer
5626 * @return true if the command was removed
5627 * @return false if there were no commands
5628 */
dmub_rb_pop_front(struct dmub_rb * rb)5629 static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
5630 {
5631 if (dmub_rb_empty(rb))
5632 return false;
5633
5634 rb->rptr += DMUB_RB_CMD_SIZE;
5635
5636 if (rb->rptr >= rb->capacity)
5637 rb->rptr %= rb->capacity;
5638
5639 return true;
5640 }
5641
5642 /**
5643 * @brief Flushes commands in the ringbuffer to framebuffer memory.
5644 *
5645 * Avoids a race condition where DMCUB accesses memory while
5646 * there are still writes in flight to framebuffer.
5647 *
5648 * @param rb DMUB ringbuffer
5649 */
dmub_rb_flush_pending(const struct dmub_rb * rb)5650 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
5651 {
5652 uint32_t rptr = rb->rptr;
5653 uint32_t wptr = rb->wrpt;
5654
5655 while (rptr != wptr) {
5656 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr);
5657 uint8_t i;
5658
5659 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
5660 (void)READ_ONCE(*data++);
5661
5662 rptr += DMUB_RB_CMD_SIZE;
5663 if (rptr >= rb->capacity)
5664 rptr %= rb->capacity;
5665 }
5666 }
5667
5668 /**
5669 * @brief Initializes a DMCUB ringbuffer
5670 *
5671 * @param rb DMUB ringbuffer
5672 * @param init_params initial configuration for the ringbuffer
5673 */
dmub_rb_init(struct dmub_rb * rb,struct dmub_rb_init_params * init_params)5674 static inline void dmub_rb_init(struct dmub_rb *rb,
5675 struct dmub_rb_init_params *init_params)
5676 {
5677 rb->base_address = init_params->base_address;
5678 rb->capacity = init_params->capacity;
5679 rb->rptr = init_params->read_ptr;
5680 rb->wrpt = init_params->write_ptr;
5681 }
5682
5683 /**
5684 * @brief Copies output data from in/out commands into the given command.
5685 *
5686 * @param rb DMUB ringbuffer
5687 * @param cmd Command to copy data into
5688 */
dmub_rb_get_return_data(struct dmub_rb * rb,union dmub_rb_cmd * cmd)5689 static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
5690 union dmub_rb_cmd *cmd)
5691 {
5692 // Copy rb entry back into command
5693 uint8_t *rd_ptr = (rb->rptr == 0) ?
5694 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
5695 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
5696
5697 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
5698 }
5699
5700 //==============================================================================
5701 //</DMUB_RB>====================================================================
5702 //==============================================================================
5703 #endif /* _DMUB_CMD_H_ */
5704