RISCV_OP_REG (definition) in projects: dports

Searched defs:RISCV_OP_REG (Results 1 – 8 of 8) sorted by relevance

/dports/emulators/qemu/qemu-6.2.0/capstone/bindings/python/capstone/
H A D	riscv_const.py	`6 RISCV_OP_REG = 1 variable`
/dports/emulators/qemu60/qemu-6.0.0/capstone/bindings/python/capstone/
H A D	riscv_const.py	`6 RISCV_OP_REG = 1 variable`
/dports/emulators/qemu5/qemu-5.2.0/capstone/bindings/python/capstone/
H A D	riscv_const.py	`6 RISCV_OP_REG = 1 variable`
/dports/emulators/qemu/qemu-6.2.0/capstone/include/capstone/
H A D	riscv.h	`29 RISCV_OP_REG, // = CS_OP_REG (Register operand). enumerator`
/dports/emulators/qemu60/qemu-6.0.0/capstone/include/capstone/
H A D	riscv.h	`29 RISCV_OP_REG, // = CS_OP_REG (Register operand). enumerator`
/dports/emulators/qemu5/qemu-5.2.0/capstone/include/capstone/
H A D	riscv.h	`29 RISCV_OP_REG, // = CS_OP_REG (Register operand). enumerator`
/dports/devel/xelfviewer/XELFViewer-0.03/XCapstone/3rdparty/Capstone/src/capstone/
H A D	riscv.h	`29 RISCV_OP_REG, // = CS_OP_REG (Register operand). enumerator`
/dports/devel/xelfviewer/XELFViewer-0.03/XCapstone/3rdparty/Capstone/src/include/capstone/
H A D	riscv.h	`29 RISCV_OP_REG, // = CS_OP_REG (Register operand). enumerator`