1 /* Public Domain */ 2 3 /* 4 * RK3288 clocks. 5 */ 6 7 #define RK3288_PLL_APLL 1 8 #define RK3288_PLL_CPLL 3 9 #define RK3288_PLL_GPLL 4 10 #define RK3288_PLL_NPLL 5 11 #define RK3288_ARMCLK 6 12 13 #define RK3288_CLK_SDMMC 68 14 #define RK3288_CLK_TSADC 72 15 #define RK3288_CLK_UART0 77 16 #define RK3288_CLK_UART1 78 17 #define RK3288_CLK_UART2 79 18 #define RK3288_CLK_UART3 80 19 #define RK3288_CLK_UART4 81 20 #define RK3288_CLK_MAC_RX 102 21 #define RK3288_CLK_MAC_TX 103 22 #define RK3288_CLK_SDMMC_DRV 114 23 #define RK3288_CLK_SDMMC_SAMPLE 118 24 #define RK3288_CLK_MAC 151 25 26 #define RK3288_ACLK_GMAC 196 27 28 #define RK3288_PCLK_I2C0 332 29 #define RK3288_PCLK_I2C1 333 30 #define RK3288_PCLK_I2C2 334 31 #define RK3288_PCLK_I2C3 335 32 #define RK3288_PCLK_I2C4 336 33 #define RK3288_PCLK_I2C5 337 34 #define RK3288_PCLK_TSADC 346 35 #define RK3288_PCLK_GMAC 349 36 37 #define RK3288_HCLK_HOST0 450 38 #define RK3288_HCLK_SDMMC 456 39 40 #define RK3288_XIN24M 1023 41 42 /* 43 * RK3308 clocks. 44 */ 45 46 #define RK3308_PLL_APLL 1 47 #define RK3308_PLL_DPLL 2 48 #define RK3308_PLL_VPLL0 3 49 #define RK3308_PLL_VPLL1 4 50 #define RK3308_ARMCLK 5 51 52 #define RK3308_USB480M 14 53 #define RK3308_CLK_RTC32K 15 54 #define RK3308_CLK_UART0 17 55 #define RK3308_CLK_UART1 18 56 #define RK3308_CLK_UART2 19 57 #define RK3308_CLK_UART3 20 58 #define RK3308_CLK_UART4 21 59 #define RK3308_CLK_PWM0 26 60 #define RK3308_CLK_SPI0 27 61 #define RK3308_CLK_SPI1 28 62 #define RK3308_CLK_SPI2 29 63 #define RK3308_CLK_TSADC 36 64 #define RK3308_CLK_SARADC 37 65 #define RK3308_CLK_CRYPTO 41 66 #define RK3308_CLK_CRYPTO_APK 42 67 #define RK3308_CLK_SDMMC 48 68 #define RK3308_CLK_SDMMC_DRV 49 69 #define RK3308_CLK_SDMMC_SAMPLE 50 70 #define RK3308_CLK_SDIO 53 71 #define RK3308_CLK_SDIO_DRV 54 72 #define RK3308_CLK_SDIO_SAMPLE 55 73 #define RK3308_CLK_EMMC 58 74 #define RK3308_CLK_MAC_SRC 63 75 #define RK3308_CLK_MAC 64 76 #define RK3308_CLK_MAC_RMII 67 77 78 #define RK3308_ACLK_BUS_SRC 130 79 #define RK3308_ACLK_BUS 131 80 #define RK3308_ACLK_PERI_SRC 132 81 #define RK3308_ACLK_PERI 133 82 #define RK3308_ACLK_MAC 134 83 #define RK3308_ACLK_CRYPTO 135 84 #define RK3308_ACLK_GIC 137 85 86 #define RK3308_HCLK_BUS 150 87 #define RK3308_HCLK_PERI 151 88 #define RK3308_HCLK_SDMMC 154 89 #define RK3308_HCLK_CRYPTO 171 90 91 #define RK3308_PCLK_BUS 190 92 #define RK3308_PCLK_PERI 192 93 #define RK3308_PCLK_MAC 195 94 95 #define RK3308_XIN24M 1023 96 97 /* 98 * RK3328 clocks. 99 */ 100 101 #define RK3328_PLL_APLL 1 102 #define RK3328_PLL_DPLL 2 103 #define RK3328_PLL_CPLL 3 104 #define RK3328_PLL_GPLL 4 105 #define RK3328_PLL_NPLL 5 106 #define RK3328_ARMCLK 6 107 108 #define RK3328_CLK_RTC32K 30 109 #define RK3328_CLK_SPI 32 110 #define RK3328_CLK_SDMMC 33 111 #define RK3328_CLK_SDIO 34 112 #define RK3328_CLK_EMMC 35 113 #define RK3328_CLK_TSADC 36 114 #define RK3328_CLK_UART0 38 115 #define RK3328_CLK_UART1 39 116 #define RK3328_CLK_UART2 40 117 #define RK3328_CLK_WIFI 53 118 #define RK3328_CLK_I2C0 55 119 #define RK3328_CLK_I2C1 56 120 #define RK3328_CLK_I2C2 57 121 #define RK3328_CLK_I2C3 58 122 #define RK3328_CLK_CRYPTO 59 123 #define RK3328_CLK_PDM 61 124 #define RK3328_CLK_VDEC_CABAC 65 125 #define RK3328_CLK_VDEC_CORE 66 126 #define RK3328_CLK_VENC_DSP 67 127 #define RK3328_CLK_VENC_CORE 68 128 #define RK3328_CLK_TSP 92 129 #define RK3328_CLK_MAC2IO_SRC 99 130 #define RK3328_CLK_MAC2IO 100 131 #define RK3328_CLK_MAC2IO_EXT 102 132 133 #define RK3328_DCLK_LCDC 120 134 #define RK3328_HDMIPHY 122 135 #define RK3328_USB480M 123 136 #define RK3328_DCLK_LCDC_SRC 124 137 138 #define RK3328_ACLK_VOP_PRE 131 139 #define RK3328_ACLK_RGA_PRE 133 140 #define RK3328_ACLK_BUS_PRE 136 141 #define RK3328_ACLK_PERI_PRE 137 142 #define RK3328_ACLK_RKVDEC_PRE 138 143 #define RK3328_ACLK_RKVENC 140 144 #define RK3328_ACLK_VPU_PRE 141 145 #define RK3328_ACLK_VIO_PRE 142 146 147 #define RK3328_PCLK_BUS_PRE 216 148 #define RK3328_PCLK_PERI 230 149 150 #define RK3328_HCLK_PERI 308 151 #define RK3328_HCLK_BUS_PRE 328 152 #define RK3328_HCLK_CRYPTO_SLV 337 153 154 #define RK3328_XIN24M 1023 155 #define RK3328_CLK_24M 1022 156 #define RK3328_GMAC_CLKIN 1021 157 158 /* 159 * RK3399 clocks. 160 */ 161 162 #define RK3399_PLL_ALPLL 1 163 #define RK3399_PLL_ABPLL 2 164 #define RK3399_PLL_DPLL 3 165 #define RK3399_PLL_CPLL 4 166 #define RK3399_PLL_GPLL 5 167 #define RK3399_PLL_NPLL 6 168 #define RK3399_PLL_VPLL 7 169 #define RK3399_ARMCLKL 8 170 #define RK3399_ARMCLKB 9 171 172 #define RK3399_CLK_I2C1 65 173 #define RK3399_CLK_I2C2 66 174 #define RK3399_CLK_I2C3 67 175 #define RK3399_CLK_I2C5 68 176 #define RK3399_CLK_I2C6 69 177 #define RK3399_CLK_I2C7 70 178 #define RK3399_CLK_SPI0 71 179 #define RK3399_CLK_SPI1 72 180 #define RK3399_CLK_SPI2 73 181 #define RK3399_CLK_SPI4 74 182 #define RK3399_CLK_SPI5 75 183 #define RK3399_CLK_SDMMC 76 184 #define RK3399_CLK_SDIO 77 185 #define RK3399_CLK_EMMC 78 186 #define RK3399_CLK_TSADC 79 187 #define RK3399_CLK_UART0 81 188 #define RK3399_CLK_UART1 82 189 #define RK3399_CLK_UART2 83 190 #define RK3399_CLK_UART3 84 191 #define RK3399_CLK_SPDIF_8CH 85 192 #define RK3399_CLK_I2S0_8CH 86 193 #define RK3399_CLK_I2S1_8CH 87 194 #define RK3399_CLK_I2S2_8CH 88 195 #define RK3399_CLK_I2S_8CH_OUT 89 196 #define RK3399_CLK_MAC_RX 103 197 #define RK3399_CLK_MAC_TX 104 198 #define RK3399_CLK_MAC 105 199 #define RK3399_CLK_USB2PHY0_REF 123 200 #define RK3399_CLK_USB2PHY1_REF 124 201 #define RK3399_CLK_UPHY0_TCPDPHY_REF 125 202 #define RK3399_CLK_UPHY0_TCPDCORE 126 203 #define RK3399_CLK_UPHY1_TCPDPHY_REF 127 204 #define RK3399_CLK_UPHY1_TCPDCORE 128 205 #define RK3399_CLK_USB3OTG0_REF 129 206 #define RK3399_CLK_USB3OTG1_REF 130 207 #define RK3399_CLK_USB3OTG0_SUSPEND 131 208 #define RK3399_CLK_USB3OTG1_SUSPEND 132 209 #define RK3399_CLK_PCIEPHY_REF 138 210 #define RK3399_CLK_SDMMC_DRV 154 211 #define RK3399_CLK_SDMMC_SAMPLE 155 212 #define RK3399_CLK_PCIEPHY_REF100M 167 213 214 #define RK3399_DCLK_VOP0 180 215 #define RK3399_DCLK_VOP1 181 216 #define RK3399_DCLK_VOP0_DIV 182 217 #define RK3399_DCLK_VOP1_DIV 183 218 #define RK3399_DCLK_VOP0_FRAC 185 219 #define RK3399_DCLK_VOP1_FRAC 186 220 221 #define RK3399_ACLK_PERIPH 192 222 #define RK3399_ACLK_PERILP0 194 223 #define RK3399_ACLK_CCI 201 224 #define RK3399_ACLK_GMAC 213 225 #define RK3399_ACLK_VOP0_NOC 216 226 #define RK3399_ACLK_VOP0 217 227 #define RK3399_ACLK_VOP1_NOC 218 228 #define RK3399_ACLK_VOP1 219 229 #define RK3399_ACLK_HDCP 222 230 #define RK3399_ACLK_VIO 227 231 #define RK3399_ACLK_EMMC 240 232 #define RK3399_ACLK_USB3OTG0 246 233 #define RK3399_ACLK_USB3OTG1 247 234 #define RK3399_ACLK_USB3_GRF 249 235 #define RK3399_ACLK_GIC_PRE 262 236 237 #define RK3399_PCLK_PERIPH 320 238 #define RK3399_PCLK_PERILP0 322 239 #define RK3399_PCLK_PERILP1 323 240 #define RK3399_PCLK_I2C1 341 241 #define RK3399_PCLK_I2C2 342 242 #define RK3399_PCLK_I2C3 343 243 #define RK3399_PCLK_I2C5 344 244 #define RK3399_PCLK_I2C6 345 245 #define RK3399_PCLK_I2C7 346 246 #define RK3399_PCLK_TSADC 356 247 #define RK3399_PCLK_GMAC 358 248 #define RK3399_PCLK_DDR 376 249 #define RK3399_PCLK_WDT 380 250 251 #define RK3399_HCLK_PERIPH 448 252 #define RK3399_HCLK_PERILP0 449 253 #define RK3399_HCLK_PERILP1 450 254 #define RK3399_HCLK_HOST0 456 255 #define RK3399_HCLK_HOST0_ARB 457 256 #define RK3399_HCLK_HOST1 458 257 #define RK3399_HCLK_HOST1_ARB 459 258 #define RK3399_HCLK_SDMMC 462 259 #define RK3399_HCLK_VOP0_NOC 472 260 #define RK3399_HCLK_VOP0 473 261 #define RK3399_HCLK_VOP1_NOC 474 262 #define RK3399_HCLK_VOP1 475 263 264 /* PMUCRU */ 265 266 #define RK3399_PLL_PPLL 1 267 268 #define RK3399_CLK_I2C0 9 269 #define RK3399_CLK_I2C4 10 270 #define RK3399_CLK_I2C8 11 271 272 #define RK3399_PCLK_I2C0 27 273 #define RK3399_PCLK_I2C4 28 274 #define RK3399_PCLK_I2C8 29 275 #define RK3399_PCLK_RKPWM 30 276 277 #define RK3399_XIN24M 1023 278 #define RK3399_CLK_32K 1022 279 #define RK3399_XIN12M 1021 280 #define RK3399_CLK_I2S0_DIV 1020 281 #define RK3399_CLK_I2S0_FRAC 1019 282 #define RK3399_CLK_I2S1_DIV 1018 283 #define RK3399_CLK_I2S1_FRAC 1017 284 #define RK3399_CLK_I2S2_DIV 1016 285 #define RK3399_CLK_I2S2_FRAC 1015 286 #define RK3399_CLK_I2SOUT_SRC 1014 287 288 /* 289 * RK3568 clocks. 290 */ 291 292 #define RK3568_PLL_APLL 1 293 #define RK3568_PLL_DPLL 2 294 #define RK3568_PLL_CPLL 3 295 #define RK3568_PLL_GPLL 4 296 #define RK3568_PLL_VPLL 5 297 #define RK3568_PLL_NPLL 6 298 299 #define RK3568_ACLK_EMMC 121 300 #define RK3568_HCLK_EMMC 122 301 #define RK3568_BCLK_EMMC 123 302 #define RK3568_CCLK_EMMC 124 303 #define RK3568_TCLK_EMMC 125 304 #define RK3568_ACLK_PHP 173 305 #define RK3568_PCLK_PHP 175 306 #define RK3568_CLK_SDMMC0 177 307 #define RK3568_CLK_SDMMC1 179 308 #define RK3568_ACLK_GMAC0 180 309 #define RK3568_PCLK_GMAC0 181 310 #define RK3568_CLK_MAC0_2TOP 182 311 #define RK3568_CLK_MAC0_REFOUT 184 312 #define RK3568_CLK_GMAC0_PTP_REF 185 313 #define RK3568_ACLK_USB 186 314 #define RK3568_PCLK_USB 188 315 #define RK3568_CLK_SDMMC2 194 316 #define RK3568_ACLK_GMAC1 195 317 #define RK3568_PCLK_GMAC1 196 318 #define RK3568_CLK_MAC1_2TOP 197 319 #define RK3568_CLK_MAC1_REFOUT 199 320 #define RK3568_CLK_GMAC1_PTP_REF 200 321 #define RK3568_CLK_TSADC_TSEN 272 322 #define RK3568_CLK_TSADC 273 323 #define RK3568_SCLK_UART1 287 324 #define RK3568_SCLK_UART2 291 325 #define RK3568_SCLK_UART3 295 326 #define RK3568_SCLK_UART4 299 327 #define RK3568_SCLK_UART5 303 328 #define RK3568_SCLK_UART6 307 329 #define RK3568_SCLK_UART7 311 330 #define RK3568_SCLK_UART8 315 331 #define RK3568_SCLK_UART9 319 332 #define RK3568_CLK_I2C 326 333 #define RK3568_CLK_I2C1 328 334 #define RK3568_CLK_I2C2 330 335 #define RK3568_CLK_I2C3 332 336 #define RK3568_CLK_I2C4 334 337 #define RK3568_CLK_I2C5 336 338 #define RK3568_CLK_SPI0 338 339 #define RK3568_CLK_SPI1 340 340 #define RK3568_CLK_SPI2 342 341 #define RK3568_CLK_SPI3 344 342 #define RK3568_SCLK_GMAC0 386 343 #define RK3568_SCLK_GMAC0_RGMII_SPEED 387 344 #define RK3568_SCLK_GMAC0_RMII_SPEED 388 345 #define RK3568_SCLK_GMAC0_RX_TX 389 346 #define RK3568_SCLK_GMAC1 390 347 #define RK3568_SCLK_GMAC1_RGMII_SPEED 391 348 #define RK3568_SCLK_GMAC1_RMII_SPEED 392 349 #define RK3568_SCLK_GMAC1_RX_TX 393 350 351 #define RK3568_CPLL_125M 413 352 #define RK3568_CPLL_62P5M 414 353 #define RK3568_CPLL_50M 415 354 #define RK3568_CPLL_25M 416 355 #define RK3568_CPLL_100M 417 356 357 #define RK3568_SCLK_GMAC0_DIV_50 1005 358 #define RK3568_SCLK_GMAC0_DIV_5 1006 359 #define RK3568_SCLK_GMAC0_DIV_20 1007 360 #define RK3568_SCLK_GMAC0_DIV_2 1008 361 #define RK3568_SCLK_GMAC1_DIV_50 1009 362 #define RK3568_SCLK_GMAC1_DIV_5 1010 363 #define RK3568_SCLK_GMAC1_DIV_20 1011 364 #define RK3568_SCLK_GMAC1_DIV_2 1012 365 #define RK3568_GPLL_400M 1013 366 #define RK3568_GPLL_300M 1014 367 #define RK3568_GPLL_200M 1015 368 #define RK3568_GPLL_150M 1016 369 #define RK3568_GPLL_100M 1017 370 #define RK3568_CLK_OSC0_DIV_375K 1018 371 #define RK3568_CLK_OSC0_DIV_750K 1019 372 #define RK3568_GMAC0_CLKIN 1020 373 #define RK3568_GMAC1_CLKIN 1021 374 #define RK3568_XIN32K 1022 375 #define RK3568_XIN24M 1023 376 377 /* PMUCRU */ 378 379 #define RK3568_PLL_PPLL 1 380 #define RK3568_PLL_HPLL 2 381 382 #define RK3568_CLK_RTC_32K 5 383 #define RK3568_CLK_I2C0 7 384 #define RK3568_CLK_RTC32K_FRAC 8 385 #define RK3568_SCLK_UART0 11 386 #define RK3568_CLK_USBPHY0_REF 19 387 #define RK3568_CLK_USBPHY1_REF 21 388 #define RK3568_CLK_PCIEPHY0_DIV 29 389 #define RK3568_CLK_PCIEPHY0_OSC0 30 390 #define RK3568_CLK_PCIEPHY0_REF 31 391 #define RK3568_CLK_PCIEPHY1_DIV 32 392 #define RK3568_CLK_PCIEPHY1_OSC0 33 393 #define RK3568_CLK_PCIEPHY1_REF 34 394 #define RK3568_CLK_PCIEPHY2_DIV 35 395 #define RK3568_CLK_PCIEPHY2_OSC0 36 396 #define RK3568_CLK_PCIEPHY2_REF 37 397 #define RK3568_CLK_PCIE30PHY_REF_M 38 398 #define RK3568_CLK_PCIE30PHY_REF_N 39 399 #define RK3568_PCLK_I2C0 45 400 #define RK3568_CLK_PDPMU 49 401 402 #define RK3568_PPLL_PH0 1021 403 404 /* 405 * RK3588 clocks. 406 */ 407 #define RK3588_PLL_AUPLL 4 408 #define RK3588_PLL_CPLL 5 409 #define RK3588_PLL_GPLL 6 410 #define RK3588_PLL_NPLL 7 411 #define RK3588_PLL_PPLL 8 412 413 #define RK3588_CLK_PWM1 76 414 #define RK3588_CLK_PWM2 79 415 #define RK3588_CLK_PWM3 82 416 #define RK3588_ACLK_BUS_ROOT 113 417 #define RK3588_CLK_I2C1 131 418 #define RK3588_CLK_I2C2 132 419 #define RK3588_CLK_I2C3 133 420 #define RK3588_CLK_I2C4 134 421 #define RK3588_CLK_I2C5 135 422 #define RK3588_CLK_I2C6 136 423 #define RK3588_CLK_I2C7 137 424 #define RK3588_CLK_I2C8 138 425 #define RK3588_CLK_SPI0 151 426 #define RK3588_CLK_SPI1 152 427 #define RK3588_CLK_SPI2 153 428 #define RK3588_CLK_SPI3 154 429 #define RK3588_CLK_SPI4 155 430 #define RK3588_CLK_TSADC 158 431 #define RK3588_CLK_UART1_SRC 168 432 #define RK3588_CLK_UART1_FRAC 169 433 #define RK3588_CLK_UART1 170 434 #define RK3588_SCLK_UART1 171 435 #define RK3588_CLK_UART2_SRC 172 436 #define RK3588_CLK_UART2_FRAC 173 437 #define RK3588_CLK_UART2 174 438 #define RK3588_SCLK_UART2 175 439 #define RK3588_CLK_UART3_SRC 176 440 #define RK3588_CLK_UART3_FRAC 177 441 #define RK3588_CLK_UART3 178 442 #define RK3588_SCLK_UART3 179 443 #define RK3588_CLK_UART4_SRC 180 444 #define RK3588_CLK_UART4_FRAC 181 445 #define RK3588_CLK_UART4 182 446 #define RK3588_SCLK_UART4 183 447 #define RK3588_CLK_UART5_SRC 184 448 #define RK3588_CLK_UART5_FRAC 185 449 #define RK3588_CLK_UART5 186 450 #define RK3588_SCLK_UART5 187 451 #define RK3588_CLK_UART6_SRC 188 452 #define RK3588_CLK_UART6_FRAC 189 453 #define RK3588_CLK_UART6 190 454 #define RK3588_SCLK_UART6 191 455 #define RK3588_CLK_UART7_SRC 192 456 #define RK3588_CLK_UART7_FRAC 193 457 #define RK3588_CLK_UART7 194 458 #define RK3588_SCLK_UART7 195 459 #define RK3588_CLK_UART8_SRC 196 460 #define RK3588_CLK_UART8_FRAC 197 461 #define RK3588_CLK_UART8 198 462 #define RK3588_SCLK_UART8 199 463 #define RK3588_CLK_UART9_SRC 200 464 #define RK3588_CLK_UART9_FRAC 201 465 #define RK3588_CLK_UART9 202 466 #define RK3588_SCLK_UART9 203 467 #define RK3588_ACLK_CENTER_ROOT 204 468 #define RK3588_ACLK_CENTER_LOW_ROOT 205 469 #define RK3588_HCLK_CENTER_ROOT 206 470 #define RK3588_CLK_50M_SRC 222 471 #define RK3588_CLK_100M_SRC 223 472 #define RK3588_CLK_150M_SRC 224 473 #define RK3588_CLK_200M_SRC 225 474 #define RK3588_CLK_250M_SRC 226 475 #define RK3588_CLK_400M_SRC 229 476 #define RK3588_CLK_500M_SRC 231 477 #define RK3588_CLK_700M_SRC 234 478 #define RK3588_ACLK_TOP_ROOT 256 479 #define RK3588_PCLK_TOP_ROOT 257 480 #define RK3588_ACLK_LOW_TOP_ROOT 258 481 #define RK3588_CLK_GPU_SRC 261 482 #define RK3588_CLK_GPU 262 483 #define RK3588_HCLK_EMMC 298 484 #define RK3588_ACLK_EMMC 299 485 #define RK3588_CCLK_EMMC 300 486 #define RK3588_BCLK_EMMC 301 487 #define RK3588_TMCLK_EMMC 302 488 #define RK3588_CLK_GMAC_125M 310 489 #define RK3588_CCLK_SRC_SDIO 395 490 #define RK3588_ACLK_VOP_ROOT 600 491 #define RK3588_ACLK_VOP 605 492 #define RK3588_ACLK_VOP_SUB_SRC 619 493 #define RK3588_CLK_I2C0 628 494 #define RK3588_CLK_PMU1_50M_SRC 639 495 #define RK3588_CLK_PMU1_100M_SRC 640 496 #define RK3588_CLK_PMU1_200M_SRC 641 497 #define RK3588_CLK_PMU1_400M_SRC 643 498 #define RK3588_PCLK_PMU1_ROOT 645 499 #define RK3588_PCLK_PMU0_ROOT 646 500 #define RK3588_HCLK_PMU_CM0_ROOT 647 501 #define RK3588_CLK_PMU1PWM 658 502 #define RK3588_CLK_UART0_SRC 664 503 #define RK3588_CLK_UART0_FRAC 665 504 #define RK3588_CLK_UART0 666 505 #define RK3588_SCLK_UART0 667 506 #define RK3588_CLK_REF_PIPE_PHY0_OSC_SRC 674 507 #define RK3588_CLK_REF_PIPE_PHY1_OSC_SRC 675 508 #define RK3588_CLK_REF_PIPE_PHY2_OSC_SRC 676 509 #define RK3588_CLK_REF_PIPE_PHY0_PLL_SRC 677 510 #define RK3588_CLK_REF_PIPE_PHY1_PLL_SRC 678 511 #define RK3588_CLK_REF_PIPE_PHY2_PLL_SRC 679 512 #define RK3588_CLK_REF_PIPE_PHY0 680 513 #define RK3588_CLK_REF_PIPE_PHY1 681 514 #define RK3588_CLK_REF_PIPE_PHY2 682 515 516 #define RK3588_PLL_SPLL 1022 517 #define RK3588_XIN24M 1023 518 519 #define RK3588_SRST_P_TSADC 86 520 #define RK3588_SRST_TSADC 87 521 #define RK3588_SRST_H_EMMC 278 522 #define RK3588_SRST_A_EMMC 279 523 #define RK3588_SRST_C_EMMC 280 524 #define RK3588_SRST_B_EMMC 281 525 #define RK3588_SRST_T_EMMC 282 526 #define RK3588_SRST_A_GMAC0 291 527 #define RK3588_SRST_A_GMAC1 292 528 #define RK3588_SRST_PCIE0_POWER_UP 294 529 #define RK3588_SRST_PCIE1_POWER_UP 295 530 #define RK3588_SRST_PCIE2_POWER_UP 296 531 #define RK3588_SRST_PCIE3_POWER_UP 297 532 #define RK3588_SRST_PCIE4_POWER_UP 298 533 #define RK3588_SRST_P_PCIE0 299 534 #define RK3588_SRST_P_PCIE1 300 535 #define RK3588_SRST_P_PCIE2 301 536 #define RK3588_SRST_P_PCIE3 302 537 #define RK3588_SRST_P_PCIE4 303 538 #define RK3588_SRST_A_USB3OTG2 308 539 #define RK3588_SRST_A_USB3OTG0 338 540 #define RK3588_SRST_A_USB3OTG1 339 541 #define RK3588_SRST_REF_PIPE_PHY0 572 542 #define RK3588_SRST_REF_PIPE_PHY1 573 543 #define RK3588_SRST_REF_PIPE_PHY2 574 544 #define RK3588_SRST_P_PCIE2_PHY0 579 545 #define RK3588_SRST_P_PCIE2_PHY1 580 546 #define RK3588_SRST_P_PCIE2_PHY2 581 547 #define RK3588_SRST_PCIE30_PHY 584 548