1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/bus.h>
30 #include <sys/kernel.h>
31 #include <sys/module.h>
32 #include <sys/mutex.h>
33 #include <sys/rman.h>
34 #include <machine/bus.h>
35
36 #include <dev/ofw/ofw_bus.h>
37 #include <dev/ofw/ofw_bus_subr.h>
38
39 #include <dev/iicbus/iiconf.h>
40 #include <dev/iicbus/iicbus.h>
41
42 #include <dev/clk/clk.h>
43
44 #include "iicbus_if.h"
45
46 #define RK_I2C_CON 0x00
47 #define RK_I2C_CON_EN (1 << 0)
48 #define RK_I2C_CON_MODE_SHIFT 1
49 #define RK_I2C_CON_MODE_TX 0
50 #define RK_I2C_CON_MODE_RRX 1
51 #define RK_I2C_CON_MODE_RX 2
52 #define RK_I2C_CON_MODE_RTX 3
53 #define RK_I2C_CON_MODE_MASK 0x6
54 #define RK_I2C_CON_START (1 << 3)
55 #define RK_I2C_CON_STOP (1 << 4)
56 #define RK_I2C_CON_LASTACK (1 << 5)
57 #define RK_I2C_CON_NAKSTOP (1 << 6)
58 #define RK_I2C_CON_CTRL_MASK 0xFF
59
60 #define RK_I2C_CLKDIV 0x04
61 #define RK_I2C_CLKDIVL_MASK 0xFFFF
62 #define RK_I2C_CLKDIVL_SHIFT 0
63 #define RK_I2C_CLKDIVH_MASK 0xFFFF0000
64 #define RK_I2C_CLKDIVH_SHIFT 16
65 #define RK_I2C_CLKDIV_MUL 8
66
67 #define RK_I2C_MRXADDR 0x08
68 #define RK_I2C_MRXADDR_SADDR_MASK 0xFFFFFF
69 #define RK_I2C_MRXADDR_VALID(x) (1 << (24 + x))
70
71 #define RK_I2C_MRXRADDR 0x0C
72 #define RK_I2C_MRXRADDR_SRADDR_MASK 0xFFFFFF
73 #define RK_I2C_MRXRADDR_VALID(x) (1 << (24 + x))
74
75 #define RK_I2C_MTXCNT 0x10
76 #define RK_I2C_MTXCNT_MASK 0x3F
77
78 #define RK_I2C_MRXCNT 0x14
79 #define RK_I2C_MRXCNT_MASK 0x3F
80
81 #define RK_I2C_IEN 0x18
82 #define RK_I2C_IEN_BTFIEN (1 << 0)
83 #define RK_I2C_IEN_BRFIEN (1 << 1)
84 #define RK_I2C_IEN_MBTFIEN (1 << 2)
85 #define RK_I2C_IEN_MBRFIEN (1 << 3)
86 #define RK_I2C_IEN_STARTIEN (1 << 4)
87 #define RK_I2C_IEN_STOPIEN (1 << 5)
88 #define RK_I2C_IEN_NAKRCVIEN (1 << 6)
89 #define RK_I2C_IEN_ALL (RK_I2C_IEN_MBTFIEN | RK_I2C_IEN_MBRFIEN | \
90 RK_I2C_IEN_STARTIEN | RK_I2C_IEN_STOPIEN | RK_I2C_IEN_NAKRCVIEN)
91
92 #define RK_I2C_IPD 0x1C
93 #define RK_I2C_IPD_BTFIPD (1 << 0)
94 #define RK_I2C_IPD_BRFIPD (1 << 1)
95 #define RK_I2C_IPD_MBTFIPD (1 << 2)
96 #define RK_I2C_IPD_MBRFIPD (1 << 3)
97 #define RK_I2C_IPD_STARTIPD (1 << 4)
98 #define RK_I2C_IPD_STOPIPD (1 << 5)
99 #define RK_I2C_IPD_NAKRCVIPD (1 << 6)
100 #define RK_I2C_IPD_ALL (RK_I2C_IPD_MBTFIPD | RK_I2C_IPD_MBRFIPD | \
101 RK_I2C_IPD_STARTIPD | RK_I2C_IPD_STOPIPD | RK_I2C_IPD_NAKRCVIPD)
102
103 #define RK_I2C_FNCT 0x20
104 #define RK_I2C_FNCT_MASK 0x3F
105
106 #define RK_I2C_TXDATA_BASE 0x100
107
108 #define RK_I2C_RXDATA_BASE 0x200
109
110 /* 8 data registers, 4 bytes each. */
111 #define RK_I2C_MAX_RXTX_LEN 32
112
113 enum rk_i2c_state {
114 STATE_IDLE = 0,
115 STATE_START,
116 STATE_READ,
117 STATE_WRITE,
118 STATE_STOP
119 };
120
121 struct rk_i2c_softc {
122 device_t dev;
123 struct resource *res[2];
124 struct mtx mtx;
125 clk_t sclk;
126 clk_t pclk;
127 int busy;
128 void * intrhand;
129 uint32_t intr;
130 uint32_t ipd;
131 struct iic_msg *msg;
132 size_t cnt;
133 bool transfer_done;
134 bool nak_recv;
135 bool tx_slave_addr;
136 uint8_t mode;
137 uint8_t state;
138
139 device_t iicbus;
140 };
141
142 static struct ofw_compat_data compat_data[] = {
143 {"rockchip,rk3288-i2c", 1},
144 {"rockchip,rk3328-i2c", 1},
145 {"rockchip,rk3399-i2c", 1},
146 {NULL, 0}
147 };
148
149 static struct resource_spec rk_i2c_spec[] = {
150 { SYS_RES_MEMORY, 0, RF_ACTIVE },
151 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
152 { -1, 0 }
153 };
154
155 static int rk_i2c_probe(device_t dev);
156 static int rk_i2c_attach(device_t dev);
157 static int rk_i2c_detach(device_t dev);
158
159 #define RK_I2C_LOCK(sc) mtx_lock(&(sc)->mtx)
160 #define RK_I2C_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
161 #define RK_I2C_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
162 #define RK_I2C_READ(sc, reg) bus_read_4((sc)->res[0], (reg))
163 #define RK_I2C_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
164
165 static uint32_t
rk_i2c_get_clkdiv(struct rk_i2c_softc * sc,uint32_t speed)166 rk_i2c_get_clkdiv(struct rk_i2c_softc *sc, uint32_t speed)
167 {
168 uint64_t sclk_freq;
169 uint32_t clkdiv;
170 int err;
171
172 err = clk_get_freq(sc->sclk, &sclk_freq);
173 if (err != 0)
174 return (err);
175
176 clkdiv = (sclk_freq / speed / RK_I2C_CLKDIV_MUL / 2) - 1;
177 clkdiv &= RK_I2C_CLKDIVL_MASK;
178
179 clkdiv = clkdiv << RK_I2C_CLKDIVH_SHIFT | clkdiv;
180
181 return (clkdiv);
182 }
183
184 static int
rk_i2c_reset(device_t dev,u_char speed,u_char addr,u_char * oldaddr)185 rk_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
186 {
187 struct rk_i2c_softc *sc;
188 uint32_t clkdiv;
189 u_int busfreq;
190
191 sc = device_get_softc(dev);
192
193 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
194
195 clkdiv = rk_i2c_get_clkdiv(sc, busfreq);
196
197 RK_I2C_LOCK(sc);
198
199 /* Set the clock divider */
200 RK_I2C_WRITE(sc, RK_I2C_CLKDIV, clkdiv);
201
202 /* Disable the module */
203 RK_I2C_WRITE(sc, RK_I2C_CON, 0);
204
205 RK_I2C_UNLOCK(sc);
206
207 return (0);
208 }
209
210 static uint8_t
rk_i2c_fill_tx(struct rk_i2c_softc * sc)211 rk_i2c_fill_tx(struct rk_i2c_softc *sc)
212 {
213 uint32_t buf32;
214 uint8_t buf;
215 int i, j, len;
216
217 len = sc->msg->len - sc->cnt;
218 if (sc->tx_slave_addr) {
219 KASSERT(sc->cnt == 0, ("tx_slave_addr in the middle of data"));
220 len++;
221 }
222
223 if (len > RK_I2C_MAX_RXTX_LEN)
224 len = RK_I2C_MAX_RXTX_LEN;
225
226 for (i = 0; i < len; ) {
227 buf32 = 0;
228
229 /* Process next 4 bytes or whatever remains. */
230 for (j = 0; j < MIN(len - i, 4); j++) {
231 /* Fill the addr if needed */
232 if (sc->tx_slave_addr) {
233 buf = sc->msg->slave;
234 sc->tx_slave_addr = false;
235 } else {
236 KASSERT(sc->cnt < sc->msg->len,
237 ("%s: data buffer overrun", __func__));
238 buf = sc->msg->buf[sc->cnt];
239 sc->cnt++;
240 }
241 buf32 |= (uint32_t)buf << (j * 8);
242 }
243
244 KASSERT(i % 4 == 0, ("%s: misaligned write offset", __func__));
245 RK_I2C_WRITE(sc, RK_I2C_TXDATA_BASE + i, buf32);
246
247 i += j;
248 }
249
250 return (len);
251 }
252
253 static void
rk_i2c_drain_rx(struct rk_i2c_softc * sc)254 rk_i2c_drain_rx(struct rk_i2c_softc *sc)
255 {
256 uint32_t buf32 = 0;
257 uint8_t buf8;
258 int len;
259 int i;
260
261 if (sc->msg == NULL) {
262 device_printf(sc->dev, "No current iic msg\n");
263 return;
264 }
265
266 len = sc->msg->len - sc->cnt;
267 if (len > RK_I2C_MAX_RXTX_LEN)
268 len = RK_I2C_MAX_RXTX_LEN;
269
270 for (i = 0; i < len; i++) {
271 if (i % 4 == 0)
272 buf32 = RK_I2C_READ(sc, RK_I2C_RXDATA_BASE + i);
273
274 buf8 = (buf32 >> ((i % 4) * 8)) & 0xFF;
275 sc->msg->buf[sc->cnt++] = buf8;
276 }
277 }
278
279 static void
rk_i2c_send_stop(struct rk_i2c_softc * sc)280 rk_i2c_send_stop(struct rk_i2c_softc *sc)
281 {
282 uint32_t reg;
283
284 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STOPIEN);
285
286 sc->state = STATE_STOP;
287
288 reg = RK_I2C_READ(sc, RK_I2C_CON);
289 reg |= RK_I2C_CON_STOP;
290 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
291 }
292
293 static void
rk_i2c_intr_locked(struct rk_i2c_softc * sc)294 rk_i2c_intr_locked(struct rk_i2c_softc *sc)
295 {
296 uint32_t reg;
297 int transfer_len;
298
299 sc->ipd = RK_I2C_READ(sc, RK_I2C_IPD);
300
301 /* Something to handle? */
302 if ((sc->ipd & RK_I2C_IPD_ALL) == 0)
303 return;
304
305 RK_I2C_WRITE(sc, RK_I2C_IPD, sc->ipd);
306 sc->ipd &= RK_I2C_IPD_ALL;
307
308 if (sc->ipd & RK_I2C_IPD_NAKRCVIPD) {
309 /* NACK received */
310 sc->ipd &= ~RK_I2C_IPD_NAKRCVIPD;
311 sc->nak_recv = true;
312 /* XXXX last byte !!!, signal error !!! */
313 sc->transfer_done = true;
314 sc->state = STATE_IDLE;
315 goto err;
316 }
317
318 switch (sc->state) {
319 case STATE_START:
320 /* Disable start bit */
321 reg = RK_I2C_READ(sc, RK_I2C_CON);
322 reg &= ~RK_I2C_CON_START;
323 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
324
325 if (sc->mode == RK_I2C_CON_MODE_RRX ||
326 sc->mode == RK_I2C_CON_MODE_RX) {
327 sc->state = STATE_READ;
328 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN |
329 RK_I2C_IEN_NAKRCVIEN);
330
331 if ((sc->msg->len - sc->cnt) > 32)
332 transfer_len = 32;
333 else {
334 transfer_len = sc->msg->len - sc->cnt;
335 reg = RK_I2C_READ(sc, RK_I2C_CON);
336 reg |= RK_I2C_CON_LASTACK;
337 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
338 }
339
340 RK_I2C_WRITE(sc, RK_I2C_MRXCNT, transfer_len);
341 } else {
342 sc->state = STATE_WRITE;
343 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN |
344 RK_I2C_IEN_NAKRCVIEN);
345
346 transfer_len = rk_i2c_fill_tx(sc);
347 RK_I2C_WRITE(sc, RK_I2C_MTXCNT, transfer_len);
348 }
349 break;
350 case STATE_READ:
351 rk_i2c_drain_rx(sc);
352
353 if (sc->cnt == sc->msg->len)
354 rk_i2c_send_stop(sc);
355 else {
356 sc->mode = RK_I2C_CON_MODE_RX;
357 reg = RK_I2C_READ(sc, RK_I2C_CON) & \
358 ~RK_I2C_CON_CTRL_MASK;
359 reg |= sc->mode << RK_I2C_CON_MODE_SHIFT;
360 reg |= RK_I2C_CON_EN;
361
362 if ((sc->msg->len - sc->cnt) > 32)
363 transfer_len = 32;
364 else {
365 transfer_len = sc->msg->len - sc->cnt;
366 reg |= RK_I2C_CON_LASTACK;
367 }
368
369 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
370 RK_I2C_WRITE(sc, RK_I2C_MRXCNT, transfer_len);
371 }
372
373 break;
374 case STATE_WRITE:
375 if (sc->cnt < sc->msg->len) {
376 /* Keep writing. */
377 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN |
378 RK_I2C_IEN_NAKRCVIEN);
379 transfer_len = rk_i2c_fill_tx(sc);
380 RK_I2C_WRITE(sc, RK_I2C_MTXCNT, transfer_len);
381 break;
382 } else if (!(sc->msg->flags & IIC_M_NOSTOP)) {
383 rk_i2c_send_stop(sc);
384 break;
385 }
386 /* passthru */
387 case STATE_STOP:
388 /* Disable stop bit */
389 reg = RK_I2C_READ(sc, RK_I2C_CON);
390 reg &= ~RK_I2C_CON_STOP;
391 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
392
393 sc->transfer_done = 1;
394 sc->state = STATE_IDLE;
395 break;
396 case STATE_IDLE:
397 break;
398 }
399
400 err:
401 wakeup(sc);
402 }
403
404 static void
rk_i2c_intr(void * arg)405 rk_i2c_intr(void *arg)
406 {
407 struct rk_i2c_softc *sc;
408
409 sc = (struct rk_i2c_softc *)arg;
410
411 RK_I2C_LOCK(sc);
412 rk_i2c_intr_locked(sc);
413 RK_I2C_UNLOCK(sc);
414 }
415
416 static void
rk_i2c_start_xfer(struct rk_i2c_softc * sc,struct iic_msg * msg,boolean_t last)417 rk_i2c_start_xfer(struct rk_i2c_softc *sc, struct iic_msg *msg, boolean_t last)
418 {
419 uint32_t reg;
420 uint8_t len;
421
422 sc->transfer_done = false;
423 sc->nak_recv = false;
424 sc->tx_slave_addr = false;
425 sc->cnt = 0;
426 sc->state = STATE_IDLE;
427 sc->msg = msg;
428
429 reg = RK_I2C_READ(sc, RK_I2C_CON) & ~RK_I2C_CON_CTRL_MASK;
430 if (!(sc->msg->flags & IIC_M_NOSTART)) {
431 /* Stadard message */
432 if (sc->mode == RK_I2C_CON_MODE_TX) {
433 sc->tx_slave_addr = true;
434 }
435 sc->state = STATE_START;
436 reg |= RK_I2C_CON_START;
437
438 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STARTIEN);
439 } else {
440 /* Continuation message */
441 if (sc->mode == RK_I2C_CON_MODE_RX) {
442 sc->state = STATE_READ;
443 if (last)
444 reg |= RK_I2C_CON_LASTACK;
445
446 RK_I2C_WRITE(sc, RK_I2C_MRXCNT, sc->msg->len);
447 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN |
448 RK_I2C_IEN_NAKRCVIEN);
449 } else {
450 sc->state = STATE_WRITE;
451 len = rk_i2c_fill_tx(sc);
452
453 RK_I2C_WRITE(sc, RK_I2C_MTXCNT, len);
454
455 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN |
456 RK_I2C_IEN_NAKRCVIEN);
457 }
458 }
459 reg |= RK_I2C_CON_NAKSTOP;
460 reg |= sc->mode << RK_I2C_CON_MODE_SHIFT;
461 reg |= RK_I2C_CON_EN;
462 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
463 }
464
465 static int
rk_i2c_transfer(device_t dev,struct iic_msg * msgs,uint32_t nmsgs)466 rk_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
467 {
468 struct rk_i2c_softc *sc;
469 uint32_t reg;
470 bool last_msg;
471 int i, j, timeout, err;
472
473 sc = device_get_softc(dev);
474
475 RK_I2C_LOCK(sc);
476
477 while (sc->busy)
478 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0);
479 sc->busy = 1;
480
481 /* Disable the module and interrupts */
482 RK_I2C_WRITE(sc, RK_I2C_CON, 0);
483 RK_I2C_WRITE(sc, RK_I2C_IEN, 0);
484
485 /* Clean stale interrupts */
486 RK_I2C_WRITE(sc, RK_I2C_IPD, RK_I2C_IPD_ALL);
487
488 err = 0;
489 for (i = 0; i < nmsgs; i++) {
490 /* Validate parameters. */
491 if (msgs == NULL || msgs[i].buf == NULL ||
492 msgs[i].len == 0) {
493 err = IIC_ENOTSUPP;
494 break;
495 }
496 /*
497 * If next message have NOSTART flag, then they both
498 * should be same type (read/write) and same address.
499 */
500 if (i < nmsgs - 1) {
501 if ((msgs[i + 1].flags & IIC_M_NOSTART) &&
502 ((msgs[i].flags & IIC_M_RD) !=
503 (msgs[i + 1].flags & IIC_M_RD) ||
504 (msgs[i].slave != msgs[i + 1].slave))) {
505 err = IIC_ENOTSUPP;
506 break;
507 }
508 }
509 /*
510 * Detect simple register read case.
511 * The first message should be IIC_M_WR | IIC_M_NOSTOP,
512 * next pure IIC_M_RD (no other flags allowed). Both
513 * messages should have same slave address.
514 */
515
516 if (nmsgs - i >= 2 && msgs[i].len < 4 &&
517 msgs[i].flags == (IIC_M_WR | IIC_M_NOSTOP) &&
518 msgs[i + 1].flags == IIC_M_RD &&
519 (msgs[i].slave & ~LSB) == (msgs[i + 1].slave & ~LSB)) {
520 sc->mode = RK_I2C_CON_MODE_RRX;
521
522 /* Write slave address */
523 reg = msgs[i].slave & ~LSB;
524 reg |= RK_I2C_MRXADDR_VALID(0);
525 RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg);
526
527 /* Write slave register address */
528 reg = 0;
529 for (j = 0; j < msgs[i].len ; j++) {
530 reg |= (uint32_t)msgs[i].buf[j] << (j * 8);
531 reg |= RK_I2C_MRXADDR_VALID(j);
532 }
533 RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, reg);
534
535 i++;
536 } else {
537 if (msgs[i].flags & IIC_M_RD) {
538 if (msgs[i].flags & IIC_M_NOSTART) {
539 sc->mode = RK_I2C_CON_MODE_RX;
540 } else {
541 sc->mode = RK_I2C_CON_MODE_RRX;
542 reg = msgs[i].slave & ~LSB;
543 reg |= RK_I2C_MRXADDR_VALID(0);
544 RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg);
545 RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, 0);
546 }
547 } else {
548 sc->mode = RK_I2C_CON_MODE_TX;
549 }
550 }
551 /* last message ? */
552 last_msg = (i >= nmsgs - 1) ||
553 !(msgs[i + 1].flags & IIC_M_NOSTART);
554 rk_i2c_start_xfer(sc, msgs + i, last_msg);
555
556 if (cold) {
557 for(timeout = 10000; timeout > 0; timeout--) {
558 rk_i2c_intr_locked(sc);
559 if (sc->transfer_done)
560 break;
561 DELAY(1000);
562 }
563 if (timeout <= 0)
564 err = IIC_ETIMEOUT;
565 } else {
566 while (err == 0 && !sc->transfer_done) {
567 err = msleep(sc, &sc->mtx, PZERO, "rk_i2c",
568 10 * hz);
569 }
570 }
571 }
572
573 /* Disable the module and interrupts */
574 RK_I2C_WRITE(sc, RK_I2C_CON, 0);
575 RK_I2C_WRITE(sc, RK_I2C_IEN, 0);
576
577 sc->busy = 0;
578
579 if (sc->nak_recv)
580 err = IIC_ENOACK;
581
582 RK_I2C_UNLOCK(sc);
583 return (err);
584 }
585
586 static int
rk_i2c_probe(device_t dev)587 rk_i2c_probe(device_t dev)
588 {
589
590 if (!ofw_bus_status_okay(dev))
591 return (ENXIO);
592 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
593 return (ENXIO);
594
595 device_set_desc(dev, "RockChip I2C");
596 return (BUS_PROBE_DEFAULT);
597 }
598
599 static int
rk_i2c_attach(device_t dev)600 rk_i2c_attach(device_t dev)
601 {
602 struct rk_i2c_softc *sc;
603 int error;
604
605 sc = device_get_softc(dev);
606 sc->dev = dev;
607
608 mtx_init(&sc->mtx, device_get_nameunit(dev), "rk_i2c", MTX_DEF);
609
610 if (bus_alloc_resources(dev, rk_i2c_spec, sc->res) != 0) {
611 device_printf(dev, "cannot allocate resources for device\n");
612 error = ENXIO;
613 goto fail;
614 }
615
616 if (bus_setup_intr(dev, sc->res[1],
617 INTR_TYPE_MISC | INTR_MPSAFE, NULL, rk_i2c_intr, sc,
618 &sc->intrhand)) {
619 bus_release_resources(dev, rk_i2c_spec, sc->res);
620 device_printf(dev, "cannot setup interrupt handler\n");
621 return (ENXIO);
622 }
623
624 clk_set_assigned(dev, ofw_bus_get_node(dev));
625
626 /* Activate the module clocks. */
627 error = clk_get_by_ofw_name(dev, 0, "i2c", &sc->sclk);
628 if (error != 0) {
629 device_printf(dev, "cannot get i2c clock\n");
630 goto fail;
631 }
632 error = clk_enable(sc->sclk);
633 if (error != 0) {
634 device_printf(dev, "cannot enable i2c clock\n");
635 goto fail;
636 }
637 /* pclk clock is optional. */
638 error = clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk);
639 if (error != 0 && error != ENOENT) {
640 device_printf(dev, "cannot get pclk clock\n");
641 goto fail;
642 }
643 if (sc->pclk != NULL) {
644 error = clk_enable(sc->pclk);
645 if (error != 0) {
646 device_printf(dev, "cannot enable pclk clock\n");
647 goto fail;
648 }
649 }
650
651 sc->iicbus = device_add_child(dev, "iicbus", -1);
652 if (sc->iicbus == NULL) {
653 device_printf(dev, "cannot add iicbus child device\n");
654 error = ENXIO;
655 goto fail;
656 }
657
658 bus_generic_attach(dev);
659
660 return (0);
661
662 fail:
663 if (rk_i2c_detach(dev) != 0)
664 device_printf(dev, "Failed to detach\n");
665 return (error);
666 }
667
668 static int
rk_i2c_detach(device_t dev)669 rk_i2c_detach(device_t dev)
670 {
671 struct rk_i2c_softc *sc;
672 int error;
673
674 sc = device_get_softc(dev);
675
676 if ((error = bus_generic_detach(dev)) != 0)
677 return (error);
678
679 if (sc->iicbus != NULL)
680 if ((error = device_delete_child(dev, sc->iicbus)) != 0)
681 return (error);
682
683 if (sc->sclk != NULL)
684 clk_release(sc->sclk);
685 if (sc->pclk != NULL)
686 clk_release(sc->pclk);
687
688 if (sc->intrhand != NULL)
689 bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand);
690
691 bus_release_resources(dev, rk_i2c_spec, sc->res);
692
693 mtx_destroy(&sc->mtx);
694
695 return (0);
696 }
697
698 static phandle_t
rk_i2c_get_node(device_t bus,device_t dev)699 rk_i2c_get_node(device_t bus, device_t dev)
700 {
701
702 return ofw_bus_get_node(bus);
703 }
704
705 static device_method_t rk_i2c_methods[] = {
706 DEVMETHOD(device_probe, rk_i2c_probe),
707 DEVMETHOD(device_attach, rk_i2c_attach),
708 DEVMETHOD(device_detach, rk_i2c_detach),
709
710 /* OFW methods */
711 DEVMETHOD(ofw_bus_get_node, rk_i2c_get_node),
712
713 DEVMETHOD(iicbus_callback, iicbus_null_callback),
714 DEVMETHOD(iicbus_reset, rk_i2c_reset),
715 DEVMETHOD(iicbus_transfer, rk_i2c_transfer),
716
717 DEVMETHOD_END
718 };
719
720 static driver_t rk_i2c_driver = {
721 "rk_i2c",
722 rk_i2c_methods,
723 sizeof(struct rk_i2c_softc),
724 };
725
726 EARLY_DRIVER_MODULE(rk_i2c, simplebus, rk_i2c_driver, 0, 0,
727 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
728 EARLY_DRIVER_MODULE(ofw_iicbus, rk_i2c, ofw_iicbus_driver,
729 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
730 MODULE_DEPEND(rk_i2c, iicbus, 1, 1, 1);
731 MODULE_VERSION(rk_i2c, 1);
732