1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/alc/if_alcreg.h,v 1.1 2009/06/10 02:07:58 yongari Exp $ 28 */ 29 30 #ifndef _IF_ALCREG_H 31 #define _IF_ALCREG_H 32 33 /* 34 * Atheros Communucations, Inc. PCI vendor ID 35 */ 36 #define VENDORID_ATHEROS 0x1969 37 38 /* 39 * Atheros AR813x/AR815x device ID 40 */ 41 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */ 42 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */ 43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */ 44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */ 45 #define DEVICEID_ATHEROS_AR8162 0x1090 46 #define DEVICEID_ATHEROS_AR8161 0x1091 47 #define DEVICEID_ATHEROS_AR8172 0x10A0 48 #define DEVICEID_ATHEROS_AR8171 0x10A1 49 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */ 50 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */ 51 #define DEVICEID_ATHEROS_E2200 0xE091 52 #define DEVICEID_ATHEROS_E2400 0xE0A1 53 #define DEVICEID_ATHEROS_E2500 0xE0B1 54 55 #define ATHEROS_AR8152_B_V10 0xC0 56 #define ATHEROS_AR8152_B_V11 0xC1 57 58 /* 59 * Atheros AR816x/AR817x revisions 60 */ 61 #define AR816X_REV_A0 0 62 #define AR816X_REV_A1 1 63 #define AR816X_REV_B0 2 64 #define AR816X_REV_C0 3 65 66 #define AR816X_REV_SHIFT 3 67 #define AR816X_REV(x) ((x) >> AR816X_REV_SHIFT) 68 69 /* 70 * From FreeBSD dev/pci/pcireg.h 71 * 72 * PCIM_xxx: mask to locate subfield in register 73 * PCIR_xxx: config register offset 74 */ 75 #define PCIR_EXPRESS_DEVICE_CTL 0x8 76 #define PCIR_EXPRESS_LINK_CAP 0xc 77 #define PCIR_EXPRESS_LINK_CTL 0x10 78 #define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000 79 #define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0 80 #define PCIM_LINK_CAP_ASPM 0x00000c00 81 82 /* 0x0000 - 0x02FF : PCIe configuration space */ 83 84 #define ALC_PEX_UNC_ERR_SEV 0x10C 85 #define PEX_UNC_ERR_SEV_TRN 0x00000001 86 #define PEX_UNC_ERR_SEV_DLP 0x00000010 87 #define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000 88 #define PEX_UNC_ERR_SEV_FCP 0x00002000 89 #define PEX_UNC_ERR_SEV_CPL_TO 0x00004000 90 #define PEX_UNC_ERR_SEV_CA 0x00008000 91 #define PEX_UNC_ERR_SEV_UC 0x00010000 92 #define PEX_UNC_ERR_SEV_ROV 0x00020000 93 #define PEX_UNC_ERR_SEV_MLFP 0x00040000 94 #define PEX_UNC_ERR_SEV_ECRC 0x00080000 95 #define PEX_UNC_ERR_SEV_UR 0x00100000 96 97 #define ALC_EEPROM_LD 0x204 /* AR816x */ 98 #define EEPROM_LD_START 0x00000001 99 #define EEPROM_LD_IDLE 0x00000010 100 #define EEPROM_LD_DONE 0x00000000 101 #define EEPROM_LD_PROGRESS 0x00000020 102 #define EEPROM_LD_EXIST 0x00000100 103 #define EEPROM_LD_EEPROM_EXIST 0x00000200 104 #define EEPROM_LD_FLASH_EXIST 0x00000400 105 #define EEPROM_LD_FLASH_END_ADDR_MASK 0x03FF0000 106 #define EEPROM_LD_FLASH_END_ADDR_SHIFT 16 107 108 #define ALC_TWSI_CFG 0x218 109 #define TWSI_CFG_SW_LD_START 0x00000800 110 #define TWSI_CFG_HW_LD_START 0x00001000 111 #define TWSI_CFG_LD_EXIST 0x00400000 112 113 #define ALC_SLD 0x218 /* AR816x */ 114 #define SLD_START 0x00000800 115 #define SLD_PROGRESS 0x00001000 116 #define SLD_IDLE 0x00002000 117 #define SLD_SLVADDR_MASK 0x007F0000 118 #define SLD_EXIST 0x00800000 119 #define SLD_FREQ_MASK 0x03000000 120 #define SLD_FREQ_100K 0x00000000 121 #define SLD_FREQ_200K 0x01000000 122 #define SLD_FREQ_300K 0x02000000 123 #define SLD_FREQ_400K 0x03000000 124 125 #define ALC_PCIE_PHYMISC 0x1000 126 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 127 128 #define ALC_PCIE_PHYMISC2 0x1004 129 #define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000 130 #define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000 131 #define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16 132 #define PCIE_PHYMISC2_SERDES_TH_SHIFT 18 133 134 #define ALC_PDLL_TRNS1 0x1104 135 #define PDLL_TRNS1_D3PLLOFF_ENB 0x00000800 136 137 #define ALC_TWSI_DEBUG 0x1108 138 #define TWSI_DEBUG_DEV_EXIST 0x20000000 139 140 #define ALC_EEPROM_CFG 0x12C0 141 #define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF 142 #define EEPROM_CFG_ADDR_MASK 0x03FF0000 143 #define EEPROM_CFG_ACK 0x40000000 144 #define EEPROM_CFG_RW 0x80000000 145 #define EEPROM_CFG_DATA_HI_SHIFT 0 146 #define EEPROM_CFG_ADDR_SHIFT 16 147 148 #define ALC_EEPROM_DATA_LO 0x12C4 149 150 #define ALC_OPT_CFG 0x12F0 151 #define OPT_CFG_CLK_ENB 0x00000002 152 153 #define ALC_PM_CFG 0x12F8 154 #define PM_CFG_SERDES_ENB 0x00000001 155 #define PM_CFG_RBER_ENB 0x00000002 156 #define PM_CFG_CLK_REQ_ENB 0x00000004 157 #define PM_CFG_ASPM_L1_ENB 0x00000008 158 #define PM_CFG_SERDES_L1_ENB 0x00000010 159 #define PM_CFG_SERDES_PLL_L1_ENB 0x00000020 160 #define PM_CFG_SERDES_PD_EX_L1 0x00000040 161 #define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080 162 #define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00 163 #define PM_CFG_RX_L1_AFTER_L0S 0x00000800 164 #define PM_CFG_ASPM_L0S_ENB 0x00001000 165 #define PM_CFG_CLK_SWH_L1 0x00002000 166 #define PM_CFG_CLK_PWM_VER1_1 0x00004000 167 #define PM_CFG_PCIE_RECV 0x00008000 168 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000 169 #define PM_CFG_L1_ENTRY_TIMER_816X_MASK 0x00070000 170 #define PM_CFG_TX_L1_AFTER_L0S 0x00080000 171 #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000 172 #define PM_CFG_LCKDET_TIMER_MASK 0x0F000000 173 #define PM_CFG_EN_BUFS_RX_L0S 0x10000000 174 #define PM_CFG_SA_DLY_ENB 0x20000000 175 #define PM_CFG_MAC_ASPM_CHK 0x40000000 176 #define PM_CFG_HOTRST 0x80000000 177 #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8 178 #define PM_CFG_L1_ENTRY_TIMER_SHIFT 16 179 #define PM_CFG_PM_REQ_TIMER_SHIFT 20 180 #define PM_CFG_LCKDET_TIMER_SHIFT 24 181 182 #define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6 183 #define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1 184 #define PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT 4 185 #define PM_CFG_LCKDET_TIMER_DEFAULT 12 186 #define PM_CFG_PM_REQ_TIMER_DEFAULT 12 187 #define PM_CFG_PM_REQ_TIMER_816X_DEFAULT 15 188 189 #define ALC_LTSSM_ID_CFG 0x12FC 190 #define LTSSM_ID_WRO_ENB 0x00001000 191 192 #define ALC_MASTER_CFG 0x1400 193 #define MASTER_RESET 0x00000001 194 #define MASTER_TEST_MODE_MASK 0x0000000C 195 #define MASTER_BERT_START 0x00000010 196 #define MASTER_WAKEN_25M 0x00000020 197 #define MASTER_OOB_DIS_OFF 0x00000040 198 #define MASTER_SA_TIMER_ENB 0x00000080 199 #define MASTER_MTIMER_ENB 0x00000100 200 #define MASTER_MANUAL_INTR_ENB 0x00000200 201 #define MASTER_IM_TX_TIMER_ENB 0x00000400 202 #define MASTER_IM_RX_TIMER_ENB 0x00000800 203 #define MASTER_CLK_SEL_DIS 0x00001000 204 #define MASTER_CLK_SWH_MODE 0x00002000 205 #define MASTER_INTR_RD_CLR 0x00004000 206 #define MASTER_CHIP_REV_MASK 0x00FF0000 207 #define MASTER_CHIP_ID_MASK 0x7F000000 208 #define MASTER_OTP_SEL 0x80000000 209 #define MASTER_TEST_MODE_SHIFT 2 210 #define MASTER_CHIP_REV_SHIFT 16 211 #define MASTER_CHIP_ID_SHIFT 24 212 213 /* Number of ticks per usec for AR813x/AR815x. */ 214 #define ALC_TICK_USECS 2 215 #define ALC_USECS(x) ((x) / ALC_TICK_USECS) 216 217 #define ALC_MANUAL_TIMER 0x1404 218 219 #define ALC_IM_TIMER 0x1408 220 #define IM_TIMER_TX_MASK 0x0000FFFF 221 #define IM_TIMER_RX_MASK 0xFFFF0000 222 #define IM_TIMER_TX_SHIFT 0 223 #define IM_TIMER_RX_SHIFT 16 224 #define ALC_IM_TIMER_MIN 0 225 #define ALC_IM_TIMER_MAX 130000 /* 130ms */ 226 /* 227 * 100us will ensure alc(4) wouldn't generate more than 10000 Rx 228 * interrupts in a second. 229 */ 230 #define ALC_IM_RX_TIMER_DEFAULT 100 /* 100us */ 231 /* 232 * alc(4) does not rely on Tx completion interrupts, so set it 233 * somewhat large value to reduce Tx completion interrupts. 234 */ 235 #define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */ 236 237 #define ALC_GPHY_CFG 0x140C /* 16 bits, 32 bits on AR816x */ 238 #define GPHY_CFG_EXT_RESET 0x0001 239 #define GPHY_CFG_RTL_MODE 0x0002 240 #define GPHY_CFG_LED_MODE 0x0004 241 #define GPHY_CFG_ANEG_NOW 0x0008 242 #define GPHY_CFG_RECV_ANEG 0x0010 243 #define GPHY_CFG_GATE_25M_ENB 0x0020 244 #define GPHY_CFG_LPW_EXIT 0x0040 245 #define GPHY_CFG_PHY_IDDQ 0x0080 246 #define GPHY_CFG_PHY_IDDQ_DIS 0x0100 247 #define GPHY_CFG_PCLK_SEL_DIS 0x0200 248 #define GPHY_CFG_HIB_EN 0x0400 249 #define GPHY_CFG_HIB_PULSE 0x0800 250 #define GPHY_CFG_SEL_ANA_RESET 0x1000 251 #define GPHY_CFG_PHY_PLL_ON 0x2000 252 #define GPHY_CFG_PWDOWN_HW 0x4000 253 #define GPHY_CFG_PHY_PLL_BYPASS 0x8000 254 #define GPHY_CFG_100AB_ENB 0x00020000 255 256 #define ALC_IDLE_STATUS 0x1410 257 #define IDLE_STATUS_RXMAC 0x00000001 258 #define IDLE_STATUS_TXMAC 0x00000002 259 #define IDLE_STATUS_RXQ 0x00000004 260 #define IDLE_STATUS_TXQ 0x00000008 261 #define IDLE_STATUS_DMARD 0x00000010 262 #define IDLE_STATUS_DMAWR 0x00000020 263 #define IDLE_STATUS_SMB 0x00000040 264 #define IDLE_STATUS_CMB 0x00000080 265 266 #define ALC_MDIO 0x1414 267 #define MDIO_DATA_MASK 0x0000FFFF 268 #define MDIO_REG_ADDR_MASK 0x001F0000 269 #define MDIO_OP_READ 0x00200000 270 #define MDIO_OP_WRITE 0x00000000 271 #define MDIO_SUP_PREAMBLE 0x00400000 272 #define MDIO_OP_EXECUTE 0x00800000 273 #define MDIO_CLK_25_4 0x00000000 274 #define MDIO_CLK_25_6 0x02000000 275 #define MDIO_CLK_25_8 0x03000000 276 #define MDIO_CLK_25_10 0x04000000 277 #define MDIO_CLK_25_14 0x05000000 278 #define MDIO_CLK_25_20 0x06000000 279 #define MDIO_CLK_25_128 0x07000000 280 #define MDIO_OP_BUSY 0x08000000 281 #define MDIO_AP_ENB 0x10000000 282 #define MDIO_MODE_EXT 0x40000000 283 #define MDIO_DATA_SHIFT 0 284 #define MDIO_REG_ADDR_SHIFT 16 285 286 #define MDIO_REG_ADDR(x) \ 287 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 288 /* Default PHY address. */ 289 #define ALC_PHY_ADDR 0 290 291 #define ALC_PHY_STATUS 0x1418 292 #define PHY_STATUS_RECV_ENB 0x00000001 293 #define PHY_STATUS_GENERAL_MASK 0x0000FFFF 294 #define PHY_STATUS_OE_PWSP_MASK 0x07FF0000 295 #define PHY_STATUS_LPW_STATE 0x80000000 296 #define PHY_STATIS_OE_PWSP_SHIFT 16 297 298 /* Packet memory BIST. */ 299 #define ALC_BIST0 0x141C 300 #define BIST0_ENB 0x00000001 301 #define BIST0_SRAM_FAIL 0x00000002 302 #define BIST0_FUSE_FLAG 0x00000004 303 304 /* PCIe retry buffer BIST. */ 305 #define ALC_BIST1 0x1420 306 #define BIST1_ENB 0x00000001 307 #define BIST1_SRAM_FAIL 0x00000002 308 #define BIST1_FUSE_FLAG 0x00000004 309 310 #define ALC_SERDES_LOCK 0x1424 311 #define SERDES_LOCK_DET 0x00000001 312 #define SERDES_LOCK_DET_ENB 0x00000002 313 #define SERDES_MAC_CLK_SLOWDOWN 0x00020000 314 #define SERDES_PHY_CLK_SLOWDOWN 0x00040000 315 316 #define ALC_LPI_CTL 0x1440 317 #define LPI_CTL_ENB 0x00000001 318 319 #define ALC_EXT_MDIO 0x1448 320 #define EXT_MDIO_REG_MASK 0x0000FFFF 321 #define EXT_MDIO_DEVADDR_MASK 0x001F0000 322 #define EXT_MDIO_REG_SHIFT 0 323 #define EXT_MDIO_DEVADDR_SHIFT 16 324 325 #define EXT_MDIO_REG(x) \ 326 (((x) << EXT_MDIO_REG_SHIFT) & EXT_MDIO_REG_MASK) 327 #define EXT_MDIO_DEVADDR(x) \ 328 (((x) << EXT_MDIO_DEVADDR_SHIFT) & EXT_MDIO_DEVADDR_MASK) 329 330 #define ALC_IDLE_DECISN_TIMER 0x1474 331 #define IDLE_DECISN_TIMER_DEFAULT_1MS 0x400 332 333 #define ALC_MAC_CFG 0x1480 334 #define MAC_CFG_TX_ENB 0x00000001 335 #define MAC_CFG_RX_ENB 0x00000002 336 #define MAC_CFG_TX_FC 0x00000004 337 #define MAC_CFG_RX_FC 0x00000008 338 #define MAC_CFG_LOOP 0x00000010 339 #define MAC_CFG_FULL_DUPLEX 0x00000020 340 #define MAC_CFG_TX_CRC_ENB 0x00000040 341 #define MAC_CFG_TX_AUTO_PAD 0x00000080 342 #define MAC_CFG_TX_LENCHK 0x00000100 343 #define MAC_CFG_RX_JUMBO_ENB 0x00000200 344 #define MAC_CFG_PREAMBLE_MASK 0x00003C00 345 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 346 #define MAC_CFG_PROMISC 0x00008000 347 #define MAC_CFG_TX_PAUSE 0x00010000 348 #define MAC_CFG_SCNT 0x00020000 349 #define MAC_CFG_SYNC_RST_TX 0x00040000 350 #define MAC_CFG_SIM_RST_TX 0x00080000 351 #define MAC_CFG_SPEED_MASK 0x00300000 352 #define MAC_CFG_SPEED_10_100 0x00100000 353 #define MAC_CFG_SPEED_1000 0x00200000 354 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 355 #define MAC_CFG_TX_JUMBO_ENB 0x00800000 356 #define MAC_CFG_RXCSUM_ENB 0x01000000 357 #define MAC_CFG_ALLMULTI 0x02000000 358 #define MAC_CFG_BCAST 0x04000000 359 #define MAC_CFG_DBG 0x08000000 360 #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000 361 #define MAC_CFG_HASH_ALG_CRC32 0x20000000 362 #define MAC_CFG_SPEED_MODE_SW 0x40000000 363 #define MAC_CFG_FAST_PAUSE 0x80000000 364 #define MAC_CFG_PREAMBLE_SHIFT 10 365 #define MAC_CFG_PREAMBLE_DEFAULT 7 366 367 #define ALC_IPG_IFG_CFG 0x1484 368 #define IPG_IFG_IPGT_MASK 0x0000007F 369 #define IPG_IFG_MIFG_MASK 0x0000FF00 370 #define IPG_IFG_IPG1_MASK 0x007F0000 371 #define IPG_IFG_IPG2_MASK 0x7F000000 372 #define IPG_IFG_IPGT_SHIFT 0 373 #define IPG_IFG_IPGT_DEFAULT 0x60 374 #define IPG_IFG_MIFG_SHIFT 8 375 #define IPG_IFG_MIFG_DEFAULT 0x50 376 #define IPG_IFG_IPG1_SHIFT 16 377 #define IPG_IFG_IPG1_DEFAULT 0x40 378 #define IPG_IFG_IPG2_SHIFT 24 379 #define IPG_IFG_IPG2_DEFAULT 0x60 380 381 /* Station address. */ 382 #define ALC_PAR0 0x1488 383 #define ALC_PAR1 0x148C 384 385 /* 64bit multicast hash register. */ 386 #define ALC_MAR0 0x1490 387 #define ALC_MAR1 0x1494 388 389 /* half-duplex parameter configuration. */ 390 #define ALC_HDPX_CFG 0x1498 391 #define HDPX_CFG_LCOL_MASK 0x000003FF 392 #define HDPX_CFG_RETRY_MASK 0x0000F000 393 #define HDPX_CFG_EXC_DEF_EN 0x00010000 394 #define HDPX_CFG_NO_BACK_C 0x00020000 395 #define HDPX_CFG_NO_BACK_P 0x00040000 396 #define HDPX_CFG_ABEBE 0x00080000 397 #define HDPX_CFG_ABEBT_MASK 0x00F00000 398 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 399 #define HDPX_CFG_LCOL_SHIFT 0 400 #define HDPX_CFG_LCOL_DEFAULT 0x37 401 #define HDPX_CFG_RETRY_SHIFT 12 402 #define HDPX_CFG_RETRY_DEFAULT 0x0F 403 #define HDPX_CFG_ABEBT_SHIFT 20 404 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 405 #define HDPX_CFG_JAMIPG_SHIFT 24 406 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 407 408 #define ALC_FRAME_SIZE 0x149C 409 410 #define ALC_WOL_CFG 0x14A0 411 #define WOL_CFG_PATTERN 0x00000001 412 #define WOL_CFG_PATTERN_ENB 0x00000002 413 #define WOL_CFG_MAGIC 0x00000004 414 #define WOL_CFG_MAGIC_ENB 0x00000008 415 #define WOL_CFG_LINK_CHG 0x00000010 416 #define WOL_CFG_LINK_CHG_ENB 0x00000020 417 #define WOL_CFG_PATTERN_DET 0x00000100 418 #define WOL_CFG_MAGIC_DET 0x00000200 419 #define WOL_CFG_LINK_CHG_DET 0x00000400 420 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 421 #define WOL_CFG_PATTERN0 0x00010000 422 #define WOL_CFG_PATTERN1 0x00020000 423 #define WOL_CFG_PATTERN2 0x00040000 424 #define WOL_CFG_PATTERN3 0x00080000 425 #define WOL_CFG_PATTERN4 0x00100000 426 #define WOL_CFG_PATTERN5 0x00200000 427 #define WOL_CFG_PATTERN6 0x00400000 428 429 /* WOL pattern length. */ 430 #define ALC_PATTERN_CFG0 0x14A4 431 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 432 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 433 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 434 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 435 436 #define ALC_PATTERN_CFG1 0x14A8 437 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 438 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 439 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 440 441 /* RSS */ 442 #define ALC_RSS_KEY0 0x14B0 443 444 #define ALC_RSS_KEY1 0x14B4 445 446 #define ALC_RSS_KEY2 0x14B8 447 448 #define ALC_RSS_KEY3 0x14BC 449 450 #define ALC_RSS_KEY4 0x14C0 451 452 #define ALC_RSS_KEY5 0x14C4 453 454 #define ALC_RSS_KEY6 0x14C8 455 456 #define ALC_RSS_KEY7 0x14CC 457 458 #define ALC_RSS_KEY8 0x14D0 459 460 #define ALC_RSS_KEY9 0x14D4 461 462 #define ALC_RSS_IDT_TABLE0 0x14E0 463 464 #define ALC_TD_PRI2_HEAD_ADDR_LO 0x14E0 /* AR816x */ 465 466 #define ALC_RSS_IDT_TABLE1 0x14E4 467 468 #define ALC_TD_PRI3_HEAD_ADDR_LO 0x14E4 /* AR816x */ 469 470 #define ALC_RSS_IDT_TABLE2 0x14E8 471 472 #define ALC_RSS_IDT_TABLE3 0x14EC 473 474 #define ALC_RSS_IDT_TABLE4 0x14F0 475 476 #define ALC_RSS_IDT_TABLE5 0x14F4 477 478 #define ALC_RSS_IDT_TABLE6 0x14F8 479 480 #define ALC_RSS_IDT_TABLE7 0x14FC 481 482 #define ALC_SRAM_RD0_ADDR 0x1500 483 484 #define ALC_SRAM_RD1_ADDR 0x1504 485 486 #define ALC_SRAM_RD2_ADDR 0x1508 487 488 #define ALC_SRAM_RD3_ADDR 0x150C 489 490 #define RD_HEAD_ADDR_MASK 0x000003FF 491 #define RD_TAIL_ADDR_MASK 0x03FF0000 492 #define RD_HEAD_ADDR_SHIFT 0 493 #define RD_TAIL_ADDR_SHIFT 16 494 495 #define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */ 496 #define RD_NIC_LEN_MASK 0x000003FF 497 498 #define ALC_RD_NIC_LEN1 0x1514 499 500 #define ALC_SRAM_TD_ADDR 0x1518 501 #define TD_HEAD_ADDR_MASK 0x000003FF 502 #define TD_TAIL_ADDR_MASK 0x03FF0000 503 #define TD_HEAD_ADDR_SHIFT 0 504 #define TD_TAIL_ADDR_SHIFT 16 505 506 #define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */ 507 #define SRAM_TD_LEN_MASK 0x000003FF 508 509 #define ALC_SRAM_RX_FIFO_ADDR 0x1520 510 511 #define ALC_SRAM_RX_FIFO_LEN 0x1524 512 #define SRAM_RX_FIFO_LEN_MASK 0x00000FFF 513 #define SRAM_RX_FIFO_LEN_SHIFT 0 514 515 #define ALC_SRAM_TX_FIFO_ADDR 0x1528 516 517 #define ALC_SRAM_TX_FIFO_LEN 0x152C 518 519 #define ALC_SRAM_TCPH_ADDR 0x1530 520 #define SRAM_TCPH_ADDR_MASK 0x00000FFF 521 #define SRAM_PATH_ADDR_MASK 0x0FFF0000 522 #define SRAM_TCPH_ADDR_SHIFT 0 523 #define SRAM_PKTH_ADDR_SHIFT 16 524 525 #define ALC_DMA_BLOCK 0x1534 526 #define DMA_BLOCK_LOAD 0x00000001 527 528 #define ALC_RX_BASE_ADDR_HI 0x1540 529 530 #define ALC_TX_BASE_ADDR_HI 0x1544 531 532 #define ALC_SMB_BASE_ADDR_HI 0x1548 533 534 #define ALC_SMB_BASE_ADDR_LO 0x154C 535 536 #define ALC_RD0_HEAD_ADDR_LO 0x1550 537 538 #define ALC_RD1_HEAD_ADDR_LO 0x1554 539 540 #define ALC_RD2_HEAD_ADDR_LO 0x1558 541 542 #define ALC_RD3_HEAD_ADDR_LO 0x155C 543 544 #define ALC_RD_RING_CNT 0x1560 545 #define RD_RING_CNT_MASK 0x00000FFF 546 #define RD_RING_CNT_SHIFT 0 547 548 #define ALC_RX_BUF_SIZE 0x1564 549 #define RX_BUF_SIZE_MASK 0x0000FFFF 550 /* 551 * If larger buffer size than 1536 is specified the controller 552 * will be locked up. This is hardware limitation. 553 */ 554 #define RX_BUF_SIZE_MAX 1536 555 556 #define ALC_RRD0_HEAD_ADDR_LO 0x1568 557 558 #define ALC_RRD1_HEAD_ADDR_LO 0x156C 559 560 #define ALC_RRD2_HEAD_ADDR_LO 0x1570 561 562 #define ALC_RRD3_HEAD_ADDR_LO 0x1574 563 564 #define ALC_RRD_RING_CNT 0x1578 565 #define RRD_RING_CNT_MASK 0x00000FFF 566 #define RRD_RING_CNT_SHIFT 0 567 568 #define ALC_TDH_HEAD_ADDR_LO 0x157C 569 570 #define ALC_TD_PRI1_HEAD_ADDR_LO 0x157C /* AR816x */ 571 572 #define ALC_TDL_HEAD_ADDR_LO 0x1580 573 574 #define ALC_TD_PRI0_HEAD_ADDR_LO 0x1580 /* AR816x */ 575 576 #define ALC_TD_RING_CNT 0x1584 577 #define TD_RING_CNT_MASK 0x0000FFFF 578 #define TD_RING_CNT_SHIFT 0 579 580 #define ALC_CMB_BASE_ADDR_LO 0x1588 581 582 #define ALC_TXQ_CFG 0x1590 583 #define TXQ_CFG_TD_BURST_MASK 0x0000000F 584 #define TXQ_CFG_IP_OPTION_ENB 0x00000010 585 #define TXQ_CFG_ENB 0x00000020 586 #define TXQ_CFG_ENHANCED_MODE 0x00000040 587 #define TXQ_CFG_8023_ENB 0x00000080 588 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 589 #define TXQ_CFG_TD_BURST_SHIFT 0 590 #define TXQ_CFG_TD_BURST_DEFAULT 5 591 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 592 593 #define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */ 594 #define TSO_OFFLOAD_THRESH_MASK 0x000007FF 595 #define TSO_OFFLOAD_ERRLGPKT_DROP_ENB 0x00000800 596 #define TSO_OFFLOAD_THRESH_SHIFT 0 597 #define TSO_OFFLOAD_THRESH_UNIT 8 598 #define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3 599 600 #define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */ 601 #define TXF_WATER_MARK_HI_MASK 0x00000FFF 602 #define TXF_WATER_MARK_LO_MASK 0x0FFF0000 603 #define TXF_WATER_MARK_BURST_ENB 0x80000000 604 #define TXF_WATER_MARK_LO_SHIFT 0 605 #define TXF_WATER_MARK_HI_SHIFT 16 606 607 #define ALC_THROUGHPUT_MON 0x159C 608 #define THROUGHPUT_MON_RATE_MASK 0x00000003 609 #define THROUGHPUT_MON_ENB 0x00000080 610 #define THROUGHPUT_MON_RATE_SHIFT 0 611 612 #define ALC_RXQ_CFG 0x15A0 613 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003 614 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000 615 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001 616 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002 617 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003 618 #define RXQ_CFG_QUEUE1_ENB 0x00000010 619 #define RXQ_CFG_QUEUE2_ENB 0x00000020 620 #define RXQ_CFG_QUEUE3_ENB 0x00000040 621 #define RXQ_CFG_IPV6_CSUM_ENB 0x00000080 622 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 623 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000 624 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 625 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000 626 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 627 #define RXQ_CFG_RD_BURST_MASK 0x03F00000 628 #define RXQ_CFG_RSS_MODE_DIS 0x00000000 629 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 630 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 631 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 632 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 633 #define RXQ_CFG_RSS_HASH_ENB 0x20000000 634 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 635 #define RXQ_CFG_QUEUE0_ENB 0x80000000 636 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 637 #define RXQ_CFG_RD_BURST_DEFAULT 8 638 #define RXQ_CFG_RD_BURST_SHIFT 20 639 #define RXQ_CFG_ENB \ 640 (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \ 641 RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB) 642 643 /* AR816x specific bits */ 644 #define RXQ_CFG_816X_RSS_HASH_IPV4 0x00000004 645 #define RXQ_CFG_816X_RSS_HASH_IPV4_TCP 0x00000008 646 #define RXQ_CFG_816X_RSS_HASH_IPV6 0x00000010 647 #define RXQ_CFG_816X_RSS_HASH_IPV6_TCP 0x00000020 648 #define RXQ_CFG_816X_RSS_HASH_MASK 0x0000003C 649 #define RXQ_CFG_816X_IPV6_PARSE_ENB 0x00000080 650 #define RXQ_CFG_816X_IDT_TBL_SIZE_MASK 0x0001FF00 651 #define RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT 8 652 #define RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT 0x100 653 654 #define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */ 655 #define RX_RD_FREE_THRESH_HI_MASK 0x0000003F 656 #define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0 657 #define RX_RD_FREE_THRESH_HI_SHIFT 0 658 #define RX_RD_FREE_THRESH_LO_SHIFT 6 659 #define RX_RD_FREE_THRESH_HI_DEFAULT 16 660 #define RX_RD_FREE_THRESH_LO_DEFAULT 8 661 662 #define ALC_RX_FIFO_PAUSE_THRESH 0x15A8 663 #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 664 #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 665 #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 666 #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 667 668 /* 669 * Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) + 670 * rx-packet(1522) + delay-of-link(64) 671 * = 3212. 672 */ 673 #define RX_FIFO_PAUSE_816X_RSVD 3212 674 675 #define ALC_RD_DMA_CFG 0x15AC 676 #define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */ 677 #define RD_DMA_CFG_TIMER_MASK 0xFFFF0000 678 #define RD_DMA_CFG_THRESH_SHIFT 0 679 #define RD_DMA_CFG_TIMER_SHIFT 16 680 #define RD_DMA_CFG_THRESH_DEFAULT 0x100 681 #define RD_DMA_CFG_TIMER_DEFAULT 0 682 #define RD_DMA_CFG_TICK_USECS 8 683 #define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS) 684 685 #define ALC_RSS_HASH_VALUE 0x15B0 686 687 #define ALC_RSS_HASH_FLAG 0x15B4 688 689 #define ALC_RSS_CPU 0x15B8 690 691 #define ALC_DMA_CFG 0x15C0 692 #define DMA_CFG_IN_ORDER 0x00000001 693 #define DMA_CFG_ENH_ORDER 0x00000002 694 #define DMA_CFG_OUT_ORDER 0x00000004 695 #define DMA_CFG_RCB_64 0x00000000 696 #define DMA_CFG_RCB_128 0x00000008 697 #define DMA_CFG_PEND_AUTO_RST 0x00000008 698 #define DMA_CFG_RD_BURST_128 0x00000000 699 #define DMA_CFG_RD_BURST_256 0x00000010 700 #define DMA_CFG_RD_BURST_512 0x00000020 701 #define DMA_CFG_RD_BURST_1024 0x00000030 702 #define DMA_CFG_RD_BURST_2048 0x00000040 703 #define DMA_CFG_RD_BURST_4096 0x00000050 704 #define DMA_CFG_WR_BURST_128 0x00000000 705 #define DMA_CFG_WR_BURST_256 0x00000080 706 #define DMA_CFG_WR_BURST_512 0x00000100 707 #define DMA_CFG_WR_BURST_1024 0x00000180 708 #define DMA_CFG_WR_BURST_2048 0x00000200 709 #define DMA_CFG_WR_BURST_4096 0x00000280 710 #define DMA_CFG_RD_REQ_PRI 0x00000400 711 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 712 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 713 #define DMA_CFG_CMB_ENB 0x00100000 714 #define DMA_CFG_SMB_ENB 0x00200000 715 #define DMA_CFG_CMB_NOW 0x00400000 716 #define DMA_CFG_SMB_DIS 0x01000000 717 #define DMA_CFG_RD_CHNL_SEL_MASK 0x0C000000 718 #define DMA_CFG_RD_CHNL_SEL_1 0x00000000 719 #define DMA_CFG_RD_CHNL_SEL_2 0x04000000 720 #define DMA_CFG_RD_CHNL_SEL_3 0x08000000 721 #define DMA_CFG_RD_CHNL_SEL_4 0x0C000000 722 #define DMA_CFG_WSRAM_RDCTL 0x10000000 723 #define DMA_CFG_RD_PEND_CLR 0x20000000 724 #define DMA_CFG_WR_PEND_CLR 0x40000000 725 #define DMA_CFG_SMB_NOW 0x80000000 726 #define DMA_CFG_RD_BURST_MASK 0x07 727 #define DMA_CFG_RD_BURST_SHIFT 4 728 #define DMA_CFG_WR_BURST_MASK 0x07 729 #define DMA_CFG_WR_BURST_SHIFT 7 730 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11 731 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16 732 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 733 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 734 735 #define ALC_SMB_STAT_TIMER 0x15C4 736 #define SMB_STAT_TIMER_MASK 0x00FFFFFF 737 #define SMB_STAT_TIMER_SHIFT 0 738 739 #define ALC_CMB_TD_THRESH 0x15C8 740 #define CMB_TD_THRESH_MASK 0x0000FFFF 741 #define CMB_TD_THRESH_SHIFT 0 742 743 #define ALC_CMB_TX_TIMER 0x15CC 744 #define CMB_TX_TIMER_MASK 0x0000FFFF 745 #define CMB_TX_TIMER_SHIFT 0 746 747 #define ALC_MSI_MAP_TBL1 0x15D0 748 749 #define ALC_MSI_ID_MAP 0x15D4 750 751 #define ALC_MSI_MAP_TBL2 0x15D8 752 753 #define ALC_MBOX_RD0_PROD_IDX 0x15E0 754 755 #define ALC_MBOX_RD1_PROD_IDX 0x15E4 756 757 #define ALC_MBOX_RD2_PROD_IDX 0x15E8 758 759 #define ALC_MBOX_RD3_PROD_IDX 0x15EC 760 761 #define ALC_MBOX_RD_PROD_MASK 0x0000FFFF 762 #define MBOX_RD_PROD_SHIFT 0 763 764 #define ALC_MBOX_TD_PROD_IDX 0x15F0 765 #define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF 766 #define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000 767 #define MBOX_TD_PROD_HI_IDX_SHIFT 0 768 #define MBOX_TD_PROD_LO_IDX_SHIFT 16 769 770 #define ALC_MBOX_TD_PRI1_PROD_IDX 0x15F0 /* 16 bits AR816x */ 771 772 #define ALC_MBOX_TD_PRI0_PROD_IDX 0x15F2 /* 16 bits AR816x */ 773 774 #define ALC_MBOX_TD_CONS_IDX 0x15F4 775 #define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF 776 #define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000 777 #define MBOX_TD_CONS_HI_IDX_SHIFT 0 778 #define MBOX_TD_CONS_LO_IDX_SHIFT 16 779 780 #define ALC_MBOX_TD_PRI1_CONS_IDX 0x15F4 /* 16 bits AR816x */ 781 782 #define ALC_MBOX_TD_PRI0_CONS_IDX 0x15F6 /* 16 bits AR816x */ 783 784 #define ALC_MBOX_RD01_CONS_IDX 0x15F8 785 #define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF 786 #define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000 787 #define MBOX_RD0_CONS_IDX_SHIFT 0 788 #define MBOX_RD1_CONS_IDX_SHIFT 16 789 790 #define ALC_MBOX_RD23_CONS_IDX 0x15FC 791 #define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF 792 #define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000 793 #define MBOX_RD2_CONS_IDX_SHIFT 0 794 #define MBOX_RD3_CONS_IDX_SHIFT 16 795 796 #define ALC_INTR_STATUS 0x1600 797 #define INTR_SMB 0x00000001 798 #define INTR_TIMER 0x00000002 799 #define INTR_MANUAL_TIMER 0x00000004 800 #define INTR_RX_FIFO_OFLOW 0x00000008 801 #define INTR_RD0_UNDERRUN 0x00000010 802 #define INTR_RD1_UNDERRUN 0x00000020 803 #define INTR_RD2_UNDERRUN 0x00000040 804 #define INTR_RD3_UNDERRUN 0x00000080 805 #define INTR_TX_FIFO_UNDERRUN 0x00000100 806 #define INTR_DMA_RD_TO_RST 0x00000200 807 #define INTR_DMA_WR_TO_RST 0x00000400 808 #define INTR_TX_CREDIT 0x00000800 809 #define INTR_GPHY 0x00001000 810 #define INTR_GPHY_LOW_PW 0x00002000 811 #define INTR_TXQ_TO_RST 0x00004000 812 #define INTR_TX_PKT0 0x00008000 813 #define INTR_RX_PKT0 0x00010000 814 #define INTR_RX_PKT1 0x00020000 815 #define INTR_RX_PKT2 0x00040000 816 #define INTR_RX_PKT3 0x00080000 817 #define INTR_MAC_RX 0x00100000 818 #define INTR_MAC_TX 0x00200000 819 #define INTR_UNDERRUN 0x00400000 820 #define INTR_FRAME_ERROR 0x00800000 821 #define INTR_FRAME_OK 0x01000000 822 #define INTR_CSUM_ERROR 0x02000000 823 #define INTR_PHY_LINK_DOWN 0x04000000 824 #define INTR_DIS_INT 0x80000000 825 826 /* INTR status for AR816x/AR817x 4 TX queues, 8 RX queues */ 827 #define INTR_TX_PKT1 0x00000020 828 #define INTR_TX_PKT2 0x00000040 829 #define INTR_TX_PKT3 0x00000080 830 #define INTR_RX_PKT4 0x08000000 831 #define INTR_RX_PKT5 0x10000000 832 #define INTR_RX_PKT6 0x20000000 833 #define INTR_RX_PKT7 0x40000000 834 835 /* Interrupt Mask Register */ 836 #define ALC_INTR_MASK 0x1604 837 838 #ifdef notyet 839 #define INTR_RX_PKT \ 840 (INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 | \ 841 INTR_RX_PKT3) 842 #define INTR_RD_UNDERRUN \ 843 (INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \ 844 INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN) 845 #else 846 #define INTR_TX_PKT INTR_TX_PKT0 847 #define INTR_RX_PKT INTR_RX_PKT0 848 #define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN 849 #endif 850 851 #define ALC_INTRS \ 852 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 853 INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \ 854 INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \ 855 INTR_TX_FIFO_UNDERRUN) 856 857 #define ALC_INTR_RETRIG_TIMER 0x1608 858 #define INTR_RETRIG_TIMER_MASK 0x0000FFFF 859 #define INTR_RETRIG_TIMER_SHIFT 0 860 861 #define ALC_HDS_CFG 0x160C 862 #define HDS_CFG_ENB 0x00000001 863 #define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00 864 #define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000 865 #define HDS_CFG_BACKFILLSIZE_SHIFT 8 866 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20 867 868 #define ALC_MBOX_TD_PRI3_PROD_IDX 0x1618 /* 16 bits AR816x */ 869 870 #define ALC_MBOX_TD_PRI2_PROD_IDX 0x161A /* 16 bits AR816x */ 871 872 #define ALC_MBOX_TD_PRI3_CONS_IDX 0x161C /* 16 bits AR816x */ 873 874 #define ALC_MBOX_TD_PRI2_CONS_IDX 0x161E /* 16 bits AR816x */ 875 876 /* AR813x/AR815x registers for MAC statistics */ 877 #define ALC_RX_MIB_BASE 0x1700 878 879 #define ALC_TX_MIB_BASE 0x1760 880 881 #define ALC_DRV 0x1804 /* AR816x */ 882 #define DRV_ASPM_SPD10LMT_1M 0x00000000 883 #define DRV_ASPM_SPD10LMT_10M 0x00000001 884 #define DRV_ASPM_SPD10LMT_100M 0x00000002 885 #define DRV_ASPM_SPD10LMT_NO 0x00000003 886 #define DRV_ASPM_SPD10LMT_MASK 0x00000003 887 #define DRV_ASPM_SPD100LMT_1M 0x00000000 888 #define DRV_ASPM_SPD100LMT_10M 0x00000004 889 #define DRV_ASPM_SPD100LMT_100M 0x00000008 890 #define DRV_ASPM_SPD100LMT_NO 0x0000000C 891 #define DRV_ASPM_SPD100LMT_MASK 0x0000000C 892 #define DRV_ASPM_SPD1000LMT_100M 0x00000000 893 #define DRV_ASPM_SPD1000LMT_NO 0x00000010 894 #define DRV_ASPM_SPD1000LMT_1M 0x00000020 895 #define DRV_ASPM_SPD1000LMT_10M 0x00000030 896 #define DRV_ASPM_SPD1000LMT_MASK 0x00000000 897 #define DRV_WOLCAP_BIOS_EN 0x00000100 898 #define DRV_WOLMAGIC_EN 0x00000200 899 #define DRV_WOLLINKUP_EN 0x00000400 900 #define DRV_WOLPATTERN_EN 0x00000800 901 #define DRV_AZ_EN 0x00001000 902 #define DRV_WOLS5_BIOS_EN 0x00010000 903 #define DRV_WOLS5_EN 0x00020000 904 #define DRV_DISABLE 0x00040000 905 #define DRV_PHY_MASK 0x1FE00000 906 #define DRV_PHY_EEE 0x00200000 907 #define DRV_PHY_APAUSE 0x00400000 908 #define DRV_PHY_PAUSE 0x00800000 909 #define DRV_PHY_DUPLEX 0x01000000 910 #define DRV_PHY_10 0x02000000 911 #define DRV_PHY_100 0x04000000 912 #define DRV_PHY_1000 0x08000000 913 #define DRV_PHY_AUTO 0x10000000 914 #define DRV_PHY_SHIFT 21 915 916 #define ALC_CLK_GATING_CFG 0x1814 917 #define CLK_GATING_DMAW_ENB 0x0001 918 #define CLK_GATING_DMAR_ENB 0x0002 919 #define CLK_GATING_TXQ_ENB 0x0004 920 #define CLK_GATING_RXQ_ENB 0x0008 921 #define CLK_GATING_TXMAC_ENB 0x0010 922 #define CLK_GATING_RXMAC_ENB 0x0020 923 924 #define ALC_DEBUG_DATA0 0x1900 925 926 #define ALC_DEBUG_DATA1 0x1904 927 928 #define ALC_MSI_RETRANS_TIMER 0x1920 929 #define MSI_RETRANS_TIMER_MASK 0x0000FFFF 930 #define MSI_RETRANS_MASK_SEL_STD 0x00000000 931 #define MSI_RETRANS_MASK_SEL_LINE 0x00010000 932 #define MSI_RETRANS_TIMER_SHIFT 0 933 934 #define ALC_WRR 0x1938 935 #define WRR_PRI0_MASK 0x0000001F 936 #define WRR_PRI1_MASK 0x00001F00 937 #define WRR_PRI2_MASK 0x001F0000 938 #define WRR_PRI3_MASK 0x1F000000 939 #define WRR_PRI_RESTRICT_MASK 0x60000000 940 #define WRR_PRI_RESTRICT_ALL 0x00000000 941 #define WRR_PRI_RESTRICT_HI 0x20000000 942 #define WRR_PRI_RESTRICT_HI2 0x40000000 943 #define WRR_PRI_RESTRICT_NONE 0x60000000 944 #define WRR_PRI0_SHIFT 0 945 #define WRR_PRI1_SHIFT 8 946 #define WRR_PRI2_SHIFT 16 947 #define WRR_PRI3_SHIFT 24 948 #define WRR_PRI_DEFAULT 4 949 #define WRR_PRI_RESTRICT_SHIFT 29 950 951 #define ALC_HQTD_CFG 0x193C 952 #define HQTD_CFG_Q1_BURST_MASK 0x0000000F 953 #define HQTD_CFG_Q2_BURST_MASK 0x000000F0 954 #define HQTD_CFG_Q3_BURST_MASK 0x00000F00 955 #define HQTD_CFG_BURST_ENB 0x80000000 956 #define HQTD_CFG_Q1_BURST_SHIFT 0 957 #define HQTD_CFG_Q2_BURST_SHIFT 4 958 #define HQTD_CFG_Q3_BURST_SHIFT 8 959 960 #define ALC_MISC 0x19C0 961 #define MISC_INTNLOSC_OPEN 0x00000008 962 #define MISC_ISO_ENB 0x00001000 963 #define MISC_PSW_OCP_MASK 0x00E00000 964 #define MISC_PSW_OCP_SHIFT 21 965 #define MISC_PSW_OCP_DEFAULT 7 966 967 #define ALC_MISC2 0x19C8 968 #define MISC2_CALB_START 0x00000001 969 970 #define ALC_MISC3 0x19CC 971 #define MISC3_25M_NOTO_INTNL 0x00000001 972 #define MISC3_25M_BY_SW 0x00000002 973 974 #define ALC_MII_DBG_ADDR 0x1D 975 #define ALC_MII_DBG_DATA 0x1E 976 977 #define MII_ANA_CFG0 0x00 978 #define ANA_RESTART_CAL 0x0001 979 #define ANA_MANUL_SWICH_ON_MASK 0x001E 980 #define ANA_MAN_ENABLE 0x0020 981 #define ANA_SEL_HSP 0x0040 982 #define ANA_EN_HB 0x0080 983 #define ANA_EN_HBIAS 0x0100 984 #define ANA_OEN_125M 0x0200 985 #define ANA_EN_LCKDT 0x0400 986 #define ANA_LCKDT_PHY 0x0800 987 #define ANA_AFE_MODE 0x1000 988 #define ANA_VCO_SLOW 0x2000 989 #define ANA_VCO_FAST 0x4000 990 #define ANA_SEL_CLK125M_DSP 0x8000 991 #define ANA_MANUL_SWICH_ON_SHIFT 1 992 993 #define MII_DBG_ANACTL 0x00 994 #define DBG_ANACTL_DEFAULT 0x02EF 995 996 #define MII_ANA_CFG4 0x04 997 #define ANA_IECHO_ADJ_MASK 0x0F 998 #define ANA_IECHO_ADJ_3_MASK 0x000F 999 #define ANA_IECHO_ADJ_2_MASK 0x00F0 1000 #define ANA_IECHO_ADJ_1_MASK 0x0F00 1001 #define ANA_IECHO_ADJ_0_MASK 0xF000 1002 #define ANA_IECHO_ADJ_3_SHIFT 0 1003 #define ANA_IECHO_ADJ_2_SHIFT 4 1004 #define ANA_IECHO_ADJ_1_SHIFT 8 1005 #define ANA_IECHO_ADJ_0_SHIFT 12 1006 1007 #define MII_DBG_SYSMODCTL 0x04 1008 #define DBG_SYSMODCTL_DEFAULT 0xBB8B 1009 1010 #define MII_ANA_CFG5 0x05 1011 #define ANA_SERDES_CDR_BW_MASK 0x0003 1012 #define ANA_MS_PAD_DBG 0x0004 1013 #define ANA_SPEEDUP_DBG 0x0008 1014 #define ANA_SERDES_TH_LOS_MASK 0x0030 1015 #define ANA_SERDES_EN_DEEM 0x0040 1016 #define ANA_SERDES_TXELECIDLE 0x0080 1017 #define ANA_SERDES_BEACON 0x0100 1018 #define ANA_SERDES_HALFTXDR 0x0200 1019 #define ANA_SERDES_SEL_HSP 0x0400 1020 #define ANA_SERDES_EN_PLL 0x0800 1021 #define ANA_SERDES_EN 0x1000 1022 #define ANA_SERDES_EN_LCKDT 0x2000 1023 #define ANA_SERDES_CDR_BW_SHIFT 0 1024 #define ANA_SERDES_TH_LOS_SHIFT 4 1025 1026 #define MII_DBG_SRDSYSMOD 0x05 1027 #define DBG_SRDSYSMOD_DEFAULT 0x2C46 1028 1029 #define MII_ANA_CFG11 0x0B 1030 #define ANA_PS_HIB_EN 0x8000 1031 1032 #define MII_DBG_HIBNEG 0x0B 1033 #define DBG_HIBNEG_HIB_PULSE 0x1000 1034 #define DBG_HIBNEG_PSHIB_EN 0x8000 1035 #define DBG_HIBNEG_DEFAULT 0xBC40 1036 1037 #define MII_ANA_CFG18 0x12 1038 #define ANA_TEST_MODE_10BT_01MASK 0x0003 1039 #define ANA_LOOP_SEL_10BT 0x0004 1040 #define ANA_RGMII_MODE_SW 0x0008 1041 #define ANA_EN_LONGECABLE 0x0010 1042 #define ANA_TEST_MODE_10BT_2 0x0020 1043 #define ANA_EN_10BT_IDLE 0x0400 1044 #define ANA_EN_MASK_TB 0x0800 1045 #define ANA_TRIGGER_SEL_TIMER_MASK 0x3000 1046 #define ANA_INTERVAL_SEL_TIMER_MASK 0xC000 1047 #define ANA_TEST_MODE_10BT_01SHIFT 0 1048 #define ANA_TRIGGER_SEL_TIMER_SHIFT 12 1049 #define ANA_INTERVAL_SEL_TIMER_SHIFT 14 1050 1051 #define MII_DBG_TST10BTCFG 0x12 1052 #define DBG_TST10BTCFG_DEFAULT 0x4C04 1053 1054 #define MII_DBG_AZ_ANADECT 0x15 1055 #define DBG_AZ_ANADECT_DEFAULT 0x3220 1056 #define DBG_AZ_ANADECT_LONG 0x3210 1057 1058 #define MII_DBG_MSE16DB 0x18 1059 #define DBG_MSE16DB_UP 0x05EA 1060 #define DBG_MSE16DB_DOWN 0x02EA 1061 1062 #define MII_DBG_MSE20DB 0x1C 1063 #define DBG_MSE20DB_TH_MASK 0x01FC 1064 #define DBG_MSE20DB_TH_DEFAULT 0x2E 1065 #define DBG_MSE20DB_TH_HI 0x54 1066 #define DBG_MSE20DB_TH_SHIFT 2 1067 1068 #define MII_DBG_AGC 0x23 1069 #define DBG_AGC_2_VGA_MASK 0x3F00 1070 #define DBG_AGC_2_VGA_SHIFT 8 1071 #define DBG_AGC_LONG1G_LIMT 40 1072 #define DBG_AGC_LONG100M_LIMT 44 1073 1074 #define MII_ANA_CFG41 0x29 1075 #define ANA_TOP_PS_EN 0x8000 1076 1077 #define MII_DBG_LEGCYPS 0x29 1078 #define DBG_LEGCYPS_ENB 0x8000 1079 #define DBG_LEGCYPS_DEFAULT 0x129D 1080 1081 #define MII_ANA_CFG54 0x36 1082 #define ANA_LONG_CABLE_TH_100_MASK 0x003F 1083 #define ANA_DESERVED 0x0040 1084 #define ANA_EN_LIT_CH 0x0080 1085 #define ANA_SHORT_CABLE_TH_100_MASK 0x3F00 1086 #define ANA_BP_BAD_LINK_ACCUM 0x4000 1087 #define ANA_BP_SMALL_BW 0x8000 1088 #define ANA_LONG_CABLE_TH_100_SHIFT 0 1089 #define ANA_SHORT_CABLE_TH_100_SHIFT 8 1090 1091 #define MII_DBG_TST100BTCFG 0x36 1092 #define DBG_TST100BTCFG_DEFAULT 0xE12C 1093 1094 #define MII_DBG_GREENCFG 0x3B 1095 #define DBG_GREENCFG_DEFAULT 0x7078 1096 1097 #define MII_DBG_GREENCFG2 0x3D 1098 #define DBG_GREENCFG2_GATE_DFSE_EN 0x0080 1099 #define DBG_GREENCFG2_BP_GREEN 0x8000 1100 1101 /* Device addr 3 */ 1102 #define MII_EXT_PCS 3 1103 1104 #define MII_EXT_CLDCTL3 0x8003 1105 #define EXT_CLDCTL3_BP_CABLE1TH_DET_GT 0x8000 1106 1107 #define MII_EXT_CLDCTL5 0x8005 1108 #define EXT_CLDCTL5_BP_VD_HLFBIAS 0x4000 1109 1110 #define MII_EXT_CLDCTL6 0x8006 1111 #define EXT_CLDCTL6_CAB_LEN_MASK 0x00FF 1112 #define EXT_CLDCTL6_CAB_LEN_SHIFT 0 1113 #define EXT_CLDCTL6_CAB_LEN_SHORT1G 116 1114 #define EXT_CLDCTL6_CAB_LEN_SHORT100M 152 1115 1116 #define MII_EXT_VDRVBIAS 0x8062 1117 #define EXT_VDRVBIAS_DEFAULT 3 1118 1119 /* Device addr 7 */ 1120 #define MII_EXT_ANEG 7 1121 1122 #define MII_EXT_ANEG_LOCAL_EEEADV 0x3C 1123 #define ANEG_LOCA_EEEADV_100BT 0x0002 1124 #define ANEG_LOCA_EEEADV_1000BT 0x0004 1125 1126 #define MII_EXT_ANEG_AFE 0x801A 1127 #define ANEG_AFEE_10BT_100M_TH 0x0040 1128 1129 #define MII_EXT_ANEG_S3DIG10 0x8023 1130 #define ANEG_S3DIG10_SL 0x0001 1131 #define ANEG_S3DIG10_DEFAULT 0 1132 1133 #define MII_EXT_ANEG_NLP78 0x8027 1134 #define ANEG_NLP78_120M_DEFAULT 0x8A05 1135 1136 /* Statistics counters collected by the MAC. */ 1137 struct smb { 1138 /* Rx stats. */ 1139 uint32_t rx_frames; 1140 uint32_t rx_bcast_frames; 1141 uint32_t rx_mcast_frames; 1142 uint32_t rx_pause_frames; 1143 uint32_t rx_control_frames; 1144 uint32_t rx_crcerrs; 1145 uint32_t rx_lenerrs; 1146 uint32_t rx_bytes; 1147 uint32_t rx_runts; 1148 uint32_t rx_fragments; 1149 uint32_t rx_pkts_64; 1150 uint32_t rx_pkts_65_127; 1151 uint32_t rx_pkts_128_255; 1152 uint32_t rx_pkts_256_511; 1153 uint32_t rx_pkts_512_1023; 1154 uint32_t rx_pkts_1024_1518; 1155 uint32_t rx_pkts_1519_max; 1156 uint32_t rx_pkts_truncated; 1157 uint32_t rx_fifo_oflows; 1158 uint32_t rx_rrs_errs; 1159 uint32_t rx_alignerrs; 1160 uint32_t rx_bcast_bytes; 1161 uint32_t rx_mcast_bytes; 1162 uint32_t rx_pkts_filtered; 1163 /* Tx stats. */ 1164 uint32_t tx_frames; 1165 uint32_t tx_bcast_frames; 1166 uint32_t tx_mcast_frames; 1167 uint32_t tx_pause_frames; 1168 uint32_t tx_excess_defer; 1169 uint32_t tx_control_frames; 1170 uint32_t tx_deferred; 1171 uint32_t tx_bytes; 1172 uint32_t tx_pkts_64; 1173 uint32_t tx_pkts_65_127; 1174 uint32_t tx_pkts_128_255; 1175 uint32_t tx_pkts_256_511; 1176 uint32_t tx_pkts_512_1023; 1177 uint32_t tx_pkts_1024_1518; 1178 uint32_t tx_pkts_1519_max; 1179 uint32_t tx_single_colls; 1180 uint32_t tx_multi_colls; 1181 uint32_t tx_late_colls; 1182 uint32_t tx_excess_colls; 1183 uint32_t tx_underrun; 1184 uint32_t tx_desc_underrun; 1185 uint32_t tx_lenerrs; 1186 uint32_t tx_pkts_truncated; 1187 uint32_t tx_bcast_bytes; 1188 uint32_t tx_mcast_bytes; 1189 uint32_t updated; 1190 }; 1191 1192 /* CMB(Coalesing message block) */ 1193 struct cmb { 1194 uint32_t cons; 1195 }; 1196 1197 /* Rx free descriptor */ 1198 struct rx_desc { 1199 uint64_t addr; 1200 }; 1201 1202 /* Rx return descriptor */ 1203 struct rx_rdesc { 1204 uint32_t rdinfo; 1205 #define RRD_CSUM_MASK 0x0000FFFF 1206 #define RRD_RD_CNT_MASK 0x000F0000 1207 #define RRD_RD_IDX_MASK 0xFFF00000 1208 #define RRD_CSUM_SHIFT 0 1209 #define RRD_RD_CNT_SHIFT 16 1210 #define RRD_RD_IDX_SHIFT 20 1211 #define RRD_CSUM(x) \ 1212 (((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT) 1213 #define RRD_RD_CNT(x) \ 1214 (((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT) 1215 #define RRD_RD_IDX(x) \ 1216 (((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT) 1217 uint32_t rss; 1218 uint32_t vtag; 1219 #define RRD_VLAN_MASK 0x0000FFFF 1220 #define RRD_HEAD_LEN_MASK 0x00FF0000 1221 #define RRD_HDS_MASK 0x03000000 1222 #define RRD_HDS_NONE 0x00000000 1223 #define RRD_HDS_HEAD 0x01000000 1224 #define RRD_HDS_DATA 0x02000000 1225 #define RRD_CPU_MASK 0x0C000000 1226 #define RRD_HASH_FLAG_MASK 0xF0000000 1227 #define RRD_VLAN_SHIFT 0 1228 #define RRD_HEAD_LEN_SHIFT 16 1229 #define RRD_HDS_SHIFT 24 1230 #define RRD_CPU_SHIFT 26 1231 #define RRD_HASH_FLAG_SHIFT 28 1232 #define RRD_VLAN(x) \ 1233 (((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT) 1234 #define RRD_HEAD_LEN(x) \ 1235 (((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT) 1236 #define RRD_CPU(x) \ 1237 (((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT) 1238 uint32_t status; 1239 #define RRD_LEN_MASK 0x00003FFF 1240 #define RRD_LEN_SHIFT 0 1241 #define RRD_TCP_UDPCSUM_NOK 0x00004000 1242 #define RRD_IPCSUM_NOK 0x00008000 1243 #define RRD_VLAN_TAG 0x00010000 1244 #define RRD_PROTO_MASK 0x000E0000 1245 #define RRD_PROTO_IPV4 0x00020000 1246 #define RRD_PROTO_IPV6 0x000C0000 1247 #define RRD_ERR_SUM 0x00100000 1248 #define RRD_ERR_CRC 0x00200000 1249 #define RRD_ERR_ALIGN 0x00400000 1250 #define RRD_ERR_TRUNC 0x00800000 1251 #define RRD_ERR_RUNT 0x01000000 1252 #define RRD_ERR_ICMP 0x02000000 1253 #define RRD_BCAST 0x04000000 1254 #define RRD_MCAST 0x08000000 1255 #define RRD_SNAP_LLC 0x10000000 1256 #define RRD_ETHER 0x00000000 1257 #define RRD_FIFO_FULL 0x20000000 1258 #define RRD_ERR_LENGTH 0x40000000 1259 #define RRD_VALID 0x80000000 1260 #define RRD_BYTES(x) \ 1261 (((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT) 1262 #define RRD_IPV4(x) \ 1263 (((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4) 1264 }; 1265 1266 /* Tx descriptor */ 1267 struct tx_desc { 1268 uint32_t len; 1269 #define TD_BUFLEN_MASK 0x00003FFF 1270 #define TD_VLAN_MASK 0xFFFF0000 1271 #define TD_BUFLEN_SHIFT 0 1272 #define TX_BYTES(x) \ 1273 (((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK) 1274 #define TD_VLAN_SHIFT 16 1275 uint32_t flags; 1276 #define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */ 1277 #define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */ 1278 #define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */ 1279 #define TD_CUSTOM_CSUM 0x00000100 1280 #define TD_IPCSUM 0x00000200 1281 #define TD_TCPCSUM 0x00000400 1282 #define TD_UDPCSUM 0x00000800 1283 #define TD_TSO 0x00001000 1284 #define TD_TSO_DESCV1 0x00000000 1285 #define TD_TSO_DESCV2 0x00002000 1286 #define TD_CON_VLAN_TAG 0x00004000 1287 #define TD_INS_VLAN_TAG 0x00008000 1288 #define TD_IPV4_DESCV2 0x00010000 1289 #define TD_LLC_SNAP 0x00020000 1290 #define TD_ETHERNET 0x00000000 1291 #define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */ 1292 #define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000 1293 #define TD_MSS_MASK 0x7FFC0000 1294 #define TD_EOP 0x80000000 1295 #define TD_L4HDR_OFFSET_SHIFT 0 1296 #define TD_TCPHDR_OFFSET_SHIFT 0 1297 #define TD_PLOAD_OFFSET_SHIFT 0 1298 #define TD_CUSTOM_CSUM_OFFSET_SHIFT 18 1299 #define TD_MSS_SHIFT 18 1300 uint64_t addr; 1301 }; 1302 1303 #endif /* _IF_ALCREG_H */ 1304