1 /* $OpenBSD: if_rumreg.h,v 1.16 2015/06/12 15:47:31 mpi Exp $ */ 2 3 /*- 4 * Copyright (c) 2005, 2006 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2006 Niall O'Higgins <niallo@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define RT2573_TX_DESC_SIZE (sizeof (struct rum_tx_desc)) 21 #define RT2573_RX_DESC_SIZE (sizeof (struct rum_rx_desc)) 22 23 #define RT2573_MCU_CNTL 0x01 24 #define RT2573_WRITE_MAC 0x02 25 #define RT2573_READ_MAC 0x03 26 #define RT2573_WRITE_MULTI_MAC 0x06 27 #define RT2573_READ_MULTI_MAC 0x07 28 #define RT2573_READ_EEPROM 0x09 29 #define RT2573_WRITE_LED 0x0a 30 31 /* 32 * Control and status registers. 33 */ 34 #define RT2573_AIFSN_CSR 0x0400 35 #define RT2573_CWMIN_CSR 0x0404 36 #define RT2573_CWMAX_CSR 0x0408 37 #define RT2573_MCU_CODE_BASE 0x0800 38 #define RT2573_HW_BEACON_BASE0 0x2400 39 #define RT2573_HW_BEACON_BASE1 0x2500 40 #define RT2573_HW_BEACON_BASE2 0x2600 41 #define RT2573_HW_BEACON_BASE3 0x2700 42 #define RT2573_MAC_CSR0 0x3000 43 #define RT2573_MAC_CSR1 0x3004 44 #define RT2573_MAC_CSR2 0x3008 45 #define RT2573_MAC_CSR3 0x300c 46 #define RT2573_MAC_CSR4 0x3010 47 #define RT2573_MAC_CSR5 0x3014 48 #define RT2573_MAC_CSR6 0x3018 49 #define RT2573_MAC_CSR7 0x301c 50 #define RT2573_MAC_CSR8 0x3020 51 #define RT2573_MAC_CSR9 0x3024 52 #define RT2573_MAC_CSR10 0x3028 53 #define RT2573_MAC_CSR11 0x302c 54 #define RT2573_MAC_CSR12 0x3030 55 #define RT2573_MAC_CSR13 0x3034 56 #define RT2573_MAC_CSR14 0x3038 57 #define RT2573_MAC_CSR15 0x303c 58 #define RT2573_TXRX_CSR0 0x3040 59 #define RT2573_TXRX_CSR1 0x3044 60 #define RT2573_TXRX_CSR2 0x3048 61 #define RT2573_TXRX_CSR3 0x304c 62 #define RT2573_TXRX_CSR4 0x3050 63 #define RT2573_TXRX_CSR5 0x3054 64 #define RT2573_TXRX_CSR6 0x3058 65 #define RT2573_TXRX_CSR7 0x305c 66 #define RT2573_TXRX_CSR8 0x3060 67 #define RT2573_TXRX_CSR9 0x3064 68 #define RT2573_TXRX_CSR10 0x3068 69 #define RT2573_TXRX_CSR11 0x306c 70 #define RT2573_TXRX_CSR12 0x3070 71 #define RT2573_TXRX_CSR13 0x3074 72 #define RT2573_TXRX_CSR14 0x3078 73 #define RT2573_TXRX_CSR15 0x307c 74 #define RT2573_PHY_CSR0 0x3080 75 #define RT2573_PHY_CSR1 0x3084 76 #define RT2573_PHY_CSR2 0x3088 77 #define RT2573_PHY_CSR3 0x308c 78 #define RT2573_PHY_CSR4 0x3090 79 #define RT2573_PHY_CSR5 0x3094 80 #define RT2573_PHY_CSR6 0x3098 81 #define RT2573_PHY_CSR7 0x309c 82 #define RT2573_SEC_CSR0 0x30a0 83 #define RT2573_SEC_CSR1 0x30a4 84 #define RT2573_SEC_CSR2 0x30a8 85 #define RT2573_SEC_CSR3 0x30ac 86 #define RT2573_SEC_CSR4 0x30b0 87 #define RT2573_SEC_CSR5 0x30b4 88 #define RT2573_STA_CSR0 0x30c0 89 #define RT2573_STA_CSR1 0x30c4 90 #define RT2573_STA_CSR2 0x30c8 91 #define RT2573_STA_CSR3 0x30cc 92 #define RT2573_STA_CSR4 0x30d0 93 #define RT2573_STA_CSR5 0x30d4 94 95 96 /* possible flags for register RT2573_MAC_CSR1 */ 97 #define RT2573_RESET_ASIC (1 << 0) 98 #define RT2573_RESET_BBP (1 << 1) 99 #define RT2573_HOST_READY (1 << 2) 100 101 /* possible flags for register MAC_CSR5 */ 102 #define RT2573_ONE_BSSID 3 103 104 /* possible flags for register TXRX_CSR0 */ 105 /* Tx filter flags are in the low 16 bits */ 106 #define RT2573_AUTO_TX_SEQ (1 << 15) 107 /* Rx filter flags are in the high 16 bits */ 108 #define RT2573_DISABLE_RX (1 << 16) 109 #define RT2573_DROP_CRC_ERROR (1 << 17) 110 #define RT2573_DROP_PHY_ERROR (1 << 18) 111 #define RT2573_DROP_CTL (1 << 19) 112 #define RT2573_DROP_NOT_TO_ME (1 << 20) 113 #define RT2573_DROP_TODS (1 << 21) 114 #define RT2573_DROP_VER_ERROR (1 << 22) 115 #define RT2573_DROP_MULTICAST (1 << 23) 116 #define RT2573_DROP_BROADCAST (1 << 24) 117 #define RT2573_DROP_ACKCTS (1 << 25) 118 119 /* possible flags for register TXRX_CSR4 */ 120 #define RT2573_SHORT_PREAMBLE (1 << 18) 121 #define RT2573_MRR_ENABLED (1 << 19) 122 #define RT2573_MRR_CCK_FALLBACK (1 << 22) 123 124 /* possible flags for register TXRX_CSR9 */ 125 #define RT2573_TSF_TICKING (1 << 16) 126 #define RT2573_TSF_MODE(x) (((x) & 0x3) << 17) 127 /* TBTT stands for Target Beacon Transmission Time */ 128 #define RT2573_ENABLE_TBTT (1 << 19) 129 #define RT2573_GENERATE_BEACON (1 << 20) 130 131 /* possible flags for register PHY_CSR0 */ 132 #define RT2573_PA_PE_2GHZ (1 << 16) 133 #define RT2573_PA_PE_5GHZ (1 << 17) 134 135 /* possible flags for register PHY_CSR3 */ 136 #define RT2573_BBP_READ (1 << 15) 137 #define RT2573_BBP_BUSY (1 << 16) 138 /* possible flags for register PHY_CSR4 */ 139 #define RT2573_RF_20BIT (20 << 24) 140 #define RT2573_RF_BUSY (1U << 31) 141 142 /* LED values */ 143 #define RT2573_LED_RADIO (1 << 8) 144 #define RT2573_LED_G (1 << 9) 145 #define RT2573_LED_A (1 << 10) 146 #define RT2573_LED_ON 0x1e1e 147 #define RT2573_LED_OFF 0x0 148 149 #define RT2573_MCU_RUN (1 << 3) 150 151 #define RT2573_SMART_MODE (1 << 0) 152 153 #define RT2573_BBPR94_DEFAULT 6 154 155 #define RT2573_BBP_WRITE (1 << 15) 156 157 /* dual-band RF */ 158 #define RT2573_RF_5226 1 159 #define RT2573_RF_5225 3 160 /* single-band RF */ 161 #define RT2573_RF_2528 2 162 #define RT2573_RF_2527 4 163 164 #define RT2573_BBP_VERSION 0 165 166 struct rum_tx_desc { 167 uint32_t flags; 168 #define RT2573_TX_BURST (1 << 0) 169 #define RT2573_TX_VALID (1 << 1) 170 #define RT2573_TX_MORE_FRAG (1 << 2) 171 #define RT2573_TX_NEED_ACK (1 << 3) 172 #define RT2573_TX_TIMESTAMP (1 << 4) 173 #define RT2573_TX_OFDM (1 << 5) 174 #define RT2573_TX_IFS_SIFS (1 << 6) 175 #define RT2573_TX_LONG_RETRY (1 << 7) 176 177 uint16_t wme; 178 #define RT2573_QID(v) (v) 179 #define RT2573_AIFSN(v) ((v) << 4) 180 #define RT2573_LOGCWMIN(v) ((v) << 8) 181 #define RT2573_LOGCWMAX(v) ((v) << 12) 182 183 uint16_t xflags; 184 #define RT2573_TX_HWSEQ (1 << 12) 185 186 uint8_t plcp_signal; 187 uint8_t plcp_service; 188 #define RT2573_PLCP_LENGEXT 0x80 189 190 uint8_t plcp_length_lo; 191 uint8_t plcp_length_hi; 192 193 uint32_t iv; 194 uint32_t eiv; 195 196 uint8_t offset; 197 uint8_t qid; 198 uint8_t txpower; 199 #define RT2573_DEFAULT_TXPOWER 0 200 201 uint8_t reserved; 202 } __packed; 203 204 struct rum_rx_desc { 205 uint32_t flags; 206 #define RT2573_RX_BUSY (1 << 0) 207 #define RT2573_RX_DROP (1 << 1) 208 #define RT2573_RX_CRC_ERROR (1 << 6) 209 #define RT2573_RX_OFDM (1 << 7) 210 211 uint8_t rate; 212 uint8_t rssi; 213 uint8_t reserved1; 214 uint8_t offset; 215 uint32_t iv; 216 uint32_t eiv; 217 uint32_t reserved2[2]; 218 } __packed; 219 220 #define RT2573_RF1 0 221 #define RT2573_RF2 2 222 #define RT2573_RF3 1 223 #define RT2573_RF4 3 224 225 #define RT2573_EEPROM_MACBBP 0x0000 226 #define RT2573_EEPROM_ADDRESS 0x0004 227 #define RT2573_EEPROM_ANTENNA 0x0020 228 #define RT2573_EEPROM_CONFIG2 0x0022 229 #define RT2573_EEPROM_BBP_BASE 0x0026 230 #define RT2573_EEPROM_TXPOWER 0x0046 231 #define RT2573_EEPROM_FREQ_OFFSET 0x005e 232 #define RT2573_EEPROM_RSSI_2GHZ_OFFSET 0x009a 233 #define RT2573_EEPROM_RSSI_5GHZ_OFFSET 0x009c 234 235 /* 236 * Default values for MAC registers; values taken from the reference driver. 237 */ 238 #define RT2573_DEF_MAC \ 239 { RT2573_TXRX_CSR0, 0x025fb032 }, \ 240 { RT2573_TXRX_CSR1, 0x9eaa9eaf }, \ 241 { RT2573_TXRX_CSR2, 0x8a8b8c8d }, \ 242 { RT2573_TXRX_CSR3, 0x00858687 }, \ 243 { RT2573_TXRX_CSR7, 0x2e31353b }, \ 244 { RT2573_TXRX_CSR8, 0x2a2a2a2c }, \ 245 { RT2573_TXRX_CSR15, 0x0000000f }, \ 246 { RT2573_MAC_CSR6, 0x00000fff }, \ 247 { RT2573_MAC_CSR8, 0x016c030a }, \ 248 { RT2573_MAC_CSR10, 0x00000718 }, \ 249 { RT2573_MAC_CSR12, 0x00000004 }, \ 250 { RT2573_MAC_CSR13, 0x00007f00 }, \ 251 { RT2573_SEC_CSR0, 0x00000000 }, \ 252 { RT2573_SEC_CSR1, 0x00000000 }, \ 253 { RT2573_SEC_CSR5, 0x00000000 }, \ 254 { RT2573_PHY_CSR1, 0x000023b0 }, \ 255 { RT2573_PHY_CSR5, 0x00040a06 }, \ 256 { RT2573_PHY_CSR6, 0x00080606 }, \ 257 { RT2573_PHY_CSR7, 0x00000408 }, \ 258 { RT2573_AIFSN_CSR, 0x00002273 }, \ 259 { RT2573_CWMIN_CSR, 0x00002344 }, \ 260 { RT2573_CWMAX_CSR, 0x000034aa }, \ 261 { RT2573_HW_BEACON_BASE0, 0x00000000 }, \ 262 { RT2573_HW_BEACON_BASE1, 0x00000000 }, \ 263 { RT2573_HW_BEACON_BASE2, 0x00000000 }, \ 264 { RT2573_HW_BEACON_BASE3, 0x00000000 } 265 266 /* 267 * Default values for BBP registers; values taken from the reference driver. 268 */ 269 #define RT2573_DEF_BBP \ 270 { 3, 0x80 }, \ 271 { 15, 0x30 }, \ 272 { 17, 0x20 }, \ 273 { 21, 0xc8 }, \ 274 { 22, 0x38 }, \ 275 { 23, 0x06 }, \ 276 { 24, 0xfe }, \ 277 { 25, 0x0a }, \ 278 { 26, 0x0d }, \ 279 { 32, 0x0b }, \ 280 { 34, 0x12 }, \ 281 { 37, 0x07 }, \ 282 { 39, 0xf8 }, \ 283 { 41, 0x60 }, \ 284 { 53, 0x10 }, \ 285 { 54, 0x18 }, \ 286 { 60, 0x10 }, \ 287 { 61, 0x04 }, \ 288 { 62, 0x04 }, \ 289 { 75, 0xfe }, \ 290 { 86, 0xfe }, \ 291 { 88, 0xfe }, \ 292 { 90, 0x0f }, \ 293 { 99, 0x00 }, \ 294 { 102, 0x16 }, \ 295 { 107, 0x04 } 296 297 /* 298 * Default settings for RF registers; values taken from the reference driver. 299 */ 300 #define RT2573_RF5226 \ 301 { 1, 0x00b03, 0x001e1, 0x1a014, 0x30282 }, \ 302 { 2, 0x00b03, 0x001e1, 0x1a014, 0x30287 }, \ 303 { 3, 0x00b03, 0x001e2, 0x1a014, 0x30282 }, \ 304 { 4, 0x00b03, 0x001e2, 0x1a014, 0x30287 }, \ 305 { 5, 0x00b03, 0x001e3, 0x1a014, 0x30282 }, \ 306 { 6, 0x00b03, 0x001e3, 0x1a014, 0x30287 }, \ 307 { 7, 0x00b03, 0x001e4, 0x1a014, 0x30282 }, \ 308 { 8, 0x00b03, 0x001e4, 0x1a014, 0x30287 }, \ 309 { 9, 0x00b03, 0x001e5, 0x1a014, 0x30282 }, \ 310 { 10, 0x00b03, 0x001e5, 0x1a014, 0x30287 }, \ 311 { 11, 0x00b03, 0x001e6, 0x1a014, 0x30282 }, \ 312 { 12, 0x00b03, 0x001e6, 0x1a014, 0x30287 }, \ 313 { 13, 0x00b03, 0x001e7, 0x1a014, 0x30282 }, \ 314 { 14, 0x00b03, 0x001e8, 0x1a014, 0x30284 }, \ 315 \ 316 { 34, 0x00b03, 0x20266, 0x36014, 0x30282 }, \ 317 { 38, 0x00b03, 0x20267, 0x36014, 0x30284 }, \ 318 { 42, 0x00b03, 0x20268, 0x36014, 0x30286 }, \ 319 { 46, 0x00b03, 0x20269, 0x36014, 0x30288 }, \ 320 \ 321 { 36, 0x00b03, 0x00266, 0x26014, 0x30288 }, \ 322 { 40, 0x00b03, 0x00268, 0x26014, 0x30280 }, \ 323 { 44, 0x00b03, 0x00269, 0x26014, 0x30282 }, \ 324 { 48, 0x00b03, 0x0026a, 0x26014, 0x30284 }, \ 325 { 52, 0x00b03, 0x0026b, 0x26014, 0x30286 }, \ 326 { 56, 0x00b03, 0x0026c, 0x26014, 0x30288 }, \ 327 { 60, 0x00b03, 0x0026e, 0x26014, 0x30280 }, \ 328 { 64, 0x00b03, 0x0026f, 0x26014, 0x30282 }, \ 329 \ 330 { 100, 0x00b03, 0x0028a, 0x2e014, 0x30280 }, \ 331 { 104, 0x00b03, 0x0028b, 0x2e014, 0x30282 }, \ 332 { 108, 0x00b03, 0x0028c, 0x2e014, 0x30284 }, \ 333 { 112, 0x00b03, 0x0028d, 0x2e014, 0x30286 }, \ 334 { 116, 0x00b03, 0x0028e, 0x2e014, 0x30288 }, \ 335 { 120, 0x00b03, 0x002a0, 0x2e014, 0x30280 }, \ 336 { 124, 0x00b03, 0x002a1, 0x2e014, 0x30282 }, \ 337 { 128, 0x00b03, 0x002a2, 0x2e014, 0x30284 }, \ 338 { 132, 0x00b03, 0x002a3, 0x2e014, 0x30286 }, \ 339 { 136, 0x00b03, 0x002a4, 0x2e014, 0x30288 }, \ 340 { 140, 0x00b03, 0x002a6, 0x2e014, 0x30280 }, \ 341 \ 342 { 149, 0x00b03, 0x002a8, 0x2e014, 0x30287 }, \ 343 { 153, 0x00b03, 0x002a9, 0x2e014, 0x30289 }, \ 344 { 157, 0x00b03, 0x002ab, 0x2e014, 0x30281 }, \ 345 { 161, 0x00b03, 0x002ac, 0x2e014, 0x30283 }, \ 346 { 165, 0x00b03, 0x002ad, 0x2e014, 0x30285 } 347 348 #define RT2573_RF5225 \ 349 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \ 350 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \ 351 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \ 352 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \ 353 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \ 354 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \ 355 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \ 356 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \ 357 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \ 358 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \ 359 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \ 360 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \ 361 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \ 362 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \ 363 \ 364 { 34, 0x00b33, 0x01266, 0x26014, 0x30282 }, \ 365 { 38, 0x00b33, 0x01267, 0x26014, 0x30284 }, \ 366 { 42, 0x00b33, 0x01268, 0x26014, 0x30286 }, \ 367 { 46, 0x00b33, 0x01269, 0x26014, 0x30288 }, \ 368 \ 369 { 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, \ 370 { 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, \ 371 { 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, \ 372 { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, \ 373 { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, \ 374 { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, \ 375 { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, \ 376 { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, \ 377 \ 378 { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, \ 379 { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, \ 380 { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, \ 381 { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, \ 382 { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, \ 383 { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, \ 384 { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, \ 385 { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, \ 386 { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, \ 387 { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, \ 388 { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, \ 389 \ 390 { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, \ 391 { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, \ 392 { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, \ 393 { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, \ 394 { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 } 395