1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 * Copyright(c) 2020-2022 Realtek Corporation
3 */
4
5 #ifndef __RTW89_CHAN_H__
6 #define __RTW89_CHAN_H__
7
8 #include "core.h"
9
10 /* The dwell time in TU before doing rtw89_chanctx_work(). */
11 #define RTW89_CHANCTX_TIME_MCC_PREPARE 100
12 #define RTW89_CHANCTX_TIME_MCC 100
13
14 /* various MCC setting time in TU */
15 #define RTW89_MCC_LONG_TRIGGER_TIME 300
16 #define RTW89_MCC_SHORT_TRIGGER_TIME 100
17 #define RTW89_MCC_EARLY_TX_BCN_TIME 10
18 #define RTW89_MCC_EARLY_RX_BCN_TIME 5
19 #define RTW89_MCC_MIN_RX_BCN_TIME 10
20 #define RTW89_MCC_DFLT_BCN_OFST_TIME 40
21
22 #define RTW89_MCC_MIN_GO_DURATION \
23 (RTW89_MCC_EARLY_TX_BCN_TIME + RTW89_MCC_MIN_RX_BCN_TIME)
24
25 #define RTW89_MCC_MIN_STA_DURATION \
26 (RTW89_MCC_EARLY_RX_BCN_TIME + RTW89_MCC_MIN_RX_BCN_TIME)
27
28 #define RTW89_MCC_DFLT_GROUP 0
29 #define RTW89_MCC_NEXT_GROUP(cur) (((cur) + 1) % 4)
30
31 #define RTW89_MCC_DFLT_TX_NULL_EARLY 3
32 #define RTW89_MCC_DFLT_COURTESY_SLOT 3
33
34 #define NUM_OF_RTW89_MCC_ROLES 2
35
36 enum rtw89_chanctx_pause_reasons {
37 RTW89_CHANCTX_PAUSE_REASON_HW_SCAN,
38 RTW89_CHANCTX_PAUSE_REASON_ROC,
39 };
40
41 struct rtw89_entity_weight {
42 unsigned int active_chanctxs;
43 unsigned int active_roles;
44 };
45
rtw89_get_entity_state(struct rtw89_dev * rtwdev)46 static inline bool rtw89_get_entity_state(struct rtw89_dev *rtwdev)
47 {
48 struct rtw89_hal *hal = &rtwdev->hal;
49
50 return READ_ONCE(hal->entity_active);
51 }
52
rtw89_set_entity_state(struct rtw89_dev * rtwdev,bool active)53 static inline void rtw89_set_entity_state(struct rtw89_dev *rtwdev, bool active)
54 {
55 struct rtw89_hal *hal = &rtwdev->hal;
56
57 WRITE_ONCE(hal->entity_active, active);
58 }
59
60 static inline
rtw89_get_entity_mode(struct rtw89_dev * rtwdev)61 enum rtw89_entity_mode rtw89_get_entity_mode(struct rtw89_dev *rtwdev)
62 {
63 struct rtw89_hal *hal = &rtwdev->hal;
64
65 return READ_ONCE(hal->entity_mode);
66 }
67
rtw89_set_entity_mode(struct rtw89_dev * rtwdev,enum rtw89_entity_mode mode)68 static inline void rtw89_set_entity_mode(struct rtw89_dev *rtwdev,
69 enum rtw89_entity_mode mode)
70 {
71 struct rtw89_hal *hal = &rtwdev->hal;
72
73 WRITE_ONCE(hal->entity_mode, mode);
74 }
75
76 void rtw89_chan_create(struct rtw89_chan *chan, u8 center_chan, u8 primary_chan,
77 enum rtw89_band band, enum rtw89_bandwidth bandwidth);
78 bool rtw89_assign_entity_chan(struct rtw89_dev *rtwdev,
79 enum rtw89_sub_entity_idx idx,
80 const struct rtw89_chan *new);
81 void rtw89_config_entity_chandef(struct rtw89_dev *rtwdev,
82 enum rtw89_sub_entity_idx idx,
83 const struct cfg80211_chan_def *chandef);
84 void rtw89_config_roc_chandef(struct rtw89_dev *rtwdev,
85 enum rtw89_sub_entity_idx idx,
86 const struct cfg80211_chan_def *chandef);
87 void rtw89_entity_init(struct rtw89_dev *rtwdev);
88 enum rtw89_entity_mode rtw89_entity_recalc(struct rtw89_dev *rtwdev);
89 void rtw89_chanctx_work(struct work_struct *work);
90 void rtw89_queue_chanctx_work(struct rtw89_dev *rtwdev);
91 void rtw89_queue_chanctx_change(struct rtw89_dev *rtwdev,
92 enum rtw89_chanctx_changes change);
93 void rtw89_chanctx_track(struct rtw89_dev *rtwdev);
94 void rtw89_chanctx_pause(struct rtw89_dev *rtwdev,
95 enum rtw89_chanctx_pause_reasons rsn);
96 void rtw89_chanctx_proceed(struct rtw89_dev *rtwdev);
97 int rtw89_chanctx_ops_add(struct rtw89_dev *rtwdev,
98 struct ieee80211_chanctx_conf *ctx);
99 void rtw89_chanctx_ops_remove(struct rtw89_dev *rtwdev,
100 struct ieee80211_chanctx_conf *ctx);
101 void rtw89_chanctx_ops_change(struct rtw89_dev *rtwdev,
102 struct ieee80211_chanctx_conf *ctx,
103 u32 changed);
104 int rtw89_chanctx_ops_assign_vif(struct rtw89_dev *rtwdev,
105 struct rtw89_vif *rtwvif,
106 struct ieee80211_chanctx_conf *ctx);
107 void rtw89_chanctx_ops_unassign_vif(struct rtw89_dev *rtwdev,
108 struct rtw89_vif *rtwvif,
109 struct ieee80211_chanctx_conf *ctx);
110
111 #endif
112