1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_CORE_H__
6 #define __RTW89_CORE_H__
7
8 #include <linux/average.h>
9 #include <linux/bitfield.h>
10 #include <linux/dmi.h>
11 #include <linux/firmware.h>
12 #include <linux/iopoll.h>
13 #include <linux/workqueue.h>
14 #include <net/mac80211.h>
15
16 struct rtw89_dev;
17 struct rtw89_pci_info;
18 struct rtw89_mac_gen_def;
19 struct rtw89_phy_gen_def;
20 struct rtw89_efuse_block_cfg;
21 struct rtw89_h2c_rf_tssi;
22 struct rtw89_fw_txpwr_track_cfg;
23 struct rtw89_phy_rfk_log_fmt;
24
25 extern const struct ieee80211_ops rtw89_ops;
26
27 #define MASKBYTE0 0xff
28 #define MASKBYTE1 0xff00
29 #define MASKBYTE2 0xff0000
30 #define MASKBYTE3 0xff000000
31 #define MASKBYTE4 0xff00000000ULL
32 #define MASKHWORD 0xffff0000
33 #define MASKLWORD 0x0000ffff
34 #define MASKDWORD 0xffffffff
35 #define RFREG_MASK 0xfffff
36 #define INV_RF_DATA 0xffffffff
37 #define BYPASS_CR_DATA 0xbabecafe
38
39 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2)
40 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
41 #define CFO_TRACK_MAX_USER 64
42 #define MAX_RSSI 110
43 #define RSSI_FACTOR 1
44 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
45 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
46 #define DELTA_SWINGIDX_SIZE 30
47
48 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he)
49 #define RTW89_RADIOTAP_ROOM_EHT \
50 (sizeof(struct ieee80211_radiotap_tlv) + \
51 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \
52 sizeof(struct ieee80211_radiotap_tlv) + \
53 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4))
54 #define RTW89_RADIOTAP_ROOM \
55 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64)
56
57 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
58 #define RTW89_HTC_VARIANT_HE 3
59 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
60 #define RTW89_HTC_VARIANT_HE_CID_OM 1
61 #define RTW89_HTC_VARIANT_HE_CID_CAS 6
62 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
63
64 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
65 enum htc_om_channel_width {
66 HTC_OM_CHANNEL_WIDTH_20 = 0,
67 HTC_OM_CHANNEL_WIDTH_40 = 1,
68 HTC_OM_CHANNEL_WIDTH_80 = 2,
69 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
70 };
71 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
72 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
73 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
74 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
75 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
76 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
77
78 #define RTW89_TF_PAD GENMASK(11, 0)
79 #define RTW89_TF_BASIC_USER_INFO_SZ 6
80
81 #define RTW89_GET_TF_USER_INFO_AID12(data) \
82 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
83 #define RTW89_GET_TF_USER_INFO_RUA(data) \
84 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))
85 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \
86 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))
87
88 enum rtw89_subband {
89 RTW89_CH_2G = 0,
90 RTW89_CH_5G_BAND_1 = 1,
91 /* RTW89_CH_5G_BAND_2 = 2, unused */
92 RTW89_CH_5G_BAND_3 = 3,
93 RTW89_CH_5G_BAND_4 = 4,
94
95 RTW89_CH_6G_BAND_IDX0, /* Low */
96 RTW89_CH_6G_BAND_IDX1, /* Low */
97 RTW89_CH_6G_BAND_IDX2, /* Mid */
98 RTW89_CH_6G_BAND_IDX3, /* Mid */
99 RTW89_CH_6G_BAND_IDX4, /* High */
100 RTW89_CH_6G_BAND_IDX5, /* High */
101 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
102 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
103
104 RTW89_SUBBAND_NR,
105 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
106 };
107
108 enum rtw89_gain_offset {
109 RTW89_GAIN_OFFSET_2G_CCK,
110 RTW89_GAIN_OFFSET_2G_OFDM,
111 RTW89_GAIN_OFFSET_5G_LOW,
112 RTW89_GAIN_OFFSET_5G_MID,
113 RTW89_GAIN_OFFSET_5G_HIGH,
114 RTW89_GAIN_OFFSET_6G_L0,
115 RTW89_GAIN_OFFSET_6G_L1,
116 RTW89_GAIN_OFFSET_6G_M0,
117 RTW89_GAIN_OFFSET_6G_M1,
118 RTW89_GAIN_OFFSET_6G_H0,
119 RTW89_GAIN_OFFSET_6G_H1,
120 RTW89_GAIN_OFFSET_6G_UH0,
121 RTW89_GAIN_OFFSET_6G_UH1,
122
123 RTW89_GAIN_OFFSET_NR,
124 };
125
126 enum rtw89_hci_type {
127 RTW89_HCI_TYPE_PCIE,
128 RTW89_HCI_TYPE_USB,
129 RTW89_HCI_TYPE_SDIO,
130 };
131
132 enum rtw89_core_chip_id {
133 RTL8852A,
134 RTL8852B,
135 RTL8852C,
136 RTL8851B,
137 RTL8922A,
138 };
139
140 enum rtw89_chip_gen {
141 RTW89_CHIP_AX,
142 RTW89_CHIP_BE,
143
144 RTW89_CHIP_GEN_NUM,
145 };
146
147 enum rtw89_cv {
148 CHIP_CAV,
149 CHIP_CBV,
150 CHIP_CCV,
151 CHIP_CDV,
152 CHIP_CEV,
153 CHIP_CFV,
154 CHIP_CV_MAX,
155 CHIP_CV_INVALID = CHIP_CV_MAX,
156 };
157
158 enum rtw89_bacam_ver {
159 RTW89_BACAM_V0,
160 RTW89_BACAM_V1,
161
162 RTW89_BACAM_V0_EXT = 99,
163 };
164
165 enum rtw89_core_tx_type {
166 RTW89_CORE_TX_TYPE_DATA,
167 RTW89_CORE_TX_TYPE_MGMT,
168 RTW89_CORE_TX_TYPE_FWCMD,
169 };
170
171 enum rtw89_core_rx_type {
172 RTW89_CORE_RX_TYPE_WIFI = 0,
173 RTW89_CORE_RX_TYPE_PPDU_STAT = 1,
174 RTW89_CORE_RX_TYPE_CHAN_INFO = 2,
175 RTW89_CORE_RX_TYPE_BB_SCOPE = 3,
176 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4,
177 RTW89_CORE_RX_TYPE_SS2FW = 5,
178 RTW89_CORE_RX_TYPE_TX_REPORT = 6,
179 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7,
180 RTW89_CORE_RX_TYPE_DFS_REPORT = 8,
181 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9,
182 RTW89_CORE_RX_TYPE_C2H = 10,
183 RTW89_CORE_RX_TYPE_CSI = 11,
184 RTW89_CORE_RX_TYPE_CQI = 12,
185 RTW89_CORE_RX_TYPE_H2C = 13,
186 RTW89_CORE_RX_TYPE_FWDL = 14,
187 };
188
189 enum rtw89_txq_flags {
190 RTW89_TXQ_F_AMPDU = 0,
191 RTW89_TXQ_F_BLOCK_BA = 1,
192 RTW89_TXQ_F_FORBID_BA = 2,
193 };
194
195 enum rtw89_net_type {
196 RTW89_NET_TYPE_NO_LINK = 0,
197 RTW89_NET_TYPE_AD_HOC = 1,
198 RTW89_NET_TYPE_INFRA = 2,
199 RTW89_NET_TYPE_AP_MODE = 3,
200 };
201
202 enum rtw89_wifi_role {
203 RTW89_WIFI_ROLE_NONE,
204 RTW89_WIFI_ROLE_STATION,
205 RTW89_WIFI_ROLE_AP,
206 RTW89_WIFI_ROLE_AP_VLAN,
207 RTW89_WIFI_ROLE_ADHOC,
208 RTW89_WIFI_ROLE_ADHOC_MASTER,
209 RTW89_WIFI_ROLE_MESH_POINT,
210 RTW89_WIFI_ROLE_MONITOR,
211 RTW89_WIFI_ROLE_P2P_DEVICE,
212 RTW89_WIFI_ROLE_P2P_CLIENT,
213 RTW89_WIFI_ROLE_P2P_GO,
214 RTW89_WIFI_ROLE_NAN,
215 RTW89_WIFI_ROLE_MLME_MAX
216 };
217
218 enum rtw89_upd_mode {
219 RTW89_ROLE_CREATE,
220 RTW89_ROLE_REMOVE,
221 RTW89_ROLE_TYPE_CHANGE,
222 RTW89_ROLE_INFO_CHANGE,
223 RTW89_ROLE_CON_DISCONN,
224 RTW89_ROLE_BAND_SW,
225 RTW89_ROLE_FW_RESTORE,
226 };
227
228 enum rtw89_self_role {
229 RTW89_SELF_ROLE_CLIENT,
230 RTW89_SELF_ROLE_AP,
231 RTW89_SELF_ROLE_AP_CLIENT
232 };
233
234 enum rtw89_msk_sO_el {
235 RTW89_NO_MSK,
236 RTW89_SMA,
237 RTW89_TMA,
238 RTW89_BSSID
239 };
240
241 enum rtw89_sch_tx_sel {
242 RTW89_SCH_TX_SEL_ALL,
243 RTW89_SCH_TX_SEL_HIQ,
244 RTW89_SCH_TX_SEL_MG0,
245 RTW89_SCH_TX_SEL_MACID,
246 };
247
248 /* RTW89_ADDR_CAM_SEC_NONE : not enabled
249 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
250 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
251 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
252 */
253 enum rtw89_add_cam_sec_mode {
254 RTW89_ADDR_CAM_SEC_NONE = 0,
255 RTW89_ADDR_CAM_SEC_ALL_UNI = 1,
256 RTW89_ADDR_CAM_SEC_NORMAL = 2,
257 RTW89_ADDR_CAM_SEC_4GROUP = 3,
258 };
259
260 enum rtw89_sec_key_type {
261 RTW89_SEC_KEY_TYPE_NONE = 0,
262 RTW89_SEC_KEY_TYPE_WEP40 = 1,
263 RTW89_SEC_KEY_TYPE_WEP104 = 2,
264 RTW89_SEC_KEY_TYPE_TKIP = 3,
265 RTW89_SEC_KEY_TYPE_WAPI = 4,
266 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5,
267 RTW89_SEC_KEY_TYPE_CCMP128 = 6,
268 RTW89_SEC_KEY_TYPE_CCMP256 = 7,
269 RTW89_SEC_KEY_TYPE_GCMP128 = 8,
270 RTW89_SEC_KEY_TYPE_GCMP256 = 9,
271 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10,
272 };
273
274 enum rtw89_port {
275 RTW89_PORT_0 = 0,
276 RTW89_PORT_1 = 1,
277 RTW89_PORT_2 = 2,
278 RTW89_PORT_3 = 3,
279 RTW89_PORT_4 = 4,
280 RTW89_PORT_NUM
281 };
282
283 enum rtw89_band {
284 RTW89_BAND_2G = 0,
285 RTW89_BAND_5G = 1,
286 RTW89_BAND_6G = 2,
287 RTW89_BAND_NUM,
288 };
289
290 enum rtw89_hw_rate {
291 RTW89_HW_RATE_CCK1 = 0x0,
292 RTW89_HW_RATE_CCK2 = 0x1,
293 RTW89_HW_RATE_CCK5_5 = 0x2,
294 RTW89_HW_RATE_CCK11 = 0x3,
295 RTW89_HW_RATE_OFDM6 = 0x4,
296 RTW89_HW_RATE_OFDM9 = 0x5,
297 RTW89_HW_RATE_OFDM12 = 0x6,
298 RTW89_HW_RATE_OFDM18 = 0x7,
299 RTW89_HW_RATE_OFDM24 = 0x8,
300 RTW89_HW_RATE_OFDM36 = 0x9,
301 RTW89_HW_RATE_OFDM48 = 0xA,
302 RTW89_HW_RATE_OFDM54 = 0xB,
303 RTW89_HW_RATE_MCS0 = 0x80,
304 RTW89_HW_RATE_MCS1 = 0x81,
305 RTW89_HW_RATE_MCS2 = 0x82,
306 RTW89_HW_RATE_MCS3 = 0x83,
307 RTW89_HW_RATE_MCS4 = 0x84,
308 RTW89_HW_RATE_MCS5 = 0x85,
309 RTW89_HW_RATE_MCS6 = 0x86,
310 RTW89_HW_RATE_MCS7 = 0x87,
311 RTW89_HW_RATE_MCS8 = 0x88,
312 RTW89_HW_RATE_MCS9 = 0x89,
313 RTW89_HW_RATE_MCS10 = 0x8A,
314 RTW89_HW_RATE_MCS11 = 0x8B,
315 RTW89_HW_RATE_MCS12 = 0x8C,
316 RTW89_HW_RATE_MCS13 = 0x8D,
317 RTW89_HW_RATE_MCS14 = 0x8E,
318 RTW89_HW_RATE_MCS15 = 0x8F,
319 RTW89_HW_RATE_MCS16 = 0x90,
320 RTW89_HW_RATE_MCS17 = 0x91,
321 RTW89_HW_RATE_MCS18 = 0x92,
322 RTW89_HW_RATE_MCS19 = 0x93,
323 RTW89_HW_RATE_MCS20 = 0x94,
324 RTW89_HW_RATE_MCS21 = 0x95,
325 RTW89_HW_RATE_MCS22 = 0x96,
326 RTW89_HW_RATE_MCS23 = 0x97,
327 RTW89_HW_RATE_MCS24 = 0x98,
328 RTW89_HW_RATE_MCS25 = 0x99,
329 RTW89_HW_RATE_MCS26 = 0x9A,
330 RTW89_HW_RATE_MCS27 = 0x9B,
331 RTW89_HW_RATE_MCS28 = 0x9C,
332 RTW89_HW_RATE_MCS29 = 0x9D,
333 RTW89_HW_RATE_MCS30 = 0x9E,
334 RTW89_HW_RATE_MCS31 = 0x9F,
335 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100,
336 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101,
337 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102,
338 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103,
339 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104,
340 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105,
341 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106,
342 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107,
343 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108,
344 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109,
345 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110,
346 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111,
347 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112,
348 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113,
349 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114,
350 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115,
351 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116,
352 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117,
353 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118,
354 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119,
355 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120,
356 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121,
357 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122,
358 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123,
359 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124,
360 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125,
361 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126,
362 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127,
363 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128,
364 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129,
365 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130,
366 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131,
367 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132,
368 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133,
369 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134,
370 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135,
371 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136,
372 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137,
373 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138,
374 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139,
375 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180,
376 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181,
377 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182,
378 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183,
379 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184,
380 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185,
381 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186,
382 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187,
383 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188,
384 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189,
385 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A,
386 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B,
387 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190,
388 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191,
389 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192,
390 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193,
391 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194,
392 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195,
393 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196,
394 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197,
395 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198,
396 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199,
397 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A,
398 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B,
399 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0,
400 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1,
401 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2,
402 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3,
403 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4,
404 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5,
405 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6,
406 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7,
407 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8,
408 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9,
409 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA,
410 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB,
411 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0,
412 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1,
413 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2,
414 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3,
415 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4,
416 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5,
417 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6,
418 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7,
419 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8,
420 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9,
421 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA,
422 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB,
423
424 RTW89_HW_RATE_V1_MCS0 = 0x100,
425 RTW89_HW_RATE_V1_MCS1 = 0x101,
426 RTW89_HW_RATE_V1_MCS2 = 0x102,
427 RTW89_HW_RATE_V1_MCS3 = 0x103,
428 RTW89_HW_RATE_V1_MCS4 = 0x104,
429 RTW89_HW_RATE_V1_MCS5 = 0x105,
430 RTW89_HW_RATE_V1_MCS6 = 0x106,
431 RTW89_HW_RATE_V1_MCS7 = 0x107,
432 RTW89_HW_RATE_V1_MCS8 = 0x108,
433 RTW89_HW_RATE_V1_MCS9 = 0x109,
434 RTW89_HW_RATE_V1_MCS10 = 0x10A,
435 RTW89_HW_RATE_V1_MCS11 = 0x10B,
436 RTW89_HW_RATE_V1_MCS12 = 0x10C,
437 RTW89_HW_RATE_V1_MCS13 = 0x10D,
438 RTW89_HW_RATE_V1_MCS14 = 0x10E,
439 RTW89_HW_RATE_V1_MCS15 = 0x10F,
440 RTW89_HW_RATE_V1_MCS16 = 0x110,
441 RTW89_HW_RATE_V1_MCS17 = 0x111,
442 RTW89_HW_RATE_V1_MCS18 = 0x112,
443 RTW89_HW_RATE_V1_MCS19 = 0x113,
444 RTW89_HW_RATE_V1_MCS20 = 0x114,
445 RTW89_HW_RATE_V1_MCS21 = 0x115,
446 RTW89_HW_RATE_V1_MCS22 = 0x116,
447 RTW89_HW_RATE_V1_MCS23 = 0x117,
448 RTW89_HW_RATE_V1_MCS24 = 0x118,
449 RTW89_HW_RATE_V1_MCS25 = 0x119,
450 RTW89_HW_RATE_V1_MCS26 = 0x11A,
451 RTW89_HW_RATE_V1_MCS27 = 0x11B,
452 RTW89_HW_RATE_V1_MCS28 = 0x11C,
453 RTW89_HW_RATE_V1_MCS29 = 0x11D,
454 RTW89_HW_RATE_V1_MCS30 = 0x11E,
455 RTW89_HW_RATE_V1_MCS31 = 0x11F,
456 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200,
457 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201,
458 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202,
459 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203,
460 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204,
461 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205,
462 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206,
463 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207,
464 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208,
465 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209,
466 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A,
467 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B,
468 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220,
469 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221,
470 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222,
471 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223,
472 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224,
473 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225,
474 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226,
475 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227,
476 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228,
477 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229,
478 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A,
479 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B,
480 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240,
481 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241,
482 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242,
483 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243,
484 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244,
485 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245,
486 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246,
487 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247,
488 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248,
489 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249,
490 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A,
491 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B,
492 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260,
493 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261,
494 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262,
495 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263,
496 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264,
497 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265,
498 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266,
499 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267,
500 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268,
501 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269,
502 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A,
503 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B,
504 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300,
505 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301,
506 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302,
507 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303,
508 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304,
509 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305,
510 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306,
511 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307,
512 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308,
513 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309,
514 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A,
515 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B,
516 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320,
517 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321,
518 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322,
519 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323,
520 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324,
521 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325,
522 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326,
523 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327,
524 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328,
525 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329,
526 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A,
527 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B,
528 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340,
529 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341,
530 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342,
531 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343,
532 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344,
533 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345,
534 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346,
535 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347,
536 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348,
537 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349,
538 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A,
539 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B,
540 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360,
541 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361,
542 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362,
543 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363,
544 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364,
545 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365,
546 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366,
547 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367,
548 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368,
549 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369,
550 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A,
551 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B,
552 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400,
553 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401,
554 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402,
555 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403,
556 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404,
557 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405,
558 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406,
559 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407,
560 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408,
561 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409,
562 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A,
563 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B,
564 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C,
565 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D,
566 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E,
567 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F,
568 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420,
569 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421,
570 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422,
571 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423,
572 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424,
573 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425,
574 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426,
575 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427,
576 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428,
577 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429,
578 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A,
579 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B,
580 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C,
581 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D,
582 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440,
583 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441,
584 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442,
585 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443,
586 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444,
587 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445,
588 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446,
589 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447,
590 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448,
591 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449,
592 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A,
593 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B,
594 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C,
595 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D,
596 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460,
597 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461,
598 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462,
599 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463,
600 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464,
601 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465,
602 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466,
603 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467,
604 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468,
605 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469,
606 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A,
607 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B,
608 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C,
609 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D,
610
611 RTW89_HW_RATE_NR,
612 RTW89_HW_RATE_INVAL,
613
614 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
615 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
616 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8),
617 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),
618 };
619
620 /* 2G channels,
621 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
622 */
623 #define RTW89_2G_CH_NUM 14
624
625 /* 5G channels,
626 * 36, 38, 40, 42, 44, 46, 48, 50,
627 * 52, 54, 56, 58, 60, 62, 64,
628 * 100, 102, 104, 106, 108, 110, 112, 114,
629 * 116, 118, 120, 122, 124, 126, 128, 130,
630 * 132, 134, 136, 138, 140, 142, 144,
631 * 149, 151, 153, 155, 157, 159, 161, 163,
632 * 165, 167, 169, 171, 173, 175, 177
633 */
634 #define RTW89_5G_CH_NUM 53
635
636 /* 6G channels,
637 * 1, 3, 5, 7, 9, 11, 13, 15,
638 * 17, 19, 21, 23, 25, 27, 29, 33,
639 * 35, 37, 39, 41, 43, 45, 47, 49,
640 * 51, 53, 55, 57, 59, 61, 65, 67,
641 * 69, 71, 73, 75, 77, 79, 81, 83,
642 * 85, 87, 89, 91, 93, 97, 99, 101,
643 * 103, 105, 107, 109, 111, 113, 115, 117,
644 * 119, 121, 123, 125, 129, 131, 133, 135,
645 * 137, 139, 141, 143, 145, 147, 149, 151,
646 * 153, 155, 157, 161, 163, 165, 167, 169,
647 * 171, 173, 175, 177, 179, 181, 183, 185,
648 * 187, 189, 193, 195, 197, 199, 201, 203,
649 * 205, 207, 209, 211, 213, 215, 217, 219,
650 * 221, 225, 227, 229, 231, 233, 235, 237,
651 * 239, 241, 243, 245, 247, 249, 251, 253,
652 */
653 #define RTW89_6G_CH_NUM 120
654
655 enum rtw89_rate_section {
656 RTW89_RS_CCK,
657 RTW89_RS_OFDM,
658 RTW89_RS_MCS, /* for HT/VHT/HE */
659 RTW89_RS_HEDCM,
660 RTW89_RS_OFFSET,
661 RTW89_RS_NUM,
662 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
663 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
664 };
665
666 enum rtw89_rate_offset_indexes {
667 RTW89_RATE_OFFSET_HE,
668 RTW89_RATE_OFFSET_VHT,
669 RTW89_RATE_OFFSET_HT,
670 RTW89_RATE_OFFSET_OFDM,
671 RTW89_RATE_OFFSET_CCK,
672 RTW89_RATE_OFFSET_DLRU_EHT,
673 RTW89_RATE_OFFSET_DLRU_HE,
674 RTW89_RATE_OFFSET_EHT,
675 __RTW89_RATE_OFFSET_NUM,
676
677 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1,
678 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1,
679 };
680
681 enum rtw89_rate_num {
682 RTW89_RATE_CCK_NUM = 4,
683 RTW89_RATE_OFDM_NUM = 8,
684 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */
685
686 RTW89_RATE_MCS_NUM_AX = 12,
687 RTW89_RATE_MCS_NUM_BE = 16,
688 __RTW89_RATE_MCS_NUM = 16,
689 };
690
691 enum rtw89_nss {
692 RTW89_NSS_1 = 0,
693 RTW89_NSS_2 = 1,
694 /* HE DCM only support 1ss and 2ss */
695 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1,
696 RTW89_NSS_3 = 2,
697 RTW89_NSS_4 = 3,
698 RTW89_NSS_NUM,
699 };
700
701 enum rtw89_ntx {
702 RTW89_1TX = 0,
703 RTW89_2TX = 1,
704 RTW89_NTX_NUM,
705 };
706
707 enum rtw89_beamforming_type {
708 RTW89_NONBF = 0,
709 RTW89_BF = 1,
710 RTW89_BF_NUM,
711 };
712
713 enum rtw89_ofdma_type {
714 RTW89_NON_OFDMA = 0,
715 RTW89_OFDMA = 1,
716 RTW89_OFDMA_NUM,
717 };
718
719 enum rtw89_regulation_type {
720 RTW89_WW = 0,
721 RTW89_ETSI = 1,
722 RTW89_FCC = 2,
723 RTW89_MKK = 3,
724 RTW89_NA = 4,
725 RTW89_IC = 5,
726 RTW89_KCC = 6,
727 RTW89_ACMA = 7,
728 RTW89_NCC = 8,
729 RTW89_MEXICO = 9,
730 RTW89_CHILE = 10,
731 RTW89_UKRAINE = 11,
732 RTW89_CN = 12,
733 RTW89_QATAR = 13,
734 RTW89_UK = 14,
735 RTW89_THAILAND = 15,
736 RTW89_REGD_NUM,
737 };
738
739 enum rtw89_reg_6ghz_power {
740 RTW89_REG_6GHZ_POWER_VLP = 0,
741 RTW89_REG_6GHZ_POWER_LPI = 1,
742 RTW89_REG_6GHZ_POWER_STD = 2,
743
744 NUM_OF_RTW89_REG_6GHZ_POWER,
745 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP,
746 };
747
748 enum rtw89_fw_pkt_ofld_type {
749 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
750 RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
751 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
752 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
753 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
754 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
755 RTW89_PKT_OFLD_TYPE_NDP = 6,
756 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
757 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
758 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
759 RTW89_PKT_OFLD_TYPE_NUM,
760 };
761
762 struct rtw89_txpwr_byrate {
763 s8 cck[RTW89_RATE_CCK_NUM];
764 s8 ofdm[RTW89_RATE_OFDM_NUM];
765 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM];
766 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
767 s8 offset[__RTW89_RATE_OFFSET_NUM];
768 s8 trap;
769 };
770
771 struct rtw89_rate_desc {
772 enum rtw89_nss nss;
773 enum rtw89_rate_section rs;
774 enum rtw89_ofdma_type ofdma;
775 u8 idx;
776 };
777
778 #define PHY_STS_HDR_LEN 8
779 #define RF_PATH_MAX 4
780 #define RTW89_MAX_PPDU_CNT 8
781 struct rtw89_rx_phy_ppdu {
782 void *buf;
783 u32 len;
784 u8 rssi_avg;
785 u8 rssi[RF_PATH_MAX];
786 u8 mac_id;
787 u8 chan_idx;
788 u8 ie;
789 u16 rate;
790 struct {
791 bool has;
792 u8 avg_snr;
793 u8 evm_max;
794 u8 evm_min;
795 } ofdm;
796 bool to_self;
797 bool valid;
798 };
799
800 enum rtw89_mac_idx {
801 RTW89_MAC_0 = 0,
802 RTW89_MAC_1 = 1,
803 RTW89_MAC_NUM,
804 };
805
806 enum rtw89_phy_idx {
807 RTW89_PHY_0 = 0,
808 RTW89_PHY_1 = 1,
809 RTW89_PHY_MAX
810 };
811
812 enum rtw89_sub_entity_idx {
813 RTW89_SUB_ENTITY_0 = 0,
814 RTW89_SUB_ENTITY_1 = 1,
815
816 NUM_OF_RTW89_SUB_ENTITY,
817 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY,
818 };
819
820 enum rtw89_rf_path {
821 RF_PATH_A = 0,
822 RF_PATH_B = 1,
823 RF_PATH_C = 2,
824 RF_PATH_D = 3,
825 RF_PATH_AB,
826 RF_PATH_AC,
827 RF_PATH_AD,
828 RF_PATH_BC,
829 RF_PATH_BD,
830 RF_PATH_CD,
831 RF_PATH_ABC,
832 RF_PATH_ABD,
833 RF_PATH_ACD,
834 RF_PATH_BCD,
835 RF_PATH_ABCD,
836 };
837
838 enum rtw89_rf_path_bit {
839 RF_A = BIT(0),
840 RF_B = BIT(1),
841 RF_C = BIT(2),
842 RF_D = BIT(3),
843
844 RF_AB = (RF_A | RF_B),
845 RF_AC = (RF_A | RF_C),
846 RF_AD = (RF_A | RF_D),
847 RF_BC = (RF_B | RF_C),
848 RF_BD = (RF_B | RF_D),
849 RF_CD = (RF_C | RF_D),
850
851 RF_ABC = (RF_A | RF_B | RF_C),
852 RF_ABD = (RF_A | RF_B | RF_D),
853 RF_ACD = (RF_A | RF_C | RF_D),
854 RF_BCD = (RF_B | RF_C | RF_D),
855
856 RF_ABCD = (RF_A | RF_B | RF_C | RF_D),
857 };
858
859 enum rtw89_bandwidth {
860 RTW89_CHANNEL_WIDTH_20 = 0,
861 RTW89_CHANNEL_WIDTH_40 = 1,
862 RTW89_CHANNEL_WIDTH_80 = 2,
863 RTW89_CHANNEL_WIDTH_160 = 3,
864 RTW89_CHANNEL_WIDTH_320 = 4,
865
866 /* keep index order above */
867 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5,
868
869 RTW89_CHANNEL_WIDTH_80_80 = 5,
870 RTW89_CHANNEL_WIDTH_5 = 6,
871 RTW89_CHANNEL_WIDTH_10 = 7,
872 };
873
874 enum rtw89_ps_mode {
875 RTW89_PS_MODE_NONE = 0,
876 RTW89_PS_MODE_RFOFF = 1,
877 RTW89_PS_MODE_CLK_GATED = 2,
878 RTW89_PS_MODE_PWR_GATED = 3,
879 };
880
881 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
882 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
883 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
884 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
885 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
886
887 enum rtw89_ru_bandwidth {
888 RTW89_RU26 = 0,
889 RTW89_RU52 = 1,
890 RTW89_RU106 = 2,
891 RTW89_RU52_26 = 3,
892 RTW89_RU106_26 = 4,
893 RTW89_RU_NUM,
894 };
895
896 enum rtw89_sc_offset {
897 RTW89_SC_DONT_CARE = 0,
898 RTW89_SC_20_UPPER = 1,
899 RTW89_SC_20_LOWER = 2,
900 RTW89_SC_20_UPMOST = 3,
901 RTW89_SC_20_LOWEST = 4,
902 RTW89_SC_20_UP2X = 5,
903 RTW89_SC_20_LOW2X = 6,
904 RTW89_SC_20_UP3X = 7,
905 RTW89_SC_20_LOW3X = 8,
906 RTW89_SC_40_UPPER = 9,
907 RTW89_SC_40_LOWER = 10,
908 };
909
910 enum rtw89_wow_flags {
911 RTW89_WOW_FLAG_EN_MAGIC_PKT,
912 RTW89_WOW_FLAG_EN_REKEY_PKT,
913 RTW89_WOW_FLAG_EN_DISCONNECT,
914 RTW89_WOW_FLAG_NUM,
915 };
916
917 struct rtw89_chan {
918 u8 channel;
919 u8 primary_channel;
920 enum rtw89_band band_type;
921 enum rtw89_bandwidth band_width;
922
923 /* The follow-up are derived from the above. We must ensure that it
924 * is assigned correctly in rtw89_chan_create() if new one is added.
925 */
926 u32 freq;
927 enum rtw89_subband subband_type;
928 enum rtw89_sc_offset pri_ch_idx;
929 u8 pri_sb_idx;
930 };
931
932 struct rtw89_chan_rcd {
933 u8 prev_primary_channel;
934 enum rtw89_band prev_band_type;
935 bool band_changed;
936 };
937
938 struct rtw89_channel_help_params {
939 u32 tx_en;
940 };
941
942 struct rtw89_port_reg {
943 u32 port_cfg;
944 u32 tbtt_prohib;
945 u32 bcn_area;
946 u32 bcn_early;
947 u32 tbtt_early;
948 u32 tbtt_agg;
949 u32 bcn_space;
950 u32 bcn_forcetx;
951 u32 bcn_err_cnt;
952 u32 bcn_err_flag;
953 u32 dtim_ctrl;
954 u32 tbtt_shift;
955 u32 bcn_cnt_tmr;
956 u32 tsftr_l;
957 u32 tsftr_h;
958 u32 md_tsft;
959 u32 bss_color;
960 u32 mbssid;
961 u32 mbssid_drop;
962 u32 tsf_sync;
963 u32 ptcl_dbg;
964 u32 ptcl_dbg_info;
965 u32 bcn_drop_all;
966 u32 hiq_win[RTW89_PORT_NUM];
967 };
968
969 struct rtw89_txwd_body {
970 __le32 dword0;
971 __le32 dword1;
972 __le32 dword2;
973 __le32 dword3;
974 __le32 dword4;
975 __le32 dword5;
976 } __packed;
977
978 struct rtw89_txwd_body_v1 {
979 __le32 dword0;
980 __le32 dword1;
981 __le32 dword2;
982 __le32 dword3;
983 __le32 dword4;
984 __le32 dword5;
985 __le32 dword6;
986 __le32 dword7;
987 } __packed;
988
989 struct rtw89_txwd_body_v2 {
990 __le32 dword0;
991 __le32 dword1;
992 __le32 dword2;
993 __le32 dword3;
994 __le32 dword4;
995 __le32 dword5;
996 __le32 dword6;
997 __le32 dword7;
998 } __packed;
999
1000 struct rtw89_txwd_info {
1001 __le32 dword0;
1002 __le32 dword1;
1003 __le32 dword2;
1004 __le32 dword3;
1005 __le32 dword4;
1006 __le32 dword5;
1007 } __packed;
1008
1009 struct rtw89_txwd_info_v2 {
1010 __le32 dword0;
1011 __le32 dword1;
1012 __le32 dword2;
1013 __le32 dword3;
1014 __le32 dword4;
1015 __le32 dword5;
1016 __le32 dword6;
1017 __le32 dword7;
1018 } __packed;
1019
1020 struct rtw89_rx_desc_info {
1021 u16 pkt_size;
1022 u8 pkt_type;
1023 u8 drv_info_size;
1024 u8 phy_rpt_size;
1025 u8 hdr_cnv_size;
1026 u8 shift;
1027 u8 wl_hd_iv_len;
1028 bool long_rxdesc;
1029 bool bb_sel;
1030 bool mac_info_valid;
1031 u16 data_rate;
1032 u8 gi_ltf;
1033 u8 bw;
1034 u32 free_run_cnt;
1035 u8 user_id;
1036 bool sr_en;
1037 u8 ppdu_cnt;
1038 u8 ppdu_type;
1039 bool icv_err;
1040 bool crc32_err;
1041 bool hw_dec;
1042 bool sw_dec;
1043 bool addr1_match;
1044 u8 frag;
1045 u16 seq;
1046 u8 frame_type;
1047 u8 rx_pl_id;
1048 bool addr_cam_valid;
1049 u8 addr_cam_id;
1050 u8 sec_cam_id;
1051 u8 mac_id;
1052 u16 offset;
1053 u16 rxd_len;
1054 bool ready;
1055 };
1056
1057 struct rtw89_rxdesc_short {
1058 __le32 dword0;
1059 __le32 dword1;
1060 __le32 dword2;
1061 __le32 dword3;
1062 } __packed;
1063
1064 struct rtw89_rxdesc_short_v2 {
1065 __le32 dword0;
1066 __le32 dword1;
1067 __le32 dword2;
1068 __le32 dword3;
1069 __le32 dword4;
1070 __le32 dword5;
1071 } __packed;
1072
1073 struct rtw89_rxdesc_long {
1074 __le32 dword0;
1075 __le32 dword1;
1076 __le32 dword2;
1077 __le32 dword3;
1078 __le32 dword4;
1079 __le32 dword5;
1080 __le32 dword6;
1081 __le32 dword7;
1082 } __packed;
1083
1084 struct rtw89_rxdesc_long_v2 {
1085 __le32 dword0;
1086 __le32 dword1;
1087 __le32 dword2;
1088 __le32 dword3;
1089 __le32 dword4;
1090 __le32 dword5;
1091 __le32 dword6;
1092 __le32 dword7;
1093 __le32 dword8;
1094 __le32 dword9;
1095 } __packed;
1096
1097 struct rtw89_tx_desc_info {
1098 u16 pkt_size;
1099 u8 wp_offset;
1100 u8 mac_id;
1101 u8 qsel;
1102 u8 ch_dma;
1103 u8 hdr_llc_len;
1104 bool is_bmc;
1105 bool en_wd_info;
1106 bool wd_page;
1107 bool use_rate;
1108 bool dis_data_fb;
1109 bool tid_indicate;
1110 bool agg_en;
1111 bool bk;
1112 u8 ampdu_density;
1113 u8 ampdu_num;
1114 bool sec_en;
1115 u8 addr_info_nr;
1116 u8 sec_keyid;
1117 u8 sec_type;
1118 u8 sec_cam_idx;
1119 u8 sec_seq[6];
1120 u16 data_rate;
1121 u16 data_retry_lowest_rate;
1122 bool fw_dl;
1123 u16 seq;
1124 bool a_ctrl_bsr;
1125 u8 hw_ssn_sel;
1126 #define RTW89_MGMT_HW_SSN_SEL 1
1127 u8 hw_seq_mode;
1128 #define RTW89_MGMT_HW_SEQ_MODE 1
1129 bool hiq;
1130 u8 port;
1131 bool er_cap;
1132 };
1133
1134 struct rtw89_core_tx_request {
1135 enum rtw89_core_tx_type tx_type;
1136
1137 struct sk_buff *skb;
1138 struct ieee80211_vif *vif;
1139 struct ieee80211_sta *sta;
1140 struct rtw89_tx_desc_info desc_info;
1141 };
1142
1143 struct rtw89_txq {
1144 struct list_head list;
1145 unsigned long flags;
1146 int wait_cnt;
1147 };
1148
1149 struct rtw89_mac_ax_gnt {
1150 u8 gnt_bt_sw_en;
1151 u8 gnt_bt;
1152 u8 gnt_wl_sw_en;
1153 u8 gnt_wl;
1154 } __packed;
1155
1156 struct rtw89_mac_ax_wl_act {
1157 u8 wlan_act_en;
1158 u8 wlan_act;
1159 };
1160
1161 #define RTW89_MAC_AX_COEX_GNT_NR 2
1162 struct rtw89_mac_ax_coex_gnt {
1163 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
1164 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR];
1165 };
1166
1167 enum rtw89_btc_ncnt {
1168 BTC_NCNT_POWER_ON = 0x0,
1169 BTC_NCNT_POWER_OFF,
1170 BTC_NCNT_INIT_COEX,
1171 BTC_NCNT_SCAN_START,
1172 BTC_NCNT_SCAN_FINISH,
1173 BTC_NCNT_SPECIAL_PACKET,
1174 BTC_NCNT_SWITCH_BAND,
1175 BTC_NCNT_RFK_TIMEOUT,
1176 BTC_NCNT_SHOW_COEX_INFO,
1177 BTC_NCNT_ROLE_INFO,
1178 BTC_NCNT_CONTROL,
1179 BTC_NCNT_RADIO_STATE,
1180 BTC_NCNT_CUSTOMERIZE,
1181 BTC_NCNT_WL_RFK,
1182 BTC_NCNT_WL_STA,
1183 BTC_NCNT_WL_STA_LAST,
1184 BTC_NCNT_FWINFO,
1185 BTC_NCNT_TIMER,
1186 BTC_NCNT_SWITCH_CHBW,
1187 BTC_NCNT_RESUME_DL_FW,
1188 BTC_NCNT_COUNTRYCODE,
1189 BTC_NCNT_NUM,
1190 };
1191
1192 enum rtw89_btc_btinfo {
1193 BTC_BTINFO_L0 = 0,
1194 BTC_BTINFO_L1,
1195 BTC_BTINFO_L2,
1196 BTC_BTINFO_L3,
1197 BTC_BTINFO_H0,
1198 BTC_BTINFO_H1,
1199 BTC_BTINFO_H2,
1200 BTC_BTINFO_H3,
1201 BTC_BTINFO_MAX
1202 };
1203
1204 enum rtw89_btc_dcnt {
1205 BTC_DCNT_RUN = 0x0,
1206 BTC_DCNT_CX_RUNINFO,
1207 BTC_DCNT_RPT,
1208 BTC_DCNT_RPT_HANG,
1209 BTC_DCNT_CYCLE,
1210 BTC_DCNT_CYCLE_HANG,
1211 BTC_DCNT_W1,
1212 BTC_DCNT_W1_HANG,
1213 BTC_DCNT_B1,
1214 BTC_DCNT_B1_HANG,
1215 BTC_DCNT_TDMA_NONSYNC,
1216 BTC_DCNT_SLOT_NONSYNC,
1217 BTC_DCNT_BTCNT_HANG,
1218 BTC_DCNT_BTTX_HANG,
1219 BTC_DCNT_WL_SLOT_DRIFT,
1220 BTC_DCNT_WL_STA_LAST,
1221 BTC_DCNT_BT_SLOT_DRIFT,
1222 BTC_DCNT_BT_SLOT_FLOOD,
1223 BTC_DCNT_FDDT_TRIG,
1224 BTC_DCNT_E2G,
1225 BTC_DCNT_E2G_HANG,
1226 BTC_DCNT_WL_FW_VER_MATCH,
1227 BTC_DCNT_NULL_TX_FAIL,
1228 BTC_DCNT_WL_STA_NTFY,
1229 BTC_DCNT_NUM,
1230 };
1231
1232 enum rtw89_btc_wl_state_cnt {
1233 BTC_WCNT_SCANAP = 0x0,
1234 BTC_WCNT_DHCP,
1235 BTC_WCNT_EAPOL,
1236 BTC_WCNT_ARP,
1237 BTC_WCNT_SCBDUPDATE,
1238 BTC_WCNT_RFK_REQ,
1239 BTC_WCNT_RFK_GO,
1240 BTC_WCNT_RFK_REJECT,
1241 BTC_WCNT_RFK_TIMEOUT,
1242 BTC_WCNT_CH_UPDATE,
1243 BTC_WCNT_DBCC_ALL_2G,
1244 BTC_WCNT_DBCC_CHG,
1245 BTC_WCNT_RX_OK_LAST,
1246 BTC_WCNT_RX_OK_LAST2S,
1247 BTC_WCNT_RX_ERR_LAST,
1248 BTC_WCNT_RX_ERR_LAST2S,
1249 BTC_WCNT_RX_LAST,
1250 BTC_WCNT_NUM
1251 };
1252
1253 enum rtw89_btc_bt_state_cnt {
1254 BTC_BCNT_RETRY = 0x0,
1255 BTC_BCNT_REINIT,
1256 BTC_BCNT_REENABLE,
1257 BTC_BCNT_SCBDREAD,
1258 BTC_BCNT_RELINK,
1259 BTC_BCNT_IGNOWL,
1260 BTC_BCNT_INQPAG,
1261 BTC_BCNT_INQ,
1262 BTC_BCNT_PAGE,
1263 BTC_BCNT_ROLESW,
1264 BTC_BCNT_AFH,
1265 BTC_BCNT_INFOUPDATE,
1266 BTC_BCNT_INFOSAME,
1267 BTC_BCNT_SCBDUPDATE,
1268 BTC_BCNT_HIPRI_TX,
1269 BTC_BCNT_HIPRI_RX,
1270 BTC_BCNT_LOPRI_TX,
1271 BTC_BCNT_LOPRI_RX,
1272 BTC_BCNT_POLUT,
1273 BTC_BCNT_POLUT_NOW,
1274 BTC_BCNT_POLUT_DIFF,
1275 BTC_BCNT_RATECHG,
1276 BTC_BCNT_NUM,
1277 };
1278
1279 enum rtw89_btc_bt_profile {
1280 BTC_BT_NOPROFILE = 0,
1281 BTC_BT_HFP = BIT(0),
1282 BTC_BT_HID = BIT(1),
1283 BTC_BT_A2DP = BIT(2),
1284 BTC_BT_PAN = BIT(3),
1285 BTC_PROFILE_MAX = 4,
1286 };
1287
1288 struct rtw89_btc_ant_info {
1289 u8 type; /* shared, dedicated */
1290 u8 num;
1291 u8 isolation;
1292
1293 u8 single_pos: 1;/* Single antenna at S0 or S1 */
1294 u8 diversity: 1;
1295 u8 btg_pos: 2;
1296 u8 stream_cnt: 4;
1297 };
1298
1299 struct rtw89_btc_ant_info_v7 {
1300 u8 type; /* shared, dedicated(non-shared) */
1301 u8 num; /* antenna count */
1302 u8 isolation;
1303 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */
1304
1305 u8 diversity; /* only for wifi use 1-antenna */
1306 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */
1307 u8 stream_cnt; /* spatial_stream count */
1308 u8 rsvd;
1309 } __packed;
1310
1311 enum rtw89_tfc_dir {
1312 RTW89_TFC_UL,
1313 RTW89_TFC_DL,
1314 };
1315
1316 struct rtw89_btc_wl_smap {
1317 u32 busy: 1;
1318 u32 scan: 1;
1319 u32 connecting: 1;
1320 u32 roaming: 1;
1321 u32 transacting: 1;
1322 u32 _4way: 1;
1323 u32 rf_off: 1;
1324 u32 lps: 2;
1325 u32 ips: 1;
1326 u32 init_ok: 1;
1327 u32 traffic_dir : 2;
1328 u32 rf_off_pre: 1;
1329 u32 lps_pre: 2;
1330 u32 lps_exiting: 1;
1331 u32 emlsr: 1;
1332 };
1333
1334 enum rtw89_tfc_lv {
1335 RTW89_TFC_IDLE,
1336 RTW89_TFC_ULTRA_LOW,
1337 RTW89_TFC_LOW,
1338 RTW89_TFC_MID,
1339 RTW89_TFC_HIGH,
1340 };
1341
1342 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */
1343 DECLARE_EWMA(tp, 10, 2);
1344
1345 struct rtw89_traffic_stats {
1346 /* units in bytes */
1347 u64 tx_unicast;
1348 u64 rx_unicast;
1349 u32 tx_avg_len;
1350 u32 rx_avg_len;
1351
1352 /* count for packets */
1353 u64 tx_cnt;
1354 u64 rx_cnt;
1355
1356 /* units in Mbps */
1357 u32 tx_throughput;
1358 u32 rx_throughput;
1359 u32 tx_throughput_raw;
1360 u32 rx_throughput_raw;
1361
1362 u32 rx_tf_acc;
1363 u32 rx_tf_periodic;
1364
1365 enum rtw89_tfc_lv tx_tfc_lv;
1366 enum rtw89_tfc_lv rx_tfc_lv;
1367 struct ewma_tp tx_ewma_tp;
1368 struct ewma_tp rx_ewma_tp;
1369
1370 u16 tx_rate;
1371 u16 rx_rate;
1372 };
1373
1374 struct rtw89_btc_chdef {
1375 u8 center_ch;
1376 u8 band;
1377 u8 chan;
1378 enum rtw89_sc_offset offset;
1379 enum rtw89_bandwidth bw;
1380 };
1381
1382 struct rtw89_btc_statistic {
1383 u8 rssi; /* 0%~110% (dBm = rssi -110) */
1384 struct rtw89_traffic_stats traffic;
1385 };
1386
1387 #define BTC_WL_RSSI_THMAX 4
1388
1389 struct rtw89_btc_wl_link_info {
1390 struct rtw89_btc_chdef chdef;
1391 struct rtw89_btc_statistic stat;
1392 enum rtw89_tfc_dir dir;
1393 u8 rssi_state[BTC_WL_RSSI_THMAX];
1394 u8 mac_addr[ETH_ALEN];
1395 u8 busy;
1396 u8 ch;
1397 u8 bw;
1398 u8 band;
1399 u8 role;
1400 u8 pid;
1401 u8 phy;
1402 u8 dtim_period;
1403 u8 mode;
1404 u8 tx_1ss_limit;
1405
1406 u8 mac_id;
1407 u8 tx_retry;
1408
1409 u32 bcn_period;
1410 u32 busy_t;
1411 u32 tx_time;
1412 u32 client_cnt;
1413 u32 rx_rate_drop_cnt;
1414 u32 noa_duration;
1415
1416 u32 active: 1;
1417 u32 noa: 1;
1418 u32 client_ps: 1;
1419 u32 connected: 2;
1420 };
1421
1422 union rtw89_btc_wl_state_map {
1423 u32 val;
1424 struct rtw89_btc_wl_smap map;
1425 };
1426
1427 struct rtw89_btc_bt_hfp_desc {
1428 u32 exist: 1;
1429 u32 type: 2;
1430 u32 rsvd: 29;
1431 };
1432
1433 struct rtw89_btc_bt_hid_desc {
1434 u32 exist: 1;
1435 u32 slot_info: 2;
1436 u32 pair_cnt: 2;
1437 u32 type: 8;
1438 u32 rsvd: 19;
1439 };
1440
1441 struct rtw89_btc_bt_a2dp_desc {
1442 u8 exist: 1;
1443 u8 exist_last: 1;
1444 u8 play_latency: 1;
1445 u8 type: 3;
1446 u8 active: 1;
1447 u8 sink: 1;
1448 u32 handle_update: 1;
1449 u32 devinfo_query: 1;
1450 u32 no_empty_streak_2s: 8;
1451 u32 no_empty_streak_max: 8;
1452 u32 rsvd: 6;
1453
1454 u8 bitpool;
1455 u16 vendor_id;
1456 u32 device_name;
1457 u32 flush_time;
1458 };
1459
1460 struct rtw89_btc_bt_pan_desc {
1461 u32 exist: 1;
1462 u32 type: 1;
1463 u32 active: 1;
1464 u32 rsvd: 29;
1465 };
1466
1467 struct rtw89_btc_bt_rfk_info {
1468 u32 run: 1;
1469 u32 req: 1;
1470 u32 timeout: 1;
1471 u32 rsvd: 29;
1472 };
1473
1474 union rtw89_btc_bt_rfk_info_map {
1475 u32 val;
1476 struct rtw89_btc_bt_rfk_info map;
1477 };
1478
1479 struct rtw89_btc_bt_ver_info {
1480 u32 fw_coex; /* match with which coex_ver */
1481 u32 fw;
1482 };
1483
1484 struct rtw89_btc_bool_sta_chg {
1485 u32 now: 1;
1486 u32 last: 1;
1487 u32 remain: 1;
1488 u32 srvd: 29;
1489 };
1490
1491 struct rtw89_btc_u8_sta_chg {
1492 u8 now;
1493 u8 last;
1494 u8 remain;
1495 u8 rsvd;
1496 };
1497
1498 struct rtw89_btc_wl_scan_info {
1499 u8 band[RTW89_PHY_MAX];
1500 u8 phy_map;
1501 u8 rsvd;
1502 };
1503
1504 struct rtw89_btc_wl_dbcc_info {
1505 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */
1506 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */
1507 u8 real_band[RTW89_PHY_MAX];
1508 u8 role[RTW89_PHY_MAX]; /* role in each phy */
1509 };
1510
1511 struct rtw89_btc_wl_active_role {
1512 u8 connected: 1;
1513 u8 pid: 3;
1514 u8 phy: 1;
1515 u8 noa: 1;
1516 u8 band: 2;
1517
1518 u8 client_ps: 1;
1519 u8 bw: 7;
1520
1521 u8 role;
1522 u8 ch;
1523
1524 u16 tx_lvl;
1525 u16 rx_lvl;
1526 u16 tx_rate;
1527 u16 rx_rate;
1528 };
1529
1530 struct rtw89_btc_wl_active_role_v1 {
1531 u8 connected: 1;
1532 u8 pid: 3;
1533 u8 phy: 1;
1534 u8 noa: 1;
1535 u8 band: 2;
1536
1537 u8 client_ps: 1;
1538 u8 bw: 7;
1539
1540 u8 role;
1541 u8 ch;
1542
1543 u16 tx_lvl;
1544 u16 rx_lvl;
1545 u16 tx_rate;
1546 u16 rx_rate;
1547
1548 u32 noa_duration; /* ms */
1549 };
1550
1551 struct rtw89_btc_wl_active_role_v2 {
1552 u8 connected: 1;
1553 u8 pid: 3;
1554 u8 phy: 1;
1555 u8 noa: 1;
1556 u8 band: 2;
1557
1558 u8 client_ps: 1;
1559 u8 bw: 7;
1560
1561 u8 role;
1562 u8 ch;
1563
1564 u32 noa_duration; /* ms */
1565 };
1566
1567 struct rtw89_btc_wl_role_info_bpos {
1568 u16 none: 1;
1569 u16 station: 1;
1570 u16 ap: 1;
1571 u16 vap: 1;
1572 u16 adhoc: 1;
1573 u16 adhoc_master: 1;
1574 u16 mesh: 1;
1575 u16 moniter: 1;
1576 u16 p2p_device: 1;
1577 u16 p2p_gc: 1;
1578 u16 p2p_go: 1;
1579 u16 nan: 1;
1580 };
1581
1582 struct rtw89_btc_wl_scc_ctrl {
1583 u8 null_role1;
1584 u8 null_role2;
1585 u8 ebt_null; /* if tx null at EBT slot */
1586 };
1587
1588 union rtw89_btc_wl_role_info_map {
1589 u16 val;
1590 struct rtw89_btc_wl_role_info_bpos role;
1591 };
1592
1593 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1594 u8 connect_cnt;
1595 u8 link_mode;
1596 union rtw89_btc_wl_role_info_map role_map;
1597 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
1598 };
1599
1600 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */
1601 u8 connect_cnt;
1602 u8 link_mode;
1603 union rtw89_btc_wl_role_info_map role_map;
1604 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM];
1605 u32 mrole_type; /* btc_wl_mrole_type */
1606 u32 mrole_noa_duration; /* ms */
1607
1608 u32 dbcc_en: 1;
1609 u32 dbcc_chg: 1;
1610 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1611 u32 link_mode_chg: 1;
1612 u32 rsvd: 27;
1613 };
1614
1615 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */
1616 u8 connect_cnt;
1617 u8 link_mode;
1618 union rtw89_btc_wl_role_info_map role_map;
1619 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM];
1620 u32 mrole_type; /* btc_wl_mrole_type */
1621 u32 mrole_noa_duration; /* ms */
1622
1623 u32 dbcc_en: 1;
1624 u32 dbcc_chg: 1;
1625 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1626 u32 link_mode_chg: 1;
1627 u32 rsvd: 27;
1628 };
1629
1630 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */
1631 u8 connected;
1632 u8 pid;
1633 u8 phy;
1634 u8 noa;
1635
1636 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */
1637 u8 active; /* 0:rlink is under doze */
1638 u8 bw; /* enum channel_width */
1639 u8 role; /*enum role_type */
1640
1641 u8 ch;
1642 u8 noa_dur; /* ms */
1643 u8 client_cnt; /* for Role = P2P-Go/AP */
1644 u8 mode; /* wifi protocol */
1645 } __packed;
1646
1647 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6
1648 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */
1649 u8 connect_cnt;
1650 u8 link_mode;
1651 u8 link_mode_chg;
1652 u8 p2p_2g;
1653
1654 u8 pta_req_band;
1655 u8 dbcc_en; /* 1+1 and 2.4G-included */
1656 u8 dbcc_chg;
1657 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1658
1659 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1660
1661 u32 role_map;
1662 u32 mrole_type; /* btc_wl_mrole_type */
1663 u32 mrole_noa_duration; /* ms */
1664 } __packed;
1665
1666 struct rtw89_btc_wl_ver_info {
1667 u32 fw_coex; /* match with which coex_ver */
1668 u32 fw;
1669 u32 mac;
1670 u32 bb;
1671 u32 rf;
1672 };
1673
1674 struct rtw89_btc_wl_afh_info {
1675 u8 en;
1676 u8 ch;
1677 u8 bw;
1678 u8 rsvd;
1679 } __packed;
1680
1681 struct rtw89_btc_wl_rfk_info {
1682 u32 state: 2;
1683 u32 path_map: 4;
1684 u32 phy_map: 2;
1685 u32 band: 2;
1686 u32 type: 8;
1687 u32 rsvd: 14;
1688
1689 u32 start_time;
1690 u32 proc_time;
1691 };
1692
1693 struct rtw89_btc_bt_smap {
1694 u32 connect: 1;
1695 u32 ble_connect: 1;
1696 u32 acl_busy: 1;
1697 u32 sco_busy: 1;
1698 u32 mesh_busy: 1;
1699 u32 inq_pag: 1;
1700 };
1701
1702 union rtw89_btc_bt_state_map {
1703 u32 val;
1704 struct rtw89_btc_bt_smap map;
1705 };
1706
1707 #define BTC_BT_RSSI_THMAX 4
1708 #define BTC_BT_AFH_GROUP 12
1709 #define BTC_BT_AFH_LE_GROUP 5
1710
1711 struct rtw89_btc_bt_link_info {
1712 struct rtw89_btc_u8_sta_chg profile_cnt;
1713 struct rtw89_btc_bool_sta_chg multi_link;
1714 struct rtw89_btc_bool_sta_chg relink;
1715 struct rtw89_btc_bt_hfp_desc hfp_desc;
1716 struct rtw89_btc_bt_hid_desc hid_desc;
1717 struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1718 struct rtw89_btc_bt_pan_desc pan_desc;
1719 union rtw89_btc_bt_state_map status;
1720
1721 u8 sut_pwr_level[BTC_PROFILE_MAX];
1722 u8 golden_rx_shift[BTC_PROFILE_MAX];
1723 u8 rssi_state[BTC_BT_RSSI_THMAX];
1724 u8 afh_map[BTC_BT_AFH_GROUP];
1725 u8 afh_map_le[BTC_BT_AFH_LE_GROUP];
1726
1727 u32 role_sw: 1;
1728 u32 slave_role: 1;
1729 u32 afh_update: 1;
1730 u32 cqddr: 1;
1731 u32 rssi: 8;
1732 u32 tx_3m: 1;
1733 u32 rsvd: 19;
1734 };
1735
1736 struct rtw89_btc_3rdcx_info {
1737 u8 type; /* 0: none, 1:zigbee, 2:LTE */
1738 u8 hw_coex;
1739 u16 rsvd;
1740 };
1741
1742 struct rtw89_btc_dm_emap {
1743 u32 init: 1;
1744 u32 pta_owner: 1;
1745 u32 wl_rfk_timeout: 1;
1746 u32 bt_rfk_timeout: 1;
1747 u32 wl_fw_hang: 1;
1748 u32 cycle_hang: 1;
1749 u32 w1_hang: 1;
1750 u32 b1_hang: 1;
1751 u32 tdma_no_sync: 1;
1752 u32 slot_no_sync: 1;
1753 u32 wl_slot_drift: 1;
1754 u32 bt_slot_drift: 1;
1755 u32 role_num_mismatch: 1;
1756 u32 null1_tx_late: 1;
1757 u32 bt_afh_conflict: 1;
1758 u32 bt_leafh_conflict: 1;
1759 u32 bt_slot_flood: 1;
1760 u32 wl_e2g_hang: 1;
1761 u32 wl_ver_mismatch: 1;
1762 u32 bt_ver_mismatch: 1;
1763 u32 rfe_type0: 1;
1764 u32 h2c_buffer_over: 1;
1765 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/
1766 u32 wl_no_sta_ntfy: 1;
1767
1768 u32 h2c_bmap_mismatch: 1;
1769 u32 c2h_bmap_mismatch: 1;
1770 u32 h2c_struct_invalid: 1;
1771 u32 c2h_struct_invalid: 1;
1772 u32 h2c_c2h_buffer_mismatch: 1;
1773 };
1774
1775 union rtw89_btc_dm_error_map {
1776 u32 val;
1777 struct rtw89_btc_dm_emap map;
1778 };
1779
1780 struct rtw89_btc_rf_para {
1781 u32 tx_pwr_freerun;
1782 u32 rx_gain_freerun;
1783 u32 tx_pwr_perpkt;
1784 u32 rx_gain_perpkt;
1785 };
1786
1787 struct rtw89_btc_wl_nhm {
1788 u8 instant_wl_nhm_dbm;
1789 u8 instant_wl_nhm_per_mhz;
1790 u16 valid_record_times;
1791 s8 record_pwr[16];
1792 u8 record_ratio[16];
1793 s8 pwr; /* dbm_per_MHz */
1794 u8 ratio;
1795 u8 current_status;
1796 u8 refresh;
1797 bool start_flag;
1798 s8 pwr_max;
1799 s8 pwr_min;
1800 };
1801
1802 struct rtw89_btc_wl_info {
1803 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
1804 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1805 struct rtw89_btc_wl_rfk_info rfk_info;
1806 struct rtw89_btc_wl_ver_info ver_info;
1807 struct rtw89_btc_wl_afh_info afh_info;
1808 struct rtw89_btc_wl_role_info role_info;
1809 struct rtw89_btc_wl_role_info_v1 role_info_v1;
1810 struct rtw89_btc_wl_role_info_v2 role_info_v2;
1811 struct rtw89_btc_wl_role_info_v8 role_info_v8;
1812 struct rtw89_btc_wl_scan_info scan_info;
1813 struct rtw89_btc_wl_dbcc_info dbcc_info;
1814 struct rtw89_btc_rf_para rf_para;
1815 struct rtw89_btc_wl_nhm nhm;
1816 union rtw89_btc_wl_state_map status;
1817
1818 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1819 u8 rssi_level;
1820 u8 cn_report;
1821 u8 coex_mode;
1822 u8 pta_req_mac;
1823 u8 bt_polut_type[RTW89_PHY_MAX]; /* BT polluted WL-Tx type for phy0/1 */
1824
1825 bool is_5g_hi_channel;
1826 bool pta_reg_mac_chg;
1827 bool bg_mode;
1828 bool scbd_change;
1829 bool fw_ver_mismatch;
1830 u32 scbd;
1831 };
1832
1833 struct rtw89_btc_module {
1834 struct rtw89_btc_ant_info ant;
1835 u8 rfe_type;
1836 u8 cv;
1837
1838 u8 bt_solo: 1;
1839 u8 bt_pos: 1;
1840 u8 switch_type: 1;
1841 u8 wa_type: 3;
1842
1843 u8 kt_ver_adie;
1844 };
1845
1846 struct rtw89_btc_module_v7 {
1847 u8 rfe_type;
1848 u8 kt_ver;
1849 u8 bt_solo;
1850 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/
1851
1852 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */
1853 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */
1854 u8 kt_ver_adie;
1855 u8 rsvd;
1856
1857 struct rtw89_btc_ant_info_v7 ant;
1858 } __packed;
1859
1860 union rtw89_btc_module_info {
1861 struct rtw89_btc_module md;
1862 struct rtw89_btc_module_v7 md_v7;
1863 };
1864
1865 #define RTW89_BTC_DM_MAXSTEP 30
1866 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
1867
1868 struct rtw89_btc_dm_step {
1869 u16 step[RTW89_BTC_DM_MAXSTEP];
1870 u8 step_pos;
1871 bool step_ov;
1872 };
1873
1874 struct rtw89_btc_init_info {
1875 struct rtw89_btc_module module;
1876 u8 wl_guard_ch;
1877
1878 u8 wl_only: 1;
1879 u8 wl_init_ok: 1;
1880 u8 dbcc_en: 1;
1881 u8 cx_other: 1;
1882 u8 bt_only: 1;
1883
1884 u16 rsvd;
1885 };
1886
1887 struct rtw89_btc_init_info_v7 {
1888 u8 wl_guard_ch;
1889 u8 wl_only;
1890 u8 wl_init_ok;
1891 u8 rsvd3;
1892
1893 u8 cx_other;
1894 u8 bt_only;
1895 u8 pta_mode;
1896 u8 pta_direction;
1897
1898 struct rtw89_btc_module_v7 module;
1899 } __packed;
1900
1901 union rtw89_btc_init_info_u {
1902 struct rtw89_btc_init_info init;
1903 struct rtw89_btc_init_info_v7 init_v7;
1904 };
1905
1906 struct rtw89_btc_wl_tx_limit_para {
1907 u16 enable;
1908 u32 tx_time; /* unit: us */
1909 u16 tx_retry;
1910 };
1911
1912 enum rtw89_btc_bt_scan_type {
1913 BTC_SCAN_INQ = 0,
1914 BTC_SCAN_PAGE,
1915 BTC_SCAN_BLE,
1916 BTC_SCAN_INIT,
1917 BTC_SCAN_TV,
1918 BTC_SCAN_ADV,
1919 BTC_SCAN_MAX1,
1920 };
1921
1922 enum rtw89_btc_ble_scan_type {
1923 CXSCAN_BG = 0,
1924 CXSCAN_INIT,
1925 CXSCAN_LE,
1926 CXSCAN_MAX
1927 };
1928
1929 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0)
1930 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1)
1931
1932 struct rtw89_btc_bt_scan_info_v1 {
1933 __le16 win;
1934 __le16 intvl;
1935 __le32 flags;
1936 } __packed;
1937
1938 struct rtw89_btc_bt_scan_info_v2 {
1939 __le16 win;
1940 __le16 intvl;
1941 } __packed;
1942
1943 struct rtw89_btc_fbtc_btscan_v1 {
1944 u8 fver; /* btc_ver::fcxbtscan */
1945 u8 rsvd;
1946 __le16 rsvd2;
1947 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1];
1948 } __packed;
1949
1950 struct rtw89_btc_fbtc_btscan_v2 {
1951 u8 fver; /* btc_ver::fcxbtscan */
1952 u8 type;
1953 __le16 rsvd2;
1954 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
1955 } __packed;
1956
1957 struct rtw89_btc_fbtc_btscan_v7 {
1958 u8 fver; /* btc_ver::fcxbtscan */
1959 u8 type;
1960 u8 rsvd0;
1961 u8 rsvd1;
1962 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
1963 } __packed;
1964
1965 union rtw89_btc_fbtc_btscan {
1966 struct rtw89_btc_fbtc_btscan_v1 v1;
1967 struct rtw89_btc_fbtc_btscan_v2 v2;
1968 struct rtw89_btc_fbtc_btscan_v7 v7;
1969 };
1970
1971 struct rtw89_btc_bt_info {
1972 struct rtw89_btc_bt_link_info link_info;
1973 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1];
1974 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX];
1975 struct rtw89_btc_bt_ver_info ver_info;
1976 struct rtw89_btc_bool_sta_chg enable;
1977 struct rtw89_btc_bool_sta_chg inq_pag;
1978 struct rtw89_btc_rf_para rf_para;
1979 union rtw89_btc_bt_rfk_info_map rfk_info;
1980
1981 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
1982 u8 rssi_level;
1983
1984 u32 scbd;
1985 u32 feature;
1986
1987 u32 mbx_avl: 1;
1988 u32 whql_test: 1;
1989 u32 igno_wl: 1;
1990 u32 reinit: 1;
1991 u32 ble_scan_en: 1;
1992 u32 btg_type: 1;
1993 u32 inq: 1;
1994 u32 pag: 1;
1995 u32 run_patch_code: 1;
1996 u32 hi_lna_rx: 1;
1997 u32 scan_rx_low_pri: 1;
1998 u32 scan_info_update: 1;
1999 u32 lna_constrain: 3;
2000 u32 rsvd: 17;
2001 };
2002
2003 struct rtw89_btc_cx {
2004 struct rtw89_btc_wl_info wl;
2005 struct rtw89_btc_bt_info bt;
2006 struct rtw89_btc_3rdcx_info other;
2007 u32 state_map;
2008 u32 cnt_bt[BTC_BCNT_NUM];
2009 u32 cnt_wl[BTC_WCNT_NUM];
2010 };
2011
2012 struct rtw89_btc_fbtc_tdma {
2013 u8 type; /* btc_ver::fcxtdma */
2014 u8 rxflctrl;
2015 u8 txpause;
2016 u8 wtgle_n;
2017 u8 leak_n;
2018 u8 ext_ctrl;
2019 u8 rxflctrl_role;
2020 u8 option_ctrl;
2021 } __packed;
2022
2023 struct rtw89_btc_fbtc_tdma_v3 {
2024 u8 fver; /* btc_ver::fcxtdma */
2025 u8 rsvd;
2026 __le16 rsvd1;
2027 struct rtw89_btc_fbtc_tdma tdma;
2028 } __packed;
2029
2030 union rtw89_btc_fbtc_tdma_le32 {
2031 struct rtw89_btc_fbtc_tdma v1;
2032 struct rtw89_btc_fbtc_tdma_v3 v3;
2033 };
2034
2035 #define CXMREG_MAX 30
2036 #define CXMREG_MAX_V2 20
2037 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
2038 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
2039
2040 enum rtw89_btc_bt_sta_counter {
2041 BTC_BCNT_RFK_REQ = 0,
2042 BTC_BCNT_RFK_GO = 1,
2043 BTC_BCNT_RFK_REJECT = 2,
2044 BTC_BCNT_RFK_FAIL = 3,
2045 BTC_BCNT_RFK_TIMEOUT = 4,
2046 BTC_BCNT_HI_TX = 5,
2047 BTC_BCNT_HI_RX = 6,
2048 BTC_BCNT_LO_TX = 7,
2049 BTC_BCNT_LO_RX = 8,
2050 BTC_BCNT_POLLUTED = 9,
2051 BTC_BCNT_STA_MAX
2052 };
2053
2054 enum rtw89_btc_bt_sta_counter_v105 {
2055 BTC_BCNT_RFK_REQ_V105 = 0,
2056 BTC_BCNT_HI_TX_V105 = 1,
2057 BTC_BCNT_HI_RX_V105 = 2,
2058 BTC_BCNT_LO_TX_V105 = 3,
2059 BTC_BCNT_LO_RX_V105 = 4,
2060 BTC_BCNT_POLLUTED_V105 = 5,
2061 BTC_BCNT_STA_MAX_V105
2062 };
2063
2064 struct rtw89_btc_fbtc_rpt_ctrl_v1 {
2065 u16 fver; /* btc_ver::fcxbtcrpt */
2066 u16 rpt_cnt; /* tmr counters */
2067 u32 wl_fw_coex_ver; /* match which driver's coex version */
2068 u32 wl_fw_cx_offload;
2069 u32 wl_fw_ver;
2070 u32 rpt_enable;
2071 u32 rpt_para; /* ms */
2072 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
2073 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
2074 u32 mb_recv_cnt; /* fw recv mailbox counter */
2075 u32 mb_a2dp_empty_cnt; /* a2dp empty count */
2076 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
2077 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
2078 u32 bt_rfk_cnt[BTC_BCNT_HI_TX];
2079 u32 c2h_cnt; /* fw send c2h counter */
2080 u32 h2c_cnt; /* fw recv h2c counter */
2081 } __packed;
2082
2083 struct rtw89_btc_fbtc_rpt_ctrl_info {
2084 __le32 cnt; /* fw report counter */
2085 __le32 en; /* report map */
2086 __le32 para; /* not used */
2087
2088 __le32 cnt_c2h; /* fw send c2h counter */
2089 __le32 cnt_h2c; /* fw recv h2c counter */
2090 __le32 len_c2h; /* The total length of the last C2H */
2091
2092 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2093 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2094 } __packed;
2095
2096 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 {
2097 __le32 cx_ver; /* match which driver's coex version */
2098 __le32 fw_ver;
2099 __le32 en; /* report map */
2100
2101 __le16 cnt; /* fw report counter */
2102 __le16 cnt_c2h; /* fw send c2h counter */
2103 __le16 cnt_h2c; /* fw recv h2c counter */
2104 __le16 len_c2h; /* The total length of the last C2H */
2105
2106 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2107 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2108 } __packed;
2109
2110 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 {
2111 __le16 cnt; /* fw report counter */
2112 __le16 cnt_c2h; /* fw send c2h counter */
2113 __le16 cnt_h2c; /* fw recv h2c counter */
2114 __le16 len_c2h; /* The total length of the last C2H */
2115
2116 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2117 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2118
2119 __le32 cx_ver; /* match which driver's coex version */
2120 __le32 fw_ver;
2121 __le32 en; /* report map */
2122 } __packed;
2123
2124 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info {
2125 __le32 cx_ver; /* match which driver's coex version */
2126 __le32 cx_offload;
2127 __le32 fw_ver;
2128 } __packed;
2129
2130 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty {
2131 __le32 cnt_empty; /* a2dp empty count */
2132 __le32 cnt_flowctrl; /* a2dp empty flow control counter */
2133 __le32 cnt_tx;
2134 __le32 cnt_ack;
2135 __le32 cnt_nack;
2136 } __packed;
2137
2138 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox {
2139 __le32 cnt_send_ok; /* fw send mailbox ok counter */
2140 __le32 cnt_send_fail; /* fw send mailbox fail counter */
2141 __le32 cnt_recv; /* fw recv mailbox counter */
2142 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp;
2143 } __packed;
2144
2145 struct rtw89_btc_fbtc_rpt_ctrl_v4 {
2146 u8 fver;
2147 u8 rsvd;
2148 __le16 rsvd1;
2149 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info;
2150 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info;
2151 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2152 __le32 bt_cnt[BTC_BCNT_STA_MAX];
2153 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX];
2154 } __packed;
2155
2156 struct rtw89_btc_fbtc_rpt_ctrl_v5 {
2157 u8 fver;
2158 u8 rsvd;
2159 __le16 rsvd1;
2160
2161 u8 gnt_val[RTW89_PHY_MAX][4];
2162 __le16 bt_cnt[BTC_BCNT_STA_MAX];
2163
2164 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2165 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2166 } __packed;
2167
2168 struct rtw89_btc_fbtc_rpt_ctrl_v105 {
2169 u8 fver;
2170 u8 rsvd;
2171 __le16 rsvd1;
2172
2173 u8 gnt_val[RTW89_PHY_MAX][4];
2174 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2175
2176 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2177 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2178 } __packed;
2179
2180 struct rtw89_btc_fbtc_rpt_ctrl_v8 {
2181 u8 fver;
2182 u8 rsvd0;
2183 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */
2184 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */
2185
2186 u8 gnt_val[RTW89_PHY_MAX][4];
2187 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2188
2189 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info;
2190 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2191 } __packed;
2192
2193 union rtw89_btc_fbtc_rpt_ctrl_ver_info {
2194 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1;
2195 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4;
2196 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5;
2197 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105;
2198 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8;
2199 };
2200
2201 enum rtw89_fbtc_ext_ctrl_type {
2202 CXECTL_OFF = 0x0, /* tdma off */
2203 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
2204 CXECTL_EXT = 0x2,
2205 CXECTL_MAX
2206 };
2207
2208 union rtw89_btc_fbtc_rxflct {
2209 u8 val;
2210 u8 type: 3;
2211 u8 tgln_n: 5;
2212 };
2213
2214 enum rtw89_btc_cxst_state {
2215 CXST_OFF = 0x0,
2216 CXST_B2W = 0x1,
2217 CXST_W1 = 0x2,
2218 CXST_W2 = 0x3,
2219 CXST_W2B = 0x4,
2220 CXST_B1 = 0x5,
2221 CXST_B2 = 0x6,
2222 CXST_B3 = 0x7,
2223 CXST_B4 = 0x8,
2224 CXST_LK = 0x9,
2225 CXST_BLK = 0xa,
2226 CXST_E2G = 0xb,
2227 CXST_E5G = 0xc,
2228 CXST_EBT = 0xd,
2229 CXST_ENULL = 0xe,
2230 CXST_WLK = 0xf,
2231 CXST_W1FDD = 0x10,
2232 CXST_B1FDD = 0x11,
2233 CXST_MAX = 0x12,
2234 };
2235
2236 enum rtw89_btc_cxevnt {
2237 CXEVNT_TDMA_ENTRY = 0x0,
2238 CXEVNT_WL_TMR,
2239 CXEVNT_B1_TMR,
2240 CXEVNT_B2_TMR,
2241 CXEVNT_B3_TMR,
2242 CXEVNT_B4_TMR,
2243 CXEVNT_W2B_TMR,
2244 CXEVNT_B2W_TMR,
2245 CXEVNT_BCN_EARLY,
2246 CXEVNT_A2DP_EMPTY,
2247 CXEVNT_LK_END,
2248 CXEVNT_RX_ISR,
2249 CXEVNT_RX_FC0,
2250 CXEVNT_RX_FC1,
2251 CXEVNT_BT_RELINK,
2252 CXEVNT_BT_RETRY,
2253 CXEVNT_E2G,
2254 CXEVNT_E5G,
2255 CXEVNT_EBT,
2256 CXEVNT_ENULL,
2257 CXEVNT_DRV_WLK,
2258 CXEVNT_BCN_OK,
2259 CXEVNT_BT_CHANGE,
2260 CXEVNT_EBT_EXTEND,
2261 CXEVNT_E2G_NULL1,
2262 CXEVNT_B1FDD_TMR,
2263 CXEVNT_MAX
2264 };
2265
2266 enum {
2267 CXBCN_ALL = 0x0,
2268 CXBCN_ALL_OK,
2269 CXBCN_BT_SLOT,
2270 CXBCN_BT_OK,
2271 CXBCN_MAX
2272 };
2273
2274 enum btc_slot_type {
2275 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
2276 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
2277 CXSTYPE_NUM,
2278 };
2279
2280 enum { /* TIME */
2281 CXT_BT = 0x0,
2282 CXT_WL = 0x1,
2283 CXT_MAX
2284 };
2285
2286 enum { /* TIME-A2DP */
2287 CXT_FLCTRL_OFF = 0x0,
2288 CXT_FLCTRL_ON = 0x1,
2289 CXT_FLCTRL_MAX
2290 };
2291
2292 enum { /* STEP TYPE */
2293 CXSTEP_NONE = 0x0,
2294 CXSTEP_EVNT = 0x1,
2295 CXSTEP_SLOT = 0x2,
2296 CXSTEP_MAX,
2297 };
2298
2299 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */
2300 RPT_BT_AFH_SEQ_LEGACY = 0x10,
2301 RPT_BT_AFH_SEQ_LE = 0x20
2302 };
2303
2304 #define BTC_DBG_MAX1 32
2305 struct rtw89_btc_fbtc_gpio_dbg_v1 {
2306 u8 fver; /* btc_ver::fcxgpiodbg */
2307 u8 rsvd;
2308 __le16 rsvd2;
2309 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
2310 __le32 pre_state; /* the debug signal is 1 or 0 */
2311 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
2312 } __packed;
2313
2314 struct rtw89_btc_fbtc_gpio_dbg_v7 {
2315 u8 fver;
2316 u8 rsvd0;
2317 u8 rsvd1;
2318 u8 rsvd2;
2319
2320 u8 gpio_map[BTC_DBG_MAX1];
2321
2322 __le32 en_map;
2323 __le32 pre_state;
2324 } __packed;
2325
2326 union rtw89_btc_fbtc_gpio_dbg {
2327 struct rtw89_btc_fbtc_gpio_dbg_v1 v1;
2328 struct rtw89_btc_fbtc_gpio_dbg_v7 v7;
2329 };
2330
2331 struct rtw89_btc_fbtc_mreg_val_v1 {
2332 u8 fver; /* btc_ver::fcxmreg */
2333 u8 reg_num;
2334 __le16 rsvd;
2335 __le32 mreg_val[CXMREG_MAX];
2336 } __packed;
2337
2338 struct rtw89_btc_fbtc_mreg_val_v2 {
2339 u8 fver; /* btc_ver::fcxmreg */
2340 u8 reg_num;
2341 __le16 rsvd;
2342 __le32 mreg_val[CXMREG_MAX_V2];
2343 } __packed;
2344
2345 struct rtw89_btc_fbtc_mreg_val_v7 {
2346 u8 fver;
2347 u8 reg_num;
2348 u8 rsvd0;
2349 u8 rsvd1;
2350 __le32 mreg_val[CXMREG_MAX_V2];
2351 } __packed;
2352
2353 union rtw89_btc_fbtc_mreg_val {
2354 struct rtw89_btc_fbtc_mreg_val_v1 v1;
2355 struct rtw89_btc_fbtc_mreg_val_v2 v2;
2356 struct rtw89_btc_fbtc_mreg_val_v7 v7;
2357 };
2358
2359 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
2360 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
2361 .offset = cpu_to_le32(__offset), }
2362
2363 struct rtw89_btc_fbtc_mreg {
2364 __le16 type;
2365 __le16 bytes;
2366 __le32 offset;
2367 } __packed;
2368
2369 struct rtw89_btc_fbtc_slot {
2370 __le16 dur;
2371 __le32 cxtbl;
2372 __le16 cxtype;
2373 } __packed;
2374
2375 struct rtw89_btc_fbtc_slots {
2376 u8 fver; /* btc_ver::fcxslots */
2377 u8 tbl_num;
2378 __le16 rsvd;
2379 __le32 update_map;
2380 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2381 } __packed;
2382
2383 struct rtw89_btc_fbtc_slot_v7 {
2384 __le16 dur; /* slot duration */
2385 __le16 cxtype;
2386 __le32 cxtbl;
2387 } __packed;
2388
2389 struct rtw89_btc_fbtc_slot_u16 {
2390 __le16 dur; /* slot duration */
2391 __le16 cxtype;
2392 __le16 cxtbl_l16; /* coex table [15:0] */
2393 __le16 cxtbl_h16; /* coex table [31:16] */
2394 } __packed;
2395
2396 struct rtw89_btc_fbtc_1slot_v7 {
2397 u8 fver;
2398 u8 sid; /* slot id */
2399 __le16 rsvd;
2400 struct rtw89_btc_fbtc_slot_v7 slot;
2401 } __packed;
2402
2403 struct rtw89_btc_fbtc_slots_v7 {
2404 u8 fver;
2405 u8 slot_cnt;
2406 u8 rsvd0;
2407 u8 rsvd1;
2408 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX];
2409 __le32 update_map;
2410 } __packed;
2411
2412 union rtw89_btc_fbtc_slots_info {
2413 struct rtw89_btc_fbtc_slots v1;
2414 struct rtw89_btc_fbtc_slots_v7 v7;
2415 } __packed;
2416
2417 struct rtw89_btc_fbtc_step {
2418 u8 type;
2419 u8 val;
2420 __le16 difft;
2421 } __packed;
2422
2423 struct rtw89_btc_fbtc_steps_v2 {
2424 u8 fver; /* btc_ver::fcxstep */
2425 u8 rsvd;
2426 __le16 cnt;
2427 __le16 pos_old;
2428 __le16 pos_new;
2429 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2430 } __packed;
2431
2432 struct rtw89_btc_fbtc_steps_v3 {
2433 u8 fver;
2434 u8 en;
2435 __le16 rsvd;
2436 __le32 cnt;
2437 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2438 } __packed;
2439
2440 union rtw89_btc_fbtc_steps_info {
2441 struct rtw89_btc_fbtc_steps_v2 v2;
2442 struct rtw89_btc_fbtc_steps_v3 v3;
2443 };
2444
2445 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */
2446 u8 fver; /* btc_ver::fcxcysta */
2447 u8 rsvd;
2448 __le16 cycles; /* total cycle number */
2449 __le16 cycles_a2dp[CXT_FLCTRL_MAX];
2450 __le16 a2dpept; /* a2dp empty cnt */
2451 __le16 a2dpeptto; /* a2dp empty timeout cnt*/
2452 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
2453 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
2454 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2455 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
2456 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
2457 __le16 tavg_a2dpept; /* avg a2dp empty time */
2458 __le16 tmax_a2dpept; /* max a2dp empty time */
2459 __le16 tavg_lk; /* avg leak-slot time */
2460 __le16 tmax_lk; /* max leak-slot time */
2461 __le32 slot_cnt[CXST_MAX]; /* slot count */
2462 __le32 bcn_cnt[CXBCN_MAX];
2463 __le32 leakrx_cnt; /* the rximr occur at leak slot */
2464 __le32 collision_cnt; /* counter for event/timer occur at same time */
2465 __le32 skip_cnt;
2466 __le32 exception;
2467 __le32 except_cnt;
2468 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
2469 } __packed;
2470
2471 struct rtw89_btc_fbtc_fdd_try_info {
2472 __le16 cycles[CXT_FLCTRL_MAX];
2473 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
2474 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
2475 } __packed;
2476
2477 struct rtw89_btc_fbtc_cycle_time_info {
2478 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2479 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2480 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2481 } __packed;
2482
2483 struct rtw89_btc_fbtc_cycle_time_info_v5 {
2484 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2485 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2486 } __packed;
2487
2488 struct rtw89_btc_fbtc_a2dp_trx_stat {
2489 u8 empty_cnt;
2490 u8 retry_cnt;
2491 u8 tx_rate;
2492 u8 tx_cnt;
2493 u8 ack_cnt;
2494 u8 nack_cnt;
2495 u8 rsvd1;
2496 u8 rsvd2;
2497 } __packed;
2498
2499 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 {
2500 u8 empty_cnt;
2501 u8 retry_cnt;
2502 u8 tx_rate;
2503 u8 tx_cnt;
2504 u8 ack_cnt;
2505 u8 nack_cnt;
2506 u8 no_empty_cnt;
2507 u8 rsvd;
2508 } __packed;
2509
2510 struct rtw89_btc_fbtc_cycle_a2dp_empty_info {
2511 __le16 cnt; /* a2dp empty cnt */
2512 __le16 cnt_timeout; /* a2dp empty timeout cnt*/
2513 __le16 tavg; /* avg a2dp empty time */
2514 __le16 tmax; /* max a2dp empty time */
2515 } __packed;
2516
2517 struct rtw89_btc_fbtc_cycle_leak_info {
2518 __le32 cnt_rximr; /* the rximr occur at leak slot */
2519 __le16 tavg; /* avg leak-slot time */
2520 __le16 tmax; /* max leak-slot time */
2521 } __packed;
2522
2523 struct rtw89_btc_fbtc_cycle_leak_info_v7 {
2524 __le16 tavg;
2525 __le16 tamx;
2526 __le32 cnt_rximr;
2527 } __packed;
2528
2529 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)
2530 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10)
2531
2532 struct rtw89_btc_fbtc_cycle_fddt_info {
2533 __le16 train_cycle;
2534 __le16 tp;
2535
2536 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2537 s8 bt_tx_power; /* decrease Tx power (dB) */
2538 s8 bt_rx_gain; /* LNA constrain level */
2539 u8 no_empty_cnt;
2540
2541 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2542 u8 cn; /* condition_num */
2543 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2544 u8 train_result; /* refer to enum btc_fddt_check_map */
2545 } __packed;
2546
2547 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)
2548 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4)
2549
2550 struct rtw89_btc_fbtc_cycle_fddt_info_v5 {
2551 __le16 train_cycle;
2552 __le16 tp;
2553
2554 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2555 s8 bt_tx_power; /* decrease Tx power (dB) */
2556 s8 bt_rx_gain; /* LNA constrain level */
2557 u8 no_empty_cnt;
2558
2559 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2560 u8 cn; /* condition_num */
2561 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2562 u8 train_result; /* refer to enum btc_fddt_check_map */
2563 } __packed;
2564
2565 struct rtw89_btc_fbtc_fddt_cell_status {
2566 s8 wl_tx_pwr;
2567 s8 bt_tx_pwr;
2568 s8 bt_rx_gain;
2569 u8 state_phase; /* [0:3] train state, [4:7] train phase */
2570 } __packed;
2571
2572 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */
2573 u8 fver;
2574 u8 rsvd;
2575 __le16 cycles; /* total cycle number */
2576 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX];
2577 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2578 struct rtw89_btc_fbtc_fdd_try_info fdd_try;
2579 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2580 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
2581 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2582 __le32 slot_cnt[CXST_MAX]; /* slot count */
2583 __le32 bcn_cnt[CXBCN_MAX];
2584 __le32 collision_cnt; /* counter for event/timer occur at the same time */
2585 __le32 skip_cnt;
2586 __le32 except_cnt;
2587 __le32 except_map;
2588 } __packed;
2589
2590 #define FDD_TRAIN_WL_DIRECTION 2
2591 #define FDD_TRAIN_WL_RSSI_LEVEL 5
2592 #define FDD_TRAIN_BT_RSSI_LEVEL 5
2593
2594 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */
2595 u8 fver;
2596 u8 rsvd;
2597 u8 collision_cnt; /* counter for event/timer occur at the same time */
2598 u8 except_cnt;
2599
2600 __le16 skip_cnt;
2601 __le16 cycles; /* total cycle number */
2602
2603 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2604 __le16 slot_cnt[CXST_MAX]; /* slot count */
2605 __le16 bcn_cnt[CXBCN_MAX];
2606 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2607 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2608 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2609 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2610 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX];
2611 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2612 [FDD_TRAIN_WL_RSSI_LEVEL]
2613 [FDD_TRAIN_BT_RSSI_LEVEL];
2614 __le32 except_map;
2615 } __packed;
2616
2617 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */
2618 u8 fver;
2619 u8 rsvd;
2620 u8 collision_cnt; /* counter for event/timer occur at the same time */
2621 u8 except_cnt;
2622 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2623
2624 __le16 skip_cnt;
2625 __le16 cycles; /* total cycle number */
2626
2627 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2628 __le16 slot_cnt[CXST_MAX]; /* slot count */
2629 __le16 bcn_cnt[CXBCN_MAX];
2630 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2631 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2632 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2633 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2634 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX];
2635 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2636 [FDD_TRAIN_WL_RSSI_LEVEL]
2637 [FDD_TRAIN_BT_RSSI_LEVEL];
2638 __le32 except_map;
2639 } __packed;
2640
2641 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */
2642 u8 fver;
2643 u8 rsvd;
2644 u8 collision_cnt; /* counter for event/timer occur at the same time */
2645 u8 except_cnt;
2646
2647 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2648
2649 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2650
2651 __le16 skip_cnt;
2652 __le16 cycles; /* total cycle number */
2653
2654 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2655 __le16 slot_cnt[CXST_MAX]; /* slot count */
2656 __le16 bcn_cnt[CXBCN_MAX];
2657
2658 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2659 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2660 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot;
2661
2662 __le32 except_map;
2663 } __packed;
2664
2665 union rtw89_btc_fbtc_cysta_info {
2666 struct rtw89_btc_fbtc_cysta_v2 v2;
2667 struct rtw89_btc_fbtc_cysta_v3 v3;
2668 struct rtw89_btc_fbtc_cysta_v4 v4;
2669 struct rtw89_btc_fbtc_cysta_v5 v5;
2670 struct rtw89_btc_fbtc_cysta_v7 v7;
2671 };
2672
2673 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */
2674 u8 fver; /* btc_ver::fcxnullsta */
2675 u8 rsvd;
2676 __le16 rsvd2;
2677 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2678 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2679 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
2680 } __packed;
2681
2682 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */
2683 u8 fver; /* btc_ver::fcxnullsta */
2684 u8 rsvd;
2685 __le16 rsvd2;
2686 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2687 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2688 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
2689 } __packed;
2690
2691 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */
2692 u8 fver;
2693 u8 rsvd0;
2694 u8 rsvd1;
2695 u8 rsvd2;
2696
2697 __le32 tmax[2];
2698 __le32 tavg[2];
2699 __le32 result[2][5];
2700 } __packed;
2701
2702 union rtw89_btc_fbtc_cynullsta_info {
2703 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */
2704 struct rtw89_btc_fbtc_cynullsta_v2 v2;
2705 struct rtw89_btc_fbtc_cynullsta_v7 v7;
2706 };
2707
2708 struct rtw89_btc_fbtc_btver_v1 {
2709 u8 fver; /* btc_ver::fcxbtver */
2710 u8 rsvd;
2711 __le16 rsvd2;
2712 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2713 __le32 fw_ver;
2714 __le32 feature;
2715 } __packed;
2716
2717 struct rtw89_btc_fbtc_btver_v7 {
2718 u8 fver;
2719 u8 rsvd0;
2720 u8 rsvd1;
2721 u8 rsvd2;
2722
2723 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2724 __le32 fw_ver;
2725 __le32 feature;
2726 } __packed;
2727
2728 union rtw89_btc_fbtc_btver {
2729 struct rtw89_btc_fbtc_btver_v1 v1;
2730 struct rtw89_btc_fbtc_btver_v7 v7;
2731 } __packed;
2732
2733 struct rtw89_btc_fbtc_btafh {
2734 u8 fver; /* btc_ver::fcxbtafh */
2735 u8 rsvd;
2736 __le16 rsvd2;
2737 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
2738 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
2739 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
2740 } __packed;
2741
2742 struct rtw89_btc_fbtc_btafh_v2 {
2743 u8 fver; /* btc_ver::fcxbtafh */
2744 u8 rsvd;
2745 u8 rsvd2;
2746 u8 map_type;
2747 u8 afh_l[4];
2748 u8 afh_m[4];
2749 u8 afh_h[4];
2750 u8 afh_le_a[4];
2751 u8 afh_le_b[4];
2752 } __packed;
2753
2754 struct rtw89_btc_fbtc_btafh_v7 {
2755 u8 fver;
2756 u8 map_type;
2757 u8 rsvd0;
2758 u8 rsvd1;
2759 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */
2760 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */
2761 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */
2762 u8 afh_le_a[4];
2763 u8 afh_le_b[4];
2764 } __packed;
2765
2766 struct rtw89_btc_fbtc_btdevinfo {
2767 u8 fver; /* btc_ver::fcxbtdevinfo */
2768 u8 rsvd;
2769 __le16 vendor_id;
2770 __le32 dev_name; /* only 24 bits valid */
2771 __le32 flush_time;
2772 } __packed;
2773
2774 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
2775 struct rtw89_btc_rf_trx_para {
2776 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2777 u32 wl_rx_gain; /* rx gain table index (TBD.) */
2778 u8 bt_tx_power; /* decrease Tx power (dB) */
2779 u8 bt_rx_gain; /* LNA constrain level */
2780 };
2781
2782 struct rtw89_btc_trx_info {
2783 u8 tx_lvl;
2784 u8 rx_lvl;
2785 u8 wl_rssi;
2786 u8 bt_rssi;
2787
2788 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2789 s8 rx_gain; /* rx gain table index (TBD.) */
2790 s8 bt_tx_power; /* decrease Tx power (dB) */
2791 s8 bt_rx_gain; /* LNA constrain level */
2792
2793 u8 cn; /* condition_num */
2794 s8 nhm;
2795 u8 bt_profile;
2796 u8 rsvd2;
2797
2798 u16 tx_rate;
2799 u16 rx_rate;
2800
2801 u32 tx_tp;
2802 u32 rx_tp;
2803 u32 rx_err_ratio;
2804 };
2805
2806 union rtw89_btc_fbtc_slot_u {
2807 struct rtw89_btc_fbtc_slot v1[CXST_MAX];
2808 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX];
2809 };
2810
2811 struct rtw89_btc_dm {
2812 union rtw89_btc_fbtc_slot_u slot;
2813 union rtw89_btc_fbtc_slot_u slot_now;
2814 struct rtw89_btc_fbtc_tdma tdma;
2815 struct rtw89_btc_fbtc_tdma tdma_now;
2816 struct rtw89_mac_ax_coex_gnt gnt;
2817 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */
2818 struct rtw89_btc_rf_trx_para rf_trx_para;
2819 struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
2820 struct rtw89_btc_dm_step dm_step;
2821 struct rtw89_btc_wl_scc_ctrl wl_scc;
2822 struct rtw89_btc_trx_info trx_info;
2823 union rtw89_btc_dm_error_map error;
2824 u32 cnt_dm[BTC_DCNT_NUM];
2825 u32 cnt_notify[BTC_NCNT_NUM];
2826
2827 u32 update_slot_map;
2828 u32 set_ant_path;
2829 u32 e2g_slot_limit;
2830 u32 e2g_slot_nulltx_time;
2831
2832 u32 wl_only: 1;
2833 u32 wl_fw_cx_offload: 1;
2834 u32 freerun: 1;
2835 u32 fddt_train: 1;
2836 u32 wl_ps_ctrl: 2;
2837 u32 wl_mimo_ps: 1;
2838 u32 leak_ap: 1;
2839 u32 noisy_level: 3;
2840 u32 coex_info_map: 8;
2841 u32 bt_only: 1;
2842 u32 wl_btg_rx: 2;
2843 u32 trx_para_level: 8;
2844 u32 wl_stb_chg: 1;
2845 u32 pta_owner: 1;
2846
2847 u32 tdma_instant_excute: 1;
2848 u32 wl_btg_rx_rb: 2;
2849
2850 u16 slot_dur[CXST_MAX];
2851 u16 bt_slot_flood;
2852
2853 u8 run_reason;
2854 u8 run_action;
2855
2856 u8 wl_pre_agc: 2;
2857 u8 wl_lna2: 1;
2858 u8 wl_pre_agc_rb: 2;
2859 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */
2860 u8 slot_req_more: 1;
2861 };
2862
2863 struct rtw89_btc_ctrl {
2864 u32 manual: 1;
2865 u32 igno_bt: 1;
2866 u32 always_freerun: 1;
2867 u32 trace_step: 16;
2868 u32 rsvd: 12;
2869 };
2870
2871 struct rtw89_btc_ctrl_v7 {
2872 u8 manual;
2873 u8 igno_bt;
2874 u8 always_freerun;
2875 u8 rsvd;
2876 } __packed;
2877
2878 union rtw89_btc_ctrl_list {
2879 struct rtw89_btc_ctrl ctrl;
2880 struct rtw89_btc_ctrl_v7 ctrl_v7;
2881 };
2882
2883 struct rtw89_btc_dbg {
2884 /* cmd "rb" */
2885 bool rb_done;
2886 u32 rb_val;
2887 };
2888
2889 enum rtw89_btc_btf_fw_event {
2890 BTF_EVNT_RPT = 0,
2891 BTF_EVNT_BT_INFO = 1,
2892 BTF_EVNT_BT_SCBD = 2,
2893 BTF_EVNT_BT_REG = 3,
2894 BTF_EVNT_CX_RUNINFO = 4,
2895 BTF_EVNT_BT_PSD = 5,
2896 BTF_EVNT_BUF_OVERFLOW,
2897 BTF_EVNT_C2H_LOOPBACK,
2898 BTF_EVNT_MAX,
2899 };
2900
2901 enum btf_fw_event_report {
2902 BTC_RPT_TYPE_CTRL = 0x0,
2903 BTC_RPT_TYPE_TDMA,
2904 BTC_RPT_TYPE_SLOT,
2905 BTC_RPT_TYPE_CYSTA,
2906 BTC_RPT_TYPE_STEP,
2907 BTC_RPT_TYPE_NULLSTA,
2908 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */
2909 BTC_RPT_TYPE_MREG,
2910 BTC_RPT_TYPE_GPIO_DBG,
2911 BTC_RPT_TYPE_BT_VER,
2912 BTC_RPT_TYPE_BT_SCAN,
2913 BTC_RPT_TYPE_BT_AFH,
2914 BTC_RPT_TYPE_BT_DEVICE,
2915 BTC_RPT_TYPE_TEST,
2916 BTC_RPT_TYPE_MAX = 31,
2917
2918 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA,
2919 __BTC_RPT_TYPE_V0_MAX = 12,
2920 };
2921
2922 enum rtw_btc_btf_reg_type {
2923 REG_MAC = 0x0,
2924 REG_BB = 0x1,
2925 REG_RF = 0x2,
2926 REG_BT_RF = 0x3,
2927 REG_BT_MODEM = 0x4,
2928 REG_BT_BLUEWIZE = 0x5,
2929 REG_BT_VENDOR = 0x6,
2930 REG_BT_LE = 0x7,
2931 REG_MAX_TYPE,
2932 };
2933
2934 struct rtw89_btc_rpt_cmn_info {
2935 u32 rx_cnt;
2936 u32 rx_len;
2937 u32 req_len; /* expected rsp len */
2938 u8 req_fver; /* expected rsp fver */
2939 u8 rsp_fver; /* fver from fw */
2940 u8 valid;
2941 } __packed;
2942
2943 union rtw89_btc_fbtc_btafh_info {
2944 struct rtw89_btc_fbtc_btafh v1;
2945 struct rtw89_btc_fbtc_btafh_v2 v2;
2946 };
2947
2948 struct rtw89_btc_report_ctrl_state {
2949 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2950 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo;
2951 };
2952
2953 struct rtw89_btc_rpt_fbtc_tdma {
2954 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2955 union rtw89_btc_fbtc_tdma_le32 finfo;
2956 };
2957
2958 struct rtw89_btc_rpt_fbtc_slots {
2959 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2960 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */
2961 };
2962
2963 struct rtw89_btc_rpt_fbtc_cysta {
2964 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2965 union rtw89_btc_fbtc_cysta_info finfo;
2966 };
2967
2968 struct rtw89_btc_rpt_fbtc_step {
2969 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2970 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */
2971 };
2972
2973 struct rtw89_btc_rpt_fbtc_nullsta {
2974 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2975 union rtw89_btc_fbtc_cynullsta_info finfo;
2976 };
2977
2978 struct rtw89_btc_rpt_fbtc_mreg {
2979 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2980 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
2981 };
2982
2983 struct rtw89_btc_rpt_fbtc_gpio_dbg {
2984 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2985 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
2986 };
2987
2988 struct rtw89_btc_rpt_fbtc_btver {
2989 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2990 union rtw89_btc_fbtc_btver finfo; /* info from fw */
2991 };
2992
2993 struct rtw89_btc_rpt_fbtc_btscan {
2994 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2995 union rtw89_btc_fbtc_btscan finfo; /* info from fw */
2996 };
2997
2998 struct rtw89_btc_rpt_fbtc_btafh {
2999 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3000 union rtw89_btc_fbtc_btafh_info finfo;
3001 };
3002
3003 struct rtw89_btc_rpt_fbtc_btdev {
3004 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3005 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
3006 };
3007
3008 enum rtw89_btc_btfre_type {
3009 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
3010 BTFRE_UNDEF_TYPE,
3011 BTFRE_EXCEPTION,
3012 BTFRE_MAX,
3013 };
3014
3015 struct rtw89_btc_btf_fwinfo {
3016 u32 cnt_c2h;
3017 u32 cnt_h2c;
3018 u32 cnt_h2c_fail;
3019 u32 event[BTF_EVNT_MAX];
3020
3021 u32 err[BTFRE_MAX];
3022 u32 len_mismch;
3023 u32 fver_mismch;
3024 u32 rpt_en_map;
3025
3026 struct rtw89_btc_report_ctrl_state rpt_ctrl;
3027 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
3028 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
3029 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
3030 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
3031 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
3032 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
3033 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
3034 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
3035 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
3036 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
3037 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
3038 };
3039
3040 struct rtw89_btc_ver {
3041 enum rtw89_core_chip_id chip_id;
3042 u32 fw_ver_code;
3043
3044 u8 fcxbtcrpt;
3045 u8 fcxtdma;
3046 u8 fcxslots;
3047 u8 fcxcysta;
3048 u8 fcxstep;
3049 u8 fcxnullsta;
3050 u8 fcxmreg;
3051 u8 fcxgpiodbg;
3052 u8 fcxbtver;
3053 u8 fcxbtscan;
3054 u8 fcxbtafh;
3055 u8 fcxbtdevinfo;
3056 u8 fwlrole;
3057 u8 frptmap;
3058 u8 fcxctrl;
3059 u8 fcxinit;
3060
3061 u8 fwevntrptl;
3062 u8 drvinfo_type;
3063 u16 info_buf;
3064 u8 max_role_num;
3065 };
3066
3067 #define RTW89_BTC_POLICY_MAXLEN 512
3068
3069 struct rtw89_btc {
3070 const struct rtw89_btc_ver *ver;
3071
3072 struct rtw89_btc_cx cx;
3073 struct rtw89_btc_dm dm;
3074 union rtw89_btc_ctrl_list ctrl;
3075 union rtw89_btc_module_info mdinfo;
3076 struct rtw89_btc_btf_fwinfo fwinfo;
3077 struct rtw89_btc_dbg dbg;
3078
3079 struct work_struct eapol_notify_work;
3080 struct work_struct arp_notify_work;
3081 struct work_struct dhcp_notify_work;
3082 struct work_struct icmp_notify_work;
3083
3084 u32 bt_req_len;
3085
3086 u8 policy[RTW89_BTC_POLICY_MAXLEN];
3087 u8 ant_type;
3088 u8 btg_pos;
3089 u16 policy_len;
3090 u16 policy_type;
3091 u32 hubmsg_cnt;
3092 bool bt_req_en;
3093 bool update_policy_force;
3094 bool lps;
3095 bool manual_ctrl;
3096 };
3097
3098 enum rtw89_btc_hmsg {
3099 RTW89_BTC_HMSG_TMR_EN = 0x0,
3100 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1,
3101 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2,
3102 RTW89_BTC_HMSG_FW_EV = 0x3,
3103 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4,
3104 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5,
3105
3106 NUM_OF_RTW89_BTC_HMSG,
3107 };
3108
3109 enum rtw89_ra_mode {
3110 RTW89_RA_MODE_CCK = BIT(0),
3111 RTW89_RA_MODE_OFDM = BIT(1),
3112 RTW89_RA_MODE_HT = BIT(2),
3113 RTW89_RA_MODE_VHT = BIT(3),
3114 RTW89_RA_MODE_HE = BIT(4),
3115 RTW89_RA_MODE_EHT = BIT(5),
3116 };
3117
3118 enum rtw89_ra_report_mode {
3119 RTW89_RA_RPT_MODE_LEGACY,
3120 RTW89_RA_RPT_MODE_HT,
3121 RTW89_RA_RPT_MODE_VHT,
3122 RTW89_RA_RPT_MODE_HE,
3123 RTW89_RA_RPT_MODE_EHT,
3124 };
3125
3126 enum rtw89_dig_noisy_level {
3127 RTW89_DIG_NOISY_LEVEL0 = -1,
3128 RTW89_DIG_NOISY_LEVEL1 = 0,
3129 RTW89_DIG_NOISY_LEVEL2 = 1,
3130 RTW89_DIG_NOISY_LEVEL3 = 2,
3131 RTW89_DIG_NOISY_LEVEL_MAX = 3,
3132 };
3133
3134 enum rtw89_gi_ltf {
3135 RTW89_GILTF_LGI_4XHE32 = 0,
3136 RTW89_GILTF_SGI_4XHE08 = 1,
3137 RTW89_GILTF_2XHE16 = 2,
3138 RTW89_GILTF_2XHE08 = 3,
3139 RTW89_GILTF_1XHE16 = 4,
3140 RTW89_GILTF_1XHE08 = 5,
3141 RTW89_GILTF_MAX
3142 };
3143
3144 enum rtw89_rx_frame_type {
3145 RTW89_RX_TYPE_MGNT = 0,
3146 RTW89_RX_TYPE_CTRL = 1,
3147 RTW89_RX_TYPE_DATA = 2,
3148 RTW89_RX_TYPE_RSVD = 3,
3149 };
3150
3151 enum rtw89_efuse_block {
3152 RTW89_EFUSE_BLOCK_SYS = 0,
3153 RTW89_EFUSE_BLOCK_RF = 1,
3154 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2,
3155 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3,
3156 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4,
3157 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5,
3158 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6,
3159 RTW89_EFUSE_BLOCK_ADIE = 7,
3160
3161 RTW89_EFUSE_BLOCK_NUM,
3162 RTW89_EFUSE_BLOCK_IGNORE,
3163 };
3164
3165 struct rtw89_ra_info {
3166 u8 is_dis_ra:1;
3167 /* Bit0 : CCK
3168 * Bit1 : OFDM
3169 * Bit2 : HT
3170 * Bit3 : VHT
3171 * Bit4 : HE
3172 * Bit5 : EHT
3173 */
3174 u8 mode_ctrl:6;
3175 u8 bw_cap:3; /* enum rtw89_bandwidth */
3176 u8 macid;
3177 u8 dcm_cap:1;
3178 u8 er_cap:1;
3179 u8 init_rate_lv:2;
3180 u8 upd_all:1;
3181 u8 en_sgi:1;
3182 u8 ldpc_cap:1;
3183 u8 stbc_cap:1;
3184 u8 ss_num:3;
3185 u8 giltf:3;
3186 u8 upd_bw_nss_mask:1;
3187 u8 upd_mask:1;
3188 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
3189 /* BFee CSI */
3190 u8 band_num;
3191 u8 ra_csi_rate_en:1;
3192 u8 fixed_csi_rate_en:1;
3193 u8 cr_tbl_sel:1;
3194 u8 fix_giltf_en:1;
3195 u8 fix_giltf:3;
3196 u8 rsvd2:1;
3197 u8 csi_mcs_ss_idx;
3198 u8 csi_mode:2;
3199 u8 csi_gi_ltf:3;
3200 u8 csi_bw:3;
3201 };
3202
3203 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4
3204 #define RTW89_PPDU_MAC_INFO_SIZE 8
3205 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96
3206 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128
3207
3208 #define RTW89_MAX_RX_AGG_NUM 64
3209 #define RTW89_MAX_TX_AGG_NUM 128
3210
3211 struct rtw89_ampdu_params {
3212 u16 agg_num;
3213 bool amsdu;
3214 };
3215
3216 struct rtw89_ra_report {
3217 struct rate_info txrate;
3218 u32 bit_rate;
3219 u16 hw_rate;
3220 bool might_fallback_legacy;
3221 };
3222
3223 DECLARE_EWMA(rssi, 10, 16);
3224 DECLARE_EWMA(evm, 10, 16);
3225 DECLARE_EWMA(snr, 10, 16);
3226
3227 struct rtw89_ba_cam_entry {
3228 struct list_head list;
3229 u8 tid;
3230 };
3231
3232 #define RTW89_MAX_ADDR_CAM_NUM 128
3233 #define RTW89_MAX_BSSID_CAM_NUM 20
3234 #define RTW89_MAX_SEC_CAM_NUM 128
3235 #define RTW89_MAX_BA_CAM_NUM 24
3236 #define RTW89_SEC_CAM_IN_ADDR_CAM 7
3237
3238 struct rtw89_addr_cam_entry {
3239 u8 addr_cam_idx;
3240 u8 offset;
3241 u8 len;
3242 u8 valid : 1;
3243 u8 addr_mask : 6;
3244 u8 wapi : 1;
3245 u8 mask_sel : 2;
3246 u8 bssid_cam_idx: 6;
3247
3248 u8 sec_ent_mode;
3249 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
3250 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
3251 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
3252 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM];
3253 };
3254
3255 struct rtw89_bssid_cam_entry {
3256 u8 bssid[ETH_ALEN];
3257 u8 phy_idx;
3258 u8 bssid_cam_idx;
3259 u8 offset;
3260 u8 len;
3261 u8 valid : 1;
3262 u8 num;
3263 };
3264
3265 struct rtw89_sec_cam_entry {
3266 u8 sec_cam_idx;
3267 u8 offset;
3268 u8 len;
3269 u8 type : 4;
3270 u8 ext_key : 1;
3271 u8 spp_mode : 1;
3272 /* 256 bits */
3273 u8 key[32];
3274 };
3275
3276 struct rtw89_sta {
3277 u8 mac_id;
3278 bool disassoc;
3279 bool er_cap;
3280 struct rtw89_dev *rtwdev;
3281 struct rtw89_vif *rtwvif;
3282 struct rtw89_ra_info ra;
3283 struct rtw89_ra_report ra_report;
3284 int max_agg_wait;
3285 u8 prev_rssi;
3286 struct ewma_rssi avg_rssi;
3287 struct ewma_rssi rssi[RF_PATH_MAX];
3288 struct ewma_snr avg_snr;
3289 struct ewma_evm evm_min[RF_PATH_MAX];
3290 struct ewma_evm evm_max[RF_PATH_MAX];
3291 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
3292 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS);
3293 struct ieee80211_rx_status rx_status;
3294 u16 rx_hw_rate;
3295 __le32 htc_template;
3296 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */
3297 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */
3298 struct list_head ba_cam_list;
3299 struct sk_buff_head roc_queue;
3300
3301 bool use_cfg_mask;
3302 struct cfg80211_bitrate_mask mask;
3303
3304 bool cctl_tx_time;
3305 u32 ampdu_max_time:4;
3306 bool cctl_tx_retry_limit;
3307 u32 data_tx_cnt_lmt:6;
3308 };
3309
3310 struct rtw89_efuse {
3311 bool valid;
3312 bool power_k_valid;
3313 u8 xtal_cap;
3314 u8 addr[ETH_ALEN];
3315 u8 rfe_type;
3316 char country_code[2];
3317 };
3318
3319 struct rtw89_phy_rate_pattern {
3320 u64 ra_mask;
3321 u16 rate;
3322 u8 ra_mode;
3323 bool enable;
3324 };
3325
3326 struct rtw89_tx_wait_info {
3327 struct rcu_head rcu_head;
3328 struct completion completion;
3329 bool tx_done;
3330 };
3331
3332 struct rtw89_tx_skb_data {
3333 struct rtw89_tx_wait_info __rcu *wait;
3334 u8 hci_priv[];
3335 };
3336
3337 #define RTW89_ROC_IDLE_TIMEOUT 500
3338 #define RTW89_ROC_TX_TIMEOUT 30
3339 enum rtw89_roc_state {
3340 RTW89_ROC_IDLE,
3341 RTW89_ROC_NORMAL,
3342 RTW89_ROC_MGMT,
3343 };
3344
3345 struct rtw89_roc {
3346 struct ieee80211_channel chan;
3347 struct delayed_work roc_work;
3348 enum ieee80211_roc_type type;
3349 enum rtw89_roc_state state;
3350 int duration;
3351 };
3352
3353 #define RTW89_P2P_MAX_NOA_NUM 2
3354
3355 struct rtw89_p2p_ie_head {
3356 u8 eid;
3357 u8 ie_len;
3358 u8 oui[3];
3359 u8 oui_type;
3360 } __packed;
3361
3362 struct rtw89_noa_attr_head {
3363 u8 attr_type;
3364 __le16 attr_len;
3365 u8 index;
3366 u8 oppps_ctwindow;
3367 } __packed;
3368
3369 struct rtw89_p2p_noa_ie {
3370 struct rtw89_p2p_ie_head p2p_head;
3371 struct rtw89_noa_attr_head noa_head;
3372 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM];
3373 } __packed;
3374
3375 struct rtw89_p2p_noa_setter {
3376 struct rtw89_p2p_noa_ie ie;
3377 u8 noa_count;
3378 u8 noa_index;
3379 };
3380
3381 struct rtw89_vif {
3382 struct list_head list;
3383 struct rtw89_dev *rtwdev;
3384 struct rtw89_roc roc;
3385 bool chanctx_assigned; /* only valid when running with chanctx_ops */
3386 enum rtw89_sub_entity_idx sub_entity_idx;
3387 enum rtw89_reg_6ghz_power reg_6ghz_power;
3388
3389 u8 mac_id;
3390 u8 port;
3391 u8 mac_addr[ETH_ALEN];
3392 u8 bssid[ETH_ALEN];
3393 __be32 ip_addr;
3394 u8 phy_idx;
3395 u8 mac_idx;
3396 u8 net_type;
3397 u8 wifi_role;
3398 u8 self_role;
3399 u8 wmm;
3400 u8 bcn_hit_cond;
3401 u8 hit_rule;
3402 u8 last_noa_nr;
3403 u64 sync_bcn_tsf;
3404 bool offchan;
3405 bool trigger;
3406 bool lsig_txop;
3407 u8 tgt_ind;
3408 u8 frm_tgt_ind;
3409 bool wowlan_pattern;
3410 bool wowlan_uc;
3411 bool wowlan_magic;
3412 bool is_hesta;
3413 bool last_a_ctrl;
3414 bool dyn_tb_bedge_en;
3415 bool pre_pwr_diff_en;
3416 bool pwr_diff_en;
3417 u8 def_tri_idx;
3418 u32 tdls_peer;
3419 struct work_struct update_beacon_work;
3420 struct rtw89_addr_cam_entry addr_cam;
3421 struct rtw89_bssid_cam_entry bssid_cam;
3422 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
3423 struct rtw89_traffic_stats stats;
3424 struct rtw89_phy_rate_pattern rate_pattern;
3425 struct cfg80211_scan_request *scan_req;
3426 struct ieee80211_scan_ies *scan_ies;
3427 struct list_head general_pkt_list;
3428 struct rtw89_p2p_noa_setter p2p_noa;
3429 };
3430
3431 enum rtw89_lv1_rcvy_step {
3432 RTW89_LV1_RCVY_STEP_1,
3433 RTW89_LV1_RCVY_STEP_2,
3434 };
3435
3436 struct rtw89_hci_ops {
3437 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
3438 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
3439 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
3440 void (*reset)(struct rtw89_dev *rtwdev);
3441 int (*start)(struct rtw89_dev *rtwdev);
3442 void (*stop)(struct rtw89_dev *rtwdev);
3443 void (*pause)(struct rtw89_dev *rtwdev, bool pause);
3444 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
3445 void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
3446
3447 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
3448 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
3449 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
3450 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
3451 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
3452 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
3453
3454 int (*mac_pre_init)(struct rtw89_dev *rtwdev);
3455 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev);
3456 int (*mac_post_init)(struct rtw89_dev *rtwdev);
3457 int (*deinit)(struct rtw89_dev *rtwdev);
3458
3459 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
3460 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
3461 void (*dump_err_status)(struct rtw89_dev *rtwdev);
3462 int (*napi_poll)(struct napi_struct *napi, int budget);
3463
3464 /* Deal with locks inside recovery_start and recovery_complete callbacks
3465 * by hci instance, and handle things which need to consider under SER.
3466 * e.g. turn on/off interrupts except for the one for halt notification.
3467 */
3468 void (*recovery_start)(struct rtw89_dev *rtwdev);
3469 void (*recovery_complete)(struct rtw89_dev *rtwdev);
3470
3471 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
3472 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
3473 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
3474 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev);
3475 void (*clr_idx_all)(struct rtw89_dev *rtwdev);
3476 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
3477 void (*disable_intr)(struct rtw89_dev *rtwdev);
3478 void (*enable_intr)(struct rtw89_dev *rtwdev);
3479 int (*rst_bdram)(struct rtw89_dev *rtwdev);
3480 };
3481
3482 struct rtw89_hci_info {
3483 const struct rtw89_hci_ops *ops;
3484 enum rtw89_hci_type type;
3485 u32 rpwm_addr;
3486 u32 cpwm_addr;
3487 bool paused;
3488 };
3489
3490 struct rtw89_chip_ops {
3491 int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
3492 int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
3493 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3494 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3495 void (*bb_reset)(struct rtw89_dev *rtwdev,
3496 enum rtw89_phy_idx phy_idx);
3497 void (*bb_sethw)(struct rtw89_dev *rtwdev);
3498 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3499 u32 addr, u32 mask);
3500 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3501 u32 addr, u32 mask, u32 data);
3502 void (*set_channel)(struct rtw89_dev *rtwdev,
3503 const struct rtw89_chan *chan,
3504 enum rtw89_mac_idx mac_idx,
3505 enum rtw89_phy_idx phy_idx);
3506 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
3507 struct rtw89_channel_help_params *p,
3508 const struct rtw89_chan *chan,
3509 enum rtw89_mac_idx mac_idx,
3510 enum rtw89_phy_idx phy_idx);
3511 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map,
3512 enum rtw89_efuse_block block);
3513 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
3514 void (*fem_setup)(struct rtw89_dev *rtwdev);
3515 void (*rfe_gpio)(struct rtw89_dev *rtwdev);
3516 void (*rfk_hw_init)(struct rtw89_dev *rtwdev);
3517 void (*rfk_init)(struct rtw89_dev *rtwdev);
3518 void (*rfk_init_late)(struct rtw89_dev *rtwdev);
3519 void (*rfk_channel)(struct rtw89_dev *rtwdev);
3520 void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
3521 enum rtw89_phy_idx phy_idx);
3522 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start);
3523 void (*rfk_track)(struct rtw89_dev *rtwdev);
3524 void (*power_trim)(struct rtw89_dev *rtwdev);
3525 void (*set_txpwr)(struct rtw89_dev *rtwdev,
3526 const struct rtw89_chan *chan,
3527 enum rtw89_phy_idx phy_idx);
3528 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
3529 enum rtw89_phy_idx phy_idx);
3530 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3531 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
3532 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en,
3533 enum rtw89_phy_idx phy_idx);
3534 void (*query_ppdu)(struct rtw89_dev *rtwdev,
3535 struct rtw89_rx_phy_ppdu *phy_ppdu,
3536 struct ieee80211_rx_status *status);
3537 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en,
3538 enum rtw89_phy_idx phy_idx);
3539 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
3540 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
3541 s8 pw_ofst, enum rtw89_mac_idx mac_idx);
3542 int (*pwr_on_func)(struct rtw89_dev *rtwdev);
3543 int (*pwr_off_func)(struct rtw89_dev *rtwdev);
3544 void (*query_rxdesc)(struct rtw89_dev *rtwdev,
3545 struct rtw89_rx_desc_info *desc_info,
3546 u8 *data, u32 data_offset);
3547 void (*fill_txdesc)(struct rtw89_dev *rtwdev,
3548 struct rtw89_tx_desc_info *desc_info,
3549 void *txdesc);
3550 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
3551 struct rtw89_tx_desc_info *desc_info,
3552 void *txdesc);
3553 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
3554 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
3555 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
3556 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
3557 u32 *tx_en, enum rtw89_sch_tx_sel sel);
3558 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
3559 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
3560 struct rtw89_vif *rtwvif,
3561 struct rtw89_sta *rtwsta);
3562 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev,
3563 struct rtw89_vif *rtwvif,
3564 struct rtw89_sta *rtwsta);
3565 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev,
3566 struct ieee80211_vif *vif,
3567 struct ieee80211_sta *sta);
3568 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev,
3569 struct ieee80211_vif *vif,
3570 struct ieee80211_sta *sta);
3571 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev,
3572 struct rtw89_vif *rtwvif,
3573 struct rtw89_sta *rtwsta);
3574 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev,
3575 struct rtw89_vif *rtwvif);
3576 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
3577 bool valid, struct ieee80211_ampdu_params *params);
3578
3579 void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
3580 void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
3581 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
3582 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
3583 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
3584 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
3585 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
3586 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
3587 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level);
3588 };
3589
3590 enum rtw89_dma_ch {
3591 RTW89_DMA_ACH0 = 0,
3592 RTW89_DMA_ACH1 = 1,
3593 RTW89_DMA_ACH2 = 2,
3594 RTW89_DMA_ACH3 = 3,
3595 RTW89_DMA_ACH4 = 4,
3596 RTW89_DMA_ACH5 = 5,
3597 RTW89_DMA_ACH6 = 6,
3598 RTW89_DMA_ACH7 = 7,
3599 RTW89_DMA_B0MG = 8,
3600 RTW89_DMA_B0HI = 9,
3601 RTW89_DMA_B1MG = 10,
3602 RTW89_DMA_B1HI = 11,
3603 RTW89_DMA_H2C = 12,
3604 RTW89_DMA_CH_NUM = 13
3605 };
3606
3607 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0))
3608
3609 enum rtw89_mlo_dbcc_mode {
3610 MLO_DBCC_NOT_SUPPORT = 1,
3611 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1),
3612 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2),
3613 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1),
3614 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2),
3615 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1),
3616 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2),
3617 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2),
3618 DBCC_LEGACY = 0xffffffff,
3619 };
3620
3621 enum rtw89_scan_be_operation {
3622 RTW89_SCAN_OP_STOP,
3623 RTW89_SCAN_OP_START,
3624 RTW89_SCAN_OP_SETPARM,
3625 RTW89_SCAN_OP_GETRPT,
3626 RTW89_SCAN_OP_NUM
3627 };
3628
3629 enum rtw89_scan_be_mode {
3630 RTW89_SCAN_MODE_SA,
3631 RTW89_SCAN_MODE_MACC,
3632 RTW89_SCAN_MODE_NUM
3633 };
3634
3635 enum rtw89_scan_be_opmode {
3636 RTW89_SCAN_OPMODE_NONE,
3637 RTW89_SCAN_OPMODE_TBTT,
3638 RTW89_SCAN_OPMODE_INTV,
3639 RTW89_SCAN_OPMODE_CNT,
3640 RTW89_SCAN_OPMODE_NUM,
3641 };
3642
3643 struct rtw89_scan_option {
3644 bool enable;
3645 bool target_ch_mode;
3646 u8 num_macc_role;
3647 u8 num_opch;
3648 u8 repeat;
3649 u16 norm_pd;
3650 u16 slow_pd;
3651 u16 norm_cy;
3652 u8 opch_end;
3653 u64 prohib_chan;
3654 enum rtw89_phy_idx band;
3655 enum rtw89_scan_be_operation operation;
3656 enum rtw89_scan_be_mode scan_mode;
3657 enum rtw89_mlo_dbcc_mode mlo_mode;
3658 };
3659
3660 enum rtw89_qta_mode {
3661 RTW89_QTA_SCC,
3662 RTW89_QTA_DBCC,
3663 RTW89_QTA_DLFW,
3664 RTW89_QTA_WOW,
3665
3666 /* keep last */
3667 RTW89_QTA_INVALID,
3668 };
3669
3670 struct rtw89_hfc_ch_cfg {
3671 u16 min;
3672 u16 max;
3673 #define grp_0 0
3674 #define grp_1 1
3675 #define grp_num 2
3676 u8 grp;
3677 };
3678
3679 struct rtw89_hfc_ch_info {
3680 u16 aval;
3681 u16 used;
3682 };
3683
3684 struct rtw89_hfc_pub_cfg {
3685 u16 grp0;
3686 u16 grp1;
3687 u16 pub_max;
3688 u16 wp_thrd;
3689 };
3690
3691 struct rtw89_hfc_pub_info {
3692 u16 g0_used;
3693 u16 g1_used;
3694 u16 g0_aval;
3695 u16 g1_aval;
3696 u16 pub_aval;
3697 u16 wp_aval;
3698 };
3699
3700 struct rtw89_hfc_prec_cfg {
3701 u16 ch011_prec;
3702 u16 h2c_prec;
3703 u16 wp_ch07_prec;
3704 u16 wp_ch811_prec;
3705 u8 ch011_full_cond;
3706 u8 h2c_full_cond;
3707 u8 wp_ch07_full_cond;
3708 u8 wp_ch811_full_cond;
3709 };
3710
3711 struct rtw89_hfc_param {
3712 bool en;
3713 bool h2c_en;
3714 u8 mode;
3715 const struct rtw89_hfc_ch_cfg *ch_cfg;
3716 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
3717 struct rtw89_hfc_pub_cfg pub_cfg;
3718 struct rtw89_hfc_pub_info pub_info;
3719 struct rtw89_hfc_prec_cfg prec_cfg;
3720 };
3721
3722 struct rtw89_hfc_param_ini {
3723 const struct rtw89_hfc_ch_cfg *ch_cfg;
3724 const struct rtw89_hfc_pub_cfg *pub_cfg;
3725 const struct rtw89_hfc_prec_cfg *prec_cfg;
3726 u8 mode;
3727 };
3728
3729 struct rtw89_dle_size {
3730 u16 pge_size;
3731 u16 lnk_pge_num;
3732 u16 unlnk_pge_num;
3733 /* for WiFi 7 chips below */
3734 u32 srt_ofst;
3735 };
3736
3737 struct rtw89_wde_quota {
3738 u16 hif;
3739 u16 wcpu;
3740 u16 pkt_in;
3741 u16 cpu_io;
3742 };
3743
3744 struct rtw89_ple_quota {
3745 u16 cma0_tx;
3746 u16 cma1_tx;
3747 u16 c2h;
3748 u16 h2c;
3749 u16 wcpu;
3750 u16 mpdu_proc;
3751 u16 cma0_dma;
3752 u16 cma1_dma;
3753 u16 bb_rpt;
3754 u16 wd_rel;
3755 u16 cpu_io;
3756 u16 tx_rpt;
3757 /* for WiFi 7 chips below */
3758 u16 h2d;
3759 };
3760
3761 struct rtw89_rsvd_quota {
3762 u16 mpdu_info_tbl;
3763 u16 b0_csi;
3764 u16 b1_csi;
3765 u16 b0_lmr;
3766 u16 b1_lmr;
3767 u16 b0_ftm;
3768 u16 b1_ftm;
3769 u16 b0_smr;
3770 u16 b1_smr;
3771 u16 others;
3772 };
3773
3774 struct rtw89_dle_rsvd_size {
3775 u32 srt_ofst;
3776 u32 size;
3777 };
3778
3779 struct rtw89_dle_mem {
3780 enum rtw89_qta_mode mode;
3781 const struct rtw89_dle_size *wde_size;
3782 const struct rtw89_dle_size *ple_size;
3783 const struct rtw89_wde_quota *wde_min_qt;
3784 const struct rtw89_wde_quota *wde_max_qt;
3785 const struct rtw89_ple_quota *ple_min_qt;
3786 const struct rtw89_ple_quota *ple_max_qt;
3787 /* for WiFi 7 chips below */
3788 const struct rtw89_rsvd_quota *rsvd_qt;
3789 const struct rtw89_dle_rsvd_size *rsvd0_size;
3790 const struct rtw89_dle_rsvd_size *rsvd1_size;
3791 };
3792
3793 struct rtw89_reg_def {
3794 u32 addr;
3795 u32 mask;
3796 };
3797
3798 struct rtw89_reg2_def {
3799 u32 addr;
3800 u32 data;
3801 };
3802
3803 struct rtw89_reg3_def {
3804 u32 addr;
3805 u32 mask;
3806 u32 data;
3807 };
3808
3809 struct rtw89_reg5_def {
3810 u8 flag; /* recognized by parsers */
3811 u8 path;
3812 u32 addr;
3813 u32 mask;
3814 u32 data;
3815 };
3816
3817 struct rtw89_reg_imr {
3818 u32 addr;
3819 u32 clr;
3820 u32 set;
3821 };
3822
3823 struct rtw89_phy_table {
3824 const struct rtw89_reg2_def *regs;
3825 u32 n_regs;
3826 enum rtw89_rf_path rf_path;
3827 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
3828 enum rtw89_rf_path rf_path, void *data);
3829 };
3830
3831 struct rtw89_txpwr_table {
3832 const void *data;
3833 u32 size;
3834 void (*load)(struct rtw89_dev *rtwdev,
3835 const struct rtw89_txpwr_table *tbl);
3836 };
3837
3838 struct rtw89_txpwr_rule_2ghz {
3839 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
3840 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3841 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3842 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3843 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3844 };
3845
3846 struct rtw89_txpwr_rule_5ghz {
3847 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
3848 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3849 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3850 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3851 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3852 };
3853
3854 struct rtw89_txpwr_rule_6ghz {
3855 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
3856 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3857 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3858 [RTW89_6G_CH_NUM];
3859 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3860 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3861 [RTW89_6G_CH_NUM];
3862 };
3863
3864 struct rtw89_tx_shape {
3865 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
3866 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM];
3867 };
3868
3869 struct rtw89_rfe_parms {
3870 const struct rtw89_txpwr_table *byr_tbl;
3871 struct rtw89_txpwr_rule_2ghz rule_2ghz;
3872 struct rtw89_txpwr_rule_5ghz rule_5ghz;
3873 struct rtw89_txpwr_rule_6ghz rule_6ghz;
3874 struct rtw89_tx_shape tx_shape;
3875 };
3876
3877 struct rtw89_rfe_parms_conf {
3878 const struct rtw89_rfe_parms *rfe_parms;
3879 u8 rfe_type;
3880 };
3881
3882 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0
3883
3884 struct rtw89_txpwr_conf {
3885 u8 rfe_type;
3886 u8 ent_sz;
3887 u32 num_ents;
3888 const void *data;
3889 };
3890
3891 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data)
3892
3893 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \
3894 for (typecheck(const void *, cursor), (cursor) = (conf)->data, \
3895 memcpy(&(entry), cursor, \
3896 min_t(u8, sizeof(entry), (conf)->ent_sz)); \
3897 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \
3898 (cursor) += (conf)->ent_sz, \
3899 memcpy(&(entry), cursor, \
3900 min_t(u8, sizeof(entry), (conf)->ent_sz)))
3901
3902 struct rtw89_txpwr_byrate_data {
3903 struct rtw89_txpwr_conf conf;
3904 struct rtw89_txpwr_table tbl;
3905 };
3906
3907 struct rtw89_txpwr_lmt_2ghz_data {
3908 struct rtw89_txpwr_conf conf;
3909 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
3910 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3911 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3912 };
3913
3914 struct rtw89_txpwr_lmt_5ghz_data {
3915 struct rtw89_txpwr_conf conf;
3916 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
3917 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3918 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3919 };
3920
3921 struct rtw89_txpwr_lmt_6ghz_data {
3922 struct rtw89_txpwr_conf conf;
3923 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
3924 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3925 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3926 [RTW89_6G_CH_NUM];
3927 };
3928
3929 struct rtw89_txpwr_lmt_ru_2ghz_data {
3930 struct rtw89_txpwr_conf conf;
3931 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
3932 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3933 };
3934
3935 struct rtw89_txpwr_lmt_ru_5ghz_data {
3936 struct rtw89_txpwr_conf conf;
3937 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
3938 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3939 };
3940
3941 struct rtw89_txpwr_lmt_ru_6ghz_data {
3942 struct rtw89_txpwr_conf conf;
3943 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
3944 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3945 [RTW89_6G_CH_NUM];
3946 };
3947
3948 struct rtw89_tx_shape_lmt_data {
3949 struct rtw89_txpwr_conf conf;
3950 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
3951 };
3952
3953 struct rtw89_tx_shape_lmt_ru_data {
3954 struct rtw89_txpwr_conf conf;
3955 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM];
3956 };
3957
3958 struct rtw89_rfe_data {
3959 struct rtw89_txpwr_byrate_data byrate;
3960 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz;
3961 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz;
3962 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz;
3963 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz;
3964 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz;
3965 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz;
3966 struct rtw89_tx_shape_lmt_data tx_shape_lmt;
3967 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru;
3968 struct rtw89_rfe_parms rfe_parms;
3969 };
3970
3971 struct rtw89_page_regs {
3972 u32 hci_fc_ctrl;
3973 u32 ch_page_ctrl;
3974 u32 ach_page_ctrl;
3975 u32 ach_page_info;
3976 u32 pub_page_info3;
3977 u32 pub_page_ctrl1;
3978 u32 pub_page_ctrl2;
3979 u32 pub_page_info1;
3980 u32 pub_page_info2;
3981 u32 wp_page_ctrl1;
3982 u32 wp_page_ctrl2;
3983 u32 wp_page_info1;
3984 };
3985
3986 struct rtw89_imr_info {
3987 u32 wdrls_imr_set;
3988 u32 wsec_imr_reg;
3989 u32 wsec_imr_set;
3990 u32 mpdu_tx_imr_set;
3991 u32 mpdu_rx_imr_set;
3992 u32 sta_sch_imr_set;
3993 u32 txpktctl_imr_b0_reg;
3994 u32 txpktctl_imr_b0_clr;
3995 u32 txpktctl_imr_b0_set;
3996 u32 txpktctl_imr_b1_reg;
3997 u32 txpktctl_imr_b1_clr;
3998 u32 txpktctl_imr_b1_set;
3999 u32 wde_imr_clr;
4000 u32 wde_imr_set;
4001 u32 ple_imr_clr;
4002 u32 ple_imr_set;
4003 u32 host_disp_imr_clr;
4004 u32 host_disp_imr_set;
4005 u32 cpu_disp_imr_clr;
4006 u32 cpu_disp_imr_set;
4007 u32 other_disp_imr_clr;
4008 u32 other_disp_imr_set;
4009 u32 bbrpt_com_err_imr_reg;
4010 u32 bbrpt_chinfo_err_imr_reg;
4011 u32 bbrpt_err_imr_set;
4012 u32 bbrpt_dfs_err_imr_reg;
4013 u32 ptcl_imr_clr;
4014 u32 ptcl_imr_set;
4015 u32 cdma_imr_0_reg;
4016 u32 cdma_imr_0_clr;
4017 u32 cdma_imr_0_set;
4018 u32 cdma_imr_1_reg;
4019 u32 cdma_imr_1_clr;
4020 u32 cdma_imr_1_set;
4021 u32 phy_intf_imr_reg;
4022 u32 phy_intf_imr_clr;
4023 u32 phy_intf_imr_set;
4024 u32 rmac_imr_reg;
4025 u32 rmac_imr_clr;
4026 u32 rmac_imr_set;
4027 u32 tmac_imr_reg;
4028 u32 tmac_imr_clr;
4029 u32 tmac_imr_set;
4030 };
4031
4032 struct rtw89_imr_table {
4033 const struct rtw89_reg_imr *regs;
4034 u32 n_regs;
4035 };
4036
4037 struct rtw89_xtal_info {
4038 u32 xcap_reg;
4039 u32 sc_xo_mask;
4040 u32 sc_xi_mask;
4041 };
4042
4043 struct rtw89_rrsr_cfgs {
4044 struct rtw89_reg3_def ref_rate;
4045 struct rtw89_reg3_def rsc;
4046 };
4047
4048 struct rtw89_dig_regs {
4049 u32 seg0_pd_reg;
4050 u32 pd_lower_bound_mask;
4051 u32 pd_spatial_reuse_en;
4052 u32 bmode_pd_reg;
4053 u32 bmode_cca_rssi_limit_en;
4054 u32 bmode_pd_lower_bound_reg;
4055 u32 bmode_rssi_nocca_low_th_mask;
4056 struct rtw89_reg_def p0_lna_init;
4057 struct rtw89_reg_def p1_lna_init;
4058 struct rtw89_reg_def p0_tia_init;
4059 struct rtw89_reg_def p1_tia_init;
4060 struct rtw89_reg_def p0_rxb_init;
4061 struct rtw89_reg_def p1_rxb_init;
4062 struct rtw89_reg_def p0_p20_pagcugc_en;
4063 struct rtw89_reg_def p0_s20_pagcugc_en;
4064 struct rtw89_reg_def p1_p20_pagcugc_en;
4065 struct rtw89_reg_def p1_s20_pagcugc_en;
4066 };
4067
4068 struct rtw89_edcca_regs {
4069 u32 edcca_level;
4070 u32 edcca_mask;
4071 u32 edcca_p_mask;
4072 u32 ppdu_level;
4073 u32 ppdu_mask;
4074 u32 rpt_a;
4075 u32 rpt_b;
4076 u32 rpt_sel;
4077 u32 rpt_sel_mask;
4078 u32 rpt_sel_be;
4079 u32 rpt_sel_be_mask;
4080 u32 tx_collision_t2r_st;
4081 u32 tx_collision_t2r_st_mask;
4082 };
4083
4084 struct rtw89_phy_ul_tb_info {
4085 bool dyn_tb_tri_en;
4086 u8 def_if_bandedge;
4087 };
4088
4089 struct rtw89_antdiv_stats {
4090 struct ewma_rssi cck_rssi_avg;
4091 struct ewma_rssi ofdm_rssi_avg;
4092 struct ewma_rssi non_legacy_rssi_avg;
4093 u16 pkt_cnt_cck;
4094 u16 pkt_cnt_ofdm;
4095 u16 pkt_cnt_non_legacy;
4096 u32 evm;
4097 };
4098
4099 struct rtw89_antdiv_info {
4100 struct rtw89_antdiv_stats target_stats;
4101 struct rtw89_antdiv_stats main_stats;
4102 struct rtw89_antdiv_stats aux_stats;
4103 u8 training_count;
4104 u8 rssi_pre;
4105 bool get_stats;
4106 };
4107
4108 enum rtw89_chanctx_state {
4109 RTW89_CHANCTX_STATE_MCC_START,
4110 RTW89_CHANCTX_STATE_MCC_STOP,
4111 };
4112
4113 enum rtw89_chanctx_callbacks {
4114 RTW89_CHANCTX_CALLBACK_PLACEHOLDER,
4115 RTW89_CHANCTX_CALLBACK_RFK,
4116
4117 NUM_OF_RTW89_CHANCTX_CALLBACKS,
4118 };
4119
4120 struct rtw89_chanctx_listener {
4121 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS])
4122 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state);
4123 };
4124
4125 struct rtw89_chip_info {
4126 enum rtw89_core_chip_id chip_id;
4127 enum rtw89_chip_gen chip_gen;
4128 const struct rtw89_chip_ops *ops;
4129 const struct rtw89_mac_gen_def *mac_def;
4130 const struct rtw89_phy_gen_def *phy_def;
4131 const char *fw_basename;
4132 u8 fw_format_max;
4133 bool try_ce_fw;
4134 u8 bbmcu_nr;
4135 u32 needed_fw_elms;
4136 u32 fifo_size;
4137 bool small_fifo_size;
4138 u32 dle_scc_rsvd_size;
4139 u16 max_amsdu_limit;
4140 bool dis_2g_40m_ul_ofdma;
4141 u32 rsvd_ple_ofst;
4142 const struct rtw89_hfc_param_ini *hfc_param_ini;
4143 const struct rtw89_dle_mem *dle_mem;
4144 u8 wde_qempty_acq_grpnum;
4145 u8 wde_qempty_mgq_grpsel;
4146 u32 rf_base_addr[2];
4147 u8 support_chanctx_num;
4148 u8 support_bands;
4149 u16 support_bandwidths;
4150 bool support_unii4;
4151 bool support_rnr;
4152 bool ul_tb_waveform_ctrl;
4153 bool ul_tb_pwr_diff;
4154 bool hw_sec_hdr;
4155 u8 rf_path_num;
4156 u8 tx_nss;
4157 u8 rx_nss;
4158 u8 acam_num;
4159 u8 bcam_num;
4160 u8 scam_num;
4161 u8 bacam_num;
4162 u8 bacam_dynamic_num;
4163 enum rtw89_bacam_ver bacam_ver;
4164 u8 ppdu_max_usr;
4165
4166 u8 sec_ctrl_efuse_size;
4167 u32 physical_efuse_size;
4168 u32 logical_efuse_size;
4169 u32 limit_efuse_size;
4170 u32 dav_phy_efuse_size;
4171 u32 dav_log_efuse_size;
4172 u32 phycap_addr;
4173 u32 phycap_size;
4174 const struct rtw89_efuse_block_cfg *efuse_blocks;
4175
4176 const struct rtw89_pwr_cfg * const *pwr_on_seq;
4177 const struct rtw89_pwr_cfg * const *pwr_off_seq;
4178 const struct rtw89_phy_table *bb_table;
4179 const struct rtw89_phy_table *bb_gain_table;
4180 const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
4181 const struct rtw89_phy_table *nctl_table;
4182 const struct rtw89_rfk_tbl *nctl_post_table;
4183 const struct rtw89_phy_dig_gain_table *dig_table;
4184 const struct rtw89_dig_regs *dig_regs;
4185 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
4186
4187 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */
4188 const struct rtw89_rfe_parms_conf *rfe_parms_conf;
4189 const struct rtw89_rfe_parms *dflt_parms;
4190 const struct rtw89_chanctx_listener *chanctx_listener;
4191
4192 u8 txpwr_factor_rf;
4193 u8 txpwr_factor_mac;
4194
4195 u32 para_ver;
4196 u32 wlcx_desired;
4197 u8 btcx_desired;
4198 u8 scbd;
4199 u8 mailbox;
4200
4201 u8 afh_guard_ch;
4202 const u8 *wl_rssi_thres;
4203 const u8 *bt_rssi_thres;
4204 u8 rssi_tol;
4205
4206 u8 mon_reg_num;
4207 const struct rtw89_btc_fbtc_mreg *mon_reg;
4208 u8 rf_para_ulink_num;
4209 const struct rtw89_btc_rf_trx_para *rf_para_ulink;
4210 u8 rf_para_dlink_num;
4211 const struct rtw89_btc_rf_trx_para *rf_para_dlink;
4212 u8 ps_mode_supported;
4213 u8 low_power_hci_modes;
4214
4215 u32 h2c_cctl_func_id;
4216 u32 hci_func_en_addr;
4217 u32 h2c_desc_size;
4218 u32 txwd_body_size;
4219 u32 txwd_info_size;
4220 u32 h2c_ctrl_reg;
4221 const u32 *h2c_regs;
4222 struct rtw89_reg_def h2c_counter_reg;
4223 u32 c2h_ctrl_reg;
4224 const u32 *c2h_regs;
4225 struct rtw89_reg_def c2h_counter_reg;
4226 const struct rtw89_page_regs *page_regs;
4227 u32 wow_reason_reg;
4228 bool cfo_src_fd;
4229 bool cfo_hw_comp;
4230 const struct rtw89_reg_def *dcfo_comp;
4231 u8 dcfo_comp_sft;
4232 const struct rtw89_imr_info *imr_info;
4233 const struct rtw89_imr_table *imr_dmac_table;
4234 const struct rtw89_imr_table *imr_cmac_table;
4235 const struct rtw89_rrsr_cfgs *rrsr_cfgs;
4236 struct rtw89_reg_def bss_clr_vld;
4237 u32 bss_clr_map_reg;
4238 u32 dma_ch_mask;
4239 const struct rtw89_edcca_regs *edcca_regs;
4240 const struct wiphy_wowlan_support *wowlan_stub;
4241 const struct rtw89_xtal_info *xtal_info;
4242 };
4243
4244 union rtw89_bus_info {
4245 const struct rtw89_pci_info *pci;
4246 };
4247
4248 struct rtw89_driver_info {
4249 const struct rtw89_chip_info *chip;
4250 const struct dmi_system_id *quirks;
4251 union rtw89_bus_info bus;
4252 };
4253
4254 enum rtw89_hcifc_mode {
4255 RTW89_HCIFC_POH = 0,
4256 RTW89_HCIFC_STF = 1,
4257 RTW89_HCIFC_SDIO = 2,
4258
4259 /* keep last */
4260 RTW89_HCIFC_MODE_INVALID,
4261 };
4262
4263 struct rtw89_dle_info {
4264 const struct rtw89_rsvd_quota *rsvd_qt;
4265 enum rtw89_qta_mode qta_mode;
4266 u16 ple_pg_size;
4267 u16 ple_free_pg;
4268 u16 c0_rx_qta;
4269 u16 c1_rx_qta;
4270 };
4271
4272 enum rtw89_host_rpr_mode {
4273 RTW89_RPR_MODE_POH = 0,
4274 RTW89_RPR_MODE_STF
4275 };
4276
4277 #define RTW89_COMPLETION_BUF_SIZE 40
4278 #define RTW89_WAIT_COND_IDLE UINT_MAX
4279
4280 struct rtw89_completion_data {
4281 bool err;
4282 u8 buf[RTW89_COMPLETION_BUF_SIZE];
4283 };
4284
4285 struct rtw89_wait_info {
4286 atomic_t cond;
4287 struct completion completion;
4288 struct rtw89_completion_data data;
4289 };
4290
4291 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
4292
rtw89_init_wait(struct rtw89_wait_info * wait)4293 static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
4294 {
4295 init_completion(&wait->completion);
4296 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
4297 }
4298
4299 struct rtw89_mac_info {
4300 struct rtw89_dle_info dle_info;
4301 struct rtw89_hfc_param hfc_param;
4302 enum rtw89_qta_mode qta_mode;
4303 u8 rpwm_seq_num;
4304 u8 cpwm_seq_num;
4305
4306 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */
4307 struct rtw89_wait_info fw_ofld_wait;
4308 };
4309
4310 enum rtw89_fwdl_check_type {
4311 RTW89_FWDL_CHECK_FREERTOS_DONE,
4312 RTW89_FWDL_CHECK_WCPU_FWDL_DONE,
4313 RTW89_FWDL_CHECK_DCPU_FWDL_DONE,
4314 RTW89_FWDL_CHECK_BB0_FWDL_DONE,
4315 RTW89_FWDL_CHECK_BB1_FWDL_DONE,
4316 };
4317
4318 enum rtw89_fw_type {
4319 RTW89_FW_NORMAL = 1,
4320 RTW89_FW_WOWLAN = 3,
4321 RTW89_FW_NORMAL_CE = 5,
4322 RTW89_FW_BBMCU0 = 64,
4323 RTW89_FW_BBMCU1 = 65,
4324 RTW89_FW_LOGFMT = 255,
4325 };
4326
4327 enum rtw89_fw_feature {
4328 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
4329 RTW89_FW_FEATURE_SCAN_OFFLOAD,
4330 RTW89_FW_FEATURE_TX_WAKE,
4331 RTW89_FW_FEATURE_CRASH_TRIGGER,
4332 RTW89_FW_FEATURE_NO_PACKET_DROP,
4333 RTW89_FW_FEATURE_NO_DEEP_PS,
4334 RTW89_FW_FEATURE_NO_LPS_PG,
4335 RTW89_FW_FEATURE_BEACON_FILTER,
4336 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP,
4337 };
4338
4339 struct rtw89_fw_suit {
4340 enum rtw89_fw_type type;
4341 const u8 *data;
4342 u32 size;
4343 u8 major_ver;
4344 u8 minor_ver;
4345 u8 sub_ver;
4346 u8 sub_idex;
4347 u16 build_year;
4348 u16 build_mon;
4349 u16 build_date;
4350 u16 build_hour;
4351 u16 build_min;
4352 u8 cmd_ver;
4353 u8 hdr_ver;
4354 u32 commitid;
4355 };
4356
4357 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \
4358 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
4359 #define RTW89_FW_SUIT_VER_CODE(s) \
4360 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
4361
4362 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \
4363 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \
4364 (mfw_hdr)->ver.minor, \
4365 (mfw_hdr)->ver.sub, \
4366 (mfw_hdr)->ver.idx)
4367
4368 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \
4369 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \
4370 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \
4371 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \
4372 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX))
4373
4374 struct rtw89_fw_req_info {
4375 const struct firmware *firmware;
4376 struct completion completion;
4377 };
4378
4379 struct rtw89_fw_log {
4380 struct rtw89_fw_suit suit;
4381 bool enable;
4382 u32 last_fmt_id;
4383 u32 fmt_count;
4384 const __le32 *fmt_ids;
4385 const char *(*fmts)[];
4386 };
4387
4388 struct rtw89_fw_elm_info {
4389 struct rtw89_phy_table *bb_tbl;
4390 struct rtw89_phy_table *bb_gain;
4391 struct rtw89_phy_table *rf_radio[RF_PATH_MAX];
4392 struct rtw89_phy_table *rf_nctl;
4393 struct rtw89_fw_txpwr_track_cfg *txpwr_trk;
4394 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt;
4395 };
4396
4397 enum rtw89_fw_mss_dev_type {
4398 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF,
4399 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF,
4400 };
4401
4402 struct rtw89_fw_secure {
4403 bool secure_boot;
4404 u32 sb_sel_mgn;
4405 u8 mss_dev_type;
4406 u8 mss_cust_idx;
4407 u8 mss_key_num;
4408 };
4409
4410 struct rtw89_fw_info {
4411 struct rtw89_fw_req_info req;
4412 int fw_format;
4413 u8 h2c_seq;
4414 u8 rec_seq;
4415 u8 h2c_counter;
4416 u8 c2h_counter;
4417 struct rtw89_fw_suit normal;
4418 struct rtw89_fw_suit wowlan;
4419 struct rtw89_fw_suit bbmcu0;
4420 struct rtw89_fw_suit bbmcu1;
4421 struct rtw89_fw_log log;
4422 u32 feature_map;
4423 struct rtw89_fw_elm_info elm_info;
4424 struct rtw89_fw_secure sec;
4425 };
4426
4427 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \
4428 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
4429
4430 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
4431 ((_fw)->feature_map |= BIT(_fw_feature))
4432
4433 struct rtw89_cam_info {
4434 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
4435 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
4436 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
4437 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM);
4438 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM];
4439 };
4440
4441 enum rtw89_sar_sources {
4442 RTW89_SAR_SOURCE_NONE,
4443 RTW89_SAR_SOURCE_COMMON,
4444
4445 RTW89_SAR_SOURCE_NR,
4446 };
4447
4448 enum rtw89_sar_subband {
4449 RTW89_SAR_2GHZ_SUBBAND,
4450 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */
4451 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */
4452 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */
4453 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4454 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4455 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */
4456 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4457 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4458 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */
4459
4460 RTW89_SAR_SUBBAND_NR,
4461 };
4462
4463 struct rtw89_sar_cfg_common {
4464 bool set[RTW89_SAR_SUBBAND_NR];
4465 s32 cfg[RTW89_SAR_SUBBAND_NR];
4466 };
4467
4468 struct rtw89_sar_info {
4469 /* used to decide how to acces SAR cfg union */
4470 enum rtw89_sar_sources src;
4471
4472 /* reserved for different knids of SAR cfg struct.
4473 * supposed that a single cfg struct cannot handle various SAR sources.
4474 */
4475 union {
4476 struct rtw89_sar_cfg_common cfg_common;
4477 };
4478 };
4479
4480 enum rtw89_tas_state {
4481 RTW89_TAS_STATE_DPR_OFF,
4482 RTW89_TAS_STATE_DPR_ON,
4483 RTW89_TAS_STATE_DPR_FORBID,
4484 };
4485
4486 #define RTW89_TAS_MAX_WINDOW 50
4487 struct rtw89_tas_info {
4488 s16 txpwr_history[RTW89_TAS_MAX_WINDOW];
4489 s32 total_txpwr;
4490 u8 cur_idx;
4491 s8 dpr_gap;
4492 s8 delta;
4493 enum rtw89_tas_state state;
4494 bool enable;
4495 };
4496
4497 struct rtw89_chanctx_cfg {
4498 enum rtw89_sub_entity_idx idx;
4499 int ref_count;
4500 };
4501
4502 enum rtw89_chanctx_changes {
4503 RTW89_CHANCTX_REMOTE_STA_CHANGE,
4504 RTW89_CHANCTX_BCN_OFFSET_CHANGE,
4505 RTW89_CHANCTX_P2P_PS_CHANGE,
4506 RTW89_CHANCTX_BT_SLOT_CHANGE,
4507 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE,
4508
4509 NUM_OF_RTW89_CHANCTX_CHANGES,
4510 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES,
4511 };
4512
4513 enum rtw89_entity_mode {
4514 RTW89_ENTITY_MODE_SCC,
4515 RTW89_ENTITY_MODE_MCC_PREPARE,
4516 RTW89_ENTITY_MODE_MCC,
4517
4518 NUM_OF_RTW89_ENTITY_MODE,
4519 RTW89_ENTITY_MODE_INVALID = -EINVAL,
4520 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH,
4521 };
4522
4523 struct rtw89_sub_entity {
4524 struct cfg80211_chan_def chandef;
4525 struct rtw89_chan chan;
4526 struct rtw89_chan_rcd rcd;
4527
4528 /* only assigned when running with chanctx_ops */
4529 struct rtw89_chanctx_cfg *cfg;
4530 };
4531
4532 struct rtw89_edcca_bak {
4533 u8 a;
4534 u8 p;
4535 u8 ppdu;
4536 u8 th_old;
4537 };
4538
4539 enum rtw89_dm_type {
4540 RTW89_DM_DYNAMIC_EDCCA,
4541 };
4542
4543 struct rtw89_hal {
4544 u32 rx_fltr;
4545 u8 cv;
4546 u8 acv;
4547 u32 antenna_tx;
4548 u32 antenna_rx;
4549 u8 tx_nss;
4550 u8 rx_nss;
4551 bool tx_path_diversity;
4552 bool ant_diversity;
4553 bool ant_diversity_fixed;
4554 bool support_cckpd;
4555 bool support_igi;
4556 atomic_t roc_entity_idx;
4557
4558 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES);
4559 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY);
4560 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY];
4561 struct cfg80211_chan_def roc_chandef;
4562
4563 bool entity_active;
4564 bool entity_pause;
4565 enum rtw89_entity_mode entity_mode;
4566
4567 struct rtw89_edcca_bak edcca_bak;
4568 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */
4569 };
4570
4571 #define RTW89_MAX_MAC_ID_NUM 128
4572 #define RTW89_MAX_PKT_OFLD_NUM 255
4573
4574 enum rtw89_flags {
4575 RTW89_FLAG_POWERON,
4576 RTW89_FLAG_DMAC_FUNC,
4577 RTW89_FLAG_CMAC0_FUNC,
4578 RTW89_FLAG_CMAC1_FUNC,
4579 RTW89_FLAG_FW_RDY,
4580 RTW89_FLAG_RUNNING,
4581 RTW89_FLAG_PROBE_DONE,
4582 RTW89_FLAG_BFEE_MON,
4583 RTW89_FLAG_BFEE_EN,
4584 RTW89_FLAG_BFEE_TIMER_KEEP,
4585 RTW89_FLAG_NAPI_RUNNING,
4586 RTW89_FLAG_LEISURE_PS,
4587 RTW89_FLAG_LOW_POWER_MODE,
4588 RTW89_FLAG_INACTIVE_PS,
4589 RTW89_FLAG_CRASH_SIMULATING,
4590 RTW89_FLAG_SER_HANDLING,
4591 RTW89_FLAG_WOWLAN,
4592 RTW89_FLAG_FORBIDDEN_TRACK_WROK,
4593 RTW89_FLAG_CHANGING_INTERFACE,
4594
4595 NUM_OF_RTW89_FLAGS,
4596 };
4597
4598 enum rtw89_quirks {
4599 RTW89_QUIRK_PCI_BER,
4600
4601 NUM_OF_RTW89_QUIRKS,
4602 };
4603
4604 enum rtw89_pkt_drop_sel {
4605 RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
4606 RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
4607 RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
4608 RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
4609 RTW89_PKT_DROP_SEL_MACID_ALL,
4610 RTW89_PKT_DROP_SEL_MG0_ONCE,
4611 RTW89_PKT_DROP_SEL_HIQ_ONCE,
4612 RTW89_PKT_DROP_SEL_HIQ_PORT,
4613 RTW89_PKT_DROP_SEL_HIQ_MBSSID,
4614 RTW89_PKT_DROP_SEL_BAND,
4615 RTW89_PKT_DROP_SEL_BAND_ONCE,
4616 RTW89_PKT_DROP_SEL_REL_MACID,
4617 RTW89_PKT_DROP_SEL_REL_HIQ_PORT,
4618 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID,
4619 };
4620
4621 struct rtw89_pkt_drop_params {
4622 enum rtw89_pkt_drop_sel sel;
4623 enum rtw89_mac_idx mac_band;
4624 u8 macid;
4625 u8 port;
4626 u8 mbssid;
4627 bool tf_trs;
4628 u32 macid_band_sel[4];
4629 };
4630
4631 struct rtw89_pkt_stat {
4632 u16 beacon_nr;
4633 u32 rx_rate_cnt[RTW89_HW_RATE_NR];
4634 };
4635
4636 DECLARE_EWMA(thermal, 4, 4);
4637
4638 struct rtw89_phy_stat {
4639 struct ewma_thermal avg_thermal[RF_PATH_MAX];
4640 struct rtw89_pkt_stat cur_pkt_stat;
4641 struct rtw89_pkt_stat last_pkt_stat;
4642 };
4643
4644 enum rtw89_rfk_report_state {
4645 RTW89_RFK_STATE_START = 0x0,
4646 RTW89_RFK_STATE_OK = 0x1,
4647 RTW89_RFK_STATE_FAIL = 0x2,
4648 RTW89_RFK_STATE_TIMEOUT = 0x3,
4649 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4,
4650 };
4651
4652 struct rtw89_rfk_wait_info {
4653 struct completion completion;
4654 ktime_t start_time;
4655 enum rtw89_rfk_report_state state;
4656 u8 version;
4657 };
4658
4659 #define RTW89_DACK_PATH_NR 2
4660 #define RTW89_DACK_IDX_NR 2
4661 #define RTW89_DACK_MSBK_NR 16
4662 struct rtw89_dack_info {
4663 bool dack_done;
4664 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
4665 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4666 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4667 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4668 u32 dack_cnt;
4669 bool addck_timeout[RTW89_DACK_PATH_NR];
4670 bool dadck_timeout[RTW89_DACK_PATH_NR];
4671 bool msbk_timeout[RTW89_DACK_PATH_NR];
4672 };
4673
4674 #define RTW89_RFK_CHS_NR 3
4675
4676 struct rtw89_rfk_mcc_info {
4677 u8 ch[RTW89_RFK_CHS_NR];
4678 u8 band[RTW89_RFK_CHS_NR];
4679 u8 bw[RTW89_RFK_CHS_NR];
4680 u8 table_idx;
4681 };
4682
4683 #define RTW89_IQK_CHS_NR 2
4684 #define RTW89_IQK_PATH_NR 4
4685
4686 struct rtw89_lck_info {
4687 u8 thermal[RF_PATH_MAX];
4688 };
4689
4690 struct rtw89_rx_dck_info {
4691 u8 thermal[RF_PATH_MAX];
4692 };
4693
4694 struct rtw89_iqk_info {
4695 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4696 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4697 bool lok_fail[RTW89_IQK_PATH_NR];
4698 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4699 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4700 u32 iqk_fail_cnt;
4701 bool is_iqk_init;
4702 u32 iqk_channel[RTW89_IQK_CHS_NR];
4703 u8 iqk_band[RTW89_IQK_PATH_NR];
4704 u8 iqk_ch[RTW89_IQK_PATH_NR];
4705 u8 iqk_bw[RTW89_IQK_PATH_NR];
4706 u8 iqk_times;
4707 u8 version;
4708 u32 nb_txcfir[RTW89_IQK_PATH_NR];
4709 u32 nb_rxcfir[RTW89_IQK_PATH_NR];
4710 u32 bp_txkresult[RTW89_IQK_PATH_NR];
4711 u32 bp_rxkresult[RTW89_IQK_PATH_NR];
4712 u32 bp_iqkenable[RTW89_IQK_PATH_NR];
4713 bool is_wb_txiqk[RTW89_IQK_PATH_NR];
4714 bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
4715 bool is_nbiqk;
4716 bool iqk_fft_en;
4717 bool iqk_xym_en;
4718 bool iqk_sram_en;
4719 bool iqk_cfir_en;
4720 u32 syn1to2;
4721 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4722 u8 iqk_table_idx[RTW89_IQK_PATH_NR];
4723 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4724 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4725 };
4726
4727 #define RTW89_DPK_RF_PATH 2
4728 #define RTW89_DPK_AVG_THERMAL_NUM 8
4729 #define RTW89_DPK_BKUP_NUM 2
4730 struct rtw89_dpk_bkup_para {
4731 enum rtw89_band band;
4732 enum rtw89_bandwidth bw;
4733 u8 ch;
4734 bool path_ok;
4735 u8 mdpd_en;
4736 u8 txagc_dpk;
4737 u8 ther_dpk;
4738 u8 gs;
4739 u16 pwsf;
4740 };
4741
4742 struct rtw89_dpk_info {
4743 bool is_dpk_enable;
4744 bool is_dpk_reload_en;
4745 u8 dpk_gs[RTW89_PHY_MAX];
4746 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4747 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4748 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4749 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4750 u8 cur_idx[RTW89_DPK_RF_PATH];
4751 u8 cur_k_set;
4752 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4753 };
4754
4755 struct rtw89_fem_info {
4756 bool elna_2g;
4757 bool elna_5g;
4758 bool epa_2g;
4759 bool epa_5g;
4760 bool epa_6g;
4761 };
4762
4763 struct rtw89_phy_ch_info {
4764 u8 rssi_min;
4765 u16 rssi_min_macid;
4766 u8 pre_rssi_min;
4767 u8 rssi_max;
4768 u16 rssi_max_macid;
4769 u8 rxsc_160;
4770 u8 rxsc_80;
4771 u8 rxsc_40;
4772 u8 rxsc_20;
4773 u8 rxsc_l;
4774 u8 is_noisy;
4775 };
4776
4777 struct rtw89_agc_gaincode_set {
4778 u8 lna_idx;
4779 u8 tia_idx;
4780 u8 rxb_idx;
4781 };
4782
4783 #define IGI_RSSI_TH_NUM 5
4784 #define FA_TH_NUM 4
4785 #define LNA_GAIN_NUM 7
4786 #define TIA_GAIN_NUM 2
4787 struct rtw89_dig_info {
4788 struct rtw89_agc_gaincode_set cur_gaincode;
4789 bool force_gaincode_idx_en;
4790 struct rtw89_agc_gaincode_set force_gaincode;
4791 u8 igi_rssi_th[IGI_RSSI_TH_NUM];
4792 u16 fa_th[FA_TH_NUM];
4793 u8 igi_rssi;
4794 u8 igi_fa_rssi;
4795 u8 fa_rssi_ofst;
4796 u8 dyn_igi_max;
4797 u8 dyn_igi_min;
4798 bool dyn_pd_th_en;
4799 u8 dyn_pd_th_max;
4800 u8 pd_low_th_ofst;
4801 u8 ib_pbk;
4802 s8 ib_pkpwr;
4803 s8 lna_gain_a[LNA_GAIN_NUM];
4804 s8 lna_gain_g[LNA_GAIN_NUM];
4805 s8 *lna_gain;
4806 s8 tia_gain_a[TIA_GAIN_NUM];
4807 s8 tia_gain_g[TIA_GAIN_NUM];
4808 s8 *tia_gain;
4809 bool is_linked_pre;
4810 bool bypass_dig;
4811 };
4812
4813 enum rtw89_multi_cfo_mode {
4814 RTW89_PKT_BASED_AVG_MODE = 0,
4815 RTW89_ENTRY_BASED_AVG_MODE = 1,
4816 RTW89_TP_BASED_AVG_MODE = 2,
4817 };
4818
4819 enum rtw89_phy_cfo_status {
4820 RTW89_PHY_DCFO_STATE_NORMAL = 0,
4821 RTW89_PHY_DCFO_STATE_ENHANCE = 1,
4822 RTW89_PHY_DCFO_STATE_HOLD = 2,
4823 RTW89_PHY_DCFO_STATE_MAX
4824 };
4825
4826 enum rtw89_phy_cfo_ul_ofdma_acc_mode {
4827 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
4828 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1
4829 };
4830
4831 struct rtw89_cfo_tracking_info {
4832 u16 cfo_timer_ms;
4833 bool cfo_trig_by_timer_en;
4834 enum rtw89_phy_cfo_status phy_cfo_status;
4835 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode;
4836 u8 phy_cfo_trk_cnt;
4837 bool is_adjust;
4838 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
4839 bool apply_compensation;
4840 u8 crystal_cap;
4841 u8 crystal_cap_default;
4842 u8 def_x_cap;
4843 s8 x_cap_ofst;
4844 u32 sta_cfo_tolerance;
4845 s32 cfo_tail[CFO_TRACK_MAX_USER];
4846 u16 cfo_cnt[CFO_TRACK_MAX_USER];
4847 s32 cfo_avg_pre;
4848 s32 cfo_avg[CFO_TRACK_MAX_USER];
4849 s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
4850 s32 dcfo_avg;
4851 s32 dcfo_avg_pre;
4852 u32 packet_count;
4853 u32 packet_count_pre;
4854 s32 residual_cfo_acc;
4855 u8 phy_cfotrk_state;
4856 u8 phy_cfotrk_cnt;
4857 bool divergence_lock_en;
4858 u8 x_cap_lb;
4859 u8 x_cap_ub;
4860 u8 lock_cnt;
4861 };
4862
4863 enum rtw89_tssi_mode {
4864 RTW89_TSSI_NORMAL = 0,
4865 RTW89_TSSI_SCAN = 1,
4866 };
4867
4868 enum rtw89_tssi_alimk_band {
4869 TSSI_ALIMK_2G = 0,
4870 TSSI_ALIMK_5GL,
4871 TSSI_ALIMK_5GM,
4872 TSSI_ALIMK_5GH,
4873 TSSI_ALIMK_MAX
4874 };
4875
4876 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
4877 #define TSSI_TRIM_CH_GROUP_NUM 8
4878 #define TSSI_TRIM_CH_GROUP_NUM_6G 16
4879
4880 #define TSSI_CCK_CH_GROUP_NUM 6
4881 #define TSSI_MCS_2G_CH_GROUP_NUM 5
4882 #define TSSI_MCS_5G_CH_GROUP_NUM 14
4883 #define TSSI_MCS_6G_CH_GROUP_NUM 32
4884 #define TSSI_MCS_CH_GROUP_NUM \
4885 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
4886 #define TSSI_MAX_CH_NUM 67
4887 #define TSSI_ALIMK_VALUE_NUM 8
4888
4889 struct rtw89_tssi_info {
4890 u8 thermal[RF_PATH_MAX];
4891 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
4892 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
4893 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
4894 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
4895 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
4896 s8 extra_ofst[RF_PATH_MAX];
4897 bool tssi_tracking_check[RF_PATH_MAX];
4898 u8 default_txagc_offset[RF_PATH_MAX];
4899 u32 base_thermal[RF_PATH_MAX];
4900 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
4901 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
4902 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
4903 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
4904 u32 tssi_alimk_time;
4905 };
4906
4907 struct rtw89_power_trim_info {
4908 bool pg_thermal_trim;
4909 bool pg_pa_bias_trim;
4910 u8 thermal_trim[RF_PATH_MAX];
4911 u8 pa_bias_trim[RF_PATH_MAX];
4912 u8 pad_bias_trim[RF_PATH_MAX];
4913 };
4914
4915 struct rtw89_regd {
4916 char alpha2[3];
4917 u8 txpwr_regd[RTW89_BAND_NUM];
4918 };
4919
4920 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX
4921 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3
4922 #define RTW89_5GHZ_UNII4_START_INDEX 25
4923
4924 struct rtw89_regulatory_info {
4925 const struct rtw89_regd *regd;
4926 enum rtw89_reg_6ghz_power reg_6ghz_power;
4927 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM);
4928 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM);
4929 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM);
4930 };
4931
4932 enum rtw89_ifs_clm_application {
4933 RTW89_IFS_CLM_INIT = 0,
4934 RTW89_IFS_CLM_BACKGROUND = 1,
4935 RTW89_IFS_CLM_ACS = 2,
4936 RTW89_IFS_CLM_DIG = 3,
4937 RTW89_IFS_CLM_TDMA_DIG = 4,
4938 RTW89_IFS_CLM_DBG = 5,
4939 RTW89_IFS_CLM_DBG_MANUAL = 6
4940 };
4941
4942 enum rtw89_env_racing_lv {
4943 RTW89_RAC_RELEASE = 0,
4944 RTW89_RAC_LV_1 = 1,
4945 RTW89_RAC_LV_2 = 2,
4946 RTW89_RAC_LV_3 = 3,
4947 RTW89_RAC_LV_4 = 4,
4948 RTW89_RAC_MAX_NUM = 5
4949 };
4950
4951 struct rtw89_ccx_para_info {
4952 enum rtw89_env_racing_lv rac_lv;
4953 u16 mntr_time;
4954 u8 nhm_manual_th_ofst;
4955 u8 nhm_manual_th0;
4956 enum rtw89_ifs_clm_application ifs_clm_app;
4957 u32 ifs_clm_manual_th_times;
4958 u32 ifs_clm_manual_th0;
4959 u8 fahm_manual_th_ofst;
4960 u8 fahm_manual_th0;
4961 u8 fahm_numer_opt;
4962 u8 fahm_denom_opt;
4963 };
4964
4965 enum rtw89_ccx_edcca_opt_sc_idx {
4966 RTW89_CCX_EDCCA_SEG0_P0 = 0,
4967 RTW89_CCX_EDCCA_SEG0_S1 = 1,
4968 RTW89_CCX_EDCCA_SEG0_S2 = 2,
4969 RTW89_CCX_EDCCA_SEG0_S3 = 3,
4970 RTW89_CCX_EDCCA_SEG1_P0 = 4,
4971 RTW89_CCX_EDCCA_SEG1_S1 = 5,
4972 RTW89_CCX_EDCCA_SEG1_S2 = 6,
4973 RTW89_CCX_EDCCA_SEG1_S3 = 7
4974 };
4975
4976 enum rtw89_ccx_edcca_opt_bw_idx {
4977 RTW89_CCX_EDCCA_BW20_0 = 0,
4978 RTW89_CCX_EDCCA_BW20_1 = 1,
4979 RTW89_CCX_EDCCA_BW20_2 = 2,
4980 RTW89_CCX_EDCCA_BW20_3 = 3,
4981 RTW89_CCX_EDCCA_BW20_4 = 4,
4982 RTW89_CCX_EDCCA_BW20_5 = 5,
4983 RTW89_CCX_EDCCA_BW20_6 = 6,
4984 RTW89_CCX_EDCCA_BW20_7 = 7
4985 };
4986
4987 #define RTW89_NHM_TH_NUM 11
4988 #define RTW89_FAHM_TH_NUM 11
4989 #define RTW89_NHM_RPT_NUM 12
4990 #define RTW89_FAHM_RPT_NUM 12
4991 #define RTW89_IFS_CLM_NUM 4
4992 struct rtw89_env_monitor_info {
4993 u8 ccx_watchdog_result;
4994 bool ccx_ongoing;
4995 u8 ccx_rac_lv;
4996 bool ccx_manual_ctrl;
4997 u16 ifs_clm_mntr_time;
4998 enum rtw89_ifs_clm_application ifs_clm_app;
4999 u16 ccx_period;
5000 u8 ccx_unit_idx;
5001 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
5002 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
5003 u16 ifs_clm_tx;
5004 u16 ifs_clm_edcca_excl_cca;
5005 u16 ifs_clm_ofdmfa;
5006 u16 ifs_clm_ofdmcca_excl_fa;
5007 u16 ifs_clm_cckfa;
5008 u16 ifs_clm_cckcca_excl_fa;
5009 u16 ifs_clm_total_ifs;
5010 u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
5011 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
5012 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
5013 u8 ifs_clm_tx_ratio;
5014 u8 ifs_clm_edcca_excl_cca_ratio;
5015 u8 ifs_clm_cck_fa_ratio;
5016 u8 ifs_clm_ofdm_fa_ratio;
5017 u8 ifs_clm_cck_cca_excl_fa_ratio;
5018 u8 ifs_clm_ofdm_cca_excl_fa_ratio;
5019 u16 ifs_clm_cck_fa_permil;
5020 u16 ifs_clm_ofdm_fa_permil;
5021 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
5022 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
5023 };
5024
5025 enum rtw89_ser_rcvy_step {
5026 RTW89_SER_DRV_STOP_TX,
5027 RTW89_SER_DRV_STOP_RX,
5028 RTW89_SER_DRV_STOP_RUN,
5029 RTW89_SER_HAL_STOP_DMA,
5030 RTW89_SER_SUPPRESS_LOG,
5031 RTW89_NUM_OF_SER_FLAGS
5032 };
5033
5034 struct rtw89_ser {
5035 u8 state;
5036 u8 alarm_event;
5037 bool prehandle_l1;
5038
5039 struct work_struct ser_hdl_work;
5040 struct delayed_work ser_alarm_work;
5041 const struct state_ent *st_tbl;
5042 const struct event_ent *ev_tbl;
5043 struct list_head msg_q;
5044 spinlock_t msg_q_lock; /* lock when read/write ser msg */
5045 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
5046 };
5047
5048 enum rtw89_mac_ax_ps_mode {
5049 RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
5050 RTW89_MAC_AX_PS_MODE_LEGACY = 1,
5051 RTW89_MAC_AX_PS_MODE_WMMPS = 2,
5052 RTW89_MAC_AX_PS_MODE_MAX = 3,
5053 };
5054
5055 enum rtw89_last_rpwm_mode {
5056 RTW89_LAST_RPWM_PS = 0x0,
5057 RTW89_LAST_RPWM_ACTIVE = 0x6,
5058 };
5059
5060 struct rtw89_lps_parm {
5061 u8 macid;
5062 u8 psmode; /* enum rtw89_mac_ax_ps_mode */
5063 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
5064 };
5065
5066 struct rtw89_ppdu_sts_info {
5067 struct sk_buff_head rx_queue[RTW89_PHY_MAX];
5068 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX];
5069 };
5070
5071 struct rtw89_early_h2c {
5072 struct list_head list;
5073 u8 *h2c;
5074 u16 h2c_len;
5075 };
5076
5077 struct rtw89_hw_scan_info {
5078 struct ieee80211_vif *scanning_vif;
5079 struct list_head pkt_list[NUM_NL80211_BANDS];
5080 struct rtw89_chan op_chan;
5081 bool abort;
5082 u32 last_chan_idx;
5083 };
5084
5085 enum rtw89_phy_bb_gain_band {
5086 RTW89_BB_GAIN_BAND_2G = 0,
5087 RTW89_BB_GAIN_BAND_5G_L = 1,
5088 RTW89_BB_GAIN_BAND_5G_M = 2,
5089 RTW89_BB_GAIN_BAND_5G_H = 3,
5090 RTW89_BB_GAIN_BAND_6G_L = 4,
5091 RTW89_BB_GAIN_BAND_6G_M = 5,
5092 RTW89_BB_GAIN_BAND_6G_H = 6,
5093 RTW89_BB_GAIN_BAND_6G_UH = 7,
5094
5095 RTW89_BB_GAIN_BAND_NR,
5096 };
5097
5098 enum rtw89_phy_gain_band_be {
5099 RTW89_BB_GAIN_BAND_2G_BE = 0,
5100 RTW89_BB_GAIN_BAND_5G_L_BE = 1,
5101 RTW89_BB_GAIN_BAND_5G_M_BE = 2,
5102 RTW89_BB_GAIN_BAND_5G_H_BE = 3,
5103 RTW89_BB_GAIN_BAND_6G_L0_BE = 4,
5104 RTW89_BB_GAIN_BAND_6G_L1_BE = 5,
5105 RTW89_BB_GAIN_BAND_6G_M0_BE = 6,
5106 RTW89_BB_GAIN_BAND_6G_M1_BE = 7,
5107 RTW89_BB_GAIN_BAND_6G_H0_BE = 8,
5108 RTW89_BB_GAIN_BAND_6G_H1_BE = 9,
5109 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10,
5110 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11,
5111
5112 RTW89_BB_GAIN_BAND_NR_BE,
5113 };
5114
5115 enum rtw89_phy_bb_bw_be {
5116 RTW89_BB_BW_20_40 = 0,
5117 RTW89_BB_BW_80_160_320 = 1,
5118
5119 RTW89_BB_BW_NR_BE,
5120 };
5121
5122 enum rtw89_bw20_sc {
5123 RTW89_BW20_SC_20M = 1,
5124 RTW89_BW20_SC_40M = 2,
5125 RTW89_BW20_SC_80M = 4,
5126 RTW89_BW20_SC_160M = 8,
5127 RTW89_BW20_SC_320M = 16,
5128 };
5129
5130 enum rtw89_cmac_table_bw {
5131 RTW89_CMAC_BW_20M = 0,
5132 RTW89_CMAC_BW_40M = 1,
5133 RTW89_CMAC_BW_80M = 2,
5134 RTW89_CMAC_BW_160M = 3,
5135 RTW89_CMAC_BW_320M = 4,
5136
5137 RTW89_CMAC_BW_NR,
5138 };
5139
5140 enum rtw89_phy_bb_rxsc_num {
5141 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
5142 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
5143 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
5144 };
5145
5146 struct rtw89_phy_bb_gain_info {
5147 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5148 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
5149 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5150 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5151 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5152 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
5153 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
5154 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5155 [RTW89_BB_RXSC_NUM_40];
5156 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5157 [RTW89_BB_RXSC_NUM_80];
5158 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5159 [RTW89_BB_RXSC_NUM_160];
5160 };
5161
5162 struct rtw89_phy_bb_gain_info_be {
5163 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5164 [LNA_GAIN_NUM];
5165 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5166 [TIA_GAIN_NUM];
5167 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5168 [RF_PATH_MAX][LNA_GAIN_NUM];
5169 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5170 [RF_PATH_MAX][LNA_GAIN_NUM];
5171 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5172 [RF_PATH_MAX][LNA_GAIN_NUM + 1];
5173 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5174 [RTW89_BW20_SC_20M];
5175 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5176 [RTW89_BW20_SC_40M];
5177 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5178 [RTW89_BW20_SC_80M];
5179 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5180 [RTW89_BW20_SC_160M];
5181 };
5182
5183 struct rtw89_phy_efuse_gain {
5184 bool offset_valid;
5185 bool comp_valid;
5186 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
5187 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
5188 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */
5189 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
5190 };
5191
5192 #define RTW89_MAX_PATTERN_NUM 18
5193 #define RTW89_MAX_PATTERN_MASK_SIZE 4
5194 #define RTW89_MAX_PATTERN_SIZE 128
5195
5196 struct rtw89_wow_cam_info {
5197 bool r_w;
5198 u8 idx;
5199 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
5200 u16 crc;
5201 bool negative_pattern_match;
5202 bool skip_mac_hdr;
5203 bool uc;
5204 bool mc;
5205 bool bc;
5206 bool valid;
5207 };
5208
5209 struct rtw89_wow_key_info {
5210 u8 ptk_tx_iv[8];
5211 u8 valid_check;
5212 u8 symbol_check_en;
5213 u8 gtk_keyidx;
5214 u8 rsvd[5];
5215 u8 ptk_rx_iv[8];
5216 u8 gtk_rx_iv[4][8];
5217 } __packed;
5218
5219 struct rtw89_wow_gtk_info {
5220 u8 kck[32];
5221 u8 kek[32];
5222 u8 tk1[16];
5223 u8 txmickey[8];
5224 u8 rxmickey[8];
5225 __le32 igtk_keyid;
5226 __le64 ipn;
5227 u8 igtk[2][32];
5228 u8 psk[32];
5229 } __packed;
5230
5231 struct rtw89_wow_aoac_report {
5232 u8 rpt_ver;
5233 u8 sec_type;
5234 u8 key_idx;
5235 u8 pattern_idx;
5236 u8 rekey_ok;
5237 u8 ptk_tx_iv[8];
5238 u8 eapol_key_replay_count[8];
5239 u8 gtk[32];
5240 u8 ptk_rx_iv[8];
5241 u8 gtk_rx_iv[4][8];
5242 u64 igtk_key_id;
5243 u64 igtk_ipn;
5244 u8 igtk[32];
5245 u8 csa_pri_ch;
5246 u8 csa_bw;
5247 u8 csa_ch_offset;
5248 u8 csa_chsw_failed;
5249 u8 csa_ch_band;
5250 };
5251
5252 struct rtw89_wow_param {
5253 struct ieee80211_vif *wow_vif;
5254 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
5255 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
5256 struct rtw89_wow_key_info key_info;
5257 struct rtw89_wow_gtk_info gtk_info;
5258 struct rtw89_wow_aoac_report aoac_rpt;
5259 u8 pattern_cnt;
5260 u8 ptk_alg;
5261 u8 gtk_alg;
5262 u8 ptk_keyidx;
5263 u8 akm;
5264 };
5265
5266 struct rtw89_mcc_limit {
5267 bool enable;
5268 u16 max_tob; /* TU; max time offset behind */
5269 u16 max_toa; /* TU; max time offset ahead */
5270 u16 max_dur; /* TU */
5271 };
5272
5273 struct rtw89_mcc_policy {
5274 u8 c2h_rpt;
5275 u8 tx_null_early;
5276 u8 dis_tx_null;
5277 u8 in_curr_ch;
5278 u8 dis_sw_retry;
5279 u8 sw_retry_count;
5280 };
5281
5282 struct rtw89_mcc_role {
5283 struct rtw89_vif *rtwvif;
5284 struct rtw89_mcc_policy policy;
5285 struct rtw89_mcc_limit limit;
5286
5287 /* only valid when running with FW MRC mechanism */
5288 u8 slot_idx;
5289
5290 /* byte-array in LE order for FW */
5291 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)];
5292
5293 u16 duration; /* TU */
5294 u16 beacon_interval; /* TU */
5295 bool is_2ghz;
5296 bool is_go;
5297 bool is_gc;
5298 };
5299
5300 struct rtw89_mcc_bt_role {
5301 u16 duration; /* TU */
5302 };
5303
5304 struct rtw89_mcc_courtesy {
5305 bool enable;
5306 u8 slot_num;
5307 u8 macid_src;
5308 u8 macid_tgt;
5309 };
5310
5311 enum rtw89_mcc_plan {
5312 RTW89_MCC_PLAN_TAIL_BT,
5313 RTW89_MCC_PLAN_MID_BT,
5314 RTW89_MCC_PLAN_NO_BT,
5315
5316 NUM_OF_RTW89_MCC_PLAN,
5317 };
5318
5319 struct rtw89_mcc_pattern {
5320 s16 tob_ref; /* TU; time offset behind of reference role */
5321 s16 toa_ref; /* TU; time offset ahead of reference role */
5322 s16 tob_aux; /* TU; time offset behind of auxiliary role */
5323 s16 toa_aux; /* TU; time offset ahead of auxiliary role */
5324
5325 enum rtw89_mcc_plan plan;
5326 struct rtw89_mcc_courtesy courtesy;
5327 };
5328
5329 struct rtw89_mcc_sync {
5330 bool enable;
5331 u16 offset; /* TU */
5332 u8 macid_src;
5333 u8 band_src;
5334 u8 port_src;
5335 u8 macid_tgt;
5336 u8 band_tgt;
5337 u8 port_tgt;
5338 };
5339
5340 struct rtw89_mcc_config {
5341 struct rtw89_mcc_pattern pattern;
5342 struct rtw89_mcc_sync sync;
5343 u64 start_tsf;
5344 u16 mcc_interval; /* TU */
5345 u16 beacon_offset; /* TU */
5346 };
5347
5348 enum rtw89_mcc_mode {
5349 RTW89_MCC_MODE_GO_STA,
5350 RTW89_MCC_MODE_GC_STA,
5351 };
5352
5353 struct rtw89_mcc_info {
5354 struct rtw89_wait_info wait;
5355
5356 u8 group;
5357 enum rtw89_mcc_mode mode;
5358 struct rtw89_mcc_role role_ref; /* reference role */
5359 struct rtw89_mcc_role role_aux; /* auxiliary role */
5360 struct rtw89_mcc_bt_role bt_role;
5361 struct rtw89_mcc_config config;
5362 };
5363
5364 struct rtw89_dev {
5365 struct ieee80211_hw *hw;
5366 struct device *dev;
5367 const struct ieee80211_ops *ops;
5368
5369 bool dbcc_en;
5370 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode;
5371 struct rtw89_hw_scan_info scan_info;
5372 const struct rtw89_chip_info *chip;
5373 const struct rtw89_pci_info *pci_info;
5374 const struct rtw89_rfe_parms *rfe_parms;
5375 struct rtw89_hal hal;
5376 struct rtw89_mcc_info mcc;
5377 struct rtw89_mac_info mac;
5378 struct rtw89_fw_info fw;
5379 struct rtw89_hci_info hci;
5380 struct rtw89_efuse efuse;
5381 struct rtw89_traffic_stats stats;
5382 struct rtw89_rfe_data *rfe_data;
5383
5384 /* ensures exclusive access from mac80211 callbacks */
5385 struct mutex mutex;
5386 struct list_head rtwvifs_list;
5387 /* used to protect rf read write */
5388 struct mutex rf_mutex;
5389 struct workqueue_struct *txq_wq;
5390 struct work_struct txq_work;
5391 struct delayed_work txq_reinvoke_work;
5392 /* used to protect ba_list and forbid_ba_list */
5393 spinlock_t ba_lock;
5394 /* txqs to setup ba session */
5395 struct list_head ba_list;
5396 /* txqs to forbid ba session */
5397 struct list_head forbid_ba_list;
5398 struct work_struct ba_work;
5399 /* used to protect rpwm */
5400 spinlock_t rpwm_lock;
5401
5402 struct rtw89_cam_info cam_info;
5403
5404 struct sk_buff_head c2h_queue;
5405 struct work_struct c2h_work;
5406 struct work_struct ips_work;
5407 struct work_struct load_firmware_work;
5408 struct work_struct cancel_6ghz_probe_work;
5409
5410 struct list_head early_h2c_list;
5411
5412 struct rtw89_ser ser;
5413
5414 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
5415 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
5416 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
5417 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
5418 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS);
5419
5420 struct rtw89_phy_stat phystat;
5421 struct rtw89_rfk_wait_info rfk_wait;
5422 struct rtw89_dack_info dack;
5423 struct rtw89_iqk_info iqk;
5424 struct rtw89_dpk_info dpk;
5425 struct rtw89_rfk_mcc_info rfk_mcc;
5426 struct rtw89_lck_info lck;
5427 struct rtw89_rx_dck_info rx_dck;
5428 bool is_tssi_mode[RF_PATH_MAX];
5429 bool is_bt_iqk_timeout;
5430
5431 struct rtw89_fem_info fem;
5432 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM];
5433 struct rtw89_tssi_info tssi;
5434 struct rtw89_power_trim_info pwr_trim;
5435
5436 struct rtw89_cfo_tracking_info cfo_tracking;
5437 struct rtw89_env_monitor_info env_monitor;
5438 struct rtw89_dig_info dig;
5439 struct rtw89_phy_ch_info ch_info;
5440 union {
5441 struct rtw89_phy_bb_gain_info ax;
5442 struct rtw89_phy_bb_gain_info_be be;
5443 } bb_gain;
5444 struct rtw89_phy_efuse_gain efuse_gain;
5445 struct rtw89_phy_ul_tb_info ul_tb_info;
5446 struct rtw89_antdiv_info antdiv;
5447
5448 struct delayed_work track_work;
5449 struct delayed_work chanctx_work;
5450 struct delayed_work coex_act1_work;
5451 struct delayed_work coex_bt_devinfo_work;
5452 struct delayed_work coex_rfk_chk_work;
5453 struct delayed_work cfo_track_work;
5454 struct delayed_work forbid_ba_work;
5455 struct delayed_work roc_work;
5456 struct delayed_work antdiv_work;
5457 struct rtw89_ppdu_sts_info ppdu_sts;
5458 u8 total_sta_assoc;
5459 bool scanning;
5460
5461 struct rtw89_regulatory_info regulatory;
5462 struct rtw89_sar_info sar;
5463 struct rtw89_tas_info tas;
5464
5465 struct rtw89_btc btc;
5466 enum rtw89_ps_mode ps_mode;
5467 bool lps_enabled;
5468
5469 struct rtw89_wow_param wow;
5470
5471 /* napi structure */
5472 struct net_device netdev;
5473 struct napi_struct napi;
5474 int napi_budget_countdown;
5475
5476 /* HCI related data, keep last */
5477 u8 priv[] __aligned(sizeof(void *));
5478 };
5479
rtw89_hci_tx_write(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)5480 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
5481 struct rtw89_core_tx_request *tx_req)
5482 {
5483 return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
5484 }
5485
rtw89_hci_reset(struct rtw89_dev * rtwdev)5486 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
5487 {
5488 rtwdev->hci.ops->reset(rtwdev);
5489 }
5490
rtw89_hci_start(struct rtw89_dev * rtwdev)5491 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
5492 {
5493 return rtwdev->hci.ops->start(rtwdev);
5494 }
5495
rtw89_hci_stop(struct rtw89_dev * rtwdev)5496 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
5497 {
5498 rtwdev->hci.ops->stop(rtwdev);
5499 }
5500
rtw89_hci_deinit(struct rtw89_dev * rtwdev)5501 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
5502 {
5503 return rtwdev->hci.ops->deinit(rtwdev);
5504 }
5505
rtw89_hci_pause(struct rtw89_dev * rtwdev,bool pause)5506 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
5507 {
5508 rtwdev->hci.ops->pause(rtwdev, pause);
5509 }
5510
rtw89_hci_switch_mode(struct rtw89_dev * rtwdev,bool low_power)5511 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
5512 {
5513 rtwdev->hci.ops->switch_mode(rtwdev, low_power);
5514 }
5515
rtw89_hci_recalc_int_mit(struct rtw89_dev * rtwdev)5516 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
5517 {
5518 rtwdev->hci.ops->recalc_int_mit(rtwdev);
5519 }
5520
rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 txch)5521 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
5522 {
5523 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
5524 }
5525
rtw89_hci_tx_kick_off(struct rtw89_dev * rtwdev,u8 txch)5526 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
5527 {
5528 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
5529 }
5530
rtw89_hci_mac_pre_deinit(struct rtw89_dev * rtwdev)5531 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev)
5532 {
5533 return rtwdev->hci.ops->mac_pre_deinit(rtwdev);
5534 }
5535
rtw89_hci_flush_queues(struct rtw89_dev * rtwdev,u32 queues,bool drop)5536 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
5537 bool drop)
5538 {
5539 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
5540 return;
5541
5542 if (rtwdev->hci.ops->flush_queues)
5543 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
5544 }
5545
rtw89_hci_recovery_start(struct rtw89_dev * rtwdev)5546 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
5547 {
5548 if (rtwdev->hci.ops->recovery_start)
5549 rtwdev->hci.ops->recovery_start(rtwdev);
5550 }
5551
rtw89_hci_recovery_complete(struct rtw89_dev * rtwdev)5552 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
5553 {
5554 if (rtwdev->hci.ops->recovery_complete)
5555 rtwdev->hci.ops->recovery_complete(rtwdev);
5556 }
5557
rtw89_hci_enable_intr(struct rtw89_dev * rtwdev)5558 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
5559 {
5560 if (rtwdev->hci.ops->enable_intr)
5561 rtwdev->hci.ops->enable_intr(rtwdev);
5562 }
5563
rtw89_hci_disable_intr(struct rtw89_dev * rtwdev)5564 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
5565 {
5566 if (rtwdev->hci.ops->disable_intr)
5567 rtwdev->hci.ops->disable_intr(rtwdev);
5568 }
5569
rtw89_hci_ctrl_txdma_ch(struct rtw89_dev * rtwdev,bool enable)5570 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
5571 {
5572 if (rtwdev->hci.ops->ctrl_txdma_ch)
5573 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
5574 }
5575
rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev * rtwdev,bool enable)5576 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
5577 {
5578 if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
5579 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
5580 }
5581
rtw89_hci_ctrl_trxhci(struct rtw89_dev * rtwdev,bool enable)5582 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
5583 {
5584 if (rtwdev->hci.ops->ctrl_trxhci)
5585 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
5586 }
5587
rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev * rtwdev)5588 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev)
5589 {
5590 int ret = 0;
5591
5592 if (rtwdev->hci.ops->poll_txdma_ch_idle)
5593 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev);
5594 return ret;
5595 }
5596
rtw89_hci_clr_idx_all(struct rtw89_dev * rtwdev)5597 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
5598 {
5599 if (rtwdev->hci.ops->clr_idx_all)
5600 rtwdev->hci.ops->clr_idx_all(rtwdev);
5601 }
5602
rtw89_hci_rst_bdram(struct rtw89_dev * rtwdev)5603 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
5604 {
5605 int ret = 0;
5606
5607 if (rtwdev->hci.ops->rst_bdram)
5608 ret = rtwdev->hci.ops->rst_bdram(rtwdev);
5609 return ret;
5610 }
5611
rtw89_hci_clear(struct rtw89_dev * rtwdev,struct pci_dev * pdev)5612 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
5613 {
5614 if (rtwdev->hci.ops->clear)
5615 rtwdev->hci.ops->clear(rtwdev, pdev);
5616 }
5617
5618 static inline
RTW89_TX_SKB_CB(struct sk_buff * skb)5619 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb)
5620 {
5621 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
5622
5623 return (struct rtw89_tx_skb_data *)info->status.status_driver_data;
5624 }
5625
rtw89_read8(struct rtw89_dev * rtwdev,u32 addr)5626 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
5627 {
5628 return rtwdev->hci.ops->read8(rtwdev, addr);
5629 }
5630
rtw89_read16(struct rtw89_dev * rtwdev,u32 addr)5631 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
5632 {
5633 return rtwdev->hci.ops->read16(rtwdev, addr);
5634 }
5635
rtw89_read32(struct rtw89_dev * rtwdev,u32 addr)5636 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
5637 {
5638 return rtwdev->hci.ops->read32(rtwdev, addr);
5639 }
5640
rtw89_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)5641 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
5642 {
5643 rtwdev->hci.ops->write8(rtwdev, addr, data);
5644 }
5645
rtw89_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)5646 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
5647 {
5648 rtwdev->hci.ops->write16(rtwdev, addr, data);
5649 }
5650
rtw89_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)5651 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
5652 {
5653 rtwdev->hci.ops->write32(rtwdev, addr, data);
5654 }
5655
5656 static inline void
rtw89_write8_set(struct rtw89_dev * rtwdev,u32 addr,u8 bit)5657 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
5658 {
5659 u8 val;
5660
5661 val = rtw89_read8(rtwdev, addr);
5662 rtw89_write8(rtwdev, addr, val | bit);
5663 }
5664
5665 static inline void
rtw89_write16_set(struct rtw89_dev * rtwdev,u32 addr,u16 bit)5666 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
5667 {
5668 u16 val;
5669
5670 val = rtw89_read16(rtwdev, addr);
5671 rtw89_write16(rtwdev, addr, val | bit);
5672 }
5673
5674 static inline void
rtw89_write32_set(struct rtw89_dev * rtwdev,u32 addr,u32 bit)5675 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
5676 {
5677 u32 val;
5678
5679 val = rtw89_read32(rtwdev, addr);
5680 rtw89_write32(rtwdev, addr, val | bit);
5681 }
5682
5683 static inline void
rtw89_write8_clr(struct rtw89_dev * rtwdev,u32 addr,u8 bit)5684 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
5685 {
5686 u8 val;
5687
5688 val = rtw89_read8(rtwdev, addr);
5689 rtw89_write8(rtwdev, addr, val & ~bit);
5690 }
5691
5692 static inline void
rtw89_write16_clr(struct rtw89_dev * rtwdev,u32 addr,u16 bit)5693 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
5694 {
5695 u16 val;
5696
5697 val = rtw89_read16(rtwdev, addr);
5698 rtw89_write16(rtwdev, addr, val & ~bit);
5699 }
5700
5701 static inline void
rtw89_write32_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bit)5702 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
5703 {
5704 u32 val;
5705
5706 val = rtw89_read32(rtwdev, addr);
5707 rtw89_write32(rtwdev, addr, val & ~bit);
5708 }
5709
5710 static inline u32
rtw89_read32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)5711 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
5712 {
5713 u32 shift = __ffs(mask);
5714 u32 orig;
5715 u32 ret;
5716
5717 orig = rtw89_read32(rtwdev, addr);
5718 ret = (orig & mask) >> shift;
5719
5720 return ret;
5721 }
5722
5723 static inline u16
rtw89_read16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)5724 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
5725 {
5726 u32 shift = __ffs(mask);
5727 u32 orig;
5728 u32 ret;
5729
5730 orig = rtw89_read16(rtwdev, addr);
5731 ret = (orig & mask) >> shift;
5732
5733 return ret;
5734 }
5735
5736 static inline u8
rtw89_read8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)5737 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
5738 {
5739 u32 shift = __ffs(mask);
5740 u32 orig;
5741 u32 ret;
5742
5743 orig = rtw89_read8(rtwdev, addr);
5744 ret = (orig & mask) >> shift;
5745
5746 return ret;
5747 }
5748
5749 static inline void
rtw89_write32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data)5750 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
5751 {
5752 u32 shift = __ffs(mask);
5753 u32 orig;
5754 u32 set;
5755
5756 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
5757
5758 orig = rtw89_read32(rtwdev, addr);
5759 set = (orig & ~mask) | ((data << shift) & mask);
5760 rtw89_write32(rtwdev, addr, set);
5761 }
5762
5763 static inline void
rtw89_write16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u16 data)5764 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
5765 {
5766 u32 shift;
5767 u16 orig, set;
5768
5769 mask &= 0xffff;
5770 shift = __ffs(mask);
5771
5772 orig = rtw89_read16(rtwdev, addr);
5773 set = (orig & ~mask) | ((data << shift) & mask);
5774 rtw89_write16(rtwdev, addr, set);
5775 }
5776
5777 static inline void
rtw89_write8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u8 data)5778 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
5779 {
5780 u32 shift;
5781 u8 orig, set;
5782
5783 mask &= 0xff;
5784 shift = __ffs(mask);
5785
5786 orig = rtw89_read8(rtwdev, addr);
5787 set = (orig & ~mask) | ((data << shift) & mask);
5788 rtw89_write8(rtwdev, addr, set);
5789 }
5790
5791 static inline u32
rtw89_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)5792 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
5793 u32 addr, u32 mask)
5794 {
5795 u32 val;
5796
5797 mutex_lock(&rtwdev->rf_mutex);
5798 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
5799 mutex_unlock(&rtwdev->rf_mutex);
5800
5801 return val;
5802 }
5803
5804 static inline void
rtw89_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)5805 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
5806 u32 addr, u32 mask, u32 data)
5807 {
5808 mutex_lock(&rtwdev->rf_mutex);
5809 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
5810 mutex_unlock(&rtwdev->rf_mutex);
5811 }
5812
rtw89_txq_to_txq(struct rtw89_txq * rtwtxq)5813 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
5814 {
5815 void *p = rtwtxq;
5816
5817 return container_of(p, struct ieee80211_txq, drv_priv);
5818 }
5819
rtw89_core_txq_init(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq)5820 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
5821 struct ieee80211_txq *txq)
5822 {
5823 struct rtw89_txq *rtwtxq;
5824
5825 if (!txq)
5826 return;
5827
5828 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
5829 INIT_LIST_HEAD(&rtwtxq->list);
5830 }
5831
rtwvif_to_vif(struct rtw89_vif * rtwvif)5832 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
5833 {
5834 void *p = rtwvif;
5835
5836 return container_of(p, struct ieee80211_vif, drv_priv);
5837 }
5838
rtwvif_to_vif_safe(struct rtw89_vif * rtwvif)5839 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif)
5840 {
5841 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL;
5842 }
5843
vif_to_rtwvif_safe(struct ieee80211_vif * vif)5844 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif)
5845 {
5846 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL;
5847 }
5848
rtwsta_to_sta(struct rtw89_sta * rtwsta)5849 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
5850 {
5851 void *p = rtwsta;
5852
5853 return container_of(p, struct ieee80211_sta, drv_priv);
5854 }
5855
rtwsta_to_sta_safe(struct rtw89_sta * rtwsta)5856 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
5857 {
5858 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
5859 }
5860
sta_to_rtwsta_safe(struct ieee80211_sta * sta)5861 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
5862 {
5863 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
5864 }
5865
rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)5866 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
5867 {
5868 if (hw_bw == RTW89_CHANNEL_WIDTH_160)
5869 return RATE_INFO_BW_160;
5870 else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
5871 return RATE_INFO_BW_80;
5872 else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
5873 return RATE_INFO_BW_40;
5874 else
5875 return RATE_INFO_BW_20;
5876 }
5877
5878 static inline
rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)5879 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
5880 {
5881 switch (hw_band) {
5882 default:
5883 case RTW89_BAND_2G:
5884 return NL80211_BAND_2GHZ;
5885 case RTW89_BAND_5G:
5886 return NL80211_BAND_5GHZ;
5887 case RTW89_BAND_6G:
5888 return NL80211_BAND_6GHZ;
5889 }
5890 }
5891
5892 static inline
rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)5893 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)
5894 {
5895 switch (nl_band) {
5896 default:
5897 case NL80211_BAND_2GHZ:
5898 return RTW89_BAND_2G;
5899 case NL80211_BAND_5GHZ:
5900 return RTW89_BAND_5G;
5901 case NL80211_BAND_6GHZ:
5902 return RTW89_BAND_6G;
5903 }
5904 }
5905
5906 static inline
nl_to_rtw89_bandwidth(enum nl80211_chan_width width)5907 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
5908 {
5909 switch (width) {
5910 default:
5911 WARN(1, "Not support bandwidth %d\n", width);
5912 fallthrough;
5913 case NL80211_CHAN_WIDTH_20_NOHT:
5914 case NL80211_CHAN_WIDTH_20:
5915 return RTW89_CHANNEL_WIDTH_20;
5916 case NL80211_CHAN_WIDTH_40:
5917 return RTW89_CHANNEL_WIDTH_40;
5918 case NL80211_CHAN_WIDTH_80:
5919 return RTW89_CHANNEL_WIDTH_80;
5920 case NL80211_CHAN_WIDTH_160:
5921 return RTW89_CHANNEL_WIDTH_160;
5922 }
5923 }
5924
5925 static inline
rtw89_he_rua_to_ru_alloc(u16 rua)5926 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua)
5927 {
5928 switch (rua) {
5929 default:
5930 WARN(1, "Invalid RU allocation: %d\n", rua);
5931 fallthrough;
5932 case 0 ... 36:
5933 return NL80211_RATE_INFO_HE_RU_ALLOC_26;
5934 case 37 ... 52:
5935 return NL80211_RATE_INFO_HE_RU_ALLOC_52;
5936 case 53 ... 60:
5937 return NL80211_RATE_INFO_HE_RU_ALLOC_106;
5938 case 61 ... 64:
5939 return NL80211_RATE_INFO_HE_RU_ALLOC_242;
5940 case 65 ... 66:
5941 return NL80211_RATE_INFO_HE_RU_ALLOC_484;
5942 case 67:
5943 return NL80211_RATE_INFO_HE_RU_ALLOC_996;
5944 case 68:
5945 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
5946 }
5947 }
5948
5949 static inline
rtw89_get_addr_cam_of(struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)5950 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif,
5951 struct rtw89_sta *rtwsta)
5952 {
5953 if (rtwsta) {
5954 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
5955
5956 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
5957 return &rtwsta->addr_cam;
5958 }
5959 return &rtwvif->addr_cam;
5960 }
5961
5962 static inline
rtw89_get_bssid_cam_of(struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)5963 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif,
5964 struct rtw89_sta *rtwsta)
5965 {
5966 if (rtwsta) {
5967 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
5968
5969 if (sta->tdls)
5970 return &rtwsta->bssid_cam;
5971 }
5972 return &rtwvif->bssid_cam;
5973 }
5974
5975 static inline
rtw89_chip_set_channel_prepare(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)5976 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
5977 struct rtw89_channel_help_params *p,
5978 const struct rtw89_chan *chan,
5979 enum rtw89_mac_idx mac_idx,
5980 enum rtw89_phy_idx phy_idx)
5981 {
5982 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan,
5983 mac_idx, phy_idx);
5984 }
5985
5986 static inline
rtw89_chip_set_channel_done(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)5987 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
5988 struct rtw89_channel_help_params *p,
5989 const struct rtw89_chan *chan,
5990 enum rtw89_mac_idx mac_idx,
5991 enum rtw89_phy_idx phy_idx)
5992 {
5993 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan,
5994 mac_idx, phy_idx);
5995 }
5996
5997 static inline
rtw89_chandef_get(struct rtw89_dev * rtwdev,enum rtw89_sub_entity_idx idx)5998 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev,
5999 enum rtw89_sub_entity_idx idx)
6000 {
6001 struct rtw89_hal *hal = &rtwdev->hal;
6002 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx);
6003
6004 if (roc_idx == idx)
6005 return &hal->roc_chandef;
6006
6007 return &hal->sub[idx].chandef;
6008 }
6009
6010 static inline
rtw89_chan_get(struct rtw89_dev * rtwdev,enum rtw89_sub_entity_idx idx)6011 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev,
6012 enum rtw89_sub_entity_idx idx)
6013 {
6014 struct rtw89_hal *hal = &rtwdev->hal;
6015
6016 return &hal->sub[idx].chan;
6017 }
6018
6019 static inline
rtw89_chan_rcd_get(struct rtw89_dev * rtwdev,enum rtw89_sub_entity_idx idx)6020 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev,
6021 enum rtw89_sub_entity_idx idx)
6022 {
6023 struct rtw89_hal *hal = &rtwdev->hal;
6024
6025 return &hal->sub[idx].rcd;
6026 }
6027
6028 static inline
rtw89_scan_chan_get(struct rtw89_dev * rtwdev)6029 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev)
6030 {
6031 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
6032 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif);
6033
6034 if (rtwvif)
6035 return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx);
6036 else
6037 return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
6038 }
6039
rtw89_chip_fem_setup(struct rtw89_dev * rtwdev)6040 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
6041 {
6042 const struct rtw89_chip_info *chip = rtwdev->chip;
6043
6044 if (chip->ops->fem_setup)
6045 chip->ops->fem_setup(rtwdev);
6046 }
6047
rtw89_chip_rfe_gpio(struct rtw89_dev * rtwdev)6048 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
6049 {
6050 const struct rtw89_chip_info *chip = rtwdev->chip;
6051
6052 if (chip->ops->rfe_gpio)
6053 chip->ops->rfe_gpio(rtwdev);
6054 }
6055
rtw89_chip_rfk_hw_init(struct rtw89_dev * rtwdev)6056 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev)
6057 {
6058 const struct rtw89_chip_info *chip = rtwdev->chip;
6059
6060 if (chip->ops->rfk_hw_init)
6061 chip->ops->rfk_hw_init(rtwdev);
6062 }
6063
6064 static inline
rtw89_chip_bb_preinit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6065 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
6066 {
6067 const struct rtw89_chip_info *chip = rtwdev->chip;
6068
6069 if (chip->ops->bb_preinit)
6070 chip->ops->bb_preinit(rtwdev, phy_idx);
6071 }
6072
6073 static inline
rtw89_chip_bb_postinit(struct rtw89_dev * rtwdev)6074 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev)
6075 {
6076 const struct rtw89_chip_info *chip = rtwdev->chip;
6077
6078 if (!chip->ops->bb_postinit)
6079 return;
6080
6081 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0);
6082
6083 if (rtwdev->dbcc_en)
6084 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1);
6085 }
6086
rtw89_chip_bb_sethw(struct rtw89_dev * rtwdev)6087 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
6088 {
6089 const struct rtw89_chip_info *chip = rtwdev->chip;
6090
6091 if (chip->ops->bb_sethw)
6092 chip->ops->bb_sethw(rtwdev);
6093 }
6094
rtw89_chip_rfk_init(struct rtw89_dev * rtwdev)6095 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
6096 {
6097 const struct rtw89_chip_info *chip = rtwdev->chip;
6098
6099 if (chip->ops->rfk_init)
6100 chip->ops->rfk_init(rtwdev);
6101 }
6102
rtw89_chip_rfk_init_late(struct rtw89_dev * rtwdev)6103 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev)
6104 {
6105 const struct rtw89_chip_info *chip = rtwdev->chip;
6106
6107 if (chip->ops->rfk_init_late)
6108 chip->ops->rfk_init_late(rtwdev);
6109 }
6110
rtw89_chip_rfk_channel(struct rtw89_dev * rtwdev)6111 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev)
6112 {
6113 const struct rtw89_chip_info *chip = rtwdev->chip;
6114
6115 if (chip->ops->rfk_channel)
6116 chip->ops->rfk_channel(rtwdev);
6117 }
6118
rtw89_chip_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6119 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
6120 enum rtw89_phy_idx phy_idx)
6121 {
6122 const struct rtw89_chip_info *chip = rtwdev->chip;
6123
6124 if (chip->ops->rfk_band_changed)
6125 chip->ops->rfk_band_changed(rtwdev, phy_idx);
6126 }
6127
rtw89_chip_rfk_scan(struct rtw89_dev * rtwdev,bool start)6128 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start)
6129 {
6130 const struct rtw89_chip_info *chip = rtwdev->chip;
6131
6132 if (chip->ops->rfk_scan)
6133 chip->ops->rfk_scan(rtwdev, start);
6134 }
6135
rtw89_chip_rfk_track(struct rtw89_dev * rtwdev)6136 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
6137 {
6138 const struct rtw89_chip_info *chip = rtwdev->chip;
6139
6140 if (chip->ops->rfk_track)
6141 chip->ops->rfk_track(rtwdev);
6142 }
6143
rtw89_chip_set_txpwr_ctrl(struct rtw89_dev * rtwdev)6144 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
6145 {
6146 const struct rtw89_chip_info *chip = rtwdev->chip;
6147
6148 if (chip->ops->set_txpwr_ctrl)
6149 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0);
6150 }
6151
rtw89_chip_power_trim(struct rtw89_dev * rtwdev)6152 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
6153 {
6154 const struct rtw89_chip_info *chip = rtwdev->chip;
6155
6156 if (chip->ops->power_trim)
6157 chip->ops->power_trim(rtwdev);
6158 }
6159
rtw89_chip_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6160 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
6161 enum rtw89_phy_idx phy_idx)
6162 {
6163 const struct rtw89_chip_info *chip = rtwdev->chip;
6164
6165 if (chip->ops->init_txpwr_unit)
6166 chip->ops->init_txpwr_unit(rtwdev, phy_idx);
6167 }
6168
rtw89_chip_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)6169 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
6170 enum rtw89_rf_path rf_path)
6171 {
6172 const struct rtw89_chip_info *chip = rtwdev->chip;
6173
6174 if (!chip->ops->get_thermal)
6175 return 0x10;
6176
6177 return chip->ops->get_thermal(rtwdev, rf_path);
6178 }
6179
rtw89_chip_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)6180 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
6181 struct rtw89_rx_phy_ppdu *phy_ppdu,
6182 struct ieee80211_rx_status *status)
6183 {
6184 const struct rtw89_chip_info *chip = rtwdev->chip;
6185
6186 if (chip->ops->query_ppdu)
6187 chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
6188 }
6189
rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)6190 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
6191 enum rtw89_phy_idx phy_idx)
6192 {
6193 const struct rtw89_chip_info *chip = rtwdev->chip;
6194
6195 if (chip->ops->ctrl_nbtg_bt_tx)
6196 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx);
6197 }
6198
rtw89_chip_cfg_txrx_path(struct rtw89_dev * rtwdev)6199 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
6200 {
6201 const struct rtw89_chip_info *chip = rtwdev->chip;
6202
6203 if (chip->ops->cfg_txrx_path)
6204 chip->ops->cfg_txrx_path(rtwdev);
6205 }
6206
6207 static inline
rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif)6208 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
6209 struct ieee80211_vif *vif)
6210 {
6211 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
6212 const struct rtw89_chip_info *chip = rtwdev->chip;
6213
6214 if (!vif->bss_conf.he_support || !vif->cfg.assoc)
6215 return;
6216
6217 if (chip->ops->set_txpwr_ul_tb_offset)
6218 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx);
6219 }
6220
rtw89_load_txpwr_table(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)6221 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
6222 const struct rtw89_txpwr_table *tbl)
6223 {
6224 tbl->load(rtwdev, tbl);
6225 }
6226
rtw89_regd_get(struct rtw89_dev * rtwdev,u8 band)6227 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
6228 {
6229 const struct rtw89_regd *regd = rtwdev->regulatory.regd;
6230
6231 return regd->txpwr_regd[band];
6232 }
6233
rtw89_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)6234 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
6235 enum rtw89_phy_idx phy_idx)
6236 {
6237 const struct rtw89_chip_info *chip = rtwdev->chip;
6238
6239 if (chip->ops->ctrl_btg_bt_rx)
6240 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx);
6241 }
6242
6243 static inline
rtw89_chip_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)6244 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev,
6245 struct rtw89_rx_desc_info *desc_info,
6246 u8 *data, u32 data_offset)
6247 {
6248 const struct rtw89_chip_info *chip = rtwdev->chip;
6249
6250 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset);
6251 }
6252
6253 static inline
rtw89_chip_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)6254 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
6255 struct rtw89_tx_desc_info *desc_info,
6256 void *txdesc)
6257 {
6258 const struct rtw89_chip_info *chip = rtwdev->chip;
6259
6260 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
6261 }
6262
6263 static inline
rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)6264 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
6265 struct rtw89_tx_desc_info *desc_info,
6266 void *txdesc)
6267 {
6268 const struct rtw89_chip_info *chip = rtwdev->chip;
6269
6270 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
6271 }
6272
6273 static inline
rtw89_chip_mac_cfg_gnt(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)6274 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
6275 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
6276 {
6277 const struct rtw89_chip_info *chip = rtwdev->chip;
6278
6279 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
6280 }
6281
rtw89_chip_cfg_ctrl_path(struct rtw89_dev * rtwdev,bool wl)6282 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
6283 {
6284 const struct rtw89_chip_info *chip = rtwdev->chip;
6285
6286 chip->ops->cfg_ctrl_path(rtwdev, wl);
6287 }
6288
6289 static inline
rtw89_chip_stop_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)6290 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
6291 u32 *tx_en, enum rtw89_sch_tx_sel sel)
6292 {
6293 const struct rtw89_chip_info *chip = rtwdev->chip;
6294
6295 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
6296 }
6297
6298 static inline
rtw89_chip_resume_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)6299 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
6300 {
6301 const struct rtw89_chip_info *chip = rtwdev->chip;
6302
6303 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
6304 }
6305
6306 static inline
rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)6307 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
6308 struct rtw89_vif *rtwvif,
6309 struct rtw89_sta *rtwsta)
6310 {
6311 const struct rtw89_chip_info *chip = rtwdev->chip;
6312
6313 if (!chip->ops->h2c_dctl_sec_cam)
6314 return 0;
6315 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta);
6316 }
6317
get_hdr_bssid(struct ieee80211_hdr * hdr)6318 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
6319 {
6320 __le16 fc = hdr->frame_control;
6321
6322 if (ieee80211_has_tods(fc))
6323 return hdr->addr1;
6324 else if (ieee80211_has_fromds(fc))
6325 return hdr->addr2;
6326 else
6327 return hdr->addr3;
6328 }
6329
rtw89_sta_has_beamformer_cap(struct ieee80211_sta * sta)6330 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta)
6331 {
6332 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
6333 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
6334 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] &
6335 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
6336 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] &
6337 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
6338 return true;
6339 return false;
6340 }
6341
rtw89_fw_suit_get(struct rtw89_dev * rtwdev,enum rtw89_fw_type type)6342 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
6343 enum rtw89_fw_type type)
6344 {
6345 struct rtw89_fw_info *fw_info = &rtwdev->fw;
6346
6347 switch (type) {
6348 case RTW89_FW_WOWLAN:
6349 return &fw_info->wowlan;
6350 case RTW89_FW_LOGFMT:
6351 return &fw_info->log.suit;
6352 case RTW89_FW_BBMCU0:
6353 return &fw_info->bbmcu0;
6354 case RTW89_FW_BBMCU1:
6355 return &fw_info->bbmcu1;
6356 default:
6357 break;
6358 }
6359
6360 return &fw_info->normal;
6361 }
6362
rtw89_alloc_skb_for_rx(struct rtw89_dev * rtwdev,unsigned int length)6363 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
6364 unsigned int length)
6365 {
6366 struct sk_buff *skb;
6367
6368 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
6369 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
6370 if (!skb)
6371 return NULL;
6372
6373 skb_reserve(skb, RTW89_RADIOTAP_ROOM);
6374 return skb;
6375 }
6376
6377 return dev_alloc_skb(length);
6378 }
6379
rtw89_core_tx_wait_complete(struct rtw89_dev * rtwdev,struct rtw89_tx_skb_data * skb_data,bool tx_done)6380 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev,
6381 struct rtw89_tx_skb_data *skb_data,
6382 bool tx_done)
6383 {
6384 struct rtw89_tx_wait_info *wait;
6385
6386 rcu_read_lock();
6387
6388 wait = rcu_dereference(skb_data->wait);
6389 if (!wait)
6390 goto out;
6391
6392 wait->tx_done = tx_done;
6393 complete(&wait->completion);
6394
6395 out:
6396 rcu_read_unlock();
6397 }
6398
rtw89_is_mlo_1_1(struct rtw89_dev * rtwdev)6399 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev)
6400 {
6401 switch (rtwdev->mlo_dbcc_mode) {
6402 case MLO_1_PLUS_1_1RF:
6403 case MLO_1_PLUS_1_2RF:
6404 case DBCC_LEGACY:
6405 return true;
6406 default:
6407 return false;
6408 }
6409 }
6410
6411 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
6412 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
6413 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
6414 struct sk_buff *skb, bool fwdl);
6415 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
6416 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
6417 int qsel, unsigned int timeout);
6418 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
6419 struct rtw89_tx_desc_info *desc_info,
6420 void *txdesc);
6421 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
6422 struct rtw89_tx_desc_info *desc_info,
6423 void *txdesc);
6424 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
6425 struct rtw89_tx_desc_info *desc_info,
6426 void *txdesc);
6427 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
6428 struct rtw89_tx_desc_info *desc_info,
6429 void *txdesc);
6430 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
6431 struct rtw89_tx_desc_info *desc_info,
6432 void *txdesc);
6433 void rtw89_core_rx(struct rtw89_dev *rtwdev,
6434 struct rtw89_rx_desc_info *desc_info,
6435 struct sk_buff *skb);
6436 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
6437 struct rtw89_rx_desc_info *desc_info,
6438 u8 *data, u32 data_offset);
6439 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
6440 struct rtw89_rx_desc_info *desc_info,
6441 u8 *data, u32 data_offset);
6442 void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
6443 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
6444 void rtw89_core_napi_init(struct rtw89_dev *rtwdev);
6445 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
6446 int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
6447 struct ieee80211_vif *vif,
6448 struct ieee80211_sta *sta);
6449 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
6450 struct ieee80211_vif *vif,
6451 struct ieee80211_sta *sta);
6452 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,
6453 struct ieee80211_vif *vif,
6454 struct ieee80211_sta *sta);
6455 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,
6456 struct ieee80211_vif *vif,
6457 struct ieee80211_sta *sta);
6458 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
6459 struct ieee80211_vif *vif,
6460 struct ieee80211_sta *sta);
6461 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
6462 struct ieee80211_sta *sta,
6463 struct cfg80211_tid_config *tid_config);
6464 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks);
6465 int rtw89_core_init(struct rtw89_dev *rtwdev);
6466 void rtw89_core_deinit(struct rtw89_dev *rtwdev);
6467 int rtw89_core_register(struct rtw89_dev *rtwdev);
6468 void rtw89_core_unregister(struct rtw89_dev *rtwdev);
6469 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
6470 u32 bus_data_size,
6471 const struct rtw89_chip_info *chip);
6472 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev);
6473 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
6474 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
6475 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
6476 struct rtw89_chan *chan);
6477 int rtw89_set_channel(struct rtw89_dev *rtwdev);
6478 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6479 struct rtw89_chan *chan);
6480 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
6481 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
6482 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
6483 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
6484 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
6485 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
6486 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
6487 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc);
6488 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
6489 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate);
6490 int rtw89_regd_setup(struct rtw89_dev *rtwdev);
6491 int rtw89_regd_init(struct rtw89_dev *rtwdev,
6492 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request));
6493 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
6494 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
6495 struct rtw89_traffic_stats *stats);
6496 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond);
6497 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
6498 const struct rtw89_completion_data *data);
6499 int rtw89_core_start(struct rtw89_dev *rtwdev);
6500 void rtw89_core_stop(struct rtw89_dev *rtwdev);
6501 void rtw89_core_update_beacon_work(struct work_struct *work);
6502 void rtw89_roc_work(struct work_struct *work);
6503 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
6504 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
6505 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6506 const u8 *mac_addr, bool hw_scan);
6507 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
6508 struct ieee80211_vif *vif, bool hw_scan);
6509 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev,
6510 struct rtw89_vif *rtwvif, bool active);
6511 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
6512 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event);
6513
6514 #endif
6515