1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #ifndef __RTK_MAIN_H_
6 #define __RTK_MAIN_H_
7
8 #include <net/mac80211.h>
9 #include <linux/vmalloc.h>
10 #include <linux/firmware.h>
11 #include <linux/average.h>
12 #include <linux/bitops.h>
13 #include <linux/bitfield.h>
14 #include <linux/iopoll.h>
15 #include <linux/interrupt.h>
16 #include <linux/workqueue.h>
17
18 #include "util.h"
19
20 #define RTW_MAX_MAC_ID_NUM 32
21 #define RTW_MAX_SEC_CAM_NUM 32
22 #define MAX_PG_CAM_BACKUP_NUM 8
23
24 #define RTW_SCAN_MAX_SSIDS 4
25
26 #define RTW_MAX_PATTERN_NUM 12
27 #define RTW_MAX_PATTERN_MASK_SIZE 16
28 #define RTW_MAX_PATTERN_SIZE 128
29
30 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2)
31
32 #define RFREG_MASK 0xfffff
33 #define INV_RF_DATA 0xffffffff
34 #define TX_PAGE_SIZE_SHIFT 7
35 #define TX_PAGE_SIZE (1 << TX_PAGE_SIZE_SHIFT)
36
37 #define RTW_CHANNEL_WIDTH_MAX 3
38 #define RTW_RF_PATH_MAX 4
39 #define HW_FEATURE_LEN 13
40
41 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */
42
43 extern bool rtw_bf_support;
44 extern bool rtw_disable_lps_deep_mode;
45 extern unsigned int rtw_debug_mask;
46 extern bool rtw_edcca_enabled;
47 extern const struct ieee80211_ops rtw_ops;
48
49 #define RTW_MAX_CHANNEL_NUM_2G 14
50 #define RTW_MAX_CHANNEL_NUM_5G 49
51
52 struct rtw_dev;
53
54 enum rtw_hci_type {
55 RTW_HCI_TYPE_PCIE,
56 RTW_HCI_TYPE_USB,
57 RTW_HCI_TYPE_SDIO,
58
59 RTW_HCI_TYPE_UNDEFINE,
60 };
61
62 struct rtw_hci {
63 struct rtw_hci_ops *ops;
64 enum rtw_hci_type type;
65
66 u32 rpwm_addr;
67 u32 cpwm_addr;
68
69 u8 bulkout_num;
70 };
71
72 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48))
73 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64))
74 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144))
75 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177))
76
77 #define IS_CH_5G_BAND_MID(channel) \
78 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel))
79
80 #define IS_CH_2G_BAND(channel) ((channel) <= 14)
81 #define IS_CH_5G_BAND(channel) \
82 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \
83 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel))
84
85 enum rtw_supported_band {
86 RTW_BAND_2G = BIT(NL80211_BAND_2GHZ),
87 RTW_BAND_5G = BIT(NL80211_BAND_5GHZ),
88 RTW_BAND_60G = BIT(NL80211_BAND_60GHZ),
89 };
90
91 /* now, support up to 80M bw */
92 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
93
94 enum rtw_bandwidth {
95 RTW_CHANNEL_WIDTH_20 = 0,
96 RTW_CHANNEL_WIDTH_40 = 1,
97 RTW_CHANNEL_WIDTH_80 = 2,
98 RTW_CHANNEL_WIDTH_160 = 3,
99 RTW_CHANNEL_WIDTH_80_80 = 4,
100 RTW_CHANNEL_WIDTH_5 = 5,
101 RTW_CHANNEL_WIDTH_10 = 6,
102 };
103
104 enum rtw_sc_offset {
105 RTW_SC_DONT_CARE = 0,
106 RTW_SC_20_UPPER = 1,
107 RTW_SC_20_LOWER = 2,
108 RTW_SC_20_UPMOST = 3,
109 RTW_SC_20_LOWEST = 4,
110 RTW_SC_40_UPPER = 9,
111 RTW_SC_40_LOWER = 10,
112 };
113
114 enum rtw_net_type {
115 RTW_NET_NO_LINK = 0,
116 RTW_NET_AD_HOC = 1,
117 RTW_NET_MGD_LINKED = 2,
118 RTW_NET_AP_MODE = 3,
119 };
120
121 enum rtw_rf_type {
122 RF_1T1R = 0,
123 RF_1T2R = 1,
124 RF_2T2R = 2,
125 RF_2T3R = 3,
126 RF_2T4R = 4,
127 RF_3T3R = 5,
128 RF_3T4R = 6,
129 RF_4T4R = 7,
130 RF_TYPE_MAX,
131 };
132
133 enum rtw_rf_path {
134 RF_PATH_A = 0,
135 RF_PATH_B = 1,
136 RF_PATH_C = 2,
137 RF_PATH_D = 3,
138 };
139
140 enum rtw_bb_path {
141 BB_PATH_A = BIT(0),
142 BB_PATH_B = BIT(1),
143 BB_PATH_C = BIT(2),
144 BB_PATH_D = BIT(3),
145
146 BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
147 BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
148 BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
149 BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
150 BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
151 BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
152
153 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
154 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
155 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
156 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
157
158 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
159 };
160
161 enum rtw_rate_section {
162 RTW_RATE_SECTION_CCK = 0,
163 RTW_RATE_SECTION_OFDM,
164 RTW_RATE_SECTION_HT_1S,
165 RTW_RATE_SECTION_HT_2S,
166 RTW_RATE_SECTION_VHT_1S,
167 RTW_RATE_SECTION_VHT_2S,
168
169 /* keep last */
170 RTW_RATE_SECTION_MAX,
171 };
172
173 enum rtw_wireless_set {
174 WIRELESS_CCK = 0x00000001,
175 WIRELESS_OFDM = 0x00000002,
176 WIRELESS_HT = 0x00000004,
177 WIRELESS_VHT = 0x00000008,
178 };
179
180 #define HT_STBC_EN BIT(0)
181 #define VHT_STBC_EN BIT(1)
182 #define HT_LDPC_EN BIT(0)
183 #define VHT_LDPC_EN BIT(1)
184
185 enum rtw_chip_type {
186 RTW_CHIP_TYPE_8822B,
187 RTW_CHIP_TYPE_8822C,
188 RTW_CHIP_TYPE_8723D,
189 RTW_CHIP_TYPE_8821C,
190 RTW_CHIP_TYPE_8703B,
191 };
192
193 enum rtw_tx_queue_type {
194 /* the order of AC queues matters */
195 RTW_TX_QUEUE_BK = 0x0,
196 RTW_TX_QUEUE_BE = 0x1,
197 RTW_TX_QUEUE_VI = 0x2,
198 RTW_TX_QUEUE_VO = 0x3,
199
200 RTW_TX_QUEUE_BCN = 0x4,
201 RTW_TX_QUEUE_MGMT = 0x5,
202 RTW_TX_QUEUE_HI0 = 0x6,
203 RTW_TX_QUEUE_H2C = 0x7,
204 /* keep it last */
205 RTK_MAX_TX_QUEUE_NUM
206 };
207
208 enum rtw_rx_queue_type {
209 RTW_RX_QUEUE_MPDU = 0x0,
210 RTW_RX_QUEUE_C2H = 0x1,
211 /* keep it last */
212 RTK_MAX_RX_QUEUE_NUM
213 };
214
215 enum rtw_fw_type {
216 RTW_NORMAL_FW = 0x0,
217 RTW_WOWLAN_FW = 0x1,
218 };
219
220 enum rtw_rate_index {
221 RTW_RATEID_BGN_40M_2SS = 0,
222 RTW_RATEID_BGN_40M_1SS = 1,
223 RTW_RATEID_BGN_20M_2SS = 2,
224 RTW_RATEID_BGN_20M_1SS = 3,
225 RTW_RATEID_GN_N2SS = 4,
226 RTW_RATEID_GN_N1SS = 5,
227 RTW_RATEID_BG = 6,
228 RTW_RATEID_G = 7,
229 RTW_RATEID_B_20M = 8,
230 RTW_RATEID_ARFR0_AC_2SS = 9,
231 RTW_RATEID_ARFR1_AC_1SS = 10,
232 RTW_RATEID_ARFR2_AC_2G_1SS = 11,
233 RTW_RATEID_ARFR3_AC_2G_2SS = 12,
234 RTW_RATEID_ARFR4_AC_3SS = 13,
235 RTW_RATEID_ARFR5_N_3SS = 14,
236 RTW_RATEID_ARFR7_N_4SS = 15,
237 RTW_RATEID_ARFR6_AC_4SS = 16
238 };
239
240 enum rtw_trx_desc_rate {
241 DESC_RATE1M = 0x00,
242 DESC_RATE2M = 0x01,
243 DESC_RATE5_5M = 0x02,
244 DESC_RATE11M = 0x03,
245
246 DESC_RATE6M = 0x04,
247 DESC_RATE9M = 0x05,
248 DESC_RATE12M = 0x06,
249 DESC_RATE18M = 0x07,
250 DESC_RATE24M = 0x08,
251 DESC_RATE36M = 0x09,
252 DESC_RATE48M = 0x0a,
253 DESC_RATE54M = 0x0b,
254
255 DESC_RATEMCS0 = 0x0c,
256 DESC_RATEMCS1 = 0x0d,
257 DESC_RATEMCS2 = 0x0e,
258 DESC_RATEMCS3 = 0x0f,
259 DESC_RATEMCS4 = 0x10,
260 DESC_RATEMCS5 = 0x11,
261 DESC_RATEMCS6 = 0x12,
262 DESC_RATEMCS7 = 0x13,
263 DESC_RATEMCS8 = 0x14,
264 DESC_RATEMCS9 = 0x15,
265 DESC_RATEMCS10 = 0x16,
266 DESC_RATEMCS11 = 0x17,
267 DESC_RATEMCS12 = 0x18,
268 DESC_RATEMCS13 = 0x19,
269 DESC_RATEMCS14 = 0x1a,
270 DESC_RATEMCS15 = 0x1b,
271 DESC_RATEMCS16 = 0x1c,
272 DESC_RATEMCS17 = 0x1d,
273 DESC_RATEMCS18 = 0x1e,
274 DESC_RATEMCS19 = 0x1f,
275 DESC_RATEMCS20 = 0x20,
276 DESC_RATEMCS21 = 0x21,
277 DESC_RATEMCS22 = 0x22,
278 DESC_RATEMCS23 = 0x23,
279 DESC_RATEMCS24 = 0x24,
280 DESC_RATEMCS25 = 0x25,
281 DESC_RATEMCS26 = 0x26,
282 DESC_RATEMCS27 = 0x27,
283 DESC_RATEMCS28 = 0x28,
284 DESC_RATEMCS29 = 0x29,
285 DESC_RATEMCS30 = 0x2a,
286 DESC_RATEMCS31 = 0x2b,
287
288 DESC_RATEVHT1SS_MCS0 = 0x2c,
289 DESC_RATEVHT1SS_MCS1 = 0x2d,
290 DESC_RATEVHT1SS_MCS2 = 0x2e,
291 DESC_RATEVHT1SS_MCS3 = 0x2f,
292 DESC_RATEVHT1SS_MCS4 = 0x30,
293 DESC_RATEVHT1SS_MCS5 = 0x31,
294 DESC_RATEVHT1SS_MCS6 = 0x32,
295 DESC_RATEVHT1SS_MCS7 = 0x33,
296 DESC_RATEVHT1SS_MCS8 = 0x34,
297 DESC_RATEVHT1SS_MCS9 = 0x35,
298
299 DESC_RATEVHT2SS_MCS0 = 0x36,
300 DESC_RATEVHT2SS_MCS1 = 0x37,
301 DESC_RATEVHT2SS_MCS2 = 0x38,
302 DESC_RATEVHT2SS_MCS3 = 0x39,
303 DESC_RATEVHT2SS_MCS4 = 0x3a,
304 DESC_RATEVHT2SS_MCS5 = 0x3b,
305 DESC_RATEVHT2SS_MCS6 = 0x3c,
306 DESC_RATEVHT2SS_MCS7 = 0x3d,
307 DESC_RATEVHT2SS_MCS8 = 0x3e,
308 DESC_RATEVHT2SS_MCS9 = 0x3f,
309
310 DESC_RATEVHT3SS_MCS0 = 0x40,
311 DESC_RATEVHT3SS_MCS1 = 0x41,
312 DESC_RATEVHT3SS_MCS2 = 0x42,
313 DESC_RATEVHT3SS_MCS3 = 0x43,
314 DESC_RATEVHT3SS_MCS4 = 0x44,
315 DESC_RATEVHT3SS_MCS5 = 0x45,
316 DESC_RATEVHT3SS_MCS6 = 0x46,
317 DESC_RATEVHT3SS_MCS7 = 0x47,
318 DESC_RATEVHT3SS_MCS8 = 0x48,
319 DESC_RATEVHT3SS_MCS9 = 0x49,
320
321 DESC_RATEVHT4SS_MCS0 = 0x4a,
322 DESC_RATEVHT4SS_MCS1 = 0x4b,
323 DESC_RATEVHT4SS_MCS2 = 0x4c,
324 DESC_RATEVHT4SS_MCS3 = 0x4d,
325 DESC_RATEVHT4SS_MCS4 = 0x4e,
326 DESC_RATEVHT4SS_MCS5 = 0x4f,
327 DESC_RATEVHT4SS_MCS6 = 0x50,
328 DESC_RATEVHT4SS_MCS7 = 0x51,
329 DESC_RATEVHT4SS_MCS8 = 0x52,
330 DESC_RATEVHT4SS_MCS9 = 0x53,
331
332 DESC_RATE_MAX,
333 };
334
335 enum rtw_regulatory_domains {
336 RTW_REGD_FCC = 0,
337 RTW_REGD_MKK = 1,
338 RTW_REGD_ETSI = 2,
339 RTW_REGD_IC = 3,
340 RTW_REGD_KCC = 4,
341 RTW_REGD_ACMA = 5,
342 RTW_REGD_CHILE = 6,
343 RTW_REGD_UKRAINE = 7,
344 RTW_REGD_MEXICO = 8,
345 RTW_REGD_CN = 9,
346 RTW_REGD_QATAR = 10,
347 RTW_REGD_UK = 11,
348
349 RTW_REGD_WW,
350 RTW_REGD_MAX
351 };
352
353 enum rtw_txq_flags {
354 RTW_TXQ_AMPDU,
355 RTW_TXQ_BLOCK_BA,
356 };
357
358 enum rtw_flags {
359 RTW_FLAG_RUNNING,
360 RTW_FLAG_FW_RUNNING,
361 RTW_FLAG_SCANNING,
362 RTW_FLAG_POWERON,
363 RTW_FLAG_LEISURE_PS,
364 RTW_FLAG_LEISURE_PS_DEEP,
365 RTW_FLAG_DIG_DISABLE,
366 RTW_FLAG_BUSY_TRAFFIC,
367 RTW_FLAG_WOWLAN,
368 RTW_FLAG_RESTARTING,
369 RTW_FLAG_RESTART_TRIGGERING,
370 RTW_FLAG_FORCE_LOWEST_RATE,
371
372 NUM_OF_RTW_FLAGS,
373 };
374
375 enum rtw_evm {
376 RTW_EVM_OFDM = 0,
377 RTW_EVM_1SS,
378 RTW_EVM_2SS_A,
379 RTW_EVM_2SS_B,
380 /* keep it last */
381 RTW_EVM_NUM
382 };
383
384 enum rtw_snr {
385 RTW_SNR_OFDM_A = 0,
386 RTW_SNR_OFDM_B,
387 RTW_SNR_OFDM_C,
388 RTW_SNR_OFDM_D,
389 RTW_SNR_1SS_A,
390 RTW_SNR_1SS_B,
391 RTW_SNR_1SS_C,
392 RTW_SNR_1SS_D,
393 RTW_SNR_2SS_A,
394 RTW_SNR_2SS_B,
395 RTW_SNR_2SS_C,
396 RTW_SNR_2SS_D,
397 /* keep it last */
398 RTW_SNR_NUM
399 };
400
401 enum rtw_port {
402 RTW_PORT_0 = 0,
403 RTW_PORT_1 = 1,
404 RTW_PORT_2 = 2,
405 RTW_PORT_3 = 3,
406 RTW_PORT_4 = 4,
407 RTW_PORT_NUM
408 };
409
410 enum rtw_wow_flags {
411 RTW_WOW_FLAG_EN_MAGIC_PKT,
412 RTW_WOW_FLAG_EN_REKEY_PKT,
413 RTW_WOW_FLAG_EN_DISCONNECT,
414
415 /* keep it last */
416 RTW_WOW_FLAG_MAX,
417 };
418
419 /* the power index is represented by differences, which cck-1s & ht40-1s are
420 * the base values, so for 1s's differences, there are only ht20 & ofdm
421 */
422 struct rtw_2g_1s_pwr_idx_diff {
423 #ifdef __LITTLE_ENDIAN
424 s8 ofdm:4;
425 s8 bw20:4;
426 #else
427 s8 bw20:4;
428 s8 ofdm:4;
429 #endif
430 } __packed;
431
432 struct rtw_2g_ns_pwr_idx_diff {
433 #ifdef __LITTLE_ENDIAN
434 s8 bw20:4;
435 s8 bw40:4;
436 s8 cck:4;
437 s8 ofdm:4;
438 #else
439 s8 ofdm:4;
440 s8 cck:4;
441 s8 bw40:4;
442 s8 bw20:4;
443 #endif
444 } __packed;
445
446 struct rtw_2g_txpwr_idx {
447 u8 cck_base[6];
448 u8 bw40_base[5];
449 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
450 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
451 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
452 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
453 };
454
455 struct rtw_5g_ht_1s_pwr_idx_diff {
456 #ifdef __LITTLE_ENDIAN
457 s8 ofdm:4;
458 s8 bw20:4;
459 #else
460 s8 bw20:4;
461 s8 ofdm:4;
462 #endif
463 } __packed;
464
465 struct rtw_5g_ht_ns_pwr_idx_diff {
466 #ifdef __LITTLE_ENDIAN
467 s8 bw20:4;
468 s8 bw40:4;
469 #else
470 s8 bw40:4;
471 s8 bw20:4;
472 #endif
473 } __packed;
474
475 struct rtw_5g_ofdm_ns_pwr_idx_diff {
476 #ifdef __LITTLE_ENDIAN
477 s8 ofdm_3s:4;
478 s8 ofdm_2s:4;
479 s8 ofdm_4s:4;
480 s8 res:4;
481 #else
482 s8 res:4;
483 s8 ofdm_4s:4;
484 s8 ofdm_2s:4;
485 s8 ofdm_3s:4;
486 #endif
487 } __packed;
488
489 struct rtw_5g_vht_ns_pwr_idx_diff {
490 #ifdef __LITTLE_ENDIAN
491 s8 bw160:4;
492 s8 bw80:4;
493 #else
494 s8 bw80:4;
495 s8 bw160:4;
496 #endif
497 } __packed;
498
499 struct rtw_5g_txpwr_idx {
500 u8 bw40_base[14];
501 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
502 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
503 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
504 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
505 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
506 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
507 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
508 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
509 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
510 };
511
512 struct rtw_txpwr_idx {
513 struct rtw_2g_txpwr_idx pwr_idx_2g;
514 struct rtw_5g_txpwr_idx pwr_idx_5g;
515 };
516
517 struct rtw_channel_params {
518 u8 center_chan;
519 u8 primary_chan;
520 u8 bandwidth;
521 };
522
523 struct rtw_hw_reg {
524 u32 addr;
525 u32 mask;
526 };
527
528 struct rtw_hw_reg_desc {
529 u32 addr;
530 u32 mask;
531 const char *desc;
532 };
533
534 struct rtw_ltecoex_addr {
535 u32 ctrl;
536 u32 wdata;
537 u32 rdata;
538 };
539
540 struct rtw_reg_domain {
541 u32 addr;
542 u32 mask;
543 #define RTW_REG_DOMAIN_MAC32 0
544 #define RTW_REG_DOMAIN_MAC16 1
545 #define RTW_REG_DOMAIN_MAC8 2
546 #define RTW_REG_DOMAIN_RF_A 3
547 #define RTW_REG_DOMAIN_RF_B 4
548 #define RTW_REG_DOMAIN_NL 0xFF
549 u8 domain;
550 };
551
552 struct rtw_rf_sipi_addr {
553 u32 hssi_1;
554 u32 hssi_2;
555 u32 lssi_read;
556 u32 lssi_read_pi;
557 };
558
559 struct rtw_hw_reg_offset {
560 struct rtw_hw_reg hw_reg;
561 u8 offset;
562 };
563
564 struct rtw_backup_info {
565 u8 len;
566 u32 reg;
567 u32 val;
568 };
569
570 enum rtw_vif_port_set {
571 PORT_SET_MAC_ADDR = BIT(0),
572 PORT_SET_BSSID = BIT(1),
573 PORT_SET_NET_TYPE = BIT(2),
574 PORT_SET_AID = BIT(3),
575 PORT_SET_BCN_CTRL = BIT(4),
576 };
577
578 struct rtw_vif_port {
579 struct rtw_hw_reg mac_addr;
580 struct rtw_hw_reg bssid;
581 struct rtw_hw_reg net_type;
582 struct rtw_hw_reg aid;
583 struct rtw_hw_reg bcn_ctrl;
584 };
585
586 struct rtw_tx_pkt_info {
587 u32 tx_pkt_size;
588 u8 offset;
589 u8 pkt_offset;
590 u8 tim_offset;
591 u8 mac_id;
592 u8 rate_id;
593 u8 rate;
594 u8 qsel;
595 u8 bw;
596 u8 sec_type;
597 u8 sn;
598 bool ampdu_en;
599 u8 ampdu_factor;
600 u8 ampdu_density;
601 u16 seq;
602 bool stbc;
603 bool ldpc;
604 bool dis_rate_fallback;
605 bool bmc;
606 bool use_rate;
607 bool ls;
608 bool fs;
609 bool short_gi;
610 bool report;
611 bool rts;
612 bool dis_qselseq;
613 bool en_hwseq;
614 u8 hw_ssn_sel;
615 bool nav_use_hdr;
616 bool bt_null;
617 };
618
619 struct rtw_rx_pkt_stat {
620 bool phy_status;
621 bool icv_err;
622 bool crc_err;
623 bool decrypted;
624 bool is_c2h;
625
626 s32 signal_power;
627 u16 pkt_len;
628 u8 bw;
629 u8 drv_info_sz;
630 u8 shift;
631 u8 rate;
632 u8 mac_id;
633 u8 cam_id;
634 u8 ppdu_cnt;
635 u32 tsf_low;
636 s8 rx_power[RTW_RF_PATH_MAX];
637 u8 rssi;
638 u8 rxsc;
639 s8 rx_snr[RTW_RF_PATH_MAX];
640 u8 rx_evm[RTW_RF_PATH_MAX];
641 s8 cfo_tail[RTW_RF_PATH_MAX];
642 u16 freq;
643 u8 band;
644
645 struct rtw_sta_info *si;
646 struct ieee80211_vif *vif;
647 struct ieee80211_hdr *hdr;
648 };
649
650 DECLARE_EWMA(tp, 10, 2);
651
652 struct rtw_traffic_stats {
653 /* units in bytes */
654 u64 tx_unicast;
655 u64 rx_unicast;
656
657 /* count for packets */
658 u64 tx_cnt;
659 u64 rx_cnt;
660
661 /* units in Mbps */
662 u32 tx_throughput;
663 u32 rx_throughput;
664 struct ewma_tp tx_ewma_tp;
665 struct ewma_tp rx_ewma_tp;
666 };
667
668 enum rtw_lps_mode {
669 RTW_MODE_ACTIVE = 0,
670 RTW_MODE_LPS = 1,
671 RTW_MODE_WMM_PS = 2,
672 };
673
674 enum rtw_lps_deep_mode {
675 LPS_DEEP_MODE_NONE = 0,
676 LPS_DEEP_MODE_LCLK = 1,
677 LPS_DEEP_MODE_PG = 2,
678 };
679
680 enum rtw_pwr_state {
681 RTW_RF_OFF = 0x0,
682 RTW_RF_ON = 0x4,
683 RTW_ALL_ON = 0xc,
684 };
685
686 struct rtw_lps_conf {
687 enum rtw_lps_mode mode;
688 enum rtw_lps_deep_mode deep_mode;
689 enum rtw_lps_deep_mode wow_deep_mode;
690 enum rtw_pwr_state state;
691 u8 awake_interval;
692 u8 rlbm;
693 u8 smart_ps;
694 u8 port_id;
695 bool sec_cam_backup;
696 bool pattern_cam_backup;
697 };
698
699 enum rtw_hw_key_type {
700 RTW_CAM_NONE = 0,
701 RTW_CAM_WEP40 = 1,
702 RTW_CAM_TKIP = 2,
703 RTW_CAM_AES = 4,
704 RTW_CAM_WEP104 = 5,
705 };
706
707 struct rtw_cam_entry {
708 bool valid;
709 bool group;
710 u8 addr[ETH_ALEN];
711 u8 hw_key_type;
712 struct ieee80211_key_conf *key;
713 };
714
715 struct rtw_sec_desc {
716 /* search strategy */
717 bool default_key_search;
718
719 u32 total_cam_num;
720 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
721 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
722 };
723
724 struct rtw_tx_report {
725 /* protect the tx report queue */
726 spinlock_t q_lock;
727 struct sk_buff_head queue;
728 atomic_t sn;
729 struct timer_list purge_timer;
730 };
731
732 struct rtw_ra_report {
733 struct rate_info txrate;
734 u32 bit_rate;
735 u8 desc_rate;
736 };
737
738 struct rtw_txq {
739 struct list_head list;
740 unsigned long flags;
741 };
742
743 #define RTW_BC_MC_MACID 1
744 DECLARE_EWMA(rssi, 10, 16);
745
746 struct rtw_sta_info {
747 struct rtw_dev *rtwdev;
748 struct ieee80211_sta *sta;
749 struct ieee80211_vif *vif;
750
751 struct ewma_rssi avg_rssi;
752 u8 rssi_level;
753
754 u8 mac_id;
755 u8 rate_id;
756 enum rtw_bandwidth bw_mode;
757 enum rtw_rf_type rf_type;
758 u8 stbc_en:2;
759 u8 ldpc_en:2;
760 bool sgi_enable;
761 bool vht_enable;
762 u8 init_ra_lv;
763 u64 ra_mask;
764
765 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS);
766
767 struct rtw_ra_report ra_report;
768
769 bool use_cfg_mask;
770 struct cfg80211_bitrate_mask *mask;
771
772 struct work_struct rc_work;
773 };
774
775 enum rtw_bfee_role {
776 RTW_BFEE_NONE,
777 RTW_BFEE_SU,
778 RTW_BFEE_MU
779 };
780
781 struct rtw_bfee {
782 enum rtw_bfee_role role;
783
784 u16 p_aid;
785 u8 g_id;
786 u8 mac_addr[ETH_ALEN];
787 u8 sound_dim;
788
789 /* SU-MIMO */
790 u8 su_reg_index;
791
792 /* MU-MIMO */
793 u16 aid;
794 };
795
796 struct rtw_bf_info {
797 u8 bfer_mu_cnt;
798 u8 bfer_su_cnt;
799 DECLARE_BITMAP(bfer_su_reg_maping, 2);
800 u8 cur_csi_rpt_rate;
801 };
802
803 struct rtw_vif {
804 enum rtw_net_type net_type;
805 u16 aid;
806 u8 mac_id; /* for STA mode only */
807 u8 mac_addr[ETH_ALEN];
808 u8 bssid[ETH_ALEN];
809 u8 port;
810 u8 bcn_ctrl;
811 struct list_head rsvd_page_list;
812 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
813 const struct rtw_vif_port *conf;
814 struct cfg80211_scan_request *scan_req;
815 struct ieee80211_scan_ies *scan_ies;
816
817 struct rtw_traffic_stats stats;
818
819 struct rtw_bfee bfee;
820 };
821
822 struct rtw_regulatory {
823 char alpha2[2];
824 u8 txpwr_regd_2g;
825 u8 txpwr_regd_5g;
826 };
827
828 enum rtw_regd_state {
829 RTW_REGD_STATE_WORLDWIDE,
830 RTW_REGD_STATE_PROGRAMMED,
831 RTW_REGD_STATE_SETTING,
832
833 RTW_REGD_STATE_NR,
834 };
835
836 struct rtw_regd {
837 enum rtw_regd_state state;
838 const struct rtw_regulatory *regulatory;
839 enum nl80211_dfs_regions dfs_region;
840 };
841
842 struct rtw_chip_ops {
843 int (*mac_init)(struct rtw_dev *rtwdev);
844 int (*dump_fw_crash)(struct rtw_dev *rtwdev);
845 void (*shutdown)(struct rtw_dev *rtwdev);
846 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
847 void (*phy_set_param)(struct rtw_dev *rtwdev);
848 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
849 u8 bandwidth, u8 primary_chan_idx);
850 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc,
851 struct rtw_rx_pkt_stat *pkt_stat,
852 struct ieee80211_rx_status *rx_status);
853 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
854 u32 addr, u32 mask);
855 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
856 u32 addr, u32 mask, u32 data);
857 void (*set_tx_power_index)(struct rtw_dev *rtwdev);
858 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
859 u32 size);
860 int (*set_antenna)(struct rtw_dev *rtwdev,
861 u32 antenna_tx,
862 u32 antenna_rx);
863 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
864 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable);
865 void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
866 void (*phy_calibration)(struct rtw_dev *rtwdev);
867 void (*dpk_track)(struct rtw_dev *rtwdev);
868 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
869 void (*pwr_track)(struct rtw_dev *rtwdev);
870 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif,
871 struct rtw_bfee *bfee, bool enable);
872 void (*set_gid_table)(struct rtw_dev *rtwdev,
873 struct ieee80211_vif *vif,
874 struct ieee80211_bss_conf *conf);
875 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
876 u8 fixrate_en, u8 *new_rate);
877 void (*adaptivity_init)(struct rtw_dev *rtwdev);
878 void (*adaptivity)(struct rtw_dev *rtwdev);
879 void (*cfo_init)(struct rtw_dev *rtwdev);
880 void (*cfo_track)(struct rtw_dev *rtwdev);
881 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path,
882 enum rtw_bb_path tx_path_1ss,
883 enum rtw_bb_path tx_path_cck,
884 bool is_tx2_path);
885 void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path,
886 u8 rx_path, bool is_tx2_path);
887 /* for USB/SDIO only */
888 void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev,
889 struct rtw_tx_pkt_info *pkt_info,
890 u8 *txdesc);
891
892 /* for coex */
893 void (*coex_set_init)(struct rtw_dev *rtwdev);
894 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
895 u8 ctrl_type, u8 pos_type);
896 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
897 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
898 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
899 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
900 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
901 };
902
903 #define RTW_PWR_POLLING_CNT 20000
904
905 #define RTW_PWR_CMD_READ 0x00
906 #define RTW_PWR_CMD_WRITE 0x01
907 #define RTW_PWR_CMD_POLLING 0x02
908 #define RTW_PWR_CMD_DELAY 0x03
909 #define RTW_PWR_CMD_END 0x04
910
911 /* define the base address of each block */
912 #define RTW_PWR_ADDR_MAC 0x00
913 #define RTW_PWR_ADDR_USB 0x01
914 #define RTW_PWR_ADDR_PCIE 0x02
915 #define RTW_PWR_ADDR_SDIO 0x03
916
917 #define RTW_PWR_INTF_SDIO_MSK BIT(0)
918 #define RTW_PWR_INTF_USB_MSK BIT(1)
919 #define RTW_PWR_INTF_PCI_MSK BIT(2)
920 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
921
922 #define RTW_PWR_CUT_TEST_MSK BIT(0)
923 #define RTW_PWR_CUT_A_MSK BIT(1)
924 #define RTW_PWR_CUT_B_MSK BIT(2)
925 #define RTW_PWR_CUT_C_MSK BIT(3)
926 #define RTW_PWR_CUT_D_MSK BIT(4)
927 #define RTW_PWR_CUT_E_MSK BIT(5)
928 #define RTW_PWR_CUT_F_MSK BIT(6)
929 #define RTW_PWR_CUT_G_MSK BIT(7)
930 #define RTW_PWR_CUT_ALL_MSK 0xFF
931
932 enum rtw_pwr_seq_cmd_delay_unit {
933 RTW_PWR_DELAY_US,
934 RTW_PWR_DELAY_MS,
935 };
936
937 struct rtw_pwr_seq_cmd {
938 u16 offset;
939 u8 cut_mask;
940 u8 intf_mask;
941 u8 base:4;
942 u8 cmd:4;
943 u8 mask;
944 u8 value;
945 };
946
947 enum rtw_chip_ver {
948 RTW_CHIP_VER_CUT_A = 0x00,
949 RTW_CHIP_VER_CUT_B = 0x01,
950 RTW_CHIP_VER_CUT_C = 0x02,
951 RTW_CHIP_VER_CUT_D = 0x03,
952 RTW_CHIP_VER_CUT_E = 0x04,
953 RTW_CHIP_VER_CUT_F = 0x05,
954 RTW_CHIP_VER_CUT_G = 0x06,
955 };
956
957 #define RTW_INTF_PHY_PLATFORM_ALL 0
958
959 enum rtw_intf_phy_cut {
960 RTW_INTF_PHY_CUT_A = BIT(0),
961 RTW_INTF_PHY_CUT_B = BIT(1),
962 RTW_INTF_PHY_CUT_C = BIT(2),
963 RTW_INTF_PHY_CUT_D = BIT(3),
964 RTW_INTF_PHY_CUT_E = BIT(4),
965 RTW_INTF_PHY_CUT_F = BIT(5),
966 RTW_INTF_PHY_CUT_G = BIT(6),
967 RTW_INTF_PHY_CUT_ALL = 0xFFFF,
968 };
969
970 enum rtw_ip_sel {
971 RTW_IP_SEL_PHY = 0,
972 RTW_IP_SEL_MAC = 1,
973 RTW_IP_SEL_DBI = 2,
974
975 RTW_IP_SEL_UNDEF = 0xFFFF
976 };
977
978 enum rtw_pq_map_id {
979 RTW_PQ_MAP_VO = 0x0,
980 RTW_PQ_MAP_VI = 0x1,
981 RTW_PQ_MAP_BE = 0x2,
982 RTW_PQ_MAP_BK = 0x3,
983 RTW_PQ_MAP_MG = 0x4,
984 RTW_PQ_MAP_HI = 0x5,
985 RTW_PQ_MAP_NUM = 0x6,
986
987 RTW_PQ_MAP_UNDEF,
988 };
989
990 enum rtw_dma_mapping {
991 RTW_DMA_MAPPING_EXTRA = 0,
992 RTW_DMA_MAPPING_LOW = 1,
993 RTW_DMA_MAPPING_NORMAL = 2,
994 RTW_DMA_MAPPING_HIGH = 3,
995
996 RTW_DMA_MAPPING_MAX,
997 RTW_DMA_MAPPING_UNDEF,
998 };
999
1000 struct rtw_rqpn {
1001 enum rtw_dma_mapping dma_map_vo;
1002 enum rtw_dma_mapping dma_map_vi;
1003 enum rtw_dma_mapping dma_map_be;
1004 enum rtw_dma_mapping dma_map_bk;
1005 enum rtw_dma_mapping dma_map_mg;
1006 enum rtw_dma_mapping dma_map_hi;
1007 };
1008
1009 struct rtw_prioq_addr {
1010 u32 rsvd;
1011 u32 avail;
1012 };
1013
1014 struct rtw_prioq_addrs {
1015 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX];
1016 bool wsize;
1017 };
1018
1019 struct rtw_page_table {
1020 u16 hq_num;
1021 u16 nq_num;
1022 u16 lq_num;
1023 u16 exq_num;
1024 u16 gapq_num;
1025 };
1026
1027 struct rtw_intf_phy_para {
1028 u16 offset;
1029 u16 value;
1030 u16 ip_sel;
1031 u16 cut_mask;
1032 u16 platform;
1033 };
1034
1035 struct rtw_wow_pattern {
1036 u16 crc;
1037 u8 type;
1038 u8 valid;
1039 u8 mask[RTW_MAX_PATTERN_MASK_SIZE];
1040 };
1041
1042 struct rtw_pno_request {
1043 bool inited;
1044 u32 match_set_cnt;
1045 struct cfg80211_match_set *match_sets;
1046 u8 channel_cnt;
1047 struct ieee80211_channel *channels;
1048 struct cfg80211_sched_scan_plan scan_plan;
1049 };
1050
1051 struct rtw_wow_param {
1052 struct ieee80211_vif *wow_vif;
1053 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX);
1054 u8 txpause;
1055 u8 pattern_cnt;
1056 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM];
1057
1058 bool ips_enabled;
1059 struct rtw_pno_request pno_req;
1060 };
1061
1062 struct rtw_intf_phy_para_table {
1063 const struct rtw_intf_phy_para *usb2_para;
1064 const struct rtw_intf_phy_para *usb3_para;
1065 const struct rtw_intf_phy_para *gen1_para;
1066 const struct rtw_intf_phy_para *gen2_para;
1067 u8 n_usb2_para;
1068 u8 n_usb3_para;
1069 u8 n_gen1_para;
1070 u8 n_gen2_para;
1071 };
1072
1073 struct rtw_table {
1074 const void *data;
1075 const u32 size;
1076 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
1077 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1078 u32 addr, u32 data);
1079 enum rtw_rf_path rf_path;
1080 };
1081
rtw_load_table(struct rtw_dev * rtwdev,const struct rtw_table * tbl)1082 static inline void rtw_load_table(struct rtw_dev *rtwdev,
1083 const struct rtw_table *tbl)
1084 {
1085 (*tbl->parse)(rtwdev, tbl);
1086 }
1087
1088 enum rtw_rfe_fem {
1089 RTW_RFE_IFEM,
1090 RTW_RFE_EFEM,
1091 RTW_RFE_IFEM2G_EFEM5G,
1092 RTW_RFE_NUM,
1093 };
1094
1095 struct rtw_rfe_def {
1096 const struct rtw_table *phy_pg_tbl;
1097 const struct rtw_table *txpwr_lmt_tbl;
1098 const struct rtw_table *agc_btg_tbl;
1099 };
1100
1101 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \
1102 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1103 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1104 }
1105
1106 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) { \
1107 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1108 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1109 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \
1110 }
1111
1112 #define RTW_PWR_TRK_5G_1 0
1113 #define RTW_PWR_TRK_5G_2 1
1114 #define RTW_PWR_TRK_5G_3 2
1115 #define RTW_PWR_TRK_5G_NUM 3
1116
1117 #define RTW_PWR_TRK_TBL_SZ 30
1118
1119 /* This table stores the values of TX power that will be adjusted by power
1120 * tracking.
1121 *
1122 * For 5G bands, there are 3 different settings.
1123 * For 2G there are cck rate and ofdm rate with different settings.
1124 */
1125 struct rtw_pwr_track_tbl {
1126 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM];
1127 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM];
1128 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM];
1129 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM];
1130 const u8 *pwrtrk_2gb_n;
1131 const u8 *pwrtrk_2gb_p;
1132 const u8 *pwrtrk_2ga_n;
1133 const u8 *pwrtrk_2ga_p;
1134 const u8 *pwrtrk_2g_cckb_n;
1135 const u8 *pwrtrk_2g_cckb_p;
1136 const u8 *pwrtrk_2g_ccka_n;
1137 const u8 *pwrtrk_2g_ccka_p;
1138 const s8 *pwrtrk_xtal_n;
1139 const s8 *pwrtrk_xtal_p;
1140 };
1141
1142 enum rtw_wlan_cpu {
1143 RTW_WCPU_11AC,
1144 RTW_WCPU_11N,
1145 };
1146
1147 enum rtw_fw_fifo_sel {
1148 RTW_FW_FIFO_SEL_TX,
1149 RTW_FW_FIFO_SEL_RX,
1150 RTW_FW_FIFO_SEL_RSVD_PAGE,
1151 RTW_FW_FIFO_SEL_REPORT,
1152 RTW_FW_FIFO_SEL_LLT,
1153 RTW_FW_FIFO_SEL_RXBUF_FW,
1154
1155 RTW_FW_FIFO_MAX,
1156 };
1157
1158 enum rtw_fwcd_item {
1159 RTW_FWCD_TLV,
1160 RTW_FWCD_REG,
1161 RTW_FWCD_ROM,
1162 RTW_FWCD_IMEM,
1163 RTW_FWCD_DMEM,
1164 RTW_FWCD_EMEM,
1165 };
1166
1167 /* hardware configuration for each IC */
1168 struct rtw_chip_info {
1169 struct rtw_chip_ops *ops;
1170 u8 id;
1171
1172 const char *fw_name;
1173 enum rtw_wlan_cpu wlan_cpu;
1174 u8 tx_pkt_desc_sz;
1175 u8 tx_buf_desc_sz;
1176 u8 rx_pkt_desc_sz;
1177 u8 rx_buf_desc_sz;
1178 u32 phy_efuse_size;
1179 u32 log_efuse_size;
1180 u32 ptct_efuse_size;
1181 u32 txff_size;
1182 u32 rxff_size;
1183 u32 fw_rxff_size;
1184 u16 rsvd_drv_pg_num;
1185 u8 band;
1186 u8 page_size;
1187 u8 csi_buf_pg_num;
1188 u8 dig_max;
1189 u8 dig_min;
1190 u8 txgi_factor;
1191 bool is_pwr_by_rate_dec;
1192 bool rx_ldpc;
1193 bool tx_stbc;
1194 u8 max_power_index;
1195 u8 ampdu_density;
1196
1197 u16 fw_fifo_addr[RTW_FW_FIFO_MAX];
1198 const struct rtw_fwcd_segs *fwcd_segs;
1199
1200 u8 usb_tx_agg_desc_num;
1201
1202 u8 default_1ss_tx_path;
1203
1204 bool path_div_supported;
1205 bool ht_supported;
1206 bool vht_supported;
1207 u8 lps_deep_mode_supported;
1208
1209 /* init values */
1210 u8 sys_func_en;
1211 const struct rtw_pwr_seq_cmd **pwr_on_seq;
1212 const struct rtw_pwr_seq_cmd **pwr_off_seq;
1213 const struct rtw_rqpn *rqpn_table;
1214 const struct rtw_prioq_addrs *prioq_addrs;
1215 const struct rtw_page_table *page_table;
1216 const struct rtw_intf_phy_para_table *intf_table;
1217
1218 const struct rtw_hw_reg *dig;
1219 const struct rtw_hw_reg *dig_cck;
1220 u32 rf_base_addr[2];
1221 u32 rf_sipi_addr[2];
1222 const struct rtw_rf_sipi_addr *rf_sipi_read_addr;
1223 u8 fix_rf_phy_num;
1224 const struct rtw_ltecoex_addr *ltecoex_addr;
1225
1226 const struct rtw_table *mac_tbl;
1227 const struct rtw_table *agc_tbl;
1228 const struct rtw_table *bb_tbl;
1229 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
1230 const struct rtw_table *rfk_init_tbl;
1231
1232 const struct rtw_rfe_def *rfe_defs;
1233 u32 rfe_defs_size;
1234
1235 bool en_dis_dpd;
1236 u16 dpd_ratemask;
1237 u8 iqk_threshold;
1238 u8 lck_threshold;
1239 const struct rtw_pwr_track_tbl *pwr_track_tbl;
1240
1241 u8 bfer_su_max_num;
1242 u8 bfer_mu_max_num;
1243
1244 struct rtw_hw_reg_offset *edcca_th;
1245 s8 l2h_th_ini_cs;
1246 s8 l2h_th_ini_ad;
1247
1248 const char *wow_fw_name;
1249 const struct wiphy_wowlan_support *wowlan_stub;
1250 const u8 max_sched_scan_ssids;
1251 const u16 max_scan_ie_len;
1252
1253 /* coex paras */
1254 u32 coex_para_ver;
1255 u8 bt_desired_ver;
1256 bool scbd_support;
1257 bool new_scbd10_def; /* true: fix 2M(8822c) */
1258 bool ble_hid_profile_support;
1259 bool wl_mimo_ps_support;
1260 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
1261 u8 bt_rssi_type;
1262 u8 ant_isolation;
1263 u8 rssi_tolerance;
1264 u8 table_sant_num;
1265 u8 table_nsant_num;
1266 u8 tdma_sant_num;
1267 u8 tdma_nsant_num;
1268 u8 bt_afh_span_bw20;
1269 u8 bt_afh_span_bw40;
1270 u8 afh_5g_num;
1271 u8 wl_rf_para_num;
1272 u8 coex_info_hw_regs_num;
1273 const u8 *bt_rssi_step;
1274 const u8 *wl_rssi_step;
1275 const struct coex_table_para *table_nsant;
1276 const struct coex_table_para *table_sant;
1277 const struct coex_tdma_para *tdma_sant;
1278 const struct coex_tdma_para *tdma_nsant;
1279 const struct coex_rf_para *wl_rf_para_tx;
1280 const struct coex_rf_para *wl_rf_para_rx;
1281 const struct coex_5g_afh_map *afh_5g;
1282 const struct rtw_hw_reg *btg_reg;
1283 const struct rtw_reg_domain *coex_info_hw_regs;
1284 u32 wl_fw_desired_ver;
1285 };
1286
1287 enum rtw_coex_bt_state_cnt {
1288 COEX_CNT_BT_RETRY,
1289 COEX_CNT_BT_REINIT,
1290 COEX_CNT_BT_REENABLE,
1291 COEX_CNT_BT_POPEVENT,
1292 COEX_CNT_BT_SETUPLINK,
1293 COEX_CNT_BT_IGNWLANACT,
1294 COEX_CNT_BT_INQ,
1295 COEX_CNT_BT_PAGE,
1296 COEX_CNT_BT_ROLESWITCH,
1297 COEX_CNT_BT_AFHUPDATE,
1298 COEX_CNT_BT_INFOUPDATE,
1299 COEX_CNT_BT_IQK,
1300 COEX_CNT_BT_IQKFAIL,
1301
1302 COEX_CNT_BT_MAX
1303 };
1304
1305 enum rtw_coex_wl_state_cnt {
1306 COEX_CNT_WL_SCANAP,
1307 COEX_CNT_WL_CONNPKT,
1308 COEX_CNT_WL_COEXRUN,
1309 COEX_CNT_WL_NOISY0,
1310 COEX_CNT_WL_NOISY1,
1311 COEX_CNT_WL_NOISY2,
1312 COEX_CNT_WL_5MS_NOEXTEND,
1313 COEX_CNT_WL_FW_NOTIFY,
1314
1315 COEX_CNT_WL_MAX
1316 };
1317
1318 struct rtw_coex_rfe {
1319 bool ant_switch_exist;
1320 bool ant_switch_diversity;
1321 bool ant_switch_with_bt;
1322 u8 rfe_module_type;
1323 u8 ant_switch_polarity;
1324
1325 /* true if WLG at BTG, else at WLAG */
1326 bool wlg_at_btg;
1327 };
1328
1329 #define COEX_WL_TDMA_PARA_LENGTH 5
1330
1331 struct rtw_coex_dm {
1332 bool cur_ps_tdma_on;
1333 bool cur_wl_rx_low_gain_en;
1334 bool ignore_wl_act;
1335
1336 u8 reason;
1337 u8 bt_rssi_state[4];
1338 u8 wl_rssi_state[4];
1339 u8 wl_ch_info[3];
1340 u8 cur_ps_tdma;
1341 u8 cur_table;
1342 u8 ps_tdma_para[5];
1343 u8 cur_bt_pwr_lvl;
1344 u8 cur_bt_lna_lvl;
1345 u8 cur_wl_pwr_lvl;
1346 u8 bt_status;
1347 u32 cur_ant_pos_type;
1348 u32 cur_switch_status;
1349 u32 setting_tdma;
1350 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH];
1351 };
1352
1353 #define COEX_BTINFO_SRC_WL_FW 0x0
1354 #define COEX_BTINFO_SRC_BT_RSP 0x1
1355 #define COEX_BTINFO_SRC_BT_ACT 0x2
1356 #define COEX_BTINFO_SRC_BT_IQK 0x3
1357 #define COEX_BTINFO_SRC_BT_SCBD 0x4
1358 #define COEX_BTINFO_SRC_H2C60 0x5
1359 #define COEX_BTINFO_SRC_MAX 0x6
1360
1361 #define COEX_INFO_FTP BIT(7)
1362 #define COEX_INFO_A2DP BIT(6)
1363 #define COEX_INFO_HID BIT(5)
1364 #define COEX_INFO_SCO_BUSY BIT(4)
1365 #define COEX_INFO_ACL_BUSY BIT(3)
1366 #define COEX_INFO_INQ_PAGE BIT(2)
1367 #define COEX_INFO_SCO_ESCO BIT(1)
1368 #define COEX_INFO_CONNECTION BIT(0)
1369 #define COEX_BTINFO_LENGTH_MAX 10
1370 #define COEX_BTINFO_LENGTH 7
1371
1372 #define COEX_BT_HIDINFO_LIST 0x0
1373 #define COEX_BT_HIDINFO_A 0x1
1374 #define COEX_BT_HIDINFO_NAME 3
1375
1376 #define COEX_BT_HIDINFO_LENGTH 6
1377 #define COEX_BT_HIDINFO_HANDLE_NUM 4
1378 #define COEX_BT_HIDINFO_C2H_HANDLE 0
1379 #define COEX_BT_HIDINFO_C2H_VENDOR 1
1380 #define COEX_BT_BLE_HANDLE_THRS 0x10
1381 #define COEX_BT_HIDINFO_NOTCON 0xff
1382
1383 struct rtw_coex_hid {
1384 u8 hid_handle;
1385 u8 hid_vendor;
1386 u8 hid_name[COEX_BT_HIDINFO_NAME];
1387 bool hid_info_completed;
1388 bool is_game_hid;
1389 };
1390
1391 struct rtw_coex_hid_handle_list {
1392 u8 cmd_id;
1393 u8 len;
1394 u8 subid;
1395 u8 handle_cnt;
1396 u8 handle[COEX_BT_HIDINFO_HANDLE_NUM];
1397 } __packed;
1398
1399 struct rtw_coex_hid_info_a {
1400 u8 cmd_id;
1401 u8 len;
1402 u8 subid;
1403 u8 handle;
1404 u8 vendor;
1405 u8 name[COEX_BT_HIDINFO_NAME];
1406 } __packed;
1407
1408 struct rtw_coex_stat {
1409 bool bt_disabled;
1410 bool bt_disabled_pre;
1411 bool bt_link_exist;
1412 bool bt_whck_test;
1413 bool bt_inq_page;
1414 bool bt_inq_remain;
1415 bool bt_inq;
1416 bool bt_page;
1417 bool bt_ble_voice;
1418 bool bt_ble_exist;
1419 bool bt_hfp_exist;
1420 bool bt_a2dp_exist;
1421 bool bt_hid_exist;
1422 bool bt_pan_exist; /* PAN or OPP */
1423 bool bt_opp_exist; /* OPP only */
1424 bool bt_acl_busy;
1425 bool bt_fix_2M;
1426 bool bt_setup_link;
1427 bool bt_multi_link;
1428 bool bt_multi_link_pre;
1429 bool bt_multi_link_remain;
1430 bool bt_a2dp_sink;
1431 bool bt_a2dp_active;
1432 bool bt_reenable;
1433 bool bt_ble_scan_en;
1434 bool bt_init_scan;
1435 bool bt_slave;
1436 bool bt_418_hid_exist;
1437 bool bt_ble_hid_exist;
1438 bool bt_game_hid_exist;
1439 bool bt_hid_handle_cnt;
1440 bool bt_mailbox_reply;
1441
1442 bool wl_under_lps;
1443 bool wl_under_ips;
1444 bool wl_hi_pri_task1;
1445 bool wl_hi_pri_task2;
1446 bool wl_force_lps_ctrl;
1447 bool wl_gl_busy;
1448 bool wl_linkscan_proc;
1449 bool wl_ps_state_fail;
1450 bool wl_tx_limit_en;
1451 bool wl_ampdu_limit_en;
1452 bool wl_connected;
1453 bool wl_slot_extend;
1454 bool wl_cck_lock;
1455 bool wl_cck_lock_pre;
1456 bool wl_cck_lock_ever;
1457 bool wl_connecting;
1458 bool wl_slot_toggle;
1459 bool wl_slot_toggle_change; /* if toggle to no-toggle */
1460 bool wl_mimo_ps;
1461
1462 u32 bt_supported_version;
1463 u32 bt_supported_feature;
1464 u32 hi_pri_tx;
1465 u32 hi_pri_rx;
1466 u32 lo_pri_tx;
1467 u32 lo_pri_rx;
1468 u32 patch_ver;
1469 u16 bt_reg_vendor_ae;
1470 u16 bt_reg_vendor_ac;
1471 s8 bt_rssi;
1472 u8 kt_ver;
1473 u8 gnt_workaround_state;
1474 u8 tdma_timer_base;
1475 u8 bt_profile_num;
1476 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
1477 u8 bt_info_lb2;
1478 u8 bt_info_lb3;
1479 u8 bt_info_hb0;
1480 u8 bt_info_hb1;
1481 u8 bt_info_hb2;
1482 u8 bt_info_hb3;
1483 u8 bt_ble_scan_type;
1484 u8 bt_hid_pair_num;
1485 u8 bt_hid_slot;
1486 u8 bt_a2dp_bitpool;
1487 u8 bt_iqk_state;
1488
1489 u16 wl_beacon_interval;
1490 u8 wl_noisy_level;
1491 u8 wl_fw_dbg_info[10];
1492 u8 wl_fw_dbg_info_pre[10];
1493 u8 wl_rx_rate;
1494 u8 wl_tx_rate;
1495 u8 wl_rts_rx_rate;
1496 u8 wl_coex_mode;
1497 u8 wl_iot_peer;
1498 u8 ampdu_max_time;
1499 u8 wl_tput_dir;
1500
1501 u8 wl_toggle_para[6];
1502 u8 wl_toggle_interval;
1503
1504 u16 score_board;
1505 u16 retry_limit;
1506
1507 /* counters to record bt states */
1508 u32 cnt_bt[COEX_CNT_BT_MAX];
1509
1510 /* counters to record wifi states */
1511 u32 cnt_wl[COEX_CNT_WL_MAX];
1512
1513 /* counters to record bt c2h data */
1514 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX];
1515
1516 u32 darfrc;
1517 u32 darfrch;
1518
1519 struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM];
1520 struct rtw_coex_hid_handle_list hid_handle_list;
1521 };
1522
1523 struct rtw_coex {
1524 struct sk_buff_head queue;
1525 wait_queue_head_t wait;
1526
1527 bool under_5g;
1528 bool stop_dm;
1529 bool freeze;
1530 bool freerun;
1531 bool wl_rf_off;
1532 bool manual_control;
1533
1534 struct rtw_coex_stat stat;
1535 struct rtw_coex_dm dm;
1536 struct rtw_coex_rfe rfe;
1537
1538 struct delayed_work bt_relink_work;
1539 struct delayed_work bt_reenable_work;
1540 struct delayed_work defreeze_work;
1541 struct delayed_work wl_remain_work;
1542 struct delayed_work bt_remain_work;
1543 struct delayed_work wl_connecting_work;
1544 struct delayed_work bt_multi_link_remain_work;
1545 struct delayed_work wl_ccklock_work;
1546
1547 };
1548
1549 #define DPK_RF_REG_NUM 7
1550 #define DPK_RF_PATH_NUM 2
1551 #define DPK_BB_REG_NUM 18
1552 #define DPK_CHANNEL_WIDTH_80 1
1553
1554 DECLARE_EWMA(thermal, 10, 4);
1555
1556 struct rtw_dpk_info {
1557 bool is_dpk_pwr_on;
1558 bool is_reload;
1559
1560 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM);
1561
1562 u8 thermal_dpk[DPK_RF_PATH_NUM];
1563 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM];
1564
1565 u32 gnt_control;
1566 u32 gnt_value;
1567
1568 u8 result[RTW_RF_PATH_MAX];
1569 u8 dpk_txagc[RTW_RF_PATH_MAX];
1570 u32 coef[RTW_RF_PATH_MAX][20];
1571 u16 dpk_gs[RTW_RF_PATH_MAX];
1572 u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
1573 u8 pre_pwsf[RTW_RF_PATH_MAX];
1574
1575 u8 dpk_band;
1576 u8 dpk_ch;
1577 u8 dpk_bw;
1578 };
1579
1580 struct rtw_phy_cck_pd_reg {
1581 u32 reg_pd;
1582 u32 mask_pd;
1583 u32 reg_cs;
1584 u32 mask_cs;
1585 };
1586
1587 #define DACK_MSBK_BACKUP_NUM 0xf
1588 #define DACK_DCK_BACKUP_NUM 0x2
1589
1590 struct rtw_swing_table {
1591 const u8 *p[RTW_RF_PATH_MAX];
1592 const u8 *n[RTW_RF_PATH_MAX];
1593 };
1594
1595 struct rtw_pkt_count {
1596 u16 num_bcn_pkt;
1597 u16 num_qry_pkt[DESC_RATE_MAX];
1598 };
1599
1600 DECLARE_EWMA(evm, 10, 4);
1601 DECLARE_EWMA(snr, 10, 4);
1602
1603 struct rtw_iqk_info {
1604 bool done;
1605 struct {
1606 u32 s1_x;
1607 u32 s1_y;
1608 u32 s0_x;
1609 u32 s0_y;
1610 } result;
1611 };
1612
1613 enum rtw_rf_band {
1614 RF_BAND_2G_CCK,
1615 RF_BAND_2G_OFDM,
1616 RF_BAND_5G_L,
1617 RF_BAND_5G_M,
1618 RF_BAND_5G_H,
1619 RF_BAND_MAX
1620 };
1621
1622 #define RF_GAIN_NUM 11
1623 #define RF_HW_OFFSET_NUM 10
1624
1625 struct rtw_gapk_info {
1626 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX];
1627 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM];
1628 bool txgapk_bp_done;
1629 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1630 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1631 u8 read_txgain;
1632 u8 channel;
1633 };
1634
1635 #define EDCCA_TH_L2H_IDX 0
1636 #define EDCCA_TH_H2L_IDX 1
1637 #define EDCCA_TH_L2H_LB 48
1638 #define EDCCA_ADC_BACKOFF 12
1639 #define EDCCA_IGI_BASE 50
1640 #define EDCCA_IGI_L2H_DIFF 8
1641 #define EDCCA_L2H_H2L_DIFF 7
1642 #define EDCCA_L2H_H2L_DIFF_NORMAL 8
1643
1644 enum rtw_edcca_mode {
1645 RTW_EDCCA_NORMAL = 0,
1646 RTW_EDCCA_ADAPTIVITY = 1,
1647 };
1648
1649 struct rtw_cfo_track {
1650 bool is_adjust;
1651 u8 crystal_cap;
1652 s32 cfo_tail[RTW_RF_PATH_MAX];
1653 s32 cfo_cnt[RTW_RF_PATH_MAX];
1654 u32 packet_count;
1655 u32 packet_count_pre;
1656 };
1657
1658 #define RRSR_INIT_2G 0x15f
1659 #define RRSR_INIT_5G 0x150
1660
1661 enum rtw_dm_cap {
1662 RTW_DM_CAP_NA,
1663 RTW_DM_CAP_TXGAPK,
1664 RTW_DM_CAP_NUM
1665 };
1666
1667 struct rtw_dm_info {
1668 u32 cck_fa_cnt;
1669 u32 ofdm_fa_cnt;
1670 u32 total_fa_cnt;
1671 u32 cck_cca_cnt;
1672 u32 ofdm_cca_cnt;
1673 u32 total_cca_cnt;
1674
1675 u32 cck_ok_cnt;
1676 u32 cck_err_cnt;
1677 u32 ofdm_ok_cnt;
1678 u32 ofdm_err_cnt;
1679 u32 ht_ok_cnt;
1680 u32 ht_err_cnt;
1681 u32 vht_ok_cnt;
1682 u32 vht_err_cnt;
1683
1684 u8 min_rssi;
1685 u8 pre_min_rssi;
1686 u16 fa_history[4];
1687 u8 igi_history[4];
1688 u8 igi_bitmap;
1689 bool damping;
1690 u8 damping_cnt;
1691 u8 damping_rssi;
1692
1693 u8 cck_gi_u_bnd;
1694 u8 cck_gi_l_bnd;
1695
1696 u8 fix_rate;
1697 u8 tx_rate;
1698 u32 rrsr_val_init;
1699 u32 rrsr_mask_min;
1700 u8 thermal_avg[RTW_RF_PATH_MAX];
1701 u8 thermal_meter_k;
1702 u8 thermal_meter_lck;
1703 s8 delta_power_index[RTW_RF_PATH_MAX];
1704 s8 delta_power_index_last[RTW_RF_PATH_MAX];
1705 u8 default_ofdm_index;
1706 u8 default_cck_index;
1707 bool pwr_trk_triggered;
1708 bool pwr_trk_init_trigger;
1709 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX];
1710 s8 txagc_remnant_cck;
1711 s8 txagc_remnant_ofdm;
1712 u8 rx_cck_agc_report_type;
1713
1714 /* backup dack results for each path and I/Q */
1715 u32 dack_adck[RTW_RF_PATH_MAX];
1716 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM];
1717 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
1718
1719 struct rtw_dpk_info dpk_info;
1720 struct rtw_cfo_track cfo_track;
1721
1722 /* [bandwidth 0:20M/1:40M][number of path] */
1723 u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
1724 u32 cck_fa_avg;
1725 u8 cck_pd_default;
1726
1727 /* save the last rx phy status for debug */
1728 s8 rx_snr[RTW_RF_PATH_MAX];
1729 u8 rx_evm_dbm[RTW_RF_PATH_MAX];
1730 s16 cfo_tail[RTW_RF_PATH_MAX];
1731 u8 rssi[RTW_RF_PATH_MAX];
1732 u8 curr_rx_rate;
1733 struct rtw_pkt_count cur_pkt_count;
1734 struct rtw_pkt_count last_pkt_count;
1735 struct ewma_evm ewma_evm[RTW_EVM_NUM];
1736 struct ewma_snr ewma_snr[RTW_SNR_NUM];
1737
1738 u32 dm_flags; /* enum rtw_dm_cap */
1739 struct rtw_iqk_info iqk;
1740 struct rtw_gapk_info gapk;
1741 bool is_bt_iqk_timeout;
1742
1743 s8 l2h_th_ini;
1744 enum rtw_edcca_mode edcca_mode;
1745 u8 scan_density;
1746 };
1747
1748 struct rtw_efuse {
1749 u32 size;
1750 u32 physical_size;
1751 u32 logical_size;
1752 u32 protect_size;
1753
1754 u8 addr[ETH_ALEN];
1755 u8 channel_plan;
1756 u8 country_code[2];
1757 u8 rf_board_option;
1758 u8 rfe_option;
1759 u8 power_track_type;
1760 u8 thermal_meter[RTW_RF_PATH_MAX];
1761 u8 thermal_meter_k;
1762 u8 crystal_cap;
1763 u8 ant_div_cfg;
1764 u8 ant_div_type;
1765 u8 regd;
1766 u8 afe;
1767
1768 u8 lna_type_2g;
1769 u8 lna_type_5g;
1770 u8 glna_type;
1771 u8 alna_type;
1772 bool ext_lna_2g;
1773 bool ext_lna_5g;
1774 u8 pa_type_2g;
1775 u8 pa_type_5g;
1776 u8 gpa_type;
1777 u8 apa_type;
1778 bool ext_pa_2g;
1779 bool ext_pa_5g;
1780 u8 tx_bb_swing_setting_2g;
1781 u8 tx_bb_swing_setting_5g;
1782
1783 bool btcoex;
1784 /* bt share antenna with wifi */
1785 bool share_ant;
1786 u8 bt_setting;
1787
1788 struct {
1789 u8 hci;
1790 u8 bw;
1791 u8 ptcl;
1792 u8 nss;
1793 u8 ant_num;
1794 } hw_cap;
1795
1796 struct rtw_txpwr_idx txpwr_idx_table[4];
1797 };
1798
1799 struct rtw_phy_cond {
1800 #ifdef __LITTLE_ENDIAN
1801 u32 rfe:8;
1802 u32 intf:4;
1803 u32 pkg:4;
1804 u32 plat:4;
1805 u32 intf_rsvd:4;
1806 u32 cut:4;
1807 u32 branch:2;
1808 u32 neg:1;
1809 u32 pos:1;
1810 #else
1811 u32 pos:1;
1812 u32 neg:1;
1813 u32 branch:2;
1814 u32 cut:4;
1815 u32 intf_rsvd:4;
1816 u32 plat:4;
1817 u32 pkg:4;
1818 u32 intf:4;
1819 u32 rfe:8;
1820 #endif
1821 /* for intf:4 */
1822 #define INTF_PCIE BIT(0)
1823 #define INTF_USB BIT(1)
1824 #define INTF_SDIO BIT(2)
1825 /* for branch:2 */
1826 #define BRANCH_IF 0
1827 #define BRANCH_ELIF 1
1828 #define BRANCH_ELSE 2
1829 #define BRANCH_ENDIF 3
1830 };
1831
1832 struct rtw_fifo_conf {
1833 /* tx fifo information */
1834 u16 rsvd_boundary;
1835 u16 rsvd_pg_num;
1836 u16 rsvd_drv_pg_num;
1837 u16 txff_pg_num;
1838 u16 acq_pg_num;
1839 u16 rsvd_drv_addr;
1840 u16 rsvd_h2c_info_addr;
1841 u16 rsvd_h2c_sta_info_addr;
1842 u16 rsvd_h2cq_addr;
1843 u16 rsvd_cpu_instr_addr;
1844 u16 rsvd_fw_txbuf_addr;
1845 u16 rsvd_csibuf_addr;
1846 const struct rtw_rqpn *rqpn;
1847 };
1848
1849 struct rtw_fwcd_desc {
1850 u32 size;
1851 u8 *next;
1852 u8 *data;
1853 };
1854
1855 struct rtw_fwcd_segs {
1856 const u32 *segs;
1857 u8 num;
1858 };
1859
1860 #define FW_CD_TYPE 0xffff
1861 #define FW_CD_LEN 4
1862 #define FW_CD_VAL 0xaabbccdd
1863 struct rtw_fw_state {
1864 const struct firmware *firmware;
1865 struct rtw_dev *rtwdev;
1866 struct completion completion;
1867 struct rtw_fwcd_desc fwcd_desc;
1868 u16 version;
1869 u8 sub_version;
1870 u8 sub_index;
1871 u16 h2c_version;
1872 u32 feature;
1873 u32 feature_ext;
1874 enum rtw_fw_type type;
1875 };
1876
1877 enum rtw_sar_sources {
1878 RTW_SAR_SOURCE_NONE,
1879 RTW_SAR_SOURCE_COMMON,
1880 };
1881
1882 enum rtw_sar_bands {
1883 RTW_SAR_BAND_0,
1884 RTW_SAR_BAND_1,
1885 /* RTW_SAR_BAND_2, not used now */
1886 RTW_SAR_BAND_3,
1887 RTW_SAR_BAND_4,
1888
1889 RTW_SAR_BAND_NR,
1890 };
1891
1892 /* the union is reserved for other kinds of SAR sources
1893 * which might not re-use same format with array common.
1894 */
1895 union rtw_sar_cfg {
1896 s8 common[RTW_SAR_BAND_NR];
1897 };
1898
1899 struct rtw_sar {
1900 enum rtw_sar_sources src;
1901 union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_MAX];
1902 };
1903
1904 struct rtw_hal {
1905 u32 rcr;
1906
1907 u32 chip_version;
1908 u8 cut_version;
1909 u8 mp_chip;
1910 u8 oem_id;
1911 u8 pkg_type;
1912 struct rtw_phy_cond phy_cond;
1913 bool rfe_btg;
1914
1915 u8 ps_mode;
1916 u8 current_channel;
1917 u8 current_primary_channel_index;
1918 u8 current_band_width;
1919 u8 current_band_type;
1920 u8 primary_channel;
1921
1922 /* center channel for different available bandwidth,
1923 * val of (bw > current_band_width) is invalid
1924 */
1925 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
1926
1927 u8 sec_ch_offset;
1928 u8 rf_type;
1929 u8 rf_path_num;
1930 u8 rf_phy_num;
1931 u32 antenna_tx;
1932 u32 antenna_rx;
1933 u8 bfee_sts_cap;
1934 bool txrx_1ss;
1935
1936 /* protect tx power section */
1937 struct mutex tx_power_mutex;
1938 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
1939 [DESC_RATE_MAX];
1940 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
1941 [DESC_RATE_MAX];
1942 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
1943 [RTW_RATE_SECTION_MAX];
1944 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
1945 [RTW_RATE_SECTION_MAX];
1946 s8 tx_pwr_limit_2g[RTW_REGD_MAX]
1947 [RTW_CHANNEL_WIDTH_MAX]
1948 [RTW_RATE_SECTION_MAX]
1949 [RTW_MAX_CHANNEL_NUM_2G];
1950 s8 tx_pwr_limit_5g[RTW_REGD_MAX]
1951 [RTW_CHANNEL_WIDTH_MAX]
1952 [RTW_RATE_SECTION_MAX]
1953 [RTW_MAX_CHANNEL_NUM_5G];
1954 s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
1955 [DESC_RATE_MAX];
1956
1957 enum rtw_sar_bands sar_band;
1958 struct rtw_sar sar;
1959
1960 /* for 8821c set channel */
1961 u32 ch_param[3];
1962 };
1963
1964 struct rtw_path_div {
1965 enum rtw_bb_path current_tx_path;
1966 u32 path_a_sum;
1967 u32 path_b_sum;
1968 u16 path_a_cnt;
1969 u16 path_b_cnt;
1970 };
1971
1972 struct rtw_chan_info {
1973 int pri_ch_idx;
1974 int action_id;
1975 int bw;
1976 u8 extra_info;
1977 u8 channel;
1978 u16 timeout;
1979 };
1980
1981 struct rtw_chan_list {
1982 u32 buf_size;
1983 u32 ch_num;
1984 u32 size;
1985 u16 addr;
1986 };
1987
1988 struct rtw_hw_scan_info {
1989 struct ieee80211_vif *scanning_vif;
1990 u8 probe_pg_size;
1991 u8 op_pri_ch_idx;
1992 u8 op_pri_ch;
1993 u8 op_chan;
1994 u8 op_bw;
1995 };
1996
1997 struct rtw_dev {
1998 struct ieee80211_hw *hw;
1999 struct device *dev;
2000
2001 struct rtw_hci hci;
2002
2003 struct rtw_hw_scan_info scan_info;
2004 const struct rtw_chip_info *chip;
2005 struct rtw_hal hal;
2006 struct rtw_fifo_conf fifo;
2007 struct rtw_fw_state fw;
2008 struct rtw_efuse efuse;
2009 struct rtw_sec_desc sec;
2010 struct rtw_traffic_stats stats;
2011 struct rtw_regd regd;
2012 struct rtw_bf_info bf_info;
2013
2014 struct rtw_dm_info dm_info;
2015 struct rtw_coex coex;
2016
2017 /* ensures exclusive access from mac80211 callbacks */
2018 struct mutex mutex;
2019
2020 /* watch dog every 2 sec */
2021 struct delayed_work watch_dog_work;
2022 u32 watch_dog_cnt;
2023
2024 struct list_head rsvd_page_list;
2025
2026 /* c2h cmd queue & handler work */
2027 struct sk_buff_head c2h_queue;
2028 struct work_struct c2h_work;
2029 struct work_struct ips_work;
2030 struct work_struct fw_recovery_work;
2031 struct work_struct update_beacon_work;
2032
2033 /* used to protect txqs list */
2034 spinlock_t txq_lock;
2035 struct list_head txqs;
2036 struct workqueue_struct *tx_wq;
2037 struct work_struct tx_work;
2038 struct work_struct ba_work;
2039
2040 struct rtw_tx_report tx_report;
2041
2042 struct {
2043 /* indicate the mail box to use with fw */
2044 u8 last_box_num;
2045 u32 seq;
2046 } h2c;
2047
2048 /* lps power state & handler work */
2049 struct rtw_lps_conf lps_conf;
2050 bool ps_enabled;
2051 bool beacon_loss;
2052 struct completion lps_leave_check;
2053
2054 struct dentry *debugfs;
2055
2056 u8 sta_cnt;
2057 u32 rts_threshold;
2058
2059 DECLARE_BITMAP(hw_port, RTW_PORT_NUM);
2060 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
2061 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
2062
2063 u8 mp_mode;
2064 struct rtw_path_div dm_path_div;
2065
2066 struct rtw_fw_state wow_fw;
2067 struct rtw_wow_param wow;
2068
2069 bool need_rfk;
2070 struct completion fw_scan_density;
2071 bool ap_active;
2072
2073 /* hci related data, must be last */
2074 u8 priv[] __aligned(sizeof(void *));
2075 };
2076
2077 #include "hci.h"
2078
rtw_is_assoc(struct rtw_dev * rtwdev)2079 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev)
2080 {
2081 return !!rtwdev->sta_cnt;
2082 }
2083
rtwtxq_to_txq(struct rtw_txq * rtwtxq)2084 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq)
2085 {
2086 void *p = rtwtxq;
2087
2088 return container_of(p, struct ieee80211_txq, drv_priv);
2089 }
2090
rtwvif_to_vif(struct rtw_vif * rtwvif)2091 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif)
2092 {
2093 void *p = rtwvif;
2094
2095 return container_of(p, struct ieee80211_vif, drv_priv);
2096 }
2097
rtw_chip_efuse_grant_on(struct rtw_dev * rtwdev)2098 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev)
2099 {
2100 if (rtwdev->chip->ops->efuse_grant)
2101 rtwdev->chip->ops->efuse_grant(rtwdev, true);
2102 }
2103
rtw_chip_efuse_grant_off(struct rtw_dev * rtwdev)2104 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev)
2105 {
2106 if (rtwdev->chip->ops->efuse_grant)
2107 rtwdev->chip->ops->efuse_grant(rtwdev, false);
2108 }
2109
rtw_chip_wcpu_11n(struct rtw_dev * rtwdev)2110 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev)
2111 {
2112 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N;
2113 }
2114
rtw_chip_wcpu_11ac(struct rtw_dev * rtwdev)2115 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev)
2116 {
2117 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC;
2118 }
2119
rtw_chip_has_rx_ldpc(struct rtw_dev * rtwdev)2120 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev)
2121 {
2122 return rtwdev->chip->rx_ldpc;
2123 }
2124
rtw_chip_has_tx_stbc(struct rtw_dev * rtwdev)2125 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev)
2126 {
2127 return rtwdev->chip->tx_stbc;
2128 }
2129
rtw_release_macid(struct rtw_dev * rtwdev,u8 mac_id)2130 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id)
2131 {
2132 clear_bit(mac_id, rtwdev->mac_id_map);
2133 }
2134
rtw_chip_dump_fw_crash(struct rtw_dev * rtwdev)2135 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev)
2136 {
2137 if (rtwdev->chip->ops->dump_fw_crash)
2138 return rtwdev->chip->ops->dump_fw_crash(rtwdev);
2139
2140 return 0;
2141 }
2142
2143 static inline
rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band)2144 enum nl80211_band rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band)
2145 {
2146 switch (hw_band) {
2147 default:
2148 case RTW_BAND_2G:
2149 return NL80211_BAND_2GHZ;
2150 case RTW_BAND_5G:
2151 return NL80211_BAND_5GHZ;
2152 case RTW_BAND_60G:
2153 return NL80211_BAND_60GHZ;
2154 }
2155 }
2156
2157 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel);
2158 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period);
2159 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
2160 struct rtw_channel_params *ch_param);
2161 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
2162 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
2163 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
2164 void rtw_restore_reg(struct rtw_dev *rtwdev,
2165 struct rtw_backup_info *bckp, u32 num);
2166 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss);
2167 void rtw_set_channel(struct rtw_dev *rtwdev);
2168 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev);
2169 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2170 u32 config);
2171 void rtw_tx_report_purge_timer(struct timer_list *t);
2172 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
2173 bool reset_ra_mask);
2174 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2175 const u8 *mac_addr, bool hw_scan);
2176 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
2177 bool hw_scan);
2178 int rtw_core_start(struct rtw_dev *rtwdev);
2179 void rtw_core_stop(struct rtw_dev *rtwdev);
2180 int rtw_chip_info_setup(struct rtw_dev *rtwdev);
2181 int rtw_core_init(struct rtw_dev *rtwdev);
2182 void rtw_core_deinit(struct rtw_dev *rtwdev);
2183 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2184 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2185 u16 rtw_desc_to_bitrate(u8 desc_rate);
2186 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
2187 struct ieee80211_bss_conf *conf);
2188 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2189 struct ieee80211_vif *vif);
2190 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2191 bool fw_exist);
2192 void rtw_fw_recovery(struct rtw_dev *rtwdev);
2193 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
2194 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
2195 u32 fwcd_item);
2196 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size);
2197 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss);
2198 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel,
2199 u8 primary_channel, enum rtw_supported_band band,
2200 enum rtw_bandwidth bandwidth);
2201 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif);
2202 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev);
2203 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable);
2204 #endif
2205