1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #ifndef __RTK_MAIN_H_
6 #define __RTK_MAIN_H_
7
8 #include <net/mac80211.h>
9 #include <linux/vmalloc.h>
10 #include <linux/firmware.h>
11 #include <linux/average.h>
12 #include <linux/bitops.h>
13 #include <linux/bitfield.h>
14 #include <linux/iopoll.h>
15 #include <linux/interrupt.h>
16 #include <linux/workqueue.h>
17 #if defined(__FreeBSD__)
18 #include <linux/kernel.h>
19 #include <linux/delay.h>
20 #include <linux/etherdevice.h>
21 #include <linux/rcupdate.h>
22 #include <linux/lockdep.h>
23 #include <linux/seq_file.h>
24 #endif
25
26 #include "util.h"
27
28 #define RTW_MAX_MAC_ID_NUM 32
29 #define RTW_MAX_SEC_CAM_NUM 32
30 #define MAX_PG_CAM_BACKUP_NUM 8
31
32 #define RTW_SCAN_MAX_SSIDS 4
33
34 #define RTW_MAX_PATTERN_NUM 12
35 #define RTW_MAX_PATTERN_MASK_SIZE 16
36 #define RTW_MAX_PATTERN_SIZE 128
37
38 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2)
39
40 #define RFREG_MASK 0xfffff
41 #define INV_RF_DATA 0xffffffff
42 #define TX_PAGE_SIZE_SHIFT 7
43 #define TX_PAGE_SIZE (1 << TX_PAGE_SIZE_SHIFT)
44
45 #define RTW_CHANNEL_WIDTH_MAX 3
46 #define RTW_RF_PATH_MAX 4
47 #define HW_FEATURE_LEN 13
48
49 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */
50
51 extern bool rtw_bf_support;
52 extern bool rtw_disable_lps_deep_mode;
53 extern unsigned int rtw_debug_mask;
54 extern bool rtw_edcca_enabled;
55 extern const struct ieee80211_ops rtw_ops;
56
57 #define RTW_MAX_CHANNEL_NUM_2G 14
58 #define RTW_MAX_CHANNEL_NUM_5G 49
59
60 struct rtw_dev;
61
62 enum rtw_hci_type {
63 RTW_HCI_TYPE_PCIE,
64 RTW_HCI_TYPE_USB,
65 RTW_HCI_TYPE_SDIO,
66
67 RTW_HCI_TYPE_UNDEFINE,
68 };
69
70 struct rtw_hci {
71 struct rtw_hci_ops *ops;
72 enum rtw_hci_type type;
73
74 u32 rpwm_addr;
75 u32 cpwm_addr;
76
77 u8 bulkout_num;
78 };
79
80 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48))
81 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64))
82 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144))
83 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177))
84
85 #define IS_CH_5G_BAND_MID(channel) \
86 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel))
87
88 #define IS_CH_2G_BAND(channel) ((channel) <= 14)
89 #define IS_CH_5G_BAND(channel) \
90 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \
91 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel))
92
93 enum rtw_supported_band {
94 RTW_BAND_2G = BIT(NL80211_BAND_2GHZ),
95 RTW_BAND_5G = BIT(NL80211_BAND_5GHZ),
96 RTW_BAND_60G = BIT(NL80211_BAND_60GHZ),
97 };
98
99 /* now, support up to 80M bw */
100 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
101
102 enum rtw_bandwidth {
103 RTW_CHANNEL_WIDTH_20 = 0,
104 RTW_CHANNEL_WIDTH_40 = 1,
105 RTW_CHANNEL_WIDTH_80 = 2,
106 RTW_CHANNEL_WIDTH_160 = 3,
107 RTW_CHANNEL_WIDTH_80_80 = 4,
108 RTW_CHANNEL_WIDTH_5 = 5,
109 RTW_CHANNEL_WIDTH_10 = 6,
110 };
111
112 enum rtw_sc_offset {
113 RTW_SC_DONT_CARE = 0,
114 RTW_SC_20_UPPER = 1,
115 RTW_SC_20_LOWER = 2,
116 RTW_SC_20_UPMOST = 3,
117 RTW_SC_20_LOWEST = 4,
118 RTW_SC_40_UPPER = 9,
119 RTW_SC_40_LOWER = 10,
120 };
121
122 enum rtw_net_type {
123 RTW_NET_NO_LINK = 0,
124 RTW_NET_AD_HOC = 1,
125 RTW_NET_MGD_LINKED = 2,
126 RTW_NET_AP_MODE = 3,
127 };
128
129 enum rtw_rf_type {
130 RF_1T1R = 0,
131 RF_1T2R = 1,
132 RF_2T2R = 2,
133 RF_2T3R = 3,
134 RF_2T4R = 4,
135 RF_3T3R = 5,
136 RF_3T4R = 6,
137 RF_4T4R = 7,
138 RF_TYPE_MAX,
139 };
140
141 enum rtw_rf_path {
142 RF_PATH_A = 0,
143 RF_PATH_B = 1,
144 RF_PATH_C = 2,
145 RF_PATH_D = 3,
146 };
147
148 enum rtw_bb_path {
149 BB_PATH_A = BIT(0),
150 BB_PATH_B = BIT(1),
151 BB_PATH_C = BIT(2),
152 BB_PATH_D = BIT(3),
153
154 BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
155 BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
156 BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
157 BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
158 BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
159 BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
160
161 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
162 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
163 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
164 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
165
166 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
167 };
168
169 enum rtw_rate_section {
170 RTW_RATE_SECTION_CCK = 0,
171 RTW_RATE_SECTION_OFDM,
172 RTW_RATE_SECTION_HT_1S,
173 RTW_RATE_SECTION_HT_2S,
174 RTW_RATE_SECTION_VHT_1S,
175 RTW_RATE_SECTION_VHT_2S,
176
177 /* keep last */
178 RTW_RATE_SECTION_MAX,
179 };
180
181 enum rtw_wireless_set {
182 WIRELESS_CCK = 0x00000001,
183 WIRELESS_OFDM = 0x00000002,
184 WIRELESS_HT = 0x00000004,
185 WIRELESS_VHT = 0x00000008,
186 };
187
188 #define HT_STBC_EN BIT(0)
189 #define VHT_STBC_EN BIT(1)
190 #define HT_LDPC_EN BIT(0)
191 #define VHT_LDPC_EN BIT(1)
192
193 enum rtw_chip_type {
194 RTW_CHIP_TYPE_8822B,
195 RTW_CHIP_TYPE_8822C,
196 RTW_CHIP_TYPE_8723D,
197 RTW_CHIP_TYPE_8821C,
198 };
199
200 enum rtw_tx_queue_type {
201 /* the order of AC queues matters */
202 RTW_TX_QUEUE_BK = 0x0,
203 RTW_TX_QUEUE_BE = 0x1,
204 RTW_TX_QUEUE_VI = 0x2,
205 RTW_TX_QUEUE_VO = 0x3,
206
207 RTW_TX_QUEUE_BCN = 0x4,
208 RTW_TX_QUEUE_MGMT = 0x5,
209 RTW_TX_QUEUE_HI0 = 0x6,
210 RTW_TX_QUEUE_H2C = 0x7,
211 /* keep it last */
212 RTK_MAX_TX_QUEUE_NUM
213 };
214
215 enum rtw_rx_queue_type {
216 RTW_RX_QUEUE_MPDU = 0x0,
217 RTW_RX_QUEUE_C2H = 0x1,
218 /* keep it last */
219 RTK_MAX_RX_QUEUE_NUM
220 };
221
222 enum rtw_fw_type {
223 RTW_NORMAL_FW = 0x0,
224 RTW_WOWLAN_FW = 0x1,
225 };
226
227 enum rtw_rate_index {
228 RTW_RATEID_BGN_40M_2SS = 0,
229 RTW_RATEID_BGN_40M_1SS = 1,
230 RTW_RATEID_BGN_20M_2SS = 2,
231 RTW_RATEID_BGN_20M_1SS = 3,
232 RTW_RATEID_GN_N2SS = 4,
233 RTW_RATEID_GN_N1SS = 5,
234 RTW_RATEID_BG = 6,
235 RTW_RATEID_G = 7,
236 RTW_RATEID_B_20M = 8,
237 RTW_RATEID_ARFR0_AC_2SS = 9,
238 RTW_RATEID_ARFR1_AC_1SS = 10,
239 RTW_RATEID_ARFR2_AC_2G_1SS = 11,
240 RTW_RATEID_ARFR3_AC_2G_2SS = 12,
241 RTW_RATEID_ARFR4_AC_3SS = 13,
242 RTW_RATEID_ARFR5_N_3SS = 14,
243 RTW_RATEID_ARFR7_N_4SS = 15,
244 RTW_RATEID_ARFR6_AC_4SS = 16
245 };
246
247 enum rtw_trx_desc_rate {
248 DESC_RATE1M = 0x00,
249 DESC_RATE2M = 0x01,
250 DESC_RATE5_5M = 0x02,
251 DESC_RATE11M = 0x03,
252
253 DESC_RATE6M = 0x04,
254 DESC_RATE9M = 0x05,
255 DESC_RATE12M = 0x06,
256 DESC_RATE18M = 0x07,
257 DESC_RATE24M = 0x08,
258 DESC_RATE36M = 0x09,
259 DESC_RATE48M = 0x0a,
260 DESC_RATE54M = 0x0b,
261
262 DESC_RATEMCS0 = 0x0c,
263 DESC_RATEMCS1 = 0x0d,
264 DESC_RATEMCS2 = 0x0e,
265 DESC_RATEMCS3 = 0x0f,
266 DESC_RATEMCS4 = 0x10,
267 DESC_RATEMCS5 = 0x11,
268 DESC_RATEMCS6 = 0x12,
269 DESC_RATEMCS7 = 0x13,
270 DESC_RATEMCS8 = 0x14,
271 DESC_RATEMCS9 = 0x15,
272 DESC_RATEMCS10 = 0x16,
273 DESC_RATEMCS11 = 0x17,
274 DESC_RATEMCS12 = 0x18,
275 DESC_RATEMCS13 = 0x19,
276 DESC_RATEMCS14 = 0x1a,
277 DESC_RATEMCS15 = 0x1b,
278 DESC_RATEMCS16 = 0x1c,
279 DESC_RATEMCS17 = 0x1d,
280 DESC_RATEMCS18 = 0x1e,
281 DESC_RATEMCS19 = 0x1f,
282 DESC_RATEMCS20 = 0x20,
283 DESC_RATEMCS21 = 0x21,
284 DESC_RATEMCS22 = 0x22,
285 DESC_RATEMCS23 = 0x23,
286 DESC_RATEMCS24 = 0x24,
287 DESC_RATEMCS25 = 0x25,
288 DESC_RATEMCS26 = 0x26,
289 DESC_RATEMCS27 = 0x27,
290 DESC_RATEMCS28 = 0x28,
291 DESC_RATEMCS29 = 0x29,
292 DESC_RATEMCS30 = 0x2a,
293 DESC_RATEMCS31 = 0x2b,
294
295 DESC_RATEVHT1SS_MCS0 = 0x2c,
296 DESC_RATEVHT1SS_MCS1 = 0x2d,
297 DESC_RATEVHT1SS_MCS2 = 0x2e,
298 DESC_RATEVHT1SS_MCS3 = 0x2f,
299 DESC_RATEVHT1SS_MCS4 = 0x30,
300 DESC_RATEVHT1SS_MCS5 = 0x31,
301 DESC_RATEVHT1SS_MCS6 = 0x32,
302 DESC_RATEVHT1SS_MCS7 = 0x33,
303 DESC_RATEVHT1SS_MCS8 = 0x34,
304 DESC_RATEVHT1SS_MCS9 = 0x35,
305
306 DESC_RATEVHT2SS_MCS0 = 0x36,
307 DESC_RATEVHT2SS_MCS1 = 0x37,
308 DESC_RATEVHT2SS_MCS2 = 0x38,
309 DESC_RATEVHT2SS_MCS3 = 0x39,
310 DESC_RATEVHT2SS_MCS4 = 0x3a,
311 DESC_RATEVHT2SS_MCS5 = 0x3b,
312 DESC_RATEVHT2SS_MCS6 = 0x3c,
313 DESC_RATEVHT2SS_MCS7 = 0x3d,
314 DESC_RATEVHT2SS_MCS8 = 0x3e,
315 DESC_RATEVHT2SS_MCS9 = 0x3f,
316
317 DESC_RATEVHT3SS_MCS0 = 0x40,
318 DESC_RATEVHT3SS_MCS1 = 0x41,
319 DESC_RATEVHT3SS_MCS2 = 0x42,
320 DESC_RATEVHT3SS_MCS3 = 0x43,
321 DESC_RATEVHT3SS_MCS4 = 0x44,
322 DESC_RATEVHT3SS_MCS5 = 0x45,
323 DESC_RATEVHT3SS_MCS6 = 0x46,
324 DESC_RATEVHT3SS_MCS7 = 0x47,
325 DESC_RATEVHT3SS_MCS8 = 0x48,
326 DESC_RATEVHT3SS_MCS9 = 0x49,
327
328 DESC_RATEVHT4SS_MCS0 = 0x4a,
329 DESC_RATEVHT4SS_MCS1 = 0x4b,
330 DESC_RATEVHT4SS_MCS2 = 0x4c,
331 DESC_RATEVHT4SS_MCS3 = 0x4d,
332 DESC_RATEVHT4SS_MCS4 = 0x4e,
333 DESC_RATEVHT4SS_MCS5 = 0x4f,
334 DESC_RATEVHT4SS_MCS6 = 0x50,
335 DESC_RATEVHT4SS_MCS7 = 0x51,
336 DESC_RATEVHT4SS_MCS8 = 0x52,
337 DESC_RATEVHT4SS_MCS9 = 0x53,
338
339 DESC_RATE_MAX,
340 };
341
342 enum rtw_regulatory_domains {
343 RTW_REGD_FCC = 0,
344 RTW_REGD_MKK = 1,
345 RTW_REGD_ETSI = 2,
346 RTW_REGD_IC = 3,
347 RTW_REGD_KCC = 4,
348 RTW_REGD_ACMA = 5,
349 RTW_REGD_CHILE = 6,
350 RTW_REGD_UKRAINE = 7,
351 RTW_REGD_MEXICO = 8,
352 RTW_REGD_CN = 9,
353 RTW_REGD_WW,
354
355 RTW_REGD_MAX
356 };
357
358 enum rtw_txq_flags {
359 RTW_TXQ_AMPDU,
360 RTW_TXQ_BLOCK_BA,
361 };
362
363 enum rtw_flags {
364 RTW_FLAG_RUNNING,
365 RTW_FLAG_FW_RUNNING,
366 RTW_FLAG_SCANNING,
367 RTW_FLAG_POWERON,
368 RTW_FLAG_LEISURE_PS,
369 RTW_FLAG_LEISURE_PS_DEEP,
370 RTW_FLAG_DIG_DISABLE,
371 RTW_FLAG_BUSY_TRAFFIC,
372 RTW_FLAG_WOWLAN,
373 RTW_FLAG_RESTARTING,
374 RTW_FLAG_RESTART_TRIGGERING,
375 RTW_FLAG_FORCE_LOWEST_RATE,
376
377 NUM_OF_RTW_FLAGS,
378 };
379
380 enum rtw_evm {
381 RTW_EVM_OFDM = 0,
382 RTW_EVM_1SS,
383 RTW_EVM_2SS_A,
384 RTW_EVM_2SS_B,
385 /* keep it last */
386 RTW_EVM_NUM
387 };
388
389 enum rtw_snr {
390 RTW_SNR_OFDM_A = 0,
391 RTW_SNR_OFDM_B,
392 RTW_SNR_OFDM_C,
393 RTW_SNR_OFDM_D,
394 RTW_SNR_1SS_A,
395 RTW_SNR_1SS_B,
396 RTW_SNR_1SS_C,
397 RTW_SNR_1SS_D,
398 RTW_SNR_2SS_A,
399 RTW_SNR_2SS_B,
400 RTW_SNR_2SS_C,
401 RTW_SNR_2SS_D,
402 /* keep it last */
403 RTW_SNR_NUM
404 };
405
406 enum rtw_port {
407 RTW_PORT_0 = 0,
408 RTW_PORT_1 = 1,
409 RTW_PORT_2 = 2,
410 RTW_PORT_3 = 3,
411 RTW_PORT_4 = 4,
412 RTW_PORT_NUM
413 };
414
415 enum rtw_wow_flags {
416 RTW_WOW_FLAG_EN_MAGIC_PKT,
417 RTW_WOW_FLAG_EN_REKEY_PKT,
418 RTW_WOW_FLAG_EN_DISCONNECT,
419
420 /* keep it last */
421 RTW_WOW_FLAG_MAX,
422 };
423
424 /* the power index is represented by differences, which cck-1s & ht40-1s are
425 * the base values, so for 1s's differences, there are only ht20 & ofdm
426 */
427 struct rtw_2g_1s_pwr_idx_diff {
428 #ifdef __LITTLE_ENDIAN
429 s8 ofdm:4;
430 s8 bw20:4;
431 #else
432 s8 bw20:4;
433 s8 ofdm:4;
434 #endif
435 } __packed;
436
437 struct rtw_2g_ns_pwr_idx_diff {
438 #ifdef __LITTLE_ENDIAN
439 s8 bw20:4;
440 s8 bw40:4;
441 s8 cck:4;
442 s8 ofdm:4;
443 #else
444 s8 ofdm:4;
445 s8 cck:4;
446 s8 bw40:4;
447 s8 bw20:4;
448 #endif
449 } __packed;
450
451 struct rtw_2g_txpwr_idx {
452 u8 cck_base[6];
453 u8 bw40_base[5];
454 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
455 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
456 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
457 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
458 };
459
460 struct rtw_5g_ht_1s_pwr_idx_diff {
461 #ifdef __LITTLE_ENDIAN
462 s8 ofdm:4;
463 s8 bw20:4;
464 #else
465 s8 bw20:4;
466 s8 ofdm:4;
467 #endif
468 } __packed;
469
470 struct rtw_5g_ht_ns_pwr_idx_diff {
471 #ifdef __LITTLE_ENDIAN
472 s8 bw20:4;
473 s8 bw40:4;
474 #else
475 s8 bw40:4;
476 s8 bw20:4;
477 #endif
478 } __packed;
479
480 struct rtw_5g_ofdm_ns_pwr_idx_diff {
481 #ifdef __LITTLE_ENDIAN
482 s8 ofdm_3s:4;
483 s8 ofdm_2s:4;
484 s8 ofdm_4s:4;
485 s8 res:4;
486 #else
487 s8 res:4;
488 s8 ofdm_4s:4;
489 s8 ofdm_2s:4;
490 s8 ofdm_3s:4;
491 #endif
492 } __packed;
493
494 struct rtw_5g_vht_ns_pwr_idx_diff {
495 #ifdef __LITTLE_ENDIAN
496 s8 bw160:4;
497 s8 bw80:4;
498 #else
499 s8 bw80:4;
500 s8 bw160:4;
501 #endif
502 } __packed;
503
504 struct rtw_5g_txpwr_idx {
505 u8 bw40_base[14];
506 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
507 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
508 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
509 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
510 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
511 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
512 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
513 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
514 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
515 };
516
517 struct rtw_txpwr_idx {
518 struct rtw_2g_txpwr_idx pwr_idx_2g;
519 struct rtw_5g_txpwr_idx pwr_idx_5g;
520 };
521
522 struct rtw_channel_params {
523 u8 center_chan;
524 u8 primary_chan;
525 u8 bandwidth;
526 };
527
528 struct rtw_hw_reg {
529 u32 addr;
530 u32 mask;
531 };
532
533 struct rtw_ltecoex_addr {
534 u32 ctrl;
535 u32 wdata;
536 u32 rdata;
537 };
538
539 struct rtw_reg_domain {
540 u32 addr;
541 u32 mask;
542 #define RTW_REG_DOMAIN_MAC32 0
543 #define RTW_REG_DOMAIN_MAC16 1
544 #define RTW_REG_DOMAIN_MAC8 2
545 #define RTW_REG_DOMAIN_RF_A 3
546 #define RTW_REG_DOMAIN_RF_B 4
547 #define RTW_REG_DOMAIN_NL 0xFF
548 u8 domain;
549 };
550
551 struct rtw_rf_sipi_addr {
552 u32 hssi_1;
553 u32 hssi_2;
554 u32 lssi_read;
555 u32 lssi_read_pi;
556 };
557
558 struct rtw_hw_reg_offset {
559 struct rtw_hw_reg hw_reg;
560 u8 offset;
561 };
562
563 struct rtw_backup_info {
564 u8 len;
565 u32 reg;
566 u32 val;
567 };
568
569 enum rtw_vif_port_set {
570 PORT_SET_MAC_ADDR = BIT(0),
571 PORT_SET_BSSID = BIT(1),
572 PORT_SET_NET_TYPE = BIT(2),
573 PORT_SET_AID = BIT(3),
574 PORT_SET_BCN_CTRL = BIT(4),
575 };
576
577 struct rtw_vif_port {
578 struct rtw_hw_reg mac_addr;
579 struct rtw_hw_reg bssid;
580 struct rtw_hw_reg net_type;
581 struct rtw_hw_reg aid;
582 struct rtw_hw_reg bcn_ctrl;
583 };
584
585 struct rtw_tx_pkt_info {
586 u32 tx_pkt_size;
587 u8 offset;
588 u8 pkt_offset;
589 u8 tim_offset;
590 u8 mac_id;
591 u8 rate_id;
592 u8 rate;
593 u8 qsel;
594 u8 bw;
595 u8 sec_type;
596 u8 sn;
597 bool ampdu_en;
598 u8 ampdu_factor;
599 u8 ampdu_density;
600 u16 seq;
601 bool stbc;
602 bool ldpc;
603 bool dis_rate_fallback;
604 bool bmc;
605 bool use_rate;
606 bool ls;
607 bool fs;
608 bool short_gi;
609 bool report;
610 bool rts;
611 bool dis_qselseq;
612 bool en_hwseq;
613 u8 hw_ssn_sel;
614 bool nav_use_hdr;
615 bool bt_null;
616 };
617
618 struct rtw_rx_pkt_stat {
619 bool phy_status;
620 bool icv_err;
621 bool crc_err;
622 bool decrypted;
623 bool is_c2h;
624
625 s32 signal_power;
626 u16 pkt_len;
627 u8 bw;
628 u8 drv_info_sz;
629 u8 shift;
630 u8 rate;
631 u8 mac_id;
632 u8 cam_id;
633 u8 ppdu_cnt;
634 u32 tsf_low;
635 s8 rx_power[RTW_RF_PATH_MAX];
636 u8 rssi;
637 u8 rxsc;
638 s8 rx_snr[RTW_RF_PATH_MAX];
639 u8 rx_evm[RTW_RF_PATH_MAX];
640 s8 cfo_tail[RTW_RF_PATH_MAX];
641 u16 freq;
642 u8 band;
643
644 struct rtw_sta_info *si;
645 struct ieee80211_vif *vif;
646 struct ieee80211_hdr *hdr;
647 };
648
649 DECLARE_EWMA(tp, 10, 2);
650
651 struct rtw_traffic_stats {
652 /* units in bytes */
653 u64 tx_unicast;
654 u64 rx_unicast;
655
656 /* count for packets */
657 u64 tx_cnt;
658 u64 rx_cnt;
659
660 /* units in Mbps */
661 u32 tx_throughput;
662 u32 rx_throughput;
663 struct ewma_tp tx_ewma_tp;
664 struct ewma_tp rx_ewma_tp;
665 };
666
667 enum rtw_lps_mode {
668 RTW_MODE_ACTIVE = 0,
669 RTW_MODE_LPS = 1,
670 RTW_MODE_WMM_PS = 2,
671 };
672
673 enum rtw_lps_deep_mode {
674 LPS_DEEP_MODE_NONE = 0,
675 LPS_DEEP_MODE_LCLK = 1,
676 LPS_DEEP_MODE_PG = 2,
677 };
678
679 enum rtw_pwr_state {
680 RTW_RF_OFF = 0x0,
681 RTW_RF_ON = 0x4,
682 RTW_ALL_ON = 0xc,
683 };
684
685 struct rtw_lps_conf {
686 enum rtw_lps_mode mode;
687 enum rtw_lps_deep_mode deep_mode;
688 enum rtw_lps_deep_mode wow_deep_mode;
689 enum rtw_pwr_state state;
690 u8 awake_interval;
691 u8 rlbm;
692 u8 smart_ps;
693 u8 port_id;
694 bool sec_cam_backup;
695 bool pattern_cam_backup;
696 };
697
698 enum rtw_hw_key_type {
699 RTW_CAM_NONE = 0,
700 RTW_CAM_WEP40 = 1,
701 RTW_CAM_TKIP = 2,
702 RTW_CAM_AES = 4,
703 RTW_CAM_WEP104 = 5,
704 };
705
706 struct rtw_cam_entry {
707 bool valid;
708 bool group;
709 u8 addr[ETH_ALEN];
710 u8 hw_key_type;
711 struct ieee80211_key_conf *key;
712 };
713
714 struct rtw_sec_desc {
715 /* search strategy */
716 bool default_key_search;
717
718 u32 total_cam_num;
719 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
720 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
721 };
722
723 struct rtw_tx_report {
724 /* protect the tx report queue */
725 spinlock_t q_lock;
726 struct sk_buff_head queue;
727 atomic_t sn;
728 struct timer_list purge_timer;
729 };
730
731 struct rtw_ra_report {
732 struct rate_info txrate;
733 u32 bit_rate;
734 u8 desc_rate;
735 };
736
737 struct rtw_txq {
738 struct list_head list;
739 unsigned long flags;
740 };
741
742 #define RTW_BC_MC_MACID 1
743 DECLARE_EWMA(rssi, 10, 16);
744
745 struct rtw_sta_info {
746 struct rtw_dev *rtwdev;
747 struct ieee80211_sta *sta;
748 struct ieee80211_vif *vif;
749
750 struct ewma_rssi avg_rssi;
751 u8 rssi_level;
752
753 u8 mac_id;
754 u8 rate_id;
755 enum rtw_bandwidth bw_mode;
756 enum rtw_rf_type rf_type;
757 u8 stbc_en:2;
758 u8 ldpc_en:2;
759 bool sgi_enable;
760 bool vht_enable;
761 u8 init_ra_lv;
762 u64 ra_mask;
763
764 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS);
765
766 struct rtw_ra_report ra_report;
767
768 bool use_cfg_mask;
769 struct cfg80211_bitrate_mask *mask;
770
771 struct work_struct rc_work;
772 };
773
774 enum rtw_bfee_role {
775 RTW_BFEE_NONE,
776 RTW_BFEE_SU,
777 RTW_BFEE_MU
778 };
779
780 struct rtw_bfee {
781 enum rtw_bfee_role role;
782
783 u16 p_aid;
784 u8 g_id;
785 u8 mac_addr[ETH_ALEN];
786 u8 sound_dim;
787
788 /* SU-MIMO */
789 u8 su_reg_index;
790
791 /* MU-MIMO */
792 u16 aid;
793 };
794
795 struct rtw_bf_info {
796 u8 bfer_mu_cnt;
797 u8 bfer_su_cnt;
798 DECLARE_BITMAP(bfer_su_reg_maping, 2);
799 u8 cur_csi_rpt_rate;
800 };
801
802 struct rtw_vif {
803 enum rtw_net_type net_type;
804 u16 aid;
805 u8 mac_id; /* for STA mode only */
806 u8 mac_addr[ETH_ALEN];
807 u8 bssid[ETH_ALEN];
808 u8 port;
809 u8 bcn_ctrl;
810 struct list_head rsvd_page_list;
811 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
812 const struct rtw_vif_port *conf;
813 struct cfg80211_scan_request *scan_req;
814 struct ieee80211_scan_ies *scan_ies;
815
816 struct rtw_traffic_stats stats;
817
818 struct rtw_bfee bfee;
819 };
820
821 struct rtw_regulatory {
822 char alpha2[2];
823 u8 txpwr_regd_2g;
824 u8 txpwr_regd_5g;
825 };
826
827 enum rtw_regd_state {
828 RTW_REGD_STATE_WORLDWIDE,
829 RTW_REGD_STATE_PROGRAMMED,
830 RTW_REGD_STATE_SETTING,
831
832 RTW_REGD_STATE_NR,
833 };
834
835 struct rtw_regd {
836 enum rtw_regd_state state;
837 const struct rtw_regulatory *regulatory;
838 enum nl80211_dfs_regions dfs_region;
839 };
840
841 struct rtw_chip_ops {
842 int (*mac_init)(struct rtw_dev *rtwdev);
843 int (*dump_fw_crash)(struct rtw_dev *rtwdev);
844 void (*shutdown)(struct rtw_dev *rtwdev);
845 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
846 void (*phy_set_param)(struct rtw_dev *rtwdev);
847 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
848 u8 bandwidth, u8 primary_chan_idx);
849 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc,
850 struct rtw_rx_pkt_stat *pkt_stat,
851 struct ieee80211_rx_status *rx_status);
852 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
853 u32 addr, u32 mask);
854 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
855 u32 addr, u32 mask, u32 data);
856 void (*set_tx_power_index)(struct rtw_dev *rtwdev);
857 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
858 u32 size);
859 int (*set_antenna)(struct rtw_dev *rtwdev,
860 u32 antenna_tx,
861 u32 antenna_rx);
862 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
863 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable);
864 void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
865 void (*phy_calibration)(struct rtw_dev *rtwdev);
866 void (*dpk_track)(struct rtw_dev *rtwdev);
867 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
868 void (*pwr_track)(struct rtw_dev *rtwdev);
869 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif,
870 struct rtw_bfee *bfee, bool enable);
871 void (*set_gid_table)(struct rtw_dev *rtwdev,
872 struct ieee80211_vif *vif,
873 struct ieee80211_bss_conf *conf);
874 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
875 u8 fixrate_en, u8 *new_rate);
876 void (*adaptivity_init)(struct rtw_dev *rtwdev);
877 void (*adaptivity)(struct rtw_dev *rtwdev);
878 void (*cfo_init)(struct rtw_dev *rtwdev);
879 void (*cfo_track)(struct rtw_dev *rtwdev);
880 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path,
881 enum rtw_bb_path tx_path_1ss,
882 enum rtw_bb_path tx_path_cck,
883 bool is_tx2_path);
884 void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path,
885 u8 rx_path, bool is_tx2_path);
886 /* for USB/SDIO only */
887 void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev,
888 struct rtw_tx_pkt_info *pkt_info,
889 u8 *txdesc);
890
891 /* for coex */
892 void (*coex_set_init)(struct rtw_dev *rtwdev);
893 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
894 u8 ctrl_type, u8 pos_type);
895 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
896 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
897 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
898 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
899 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
900 };
901
902 #define RTW_PWR_POLLING_CNT 20000
903
904 #define RTW_PWR_CMD_READ 0x00
905 #define RTW_PWR_CMD_WRITE 0x01
906 #define RTW_PWR_CMD_POLLING 0x02
907 #define RTW_PWR_CMD_DELAY 0x03
908 #define RTW_PWR_CMD_END 0x04
909
910 /* define the base address of each block */
911 #define RTW_PWR_ADDR_MAC 0x00
912 #define RTW_PWR_ADDR_USB 0x01
913 #define RTW_PWR_ADDR_PCIE 0x02
914 #define RTW_PWR_ADDR_SDIO 0x03
915
916 #define RTW_PWR_INTF_SDIO_MSK BIT(0)
917 #define RTW_PWR_INTF_USB_MSK BIT(1)
918 #define RTW_PWR_INTF_PCI_MSK BIT(2)
919 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
920
921 #define RTW_PWR_CUT_TEST_MSK BIT(0)
922 #define RTW_PWR_CUT_A_MSK BIT(1)
923 #define RTW_PWR_CUT_B_MSK BIT(2)
924 #define RTW_PWR_CUT_C_MSK BIT(3)
925 #define RTW_PWR_CUT_D_MSK BIT(4)
926 #define RTW_PWR_CUT_E_MSK BIT(5)
927 #define RTW_PWR_CUT_F_MSK BIT(6)
928 #define RTW_PWR_CUT_G_MSK BIT(7)
929 #define RTW_PWR_CUT_ALL_MSK 0xFF
930
931 enum rtw_pwr_seq_cmd_delay_unit {
932 RTW_PWR_DELAY_US,
933 RTW_PWR_DELAY_MS,
934 };
935
936 struct rtw_pwr_seq_cmd {
937 u16 offset;
938 u8 cut_mask;
939 u8 intf_mask;
940 u8 base:4;
941 u8 cmd:4;
942 u8 mask;
943 u8 value;
944 };
945
946 enum rtw_chip_ver {
947 RTW_CHIP_VER_CUT_A = 0x00,
948 RTW_CHIP_VER_CUT_B = 0x01,
949 RTW_CHIP_VER_CUT_C = 0x02,
950 RTW_CHIP_VER_CUT_D = 0x03,
951 RTW_CHIP_VER_CUT_E = 0x04,
952 RTW_CHIP_VER_CUT_F = 0x05,
953 RTW_CHIP_VER_CUT_G = 0x06,
954 };
955
956 #define RTW_INTF_PHY_PLATFORM_ALL 0
957
958 enum rtw_intf_phy_cut {
959 RTW_INTF_PHY_CUT_A = BIT(0),
960 RTW_INTF_PHY_CUT_B = BIT(1),
961 RTW_INTF_PHY_CUT_C = BIT(2),
962 RTW_INTF_PHY_CUT_D = BIT(3),
963 RTW_INTF_PHY_CUT_E = BIT(4),
964 RTW_INTF_PHY_CUT_F = BIT(5),
965 RTW_INTF_PHY_CUT_G = BIT(6),
966 RTW_INTF_PHY_CUT_ALL = 0xFFFF,
967 };
968
969 enum rtw_ip_sel {
970 RTW_IP_SEL_PHY = 0,
971 RTW_IP_SEL_MAC = 1,
972 RTW_IP_SEL_DBI = 2,
973
974 RTW_IP_SEL_UNDEF = 0xFFFF
975 };
976
977 enum rtw_pq_map_id {
978 RTW_PQ_MAP_VO = 0x0,
979 RTW_PQ_MAP_VI = 0x1,
980 RTW_PQ_MAP_BE = 0x2,
981 RTW_PQ_MAP_BK = 0x3,
982 RTW_PQ_MAP_MG = 0x4,
983 RTW_PQ_MAP_HI = 0x5,
984 RTW_PQ_MAP_NUM = 0x6,
985
986 RTW_PQ_MAP_UNDEF,
987 };
988
989 enum rtw_dma_mapping {
990 RTW_DMA_MAPPING_EXTRA = 0,
991 RTW_DMA_MAPPING_LOW = 1,
992 RTW_DMA_MAPPING_NORMAL = 2,
993 RTW_DMA_MAPPING_HIGH = 3,
994
995 RTW_DMA_MAPPING_MAX,
996 RTW_DMA_MAPPING_UNDEF,
997 };
998
999 struct rtw_rqpn {
1000 enum rtw_dma_mapping dma_map_vo;
1001 enum rtw_dma_mapping dma_map_vi;
1002 enum rtw_dma_mapping dma_map_be;
1003 enum rtw_dma_mapping dma_map_bk;
1004 enum rtw_dma_mapping dma_map_mg;
1005 enum rtw_dma_mapping dma_map_hi;
1006 };
1007
1008 struct rtw_prioq_addr {
1009 u32 rsvd;
1010 u32 avail;
1011 };
1012
1013 struct rtw_prioq_addrs {
1014 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX];
1015 bool wsize;
1016 };
1017
1018 struct rtw_page_table {
1019 u16 hq_num;
1020 u16 nq_num;
1021 u16 lq_num;
1022 u16 exq_num;
1023 u16 gapq_num;
1024 };
1025
1026 struct rtw_intf_phy_para {
1027 u16 offset;
1028 u16 value;
1029 u16 ip_sel;
1030 u16 cut_mask;
1031 u16 platform;
1032 };
1033
1034 struct rtw_wow_pattern {
1035 u16 crc;
1036 u8 type;
1037 u8 valid;
1038 u8 mask[RTW_MAX_PATTERN_MASK_SIZE];
1039 };
1040
1041 struct rtw_pno_request {
1042 bool inited;
1043 u32 match_set_cnt;
1044 struct cfg80211_match_set *match_sets;
1045 u8 channel_cnt;
1046 struct ieee80211_channel *channels;
1047 struct cfg80211_sched_scan_plan scan_plan;
1048 };
1049
1050 struct rtw_wow_param {
1051 struct ieee80211_vif *wow_vif;
1052 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX);
1053 u8 txpause;
1054 u8 pattern_cnt;
1055 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM];
1056
1057 bool ips_enabled;
1058 struct rtw_pno_request pno_req;
1059 };
1060
1061 struct rtw_intf_phy_para_table {
1062 const struct rtw_intf_phy_para *usb2_para;
1063 const struct rtw_intf_phy_para *usb3_para;
1064 const struct rtw_intf_phy_para *gen1_para;
1065 const struct rtw_intf_phy_para *gen2_para;
1066 u8 n_usb2_para;
1067 u8 n_usb3_para;
1068 u8 n_gen1_para;
1069 u8 n_gen2_para;
1070 };
1071
1072 struct rtw_table {
1073 const void *data;
1074 const u32 size;
1075 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
1076 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1077 u32 addr, u32 data);
1078 enum rtw_rf_path rf_path;
1079 };
1080
rtw_load_table(struct rtw_dev * rtwdev,const struct rtw_table * tbl)1081 static inline void rtw_load_table(struct rtw_dev *rtwdev,
1082 const struct rtw_table *tbl)
1083 {
1084 (*tbl->parse)(rtwdev, tbl);
1085 }
1086
1087 enum rtw_rfe_fem {
1088 RTW_RFE_IFEM,
1089 RTW_RFE_EFEM,
1090 RTW_RFE_IFEM2G_EFEM5G,
1091 RTW_RFE_NUM,
1092 };
1093
1094 struct rtw_rfe_def {
1095 const struct rtw_table *phy_pg_tbl;
1096 const struct rtw_table *txpwr_lmt_tbl;
1097 const struct rtw_table *agc_btg_tbl;
1098 };
1099
1100 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \
1101 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1102 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1103 }
1104
1105 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) { \
1106 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1107 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1108 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \
1109 }
1110
1111 #define RTW_PWR_TRK_5G_1 0
1112 #define RTW_PWR_TRK_5G_2 1
1113 #define RTW_PWR_TRK_5G_3 2
1114 #define RTW_PWR_TRK_5G_NUM 3
1115
1116 #define RTW_PWR_TRK_TBL_SZ 30
1117
1118 /* This table stores the values of TX power that will be adjusted by power
1119 * tracking.
1120 *
1121 * For 5G bands, there are 3 different settings.
1122 * For 2G there are cck rate and ofdm rate with different settings.
1123 */
1124 struct rtw_pwr_track_tbl {
1125 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM];
1126 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM];
1127 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM];
1128 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM];
1129 const u8 *pwrtrk_2gb_n;
1130 const u8 *pwrtrk_2gb_p;
1131 const u8 *pwrtrk_2ga_n;
1132 const u8 *pwrtrk_2ga_p;
1133 const u8 *pwrtrk_2g_cckb_n;
1134 const u8 *pwrtrk_2g_cckb_p;
1135 const u8 *pwrtrk_2g_ccka_n;
1136 const u8 *pwrtrk_2g_ccka_p;
1137 const s8 *pwrtrk_xtal_n;
1138 const s8 *pwrtrk_xtal_p;
1139 };
1140
1141 enum rtw_wlan_cpu {
1142 RTW_WCPU_11AC,
1143 RTW_WCPU_11N,
1144 };
1145
1146 enum rtw_fw_fifo_sel {
1147 RTW_FW_FIFO_SEL_TX,
1148 RTW_FW_FIFO_SEL_RX,
1149 RTW_FW_FIFO_SEL_RSVD_PAGE,
1150 RTW_FW_FIFO_SEL_REPORT,
1151 RTW_FW_FIFO_SEL_LLT,
1152 RTW_FW_FIFO_SEL_RXBUF_FW,
1153
1154 RTW_FW_FIFO_MAX,
1155 };
1156
1157 enum rtw_fwcd_item {
1158 RTW_FWCD_TLV,
1159 RTW_FWCD_REG,
1160 RTW_FWCD_ROM,
1161 RTW_FWCD_IMEM,
1162 RTW_FWCD_DMEM,
1163 RTW_FWCD_EMEM,
1164 };
1165
1166 /* hardware configuration for each IC */
1167 struct rtw_chip_info {
1168 struct rtw_chip_ops *ops;
1169 u8 id;
1170
1171 const char *fw_name;
1172 enum rtw_wlan_cpu wlan_cpu;
1173 u8 tx_pkt_desc_sz;
1174 u8 tx_buf_desc_sz;
1175 u8 rx_pkt_desc_sz;
1176 u8 rx_buf_desc_sz;
1177 u32 phy_efuse_size;
1178 u32 log_efuse_size;
1179 u32 ptct_efuse_size;
1180 u32 txff_size;
1181 u32 rxff_size;
1182 u32 fw_rxff_size;
1183 u16 rsvd_drv_pg_num;
1184 u8 band;
1185 u8 page_size;
1186 u8 csi_buf_pg_num;
1187 u8 dig_max;
1188 u8 dig_min;
1189 u8 txgi_factor;
1190 bool is_pwr_by_rate_dec;
1191 bool rx_ldpc;
1192 bool tx_stbc;
1193 u8 max_power_index;
1194 u8 ampdu_density;
1195
1196 u16 fw_fifo_addr[RTW_FW_FIFO_MAX];
1197 const struct rtw_fwcd_segs *fwcd_segs;
1198
1199 u8 default_1ss_tx_path;
1200
1201 bool path_div_supported;
1202 bool ht_supported;
1203 bool vht_supported;
1204 u8 lps_deep_mode_supported;
1205
1206 /* init values */
1207 u8 sys_func_en;
1208 const struct rtw_pwr_seq_cmd **pwr_on_seq;
1209 const struct rtw_pwr_seq_cmd **pwr_off_seq;
1210 const struct rtw_rqpn *rqpn_table;
1211 const struct rtw_prioq_addrs *prioq_addrs;
1212 const struct rtw_page_table *page_table;
1213 const struct rtw_intf_phy_para_table *intf_table;
1214
1215 const struct rtw_hw_reg *dig;
1216 const struct rtw_hw_reg *dig_cck;
1217 u32 rf_base_addr[2];
1218 u32 rf_sipi_addr[2];
1219 const struct rtw_rf_sipi_addr *rf_sipi_read_addr;
1220 u8 fix_rf_phy_num;
1221 const struct rtw_ltecoex_addr *ltecoex_addr;
1222
1223 const struct rtw_table *mac_tbl;
1224 const struct rtw_table *agc_tbl;
1225 const struct rtw_table *bb_tbl;
1226 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
1227 const struct rtw_table *rfk_init_tbl;
1228
1229 const struct rtw_rfe_def *rfe_defs;
1230 u32 rfe_defs_size;
1231
1232 bool en_dis_dpd;
1233 u16 dpd_ratemask;
1234 u8 iqk_threshold;
1235 u8 lck_threshold;
1236 const struct rtw_pwr_track_tbl *pwr_track_tbl;
1237
1238 u8 bfer_su_max_num;
1239 u8 bfer_mu_max_num;
1240
1241 struct rtw_hw_reg_offset *edcca_th;
1242 s8 l2h_th_ini_cs;
1243 s8 l2h_th_ini_ad;
1244
1245 const char *wow_fw_name;
1246 const struct wiphy_wowlan_support *wowlan_stub;
1247 const u8 max_sched_scan_ssids;
1248 const u16 max_scan_ie_len;
1249
1250 /* coex paras */
1251 u32 coex_para_ver;
1252 u8 bt_desired_ver;
1253 bool scbd_support;
1254 bool new_scbd10_def; /* true: fix 2M(8822c) */
1255 bool ble_hid_profile_support;
1256 bool wl_mimo_ps_support;
1257 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
1258 u8 bt_rssi_type;
1259 u8 ant_isolation;
1260 u8 rssi_tolerance;
1261 u8 table_sant_num;
1262 u8 table_nsant_num;
1263 u8 tdma_sant_num;
1264 u8 tdma_nsant_num;
1265 u8 bt_afh_span_bw20;
1266 u8 bt_afh_span_bw40;
1267 u8 afh_5g_num;
1268 u8 wl_rf_para_num;
1269 u8 coex_info_hw_regs_num;
1270 const u8 *bt_rssi_step;
1271 const u8 *wl_rssi_step;
1272 const struct coex_table_para *table_nsant;
1273 const struct coex_table_para *table_sant;
1274 const struct coex_tdma_para *tdma_sant;
1275 const struct coex_tdma_para *tdma_nsant;
1276 const struct coex_rf_para *wl_rf_para_tx;
1277 const struct coex_rf_para *wl_rf_para_rx;
1278 const struct coex_5g_afh_map *afh_5g;
1279 const struct rtw_hw_reg *btg_reg;
1280 const struct rtw_reg_domain *coex_info_hw_regs;
1281 u32 wl_fw_desired_ver;
1282 };
1283
1284 enum rtw_coex_bt_state_cnt {
1285 COEX_CNT_BT_RETRY,
1286 COEX_CNT_BT_REINIT,
1287 COEX_CNT_BT_REENABLE,
1288 COEX_CNT_BT_POPEVENT,
1289 COEX_CNT_BT_SETUPLINK,
1290 COEX_CNT_BT_IGNWLANACT,
1291 COEX_CNT_BT_INQ,
1292 COEX_CNT_BT_PAGE,
1293 COEX_CNT_BT_ROLESWITCH,
1294 COEX_CNT_BT_AFHUPDATE,
1295 COEX_CNT_BT_INFOUPDATE,
1296 COEX_CNT_BT_IQK,
1297 COEX_CNT_BT_IQKFAIL,
1298
1299 COEX_CNT_BT_MAX
1300 };
1301
1302 enum rtw_coex_wl_state_cnt {
1303 COEX_CNT_WL_SCANAP,
1304 COEX_CNT_WL_CONNPKT,
1305 COEX_CNT_WL_COEXRUN,
1306 COEX_CNT_WL_NOISY0,
1307 COEX_CNT_WL_NOISY1,
1308 COEX_CNT_WL_NOISY2,
1309 COEX_CNT_WL_5MS_NOEXTEND,
1310 COEX_CNT_WL_FW_NOTIFY,
1311
1312 COEX_CNT_WL_MAX
1313 };
1314
1315 struct rtw_coex_rfe {
1316 bool ant_switch_exist;
1317 bool ant_switch_diversity;
1318 bool ant_switch_with_bt;
1319 u8 rfe_module_type;
1320 u8 ant_switch_polarity;
1321
1322 /* true if WLG at BTG, else at WLAG */
1323 bool wlg_at_btg;
1324 };
1325
1326 #define COEX_WL_TDMA_PARA_LENGTH 5
1327
1328 struct rtw_coex_dm {
1329 bool cur_ps_tdma_on;
1330 bool cur_wl_rx_low_gain_en;
1331 bool ignore_wl_act;
1332
1333 u8 reason;
1334 u8 bt_rssi_state[4];
1335 u8 wl_rssi_state[4];
1336 u8 wl_ch_info[3];
1337 u8 cur_ps_tdma;
1338 u8 cur_table;
1339 u8 ps_tdma_para[5];
1340 u8 cur_bt_pwr_lvl;
1341 u8 cur_bt_lna_lvl;
1342 u8 cur_wl_pwr_lvl;
1343 u8 bt_status;
1344 u32 cur_ant_pos_type;
1345 u32 cur_switch_status;
1346 u32 setting_tdma;
1347 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH];
1348 };
1349
1350 #define COEX_BTINFO_SRC_WL_FW 0x0
1351 #define COEX_BTINFO_SRC_BT_RSP 0x1
1352 #define COEX_BTINFO_SRC_BT_ACT 0x2
1353 #define COEX_BTINFO_SRC_BT_IQK 0x3
1354 #define COEX_BTINFO_SRC_BT_SCBD 0x4
1355 #define COEX_BTINFO_SRC_H2C60 0x5
1356 #define COEX_BTINFO_SRC_MAX 0x6
1357
1358 #define COEX_INFO_FTP BIT(7)
1359 #define COEX_INFO_A2DP BIT(6)
1360 #define COEX_INFO_HID BIT(5)
1361 #define COEX_INFO_SCO_BUSY BIT(4)
1362 #define COEX_INFO_ACL_BUSY BIT(3)
1363 #define COEX_INFO_INQ_PAGE BIT(2)
1364 #define COEX_INFO_SCO_ESCO BIT(1)
1365 #define COEX_INFO_CONNECTION BIT(0)
1366 #define COEX_BTINFO_LENGTH_MAX 10
1367 #define COEX_BTINFO_LENGTH 7
1368
1369 #define COEX_BT_HIDINFO_LIST 0x0
1370 #define COEX_BT_HIDINFO_A 0x1
1371 #define COEX_BT_HIDINFO_NAME 3
1372
1373 #define COEX_BT_HIDINFO_LENGTH 6
1374 #define COEX_BT_HIDINFO_HANDLE_NUM 4
1375 #define COEX_BT_HIDINFO_C2H_HANDLE 0
1376 #define COEX_BT_HIDINFO_C2H_VENDOR 1
1377 #define COEX_BT_BLE_HANDLE_THRS 0x10
1378 #define COEX_BT_HIDINFO_NOTCON 0xff
1379
1380 struct rtw_coex_hid {
1381 u8 hid_handle;
1382 u8 hid_vendor;
1383 u8 hid_name[COEX_BT_HIDINFO_NAME];
1384 bool hid_info_completed;
1385 bool is_game_hid;
1386 };
1387
1388 struct rtw_coex_hid_handle_list {
1389 u8 cmd_id;
1390 u8 len;
1391 u8 subid;
1392 u8 handle_cnt;
1393 u8 handle[COEX_BT_HIDINFO_HANDLE_NUM];
1394 } __packed;
1395
1396 struct rtw_coex_hid_info_a {
1397 u8 cmd_id;
1398 u8 len;
1399 u8 subid;
1400 u8 handle;
1401 u8 vendor;
1402 u8 name[COEX_BT_HIDINFO_NAME];
1403 } __packed;
1404
1405 struct rtw_coex_stat {
1406 bool bt_disabled;
1407 bool bt_disabled_pre;
1408 bool bt_link_exist;
1409 bool bt_whck_test;
1410 bool bt_inq_page;
1411 bool bt_inq_remain;
1412 bool bt_inq;
1413 bool bt_page;
1414 bool bt_ble_voice;
1415 bool bt_ble_exist;
1416 bool bt_hfp_exist;
1417 bool bt_a2dp_exist;
1418 bool bt_hid_exist;
1419 bool bt_pan_exist; /* PAN or OPP */
1420 bool bt_opp_exist; /* OPP only */
1421 bool bt_acl_busy;
1422 bool bt_fix_2M;
1423 bool bt_setup_link;
1424 bool bt_multi_link;
1425 bool bt_multi_link_pre;
1426 bool bt_multi_link_remain;
1427 bool bt_a2dp_sink;
1428 bool bt_a2dp_active;
1429 bool bt_reenable;
1430 bool bt_ble_scan_en;
1431 bool bt_init_scan;
1432 bool bt_slave;
1433 bool bt_418_hid_exist;
1434 bool bt_ble_hid_exist;
1435 bool bt_game_hid_exist;
1436 bool bt_hid_handle_cnt;
1437 bool bt_mailbox_reply;
1438
1439 bool wl_under_lps;
1440 bool wl_under_ips;
1441 bool wl_hi_pri_task1;
1442 bool wl_hi_pri_task2;
1443 bool wl_force_lps_ctrl;
1444 bool wl_gl_busy;
1445 bool wl_linkscan_proc;
1446 bool wl_ps_state_fail;
1447 bool wl_tx_limit_en;
1448 bool wl_ampdu_limit_en;
1449 bool wl_connected;
1450 bool wl_slot_extend;
1451 bool wl_cck_lock;
1452 bool wl_cck_lock_pre;
1453 bool wl_cck_lock_ever;
1454 bool wl_connecting;
1455 bool wl_slot_toggle;
1456 bool wl_slot_toggle_change; /* if toggle to no-toggle */
1457 bool wl_mimo_ps;
1458
1459 u32 bt_supported_version;
1460 u32 bt_supported_feature;
1461 u32 hi_pri_tx;
1462 u32 hi_pri_rx;
1463 u32 lo_pri_tx;
1464 u32 lo_pri_rx;
1465 u32 patch_ver;
1466 u16 bt_reg_vendor_ae;
1467 u16 bt_reg_vendor_ac;
1468 s8 bt_rssi;
1469 u8 kt_ver;
1470 u8 gnt_workaround_state;
1471 u8 tdma_timer_base;
1472 u8 bt_profile_num;
1473 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
1474 u8 bt_info_lb2;
1475 u8 bt_info_lb3;
1476 u8 bt_info_hb0;
1477 u8 bt_info_hb1;
1478 u8 bt_info_hb2;
1479 u8 bt_info_hb3;
1480 u8 bt_ble_scan_type;
1481 u8 bt_hid_pair_num;
1482 u8 bt_hid_slot;
1483 u8 bt_a2dp_bitpool;
1484 u8 bt_iqk_state;
1485
1486 u16 wl_beacon_interval;
1487 u8 wl_noisy_level;
1488 u8 wl_fw_dbg_info[10];
1489 u8 wl_fw_dbg_info_pre[10];
1490 u8 wl_rx_rate;
1491 u8 wl_tx_rate;
1492 u8 wl_rts_rx_rate;
1493 u8 wl_coex_mode;
1494 u8 wl_iot_peer;
1495 u8 ampdu_max_time;
1496 u8 wl_tput_dir;
1497
1498 u8 wl_toggle_para[6];
1499 u8 wl_toggle_interval;
1500
1501 u16 score_board;
1502 u16 retry_limit;
1503
1504 /* counters to record bt states */
1505 u32 cnt_bt[COEX_CNT_BT_MAX];
1506
1507 /* counters to record wifi states */
1508 u32 cnt_wl[COEX_CNT_WL_MAX];
1509
1510 /* counters to record bt c2h data */
1511 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX];
1512
1513 u32 darfrc;
1514 u32 darfrch;
1515
1516 struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM];
1517 struct rtw_coex_hid_handle_list hid_handle_list;
1518 };
1519
1520 struct rtw_coex {
1521 struct sk_buff_head queue;
1522 wait_queue_head_t wait;
1523
1524 bool under_5g;
1525 bool stop_dm;
1526 bool freeze;
1527 bool freerun;
1528 bool wl_rf_off;
1529 bool manual_control;
1530
1531 struct rtw_coex_stat stat;
1532 struct rtw_coex_dm dm;
1533 struct rtw_coex_rfe rfe;
1534
1535 struct delayed_work bt_relink_work;
1536 struct delayed_work bt_reenable_work;
1537 struct delayed_work defreeze_work;
1538 struct delayed_work wl_remain_work;
1539 struct delayed_work bt_remain_work;
1540 struct delayed_work wl_connecting_work;
1541 struct delayed_work bt_multi_link_remain_work;
1542 struct delayed_work wl_ccklock_work;
1543
1544 };
1545
1546 #define DPK_RF_REG_NUM 7
1547 #define DPK_RF_PATH_NUM 2
1548 #define DPK_BB_REG_NUM 18
1549 #define DPK_CHANNEL_WIDTH_80 1
1550
1551 DECLARE_EWMA(thermal, 10, 4);
1552
1553 struct rtw_dpk_info {
1554 bool is_dpk_pwr_on;
1555 bool is_reload;
1556
1557 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM);
1558
1559 u8 thermal_dpk[DPK_RF_PATH_NUM];
1560 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM];
1561
1562 u32 gnt_control;
1563 u32 gnt_value;
1564
1565 u8 result[RTW_RF_PATH_MAX];
1566 u8 dpk_txagc[RTW_RF_PATH_MAX];
1567 u32 coef[RTW_RF_PATH_MAX][20];
1568 u16 dpk_gs[RTW_RF_PATH_MAX];
1569 u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
1570 u8 pre_pwsf[RTW_RF_PATH_MAX];
1571
1572 u8 dpk_band;
1573 u8 dpk_ch;
1574 u8 dpk_bw;
1575 };
1576
1577 struct rtw_phy_cck_pd_reg {
1578 u32 reg_pd;
1579 u32 mask_pd;
1580 u32 reg_cs;
1581 u32 mask_cs;
1582 };
1583
1584 #define DACK_MSBK_BACKUP_NUM 0xf
1585 #define DACK_DCK_BACKUP_NUM 0x2
1586
1587 struct rtw_swing_table {
1588 const u8 *p[RTW_RF_PATH_MAX];
1589 const u8 *n[RTW_RF_PATH_MAX];
1590 };
1591
1592 struct rtw_pkt_count {
1593 u16 num_bcn_pkt;
1594 u16 num_qry_pkt[DESC_RATE_MAX];
1595 };
1596
1597 DECLARE_EWMA(evm, 10, 4);
1598 DECLARE_EWMA(snr, 10, 4);
1599
1600 struct rtw_iqk_info {
1601 bool done;
1602 struct {
1603 u32 s1_x;
1604 u32 s1_y;
1605 u32 s0_x;
1606 u32 s0_y;
1607 } result;
1608 };
1609
1610 enum rtw_rf_band {
1611 RF_BAND_2G_CCK,
1612 RF_BAND_2G_OFDM,
1613 RF_BAND_5G_L,
1614 RF_BAND_5G_M,
1615 RF_BAND_5G_H,
1616 RF_BAND_MAX
1617 };
1618
1619 #define RF_GAIN_NUM 11
1620 #define RF_HW_OFFSET_NUM 10
1621
1622 struct rtw_gapk_info {
1623 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX];
1624 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM];
1625 bool txgapk_bp_done;
1626 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1627 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1628 u8 read_txgain;
1629 u8 channel;
1630 };
1631
1632 #define EDCCA_TH_L2H_IDX 0
1633 #define EDCCA_TH_H2L_IDX 1
1634 #define EDCCA_TH_L2H_LB 48
1635 #define EDCCA_ADC_BACKOFF 12
1636 #define EDCCA_IGI_BASE 50
1637 #define EDCCA_IGI_L2H_DIFF 8
1638 #define EDCCA_L2H_H2L_DIFF 7
1639 #define EDCCA_L2H_H2L_DIFF_NORMAL 8
1640
1641 enum rtw_edcca_mode {
1642 RTW_EDCCA_NORMAL = 0,
1643 RTW_EDCCA_ADAPTIVITY = 1,
1644 };
1645
1646 struct rtw_cfo_track {
1647 bool is_adjust;
1648 u8 crystal_cap;
1649 s32 cfo_tail[RTW_RF_PATH_MAX];
1650 s32 cfo_cnt[RTW_RF_PATH_MAX];
1651 u32 packet_count;
1652 u32 packet_count_pre;
1653 };
1654
1655 #define RRSR_INIT_2G 0x15f
1656 #define RRSR_INIT_5G 0x150
1657
1658 enum rtw_dm_cap {
1659 RTW_DM_CAP_NA,
1660 RTW_DM_CAP_TXGAPK,
1661 RTW_DM_CAP_NUM
1662 };
1663
1664 struct rtw_dm_info {
1665 u32 cck_fa_cnt;
1666 u32 ofdm_fa_cnt;
1667 u32 total_fa_cnt;
1668 u32 cck_cca_cnt;
1669 u32 ofdm_cca_cnt;
1670 u32 total_cca_cnt;
1671
1672 u32 cck_ok_cnt;
1673 u32 cck_err_cnt;
1674 u32 ofdm_ok_cnt;
1675 u32 ofdm_err_cnt;
1676 u32 ht_ok_cnt;
1677 u32 ht_err_cnt;
1678 u32 vht_ok_cnt;
1679 u32 vht_err_cnt;
1680
1681 u8 min_rssi;
1682 u8 pre_min_rssi;
1683 u16 fa_history[4];
1684 u8 igi_history[4];
1685 u8 igi_bitmap;
1686 bool damping;
1687 u8 damping_cnt;
1688 u8 damping_rssi;
1689
1690 u8 cck_gi_u_bnd;
1691 u8 cck_gi_l_bnd;
1692
1693 u8 fix_rate;
1694 u8 tx_rate;
1695 u32 rrsr_val_init;
1696 u32 rrsr_mask_min;
1697 u8 thermal_avg[RTW_RF_PATH_MAX];
1698 u8 thermal_meter_k;
1699 u8 thermal_meter_lck;
1700 s8 delta_power_index[RTW_RF_PATH_MAX];
1701 s8 delta_power_index_last[RTW_RF_PATH_MAX];
1702 u8 default_ofdm_index;
1703 bool pwr_trk_triggered;
1704 bool pwr_trk_init_trigger;
1705 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX];
1706 s8 txagc_remnant_cck;
1707 s8 txagc_remnant_ofdm;
1708
1709 /* backup dack results for each path and I/Q */
1710 u32 dack_adck[RTW_RF_PATH_MAX];
1711 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM];
1712 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
1713
1714 struct rtw_dpk_info dpk_info;
1715 struct rtw_cfo_track cfo_track;
1716
1717 /* [bandwidth 0:20M/1:40M][number of path] */
1718 u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
1719 u32 cck_fa_avg;
1720 u8 cck_pd_default;
1721
1722 /* save the last rx phy status for debug */
1723 s8 rx_snr[RTW_RF_PATH_MAX];
1724 u8 rx_evm_dbm[RTW_RF_PATH_MAX];
1725 s16 cfo_tail[RTW_RF_PATH_MAX];
1726 u8 rssi[RTW_RF_PATH_MAX];
1727 u8 curr_rx_rate;
1728 struct rtw_pkt_count cur_pkt_count;
1729 struct rtw_pkt_count last_pkt_count;
1730 struct ewma_evm ewma_evm[RTW_EVM_NUM];
1731 struct ewma_snr ewma_snr[RTW_SNR_NUM];
1732
1733 u32 dm_flags; /* enum rtw_dm_cap */
1734 struct rtw_iqk_info iqk;
1735 struct rtw_gapk_info gapk;
1736 bool is_bt_iqk_timeout;
1737
1738 s8 l2h_th_ini;
1739 enum rtw_edcca_mode edcca_mode;
1740 u8 scan_density;
1741 };
1742
1743 struct rtw_efuse {
1744 u32 size;
1745 u32 physical_size;
1746 u32 logical_size;
1747 u32 protect_size;
1748
1749 u8 addr[ETH_ALEN];
1750 u8 channel_plan;
1751 u8 country_code[2];
1752 u8 rf_board_option;
1753 u8 rfe_option;
1754 u8 power_track_type;
1755 u8 thermal_meter[RTW_RF_PATH_MAX];
1756 u8 thermal_meter_k;
1757 u8 crystal_cap;
1758 u8 ant_div_cfg;
1759 u8 ant_div_type;
1760 u8 regd;
1761 u8 afe;
1762
1763 u8 lna_type_2g;
1764 u8 lna_type_5g;
1765 u8 glna_type;
1766 u8 alna_type;
1767 bool ext_lna_2g;
1768 bool ext_lna_5g;
1769 u8 pa_type_2g;
1770 u8 pa_type_5g;
1771 u8 gpa_type;
1772 u8 apa_type;
1773 bool ext_pa_2g;
1774 bool ext_pa_5g;
1775 u8 tx_bb_swing_setting_2g;
1776 u8 tx_bb_swing_setting_5g;
1777
1778 bool btcoex;
1779 /* bt share antenna with wifi */
1780 bool share_ant;
1781 u8 bt_setting;
1782
1783 struct {
1784 u8 hci;
1785 u8 bw;
1786 u8 ptcl;
1787 u8 nss;
1788 u8 ant_num;
1789 } hw_cap;
1790
1791 struct rtw_txpwr_idx txpwr_idx_table[4];
1792 };
1793
1794 struct rtw_phy_cond {
1795 #ifdef __LITTLE_ENDIAN
1796 u32 rfe:8;
1797 u32 intf:4;
1798 u32 pkg:4;
1799 u32 plat:4;
1800 u32 intf_rsvd:4;
1801 u32 cut:4;
1802 u32 branch:2;
1803 u32 neg:1;
1804 u32 pos:1;
1805 #else
1806 u32 pos:1;
1807 u32 neg:1;
1808 u32 branch:2;
1809 u32 cut:4;
1810 u32 intf_rsvd:4;
1811 u32 plat:4;
1812 u32 pkg:4;
1813 u32 intf:4;
1814 u32 rfe:8;
1815 #endif
1816 /* for intf:4 */
1817 #define INTF_PCIE BIT(0)
1818 #define INTF_USB BIT(1)
1819 #define INTF_SDIO BIT(2)
1820 /* for branch:2 */
1821 #define BRANCH_IF 0
1822 #define BRANCH_ELIF 1
1823 #define BRANCH_ELSE 2
1824 #define BRANCH_ENDIF 3
1825 };
1826
1827 struct rtw_fifo_conf {
1828 /* tx fifo information */
1829 u16 rsvd_boundary;
1830 u16 rsvd_pg_num;
1831 u16 rsvd_drv_pg_num;
1832 u16 txff_pg_num;
1833 u16 acq_pg_num;
1834 u16 rsvd_drv_addr;
1835 u16 rsvd_h2c_info_addr;
1836 u16 rsvd_h2c_sta_info_addr;
1837 u16 rsvd_h2cq_addr;
1838 u16 rsvd_cpu_instr_addr;
1839 u16 rsvd_fw_txbuf_addr;
1840 u16 rsvd_csibuf_addr;
1841 const struct rtw_rqpn *rqpn;
1842 };
1843
1844 struct rtw_fwcd_desc {
1845 u32 size;
1846 u8 *next;
1847 u8 *data;
1848 };
1849
1850 struct rtw_fwcd_segs {
1851 const u32 *segs;
1852 u8 num;
1853 };
1854
1855 #define FW_CD_TYPE 0xffff
1856 #define FW_CD_LEN 4
1857 #define FW_CD_VAL 0xaabbccdd
1858 struct rtw_fw_state {
1859 const struct firmware *firmware;
1860 struct rtw_dev *rtwdev;
1861 struct completion completion;
1862 struct rtw_fwcd_desc fwcd_desc;
1863 u16 version;
1864 u8 sub_version;
1865 u8 sub_index;
1866 u16 h2c_version;
1867 u32 feature;
1868 u32 feature_ext;
1869 enum rtw_fw_type type;
1870 };
1871
1872 enum rtw_sar_sources {
1873 RTW_SAR_SOURCE_NONE,
1874 RTW_SAR_SOURCE_COMMON,
1875 };
1876
1877 enum rtw_sar_bands {
1878 RTW_SAR_BAND_0,
1879 RTW_SAR_BAND_1,
1880 /* RTW_SAR_BAND_2, not used now */
1881 RTW_SAR_BAND_3,
1882 RTW_SAR_BAND_4,
1883
1884 RTW_SAR_BAND_NR,
1885 };
1886
1887 /* the union is reserved for other kinds of SAR sources
1888 * which might not re-use same format with array common.
1889 */
1890 union rtw_sar_cfg {
1891 s8 common[RTW_SAR_BAND_NR];
1892 };
1893
1894 struct rtw_sar {
1895 enum rtw_sar_sources src;
1896 union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_MAX];
1897 };
1898
1899 struct rtw_hal {
1900 u32 rcr;
1901
1902 u32 chip_version;
1903 u8 cut_version;
1904 u8 mp_chip;
1905 u8 oem_id;
1906 u8 pkg_type;
1907 struct rtw_phy_cond phy_cond;
1908 bool rfe_btg;
1909
1910 u8 ps_mode;
1911 u8 current_channel;
1912 u8 current_primary_channel_index;
1913 u8 current_band_width;
1914 u8 current_band_type;
1915 u8 primary_channel;
1916
1917 /* center channel for different available bandwidth,
1918 * val of (bw > current_band_width) is invalid
1919 */
1920 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
1921
1922 u8 sec_ch_offset;
1923 u8 rf_type;
1924 u8 rf_path_num;
1925 u8 rf_phy_num;
1926 u32 antenna_tx;
1927 u32 antenna_rx;
1928 u8 bfee_sts_cap;
1929 bool txrx_1ss;
1930
1931 /* protect tx power section */
1932 struct mutex tx_power_mutex;
1933 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
1934 [DESC_RATE_MAX];
1935 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
1936 [DESC_RATE_MAX];
1937 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
1938 [RTW_RATE_SECTION_MAX];
1939 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
1940 [RTW_RATE_SECTION_MAX];
1941 s8 tx_pwr_limit_2g[RTW_REGD_MAX]
1942 [RTW_CHANNEL_WIDTH_MAX]
1943 [RTW_RATE_SECTION_MAX]
1944 [RTW_MAX_CHANNEL_NUM_2G];
1945 s8 tx_pwr_limit_5g[RTW_REGD_MAX]
1946 [RTW_CHANNEL_WIDTH_MAX]
1947 [RTW_RATE_SECTION_MAX]
1948 [RTW_MAX_CHANNEL_NUM_5G];
1949 s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
1950 [DESC_RATE_MAX];
1951
1952 enum rtw_sar_bands sar_band;
1953 struct rtw_sar sar;
1954
1955 /* for 8821c set channel */
1956 u32 ch_param[3];
1957 };
1958
1959 struct rtw_path_div {
1960 enum rtw_bb_path current_tx_path;
1961 u32 path_a_sum;
1962 u32 path_b_sum;
1963 u16 path_a_cnt;
1964 u16 path_b_cnt;
1965 };
1966
1967 struct rtw_chan_info {
1968 int pri_ch_idx;
1969 int action_id;
1970 int bw;
1971 u8 extra_info;
1972 u8 channel;
1973 u16 timeout;
1974 };
1975
1976 struct rtw_chan_list {
1977 u32 buf_size;
1978 u32 ch_num;
1979 u32 size;
1980 u16 addr;
1981 };
1982
1983 struct rtw_hw_scan_info {
1984 struct ieee80211_vif *scanning_vif;
1985 u8 probe_pg_size;
1986 u8 op_pri_ch_idx;
1987 u8 op_pri_ch;
1988 u8 op_chan;
1989 u8 op_bw;
1990 };
1991
1992 struct rtw_dev {
1993 struct ieee80211_hw *hw;
1994 struct device *dev;
1995
1996 struct rtw_hci hci;
1997
1998 struct rtw_hw_scan_info scan_info;
1999 const struct rtw_chip_info *chip;
2000 struct rtw_hal hal;
2001 struct rtw_fifo_conf fifo;
2002 struct rtw_fw_state fw;
2003 struct rtw_efuse efuse;
2004 struct rtw_sec_desc sec;
2005 struct rtw_traffic_stats stats;
2006 struct rtw_regd regd;
2007 struct rtw_bf_info bf_info;
2008
2009 struct rtw_dm_info dm_info;
2010 struct rtw_coex coex;
2011
2012 /* ensures exclusive access from mac80211 callbacks */
2013 struct mutex mutex;
2014
2015 /* watch dog every 2 sec */
2016 struct delayed_work watch_dog_work;
2017 u32 watch_dog_cnt;
2018
2019 struct list_head rsvd_page_list;
2020
2021 /* c2h cmd queue & handler work */
2022 struct sk_buff_head c2h_queue;
2023 struct work_struct c2h_work;
2024 struct work_struct ips_work;
2025 struct work_struct fw_recovery_work;
2026 struct work_struct update_beacon_work;
2027
2028 /* used to protect txqs list */
2029 spinlock_t txq_lock;
2030 struct list_head txqs;
2031 struct workqueue_struct *tx_wq;
2032 struct work_struct tx_work;
2033 struct work_struct ba_work;
2034
2035 struct rtw_tx_report tx_report;
2036
2037 struct {
2038 /* indicate the mail box to use with fw */
2039 u8 last_box_num;
2040 u32 seq;
2041 } h2c;
2042
2043 /* lps power state & handler work */
2044 struct rtw_lps_conf lps_conf;
2045 bool ps_enabled;
2046 bool beacon_loss;
2047 struct completion lps_leave_check;
2048
2049 struct dentry *debugfs;
2050
2051 u8 sta_cnt;
2052 u32 rts_threshold;
2053
2054 DECLARE_BITMAP(hw_port, RTW_PORT_NUM);
2055 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
2056 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
2057
2058 u8 mp_mode;
2059 struct rtw_path_div dm_path_div;
2060
2061 struct rtw_fw_state wow_fw;
2062 struct rtw_wow_param wow;
2063
2064 bool need_rfk;
2065 struct completion fw_scan_density;
2066 bool ap_active;
2067
2068 /* hci related data, must be last */
2069 u8 priv[] __aligned(sizeof(void *));
2070 };
2071
2072 #include "hci.h"
2073
rtw_is_assoc(struct rtw_dev * rtwdev)2074 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev)
2075 {
2076 return !!rtwdev->sta_cnt;
2077 }
2078
rtwtxq_to_txq(struct rtw_txq * rtwtxq)2079 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq)
2080 {
2081 void *p = rtwtxq;
2082
2083 return container_of(p, struct ieee80211_txq, drv_priv);
2084 }
2085
rtwvif_to_vif(struct rtw_vif * rtwvif)2086 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif)
2087 {
2088 void *p = rtwvif;
2089
2090 return container_of(p, struct ieee80211_vif, drv_priv);
2091 }
2092
rtw_ssid_equal(struct cfg80211_ssid * a,struct cfg80211_ssid * b)2093 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a,
2094 struct cfg80211_ssid *b)
2095 {
2096 if (!a || !b || a->ssid_len != b->ssid_len)
2097 return false;
2098
2099 if (memcmp(a->ssid, b->ssid, a->ssid_len))
2100 return false;
2101
2102 return true;
2103 }
2104
rtw_chip_efuse_grant_on(struct rtw_dev * rtwdev)2105 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev)
2106 {
2107 if (rtwdev->chip->ops->efuse_grant)
2108 rtwdev->chip->ops->efuse_grant(rtwdev, true);
2109 }
2110
rtw_chip_efuse_grant_off(struct rtw_dev * rtwdev)2111 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev)
2112 {
2113 if (rtwdev->chip->ops->efuse_grant)
2114 rtwdev->chip->ops->efuse_grant(rtwdev, false);
2115 }
2116
rtw_chip_wcpu_11n(struct rtw_dev * rtwdev)2117 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev)
2118 {
2119 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N;
2120 }
2121
rtw_chip_wcpu_11ac(struct rtw_dev * rtwdev)2122 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev)
2123 {
2124 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC;
2125 }
2126
rtw_chip_has_rx_ldpc(struct rtw_dev * rtwdev)2127 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev)
2128 {
2129 return rtwdev->chip->rx_ldpc;
2130 }
2131
rtw_chip_has_tx_stbc(struct rtw_dev * rtwdev)2132 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev)
2133 {
2134 return rtwdev->chip->tx_stbc;
2135 }
2136
rtw_release_macid(struct rtw_dev * rtwdev,u8 mac_id)2137 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id)
2138 {
2139 clear_bit(mac_id, rtwdev->mac_id_map);
2140 }
2141
rtw_chip_dump_fw_crash(struct rtw_dev * rtwdev)2142 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev)
2143 {
2144 if (rtwdev->chip->ops->dump_fw_crash)
2145 return rtwdev->chip->ops->dump_fw_crash(rtwdev);
2146
2147 return 0;
2148 }
2149
2150 static inline
rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band)2151 enum nl80211_band rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band)
2152 {
2153 switch (hw_band) {
2154 default:
2155 case RTW_BAND_2G:
2156 return NL80211_BAND_2GHZ;
2157 case RTW_BAND_5G:
2158 return NL80211_BAND_5GHZ;
2159 case RTW_BAND_60G:
2160 return NL80211_BAND_60GHZ;
2161 }
2162 }
2163
2164 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel);
2165 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period);
2166 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
2167 struct rtw_channel_params *ch_param);
2168 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
2169 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
2170 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
2171 void rtw_restore_reg(struct rtw_dev *rtwdev,
2172 struct rtw_backup_info *bckp, u32 num);
2173 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss);
2174 void rtw_set_channel(struct rtw_dev *rtwdev);
2175 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev);
2176 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2177 u32 config);
2178 void rtw_tx_report_purge_timer(struct timer_list *t);
2179 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
2180 bool reset_ra_mask);
2181 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2182 const u8 *mac_addr, bool hw_scan);
2183 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
2184 bool hw_scan);
2185 int rtw_core_start(struct rtw_dev *rtwdev);
2186 void rtw_core_stop(struct rtw_dev *rtwdev);
2187 int rtw_chip_info_setup(struct rtw_dev *rtwdev);
2188 int rtw_core_init(struct rtw_dev *rtwdev);
2189 void rtw_core_deinit(struct rtw_dev *rtwdev);
2190 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2191 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2192 u16 rtw_desc_to_bitrate(u8 desc_rate);
2193 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
2194 struct ieee80211_bss_conf *conf);
2195 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2196 struct ieee80211_vif *vif);
2197 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2198 bool fw_exist);
2199 void rtw_fw_recovery(struct rtw_dev *rtwdev);
2200 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
2201 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
2202 u32 fwcd_item);
2203 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size);
2204 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss);
2205 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel,
2206 u8 primary_channel, enum rtw_supported_band band,
2207 enum rtw_bandwidth bandwidth);
2208 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif);
2209 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev);
2210 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable);
2211 #if defined(__linux__)
2212 #define rtw88_static_assert(_x) static_assert(_x)
2213 #elif defined(__FreeBSD__)
2214 #define rtw88_static_assert(_x) _Static_assert(_x, "bad array size")
2215 #endif
2216
2217 #endif
2218