1 #ifndef MMU_RADIX64_H 2 #define MMU_RADIX64_H 3 4 #ifndef CONFIG_USER_ONLY 5 6 #include "exec/page-protection.h" 7 8 /* Radix Quadrants */ 9 #define R_EADDR_MASK 0x3FFFFFFFFFFFFFFF 10 #define R_EADDR_VALID_MASK 0xC00FFFFFFFFFFFFF 11 #define R_EADDR_QUADRANT 0xC000000000000000 12 #define R_EADDR_QUADRANT0 0x0000000000000000 13 #define R_EADDR_QUADRANT1 0x4000000000000000 14 #define R_EADDR_QUADRANT2 0x8000000000000000 15 #define R_EADDR_QUADRANT3 0xC000000000000000 16 17 /* Radix Partition Table Entry Fields */ 18 #define PATE1_R_PRTB 0x0FFFFFFFFFFFF000 19 #define PATE1_R_PRTS 0x000000000000001F 20 21 /* Radix Process Table Entry Fields */ 22 #define PRTBE_R_GET_RTS(rts) \ 23 ((((rts >> 58) & 0x18) | ((rts >> 5) & 0x7)) + 31) 24 #define PRTBE_R_RPDB 0x0FFFFFFFFFFFFF00 25 #define PRTBE_R_RPDS 0x000000000000001F 26 27 /* Radix Page Directory/Table Entry Fields */ 28 #define R_PTE_VALID 0x8000000000000000 29 #define R_PTE_LEAF 0x4000000000000000 30 #define R_PTE_SW0 0x2000000000000000 31 #define R_PTE_RPN 0x01FFFFFFFFFFF000 32 #define R_PTE_SW1 0x0000000000000E00 33 #define R_GET_SW(sw) (((sw >> 58) & 0x8) | ((sw >> 9) & 0x7)) 34 #define R_PTE_R 0x0000000000000100 35 #define R_PTE_C 0x0000000000000080 36 #define R_PTE_ATT 0x0000000000000030 37 #define R_PTE_ATT_NORMAL 0x0000000000000000 38 #define R_PTE_ATT_SAO 0x0000000000000010 39 #define R_PTE_ATT_NI_IO 0x0000000000000020 40 #define R_PTE_ATT_TOLERANT_IO 0x0000000000000030 41 #define R_PTE_EAA_PRIV 0x0000000000000008 42 #define R_PTE_EAA_R 0x0000000000000004 43 #define R_PTE_EAA_RW 0x0000000000000002 44 #define R_PTE_EAA_X 0x0000000000000001 45 #define R_PDE_NLB PRTBE_R_RPDB 46 #define R_PDE_NLS PRTBE_R_RPDS 47 48 #ifdef TARGET_PPC64 49 50 bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, 51 hwaddr *raddr, int *psizep, int *protp, int mmu_idx, 52 bool guest_visible); 53 ppc_radix64_get_prot_eaa(uint64_t pte)54static inline int ppc_radix64_get_prot_eaa(uint64_t pte) 55 { 56 return (pte & R_PTE_EAA_R ? PAGE_READ : 0) | 57 (pte & R_PTE_EAA_RW ? PAGE_READ | PAGE_WRITE : 0) | 58 (pte & R_PTE_EAA_X ? PAGE_EXEC : 0); 59 } 60 ppc_radix64_get_prot_amr(const PowerPCCPU * cpu)61static inline int ppc_radix64_get_prot_amr(const PowerPCCPU *cpu) 62 { 63 const CPUPPCState *env = &cpu->env; 64 int amr = env->spr[SPR_AMR] >> 62; /* We only care about key0 AMR63:62 */ 65 int iamr = env->spr[SPR_IAMR] >> 62; /* We only care about key0 IAMR63:62 */ 66 67 return (amr & 0x2 ? 0 : PAGE_WRITE) | /* Access denied if bit is set */ 68 (amr & 0x1 ? 0 : PAGE_READ) | 69 (iamr & 0x1 ? 0 : PAGE_EXEC); 70 } 71 72 #endif /* TARGET_PPC64 */ 73 74 #endif /* CONFIG_USER_ONLY */ 75 76 #endif /* MMU_RADIX64_H */ 77