/openbsd/sys/arch/arm64/arm64/ |
H A D | disasm.c | 746 uint64_t Rn, uint64_t Rd, in extendreg_common() 789 uint64_t Rn, uint64_t Rd, in shiftreg_common() 1033 OP4FUNC(op_adc, sf, Rm, Rn, Rd) in OP4FUNC() argument 1468 OP3FUNC(op_cls, sf, Rn, Rd) in OP3FUNC() argument 1475 OP3FUNC(op_clz, sf, Rn, Rd) in OP3FUNC() argument 2534 OP4FUNC(op_sbc, sf, Rm, Rn, Rd) argument 2722 OP3FUNC(op_smulh, Rm, Rn, Rd) argument 3157 OP3FUNC(op_umulh, Rm, Rn, Rd) argument 3589 OP3FUNC(op_pacga, Rm, Rn, Rd) argument 3597 OP1FUNC(op_xpaci, Rd) argument [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64PBQPRegAlloc.cpp | 158 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, in addIntraChainConstraint() 242 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, in addInterChainConstraint() 362 Register Rd = MI.getOperand(0).getReg(); in apply() local 372 Register Rd = MI.getOperand(0).getReg(); in apply() local
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 911 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local 1010 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local 1072 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local 1612 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local 1669 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local 1700 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local 1739 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local 1757 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local 1775 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubImmShift() local 2006 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeCPYMemOpInstruction() local [all …]
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/openbsd/gnu/llvm/lldb/source/Plugins/Instruction/ARM/ |
H A D | EmulateInstructionARM.cpp | 2397 uint32_t Rd; in EmulateSUBSPImm() local 3152 uint32_t Rd, Rn; in EmulateADDImmARM() local 3218 uint32_t Rd, Rn, Rm; in EmulateADDReg() local 5801 uint32_t Rd, Rn; in EmulateADCImm() local 5871 uint32_t Rd, Rn, Rm; in EmulateADCReg() local 5950 uint32_t Rd; in EmulateADR() local 6018 uint32_t Rd, Rn; in EmulateANDImm() local 6094 uint32_t Rd, Rn, Rm; in EmulateANDReg() local 6183 uint32_t Rd, Rn; in EmulateBICImm() local 8822 uint32_t Rd, Rn; in EmulateEORImm() local [all …]
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H A D | EmulateInstructionARM.h | 203 const uint32_t Rd) { in WriteCoreReg()
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/openbsd/gnu/llvm/lldb/source/Plugins/Instruction/RISCV/ |
H A D | RISCVInstructions.h | 22 struct Rd { struct 45 Rd rd; \ argument
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H A D | RISCVCInstructions.h | 25 operator Rd() { return Rd{rd + (shift ? 8 : 0)}; } in Rd() function
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/openbsd/gnu/llvm/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 2429 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeQADDInstruction() local 2685 unsigned Rd = fieldFromInstruction(Insn, 8, 4); in DecodeT2MOVTWInstruction() local 2710 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeArmMOVTWInstruction() local 2738 unsigned Rd = fieldFromInstruction(Insn, 16, 4); in DecodeSMLAInstruction() local 2962 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLDInstruction() local 3294 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVSTInstruction() local 3565 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD1DupInstruction() local 3613 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD2DupInstruction() local 3662 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD3DupInstruction() local 3698 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD4DupInstruction() local [all …]
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/openbsd/gnu/llvm/compiler-rt/lib/xray/ |
H A D | xray_mips.cpp | 47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
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H A D | xray_mips64.cpp | 48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
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/openbsd/gnu/llvm/llvm/lib/Target/RISCV/Disassembler/ |
H A D | RISCVDisassembler.cpp | 413 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs2() local 423 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs1Rs2() local
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/openbsd/gnu/llvm/llvm/lib/Target/MSP430/Disassembler/ |
H A D | MSP430Disassembler.cpp | 194 unsigned Rd = fieldFromInstruction(Insn, 0, 4); in DecodeDstAddrMode() local
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/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/AsmParser/ |
H A D | HexagonAsmParser.cpp | 1691 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local 1724 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local 1734 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local 1922 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
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/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/AsmParser/ |
H A D | LoongArchAsmParser.cpp | 1178 unsigned Rd = Inst.getOperand(0).getReg(); in checkTargetMatchPredicate() local 1190 unsigned Rd = Inst.getOperand(0).getReg(); in checkTargetMatchPredicate() local
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/openbsd/gnu/llvm/lldb/source/Plugins/Instruction/ARM64/ |
H A D | EmulateInstructionARM64.cpp | 620 const uint32_t Rd = Bits32(opcode, 4, 0); in EmulateADDSUBImm() local
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/openbsd/gnu/usr.bin/binutils/gas/config/ |
H A D | tc-arm.c | 9725 int Rd, Rs, Rn = FAIL; local 9895 int Rd, Rs, Rn = FAIL; local 10004 int Rd, Rs = FAIL; local 10093 int Rd, Rb, Ro = FAIL; local 10948 int Rd, Rs, Rn; local 11186 int Rd, Rb, Ro; local
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/openbsd/gnu/usr.bin/binutils-2.17/gas/config/ |
H A D | tc-arm.c | 6255 int Rd, Rn; in do_t_add_sub_w() local 6271 int Rd, Rs, Rn; in do_t_add_sub() local 6470 int Rd, Rs, Rn; in do_t_arit3() local 6553 int Rd, Rs, Rn; in do_t_arit3c() local 7786 int Rd, Rs; in do_t_rsb() local
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/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonConstExtenders.cpp | 325 Register Rd; member
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H A D | HexagonFrameLowering.cpp | 2508 Register Rd = RdOp.getReg(), Rs = RsOp.getReg(); in expandAlloca() local
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H A D | HexagonInstrInfo.cpp | 1343 Register Rd = Op0.getReg(); in expandPostRAPseudo() local
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/openbsd/gnu/usr.bin/binutils/opcodes/ |
H A D | i386-dis.c | 215 #define Rd OP_Rd, d_mode macro
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/openbsd/gnu/usr.bin/binutils-2.17/opcodes/ |
H A D | i386-dis.c | 235 #define Rd OP_Rd, d_mode macro
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