1--  Debugger for interpreter
2--  Copyright (C) 2014 Tristan Gingold
3--
4--  This program is free software: you can redistribute it and/or modify
5--  it under the terms of the GNU General Public License as published by
6--  the Free Software Foundation, either version 2 of the License, or
7--  (at your option) any later version.
8--
9--  This program is distributed in the hope that it will be useful,
10--  but WITHOUT ANY WARRANTY; without even the implied warranty of
11--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12--  GNU General Public License for more details.
13--
14--  You should have received a copy of the GNU General Public License
15--  along with this program.  If not, see <gnu.org/licenses>.
16
17with Vhdl.Nodes; use Vhdl.Nodes;
18with Simul.Environments; use Simul.Environments;
19with Grt.Types;
20
21package Simul.Debugger is
22   Flag_Debugger : Boolean := False;
23   Flag_Interractive : Boolean := False;
24
25   Flag_Need_Debug : Boolean := False;
26
27   -- Disp a message for a constraint error.
28   -- And raise the exception execution_constraint_error.
29   procedure Error_Msg_Constraint (Expr: Iir);
30   pragma No_Return (Error_Msg_Constraint);
31
32   -- Disp a message during execution.
33   procedure Error_Msg_Exec (Msg: String; Loc: Iir);
34   pragma No_Return (Error_Msg_Exec);
35
36   procedure Warning_Msg_Exec (Msg: String; Loc: Iir);
37
38   --  Disp a block instance, in a human readable way.
39   --  Used to debug.
40   procedure Disp_Block_Instance (Instance: Block_Instance_Acc);
41
42   -- Disp the instance tree.
43   procedure Disp_Instances_Tree;
44
45   --  Disp the name of an instance, without newline.  The name of
46   --  architectures is displayed unless Short is True.
47   procedure Disp_Instance_Name (Instance: Block_Instance_Acc;
48                                 Short : Boolean := False);
49
50   -- Disp the resulting processes of elaboration.
51   -- procedure Disp_Processes;
52
53   --  Disp the label of PROCESS, or <unlabeled> if PROCESS has no label.
54   procedure Disp_Label (Process : Iir);
55
56   --  Disp all signals name and values.
57   procedure Disp_Signals_Value;
58
59   --  Disp stats about the design (number of process, number of signals...)
60   procedure Disp_Design_Stats;
61
62   --  The reason why the debugger is invoked.
63   type Debug_Reason is
64     (--  Called from an external debugger while debugging ghdl.
65      Reason_Internal_Debug,
66
67      --  Interractive session, elaboration not done
68      Reason_Start,
69
70      --  At end of elaboration, for an interractive session
71      Reason_Elab,
72
73      --  Simulation time limit reached.
74      Reason_Time,
75
76      --  Before execution of a statement.
77      Reason_Break,
78
79      --  Assertion failure
80      Reason_Assert,
81
82      --  Non recoverable error occurred (such as index error, overflow...)
83      Reason_Error
84     );
85
86   Debugger_Quit : exception;
87
88   --  Time at which simulation must stop and return to user interraction.
89   Break_Time : Grt.Types.Std_Time;
90
91   --  Interractive debugger.
92   procedure Debug (Reason: Debug_Reason);
93
94   --  Call the debugger in case of error.
95   procedure Debug_Error;
96end Simul.Debugger;
97