1 /*
2 * PROJECT: ReactOS Intel PRO/1000 Driver
3 * LICENSE: GPL-2.0+ (https://spdx.org/licenses/GPL-2.0+)
4 * PURPOSE: Hardware specific functions
5 * COPYRIGHT: 2013 Cameron Gutman (cameron.gutman@reactos.org)
6 * 2018 Mark Jansen (mark.jansen@reactos.org)
7 * 2019 Victor Perevertkin (victor.perevertkin@reactos.org)
8 */
9
10 #ifndef _E1000_PCH_
11 #define _E1000_PCH_
12
13 #include <ndis.h>
14
15 #include "e1000hw.h"
16
17 #define E1000_TAG '001e'
18
19 #define MAXIMUM_FRAME_SIZE 1522
20 #define RECEIVE_BUFFER_SIZE 2048
21
22 #define DRIVER_VERSION 1
23
24 #define DEFAULT_INTERRUPT_MASK (E1000_IMS_LSC | E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_RXDMT0 | E1000_IMS_RXT0 | E1000_IMS_TXD_LOW)
25
26
27 typedef struct _E1000_ADAPTER
28 {
29 /* NIC Memory */
30 volatile PUCHAR IoBase;
31 NDIS_PHYSICAL_ADDRESS IoAddress;
32 ULONG IoLength;
33
34 // NDIS_SPIN_LOCK AdapterLock;
35
36 NDIS_HANDLE AdapterHandle;
37 USHORT VendorID;
38 USHORT DeviceID;
39 USHORT SubsystemID;
40 USHORT SubsystemVendorID;
41
42 UCHAR PermanentMacAddress[IEEE_802_ADDR_LENGTH];
43
44 struct {
45 UCHAR MacAddress[IEEE_802_ADDR_LENGTH];
46 } MulticastList[MAXIMUM_MULTICAST_ADDRESSES];
47 ULONG MulticastListSize;
48
49 ULONG LinkSpeedMbps;
50 ULONG MediaState;
51 ULONG PacketFilter;
52
53 /* Io Port */
54 ULONG IoPortAddress;
55 ULONG IoPortLength;
56 volatile PUCHAR IoPort;
57
58 /* Interrupt */
59 ULONG InterruptVector;
60 ULONG InterruptLevel;
61 BOOLEAN InterruptShared;
62 ULONG InterruptFlags;
63
64 NDIS_MINIPORT_INTERRUPT Interrupt;
65 BOOLEAN InterruptRegistered;
66
67 LONG InterruptMask;
68
69 _Interlocked_
70 volatile LONG InterruptPending;
71
72
73 /* Transmit */
74 PE1000_TRANSMIT_DESCRIPTOR TransmitDescriptors;
75 NDIS_PHYSICAL_ADDRESS TransmitDescriptorsPa;
76
77 PNDIS_PACKET TransmitPackets[NUM_TRANSMIT_DESCRIPTORS];
78
79 ULONG CurrentTxDesc;
80 ULONG LastTxDesc;
81 BOOLEAN TxFull;
82
83
84 /* Receive */
85 PE1000_RECEIVE_DESCRIPTOR ReceiveDescriptors;
86 NDIS_PHYSICAL_ADDRESS ReceiveDescriptorsPa;
87
88 E1000_RCVBUF_SIZE ReceiveBufferType;
89 volatile PUCHAR ReceiveBuffer;
90 NDIS_PHYSICAL_ADDRESS ReceiveBufferPa;
91 ULONG ReceiveBufferEntrySize;
92
93 } E1000_ADAPTER, *PE1000_ADAPTER;
94
95
96 BOOLEAN
97 NTAPI
98 NICRecognizeHardware(
99 IN PE1000_ADAPTER Adapter);
100
101 NDIS_STATUS
102 NTAPI
103 NICInitializeAdapterResources(
104 IN PE1000_ADAPTER Adapter,
105 IN PNDIS_RESOURCE_LIST ResourceList);
106
107 NDIS_STATUS
108 NTAPI
109 NICAllocateIoResources(
110 IN PE1000_ADAPTER Adapter);
111
112 NDIS_STATUS
113 NTAPI
114 NICRegisterInterrupts(
115 IN PE1000_ADAPTER Adapter);
116
117 NDIS_STATUS
118 NTAPI
119 NICUnregisterInterrupts(
120 IN PE1000_ADAPTER Adapter);
121
122 NDIS_STATUS
123 NTAPI
124 NICReleaseIoResources(
125 IN PE1000_ADAPTER Adapter);
126
127 NDIS_STATUS
128 NTAPI
129 NICPowerOn(
130 IN PE1000_ADAPTER Adapter);
131
132 NDIS_STATUS
133 NTAPI
134 NICSoftReset(
135 IN PE1000_ADAPTER Adapter);
136
137 NDIS_STATUS
138 NTAPI
139 NICEnableTxRx(
140 IN PE1000_ADAPTER Adapter);
141
142 NDIS_STATUS
143 NTAPI
144 NICDisableTxRx(
145 IN PE1000_ADAPTER Adapter);
146
147 NDIS_STATUS
148 NTAPI
149 NICGetPermanentMacAddress(
150 IN PE1000_ADAPTER Adapter,
151 OUT PUCHAR MacAddress);
152
153 NDIS_STATUS
154 NTAPI
155 NICUpdateMulticastList(
156 IN PE1000_ADAPTER Adapter);
157
158 NDIS_STATUS
159 NTAPI
160 NICApplyPacketFilter(
161 IN PE1000_ADAPTER Adapter);
162
163 VOID
164 NTAPI
165 NICUpdateLinkStatus(
166 IN PE1000_ADAPTER Adapter);
167
168 NDIS_STATUS
169 NTAPI
170 MiniportSend(
171 _In_ NDIS_HANDLE MiniportAdapterContext,
172 _In_ PNDIS_PACKET Packet,
173 _In_ UINT Flags);
174
175 NDIS_STATUS
176 NTAPI
177 MiniportSetInformation(
178 IN NDIS_HANDLE MiniportAdapterContext,
179 IN NDIS_OID Oid,
180 IN PVOID InformationBuffer,
181 IN ULONG InformationBufferLength,
182 OUT PULONG BytesRead,
183 OUT PULONG BytesNeeded);
184
185 NDIS_STATUS
186 NTAPI
187 MiniportQueryInformation(
188 IN NDIS_HANDLE MiniportAdapterContext,
189 IN NDIS_OID Oid,
190 IN PVOID InformationBuffer,
191 IN ULONG InformationBufferLength,
192 OUT PULONG BytesWritten,
193 OUT PULONG BytesNeeded);
194
195 VOID
196 NTAPI
197 MiniportISR(
198 OUT PBOOLEAN InterruptRecognized,
199 OUT PBOOLEAN QueueMiniportHandleInterrupt,
200 IN NDIS_HANDLE MiniportAdapterContext);
201
202 VOID
203 NTAPI
204 MiniportHandleInterrupt(
205 IN NDIS_HANDLE MiniportAdapterContext);
206
207 FORCEINLINE
208 VOID
E1000ReadUlong(_In_ PE1000_ADAPTER Adapter,_In_ ULONG Address,_Out_ PULONG Value)209 E1000ReadUlong(
210 _In_ PE1000_ADAPTER Adapter,
211 _In_ ULONG Address,
212 _Out_ PULONG Value)
213 {
214 NdisReadRegisterUlong((PULONG)(Adapter->IoBase + Address), Value);
215 }
216
217 FORCEINLINE
218 VOID
E1000WriteUlong(_In_ PE1000_ADAPTER Adapter,_In_ ULONG Address,_In_ ULONG Value)219 E1000WriteUlong(
220 _In_ PE1000_ADAPTER Adapter,
221 _In_ ULONG Address,
222 _In_ ULONG Value)
223 {
224 NdisWriteRegisterUlong((PULONG)(Adapter->IoBase + Address), Value);
225 }
226
227 FORCEINLINE
228 VOID
E1000WriteIoUlong(_In_ PE1000_ADAPTER Adapter,_In_ ULONG Address,_In_ ULONG Value)229 E1000WriteIoUlong(
230 _In_ PE1000_ADAPTER Adapter,
231 _In_ ULONG Address,
232 _In_ ULONG Value)
233 {
234 volatile ULONG Dummy;
235
236 NdisRawWritePortUlong((PULONG)(Adapter->IoPort), Address);
237 NdisReadRegisterUlong(Adapter->IoBase + E1000_REG_STATUS, &Dummy);
238 NdisRawWritePortUlong((PULONG)(Adapter->IoPort + 4), Value);
239 }
240
241 FORCEINLINE
242 VOID
NICApplyInterruptMask(_In_ PE1000_ADAPTER Adapter)243 NICApplyInterruptMask(
244 _In_ PE1000_ADAPTER Adapter)
245 {
246 E1000WriteUlong(Adapter, E1000_REG_IMS, Adapter->InterruptMask /*| 0x1F6DC*/);
247 }
248
249 FORCEINLINE
250 VOID
NICDisableInterrupts(_In_ PE1000_ADAPTER Adapter)251 NICDisableInterrupts(
252 _In_ PE1000_ADAPTER Adapter)
253 {
254 E1000WriteUlong(Adapter, E1000_REG_IMC, ~0);
255 }
256
257 #endif /* _E1000_PCH_ */
258