1 /*============================================================================== 2 Copyright(c) 2017 Intel Corporation 3 4 Permission is hereby granted, free of charge, to any person obtaining a 5 copy of this software and associated documentation files(the "Software"), 6 to deal in the Software without restriction, including without limitation 7 the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 and / or sell copies of the Software, and to permit persons to whom the 9 Software is furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be included 12 in all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 OTHER DEALINGS IN THE SOFTWARE. 21 ============================================================================*/ 22 #pragma once 23 24 typedef enum GMM_FLATCCS_FORMAT_ENUM 25 { 26 GMM_FLATCCS_FORMAT_R16S = 0, 27 GMM_FLATCCS_FORMAT_R16U = GMM_FLATCCS_FORMAT_R16S, 28 GMM_FLATCCS_FORMAT_RG16F = GMM_FLATCCS_FORMAT_R16S, 29 GMM_FLATCCS_FORMAT_RG16U = GMM_FLATCCS_FORMAT_R16S, 30 GMM_FLATCCS_FORMAT_RG16S = GMM_FLATCCS_FORMAT_R16S, 31 GMM_FLATCCS_FORMAT_RGBA16S = GMM_FLATCCS_FORMAT_R16S, 32 GMM_FLATCCS_FORMAT_RGBA16U = GMM_FLATCCS_FORMAT_R16S, 33 GMM_FLATCCS_FORMAT_RGBA16F = GMM_FLATCCS_FORMAT_R16S, 34 35 GMM_FLATCCS_MIN_RC_FORMAT = GMM_FLATCCS_FORMAT_R16S, 36 37 GMM_FLATCCS_FORMAT_R32F, 38 GMM_FLATCCS_FORMAT_R32S = GMM_FLATCCS_FORMAT_R32F, 39 GMM_FLATCCS_FORMAT_R32U = GMM_FLATCCS_FORMAT_R32F, 40 GMM_FLATCCS_FORMAT_RG32F = GMM_FLATCCS_FORMAT_R32F, 41 GMM_FLATCCS_FORMAT_RG32S = GMM_FLATCCS_FORMAT_R32F, 42 GMM_FLATCCS_FORMAT_RG32U = GMM_FLATCCS_FORMAT_R32F, 43 GMM_FLATCCS_FORMAT_RGBA32F = GMM_FLATCCS_FORMAT_R32F, 44 GMM_FLATCCS_FORMAT_RGBA32S = GMM_FLATCCS_FORMAT_R32F, 45 GMM_FLATCCS_FORMAT_RGBA32U = GMM_FLATCCS_FORMAT_R32F, 46 47 GMM_FLATCCS_FORMAT_RGB5A1, 48 GMM_FLATCCS_FORMAT_RGBA4 = GMM_FLATCCS_FORMAT_RGB5A1, 49 GMM_FLATCCS_FORMAT_B5G6R5 = GMM_FLATCCS_FORMAT_RGB5A1, 50 GMM_FLATCCS_FORMAT_R8S = GMM_FLATCCS_FORMAT_RGB5A1, 51 GMM_FLATCCS_FORMAT_R8U = GMM_FLATCCS_FORMAT_RGB5A1, 52 GMM_FLATCCS_FORMAT_RG8S = GMM_FLATCCS_FORMAT_RGB5A1, 53 GMM_FLATCCS_FORMAT_RG8U = GMM_FLATCCS_FORMAT_RGB5A1, 54 GMM_FLATCCS_FORMAT_RGBA8S = GMM_FLATCCS_FORMAT_RGB5A1, 55 GMM_FLATCCS_FORMAT_RGBA8U = GMM_FLATCCS_FORMAT_RGB5A1, 56 GMM_FLATCCS_FORMAT_ML8 = GMM_FLATCCS_FORMAT_RGB5A1, 57 58 GMM_FLATCCS_FORMAT_RGB10A2, 59 GMM_FLATCCS_FORMAT_RG11B10, 60 61 GMM_FLATCCS_FORMAT_R32F1, 62 GMM_FLATCCS_FORMAT_R32S1 = GMM_FLATCCS_FORMAT_R32F1, 63 GMM_FLATCCS_FORMAT_R32U1 = GMM_FLATCCS_FORMAT_R32F1, 64 65 GMM_FLATCCS_FORMAT_R16F1, 66 GMM_FLATCCS_FORMAT_R16S1 = GMM_FLATCCS_FORMAT_R16F1, 67 GMM_FLATCCS_FORMAT_R16U1 = GMM_FLATCCS_FORMAT_R16F1, 68 69 GMM_FLATCCS_FORMAT_R8S1, 70 GMM_FLATCCS_FORMAT_R8U1 = GMM_FLATCCS_FORMAT_R8S1, 71 72 GMM_FLATCCS_MAX_RC_FORMAT = GMM_FLATCCS_FORMAT_R8U1, 73 74 GMM_FLATCCS_MIN_MC_FORMAT = 0x21, //(0x1 <<5) ie Msb-5th bit turned on to identify MC encoding, to drop before SurfaceState usage 75 GMM_FLATCCS_FORMAT_RGBA16_MEDIA = GMM_FLATCCS_MIN_MC_FORMAT, 76 GMM_FLATCCS_FORMAT_Y210, 77 GMM_FLATCCS_FORMAT_YUY2, 78 GMM_FLATCCS_FORMAT_Y410, 79 GMM_FLATCCS_FORMAT_Y216, 80 GMM_FLATCCS_FORMAT_Y416, 81 GMM_FLATCCS_FORMAT_P010, 82 GMM_FLATCCS_FORMAT_P016, 83 GMM_FLATCCS_FORMAT_AYUV, 84 GMM_FLATCCS_FORMAT_ARGB8b, 85 GMM_FLATCCS_FORMAT_SWAPY, 86 GMM_FLATCCS_FORMAT_SWAPUV, 87 GMM_FLATCCS_FORMAT_SWAPUVY, 88 GMM_FLATCCS_FORMAT_RGB10b, 89 GMM_FLATCCS_FORMAT_NV12, 90 91 GMM_FLATCCS_FORMAT_YCRCB_SWAPUV = GMM_FLATCCS_FORMAT_SWAPUV, 92 GMM_FLATCCS_FORMAT_YCRCB_SWAPUVY = GMM_FLATCCS_FORMAT_SWAPUVY, 93 GMM_FLATCCS_FORMAT_YCRCB_SWAPY = GMM_FLATCCS_FORMAT_SWAPY, 94 95 GMM_FLATCCS_MAX_MC_FORMAT = GMM_FLATCCS_FORMAT_NV12, //should always be equal to last format encoding 96 97 GMM_FLATCCS_FORMAT_INVALID, //equal to last valid encoding plus one 98 } GMM_FLATCCS_FORMAT; 99 100 typedef enum GMM_UNIFIED_COMP_FORMAT_ENUM 101 { 102 GMM_UNIFIED_COMP_FORMAT_RGBA32F = 0, //0h - bpc32 RGBA F/S 103 GMM_UNIFIED_COMP_FORMAT_RGBA32S = GMM_UNIFIED_COMP_FORMAT_RGBA32F, 104 105 GMM_UNIFIED_COMP_MIN_RC_FORMAT = GMM_UNIFIED_COMP_FORMAT_RGBA32F, 106 107 GMM_UNIFIED_COMP_FORMAT_RGBA32U, //1h - bpc32 RGBA U 108 109 GMM_UNIFIED_COMP_FORMAT_RG32F, // 2h - bpc32 RG F/S 110 GMM_UNIFIED_COMP_FORMAT_RG32S = GMM_UNIFIED_COMP_FORMAT_RG32F, 111 112 GMM_UNIFIED_COMP_FORMAT_RG32U, // 3h - bpc32 RG U 113 114 GMM_UNIFIED_COMP_FORMAT_RGBA16U, // 4h - bpc16 RGBA U 115 116 GMM_UNIFIED_COMP_FORMAT_RGBA16F, // 5h - bpc16 RGBA F/S 117 GMM_UNIFIED_COMP_FORMAT_RGBA16S = GMM_UNIFIED_COMP_FORMAT_RGBA16F, 118 119 GMM_UNIFIED_COMP_FORMAT_RG16U, // 6h - bpc16 RG U 120 121 GMM_UNIFIED_COMP_FORMAT_RG16F, // 7h - bpc16 RG F/S 122 GMM_UNIFIED_COMP_FORMAT_RG16S = GMM_UNIFIED_COMP_FORMAT_RG16F, 123 124 GMM_UNIFIED_COMP_FORMAT_RGBA8U, // 8h - bpc8 RGBA U 125 GMM_UNIFIED_COMP_FORMAT_RGBA8S, // 9h - bpc8 RGBA S 126 127 GMM_UNIFIED_COMP_FORMAT_RGB5A1, // Ah - bpc8 128 GMM_UNIFIED_COMP_FORMAT_RGBA4 = GMM_UNIFIED_COMP_FORMAT_RGB5A1, 129 GMM_UNIFIED_COMP_FORMAT_B5G6R5 = GMM_UNIFIED_COMP_FORMAT_RGB5A1, 130 GMM_UNIFIED_COMP_FORMAT_RG8U = GMM_UNIFIED_COMP_FORMAT_RGB5A1, 131 132 GMM_UNIFIED_COMP_FORMAT_RG8S, // Bh - bpc8 133 GMM_UNIFIED_COMP_FORMAT_RGB10A2, // Ch - bpc8 134 GMM_UNIFIED_COMP_FORMAT_RG11B10, // Dh - bpc8 135 136 GMM_UNIFIED_COMP_FORMAT_R32F = 0x10, // 10h - bpc32 R F/S 137 GMM_UNIFIED_COMP_FORMAT_R32F1 = GMM_UNIFIED_COMP_FORMAT_R32F, 138 GMM_UNIFIED_COMP_FORMAT_R32S = GMM_UNIFIED_COMP_FORMAT_R32F, 139 GMM_UNIFIED_COMP_FORMAT_R32S1 = GMM_UNIFIED_COMP_FORMAT_R32F, 140 141 GMM_UNIFIED_COMP_FORMAT_R32U, // 11h - bpc32 R U 142 GMM_UNIFIED_COMP_FORMAT_R32U1 = GMM_UNIFIED_COMP_FORMAT_R32U, 143 GMM_UNIFIED_COMP_FORMAT_D32U = GMM_UNIFIED_COMP_FORMAT_R32U, 144 145 GMM_UNIFIED_COMP_FORMAT_R16U = 0x14, // 14h - bpc16 R U 146 GMM_UNIFIED_COMP_FORMAT_R16U1 = GMM_UNIFIED_COMP_FORMAT_R16U, // 14h - bpc16 R U 147 148 GMM_UNIFIED_COMP_FORMAT_R16F, // 15h - bpc16 R F/S 149 GMM_UNIFIED_COMP_FORMAT_R16F1 = GMM_UNIFIED_COMP_FORMAT_R16F, 150 GMM_UNIFIED_COMP_FORMAT_R16S = GMM_UNIFIED_COMP_FORMAT_R16F, 151 GMM_UNIFIED_COMP_FORMAT_R16S1 = GMM_UNIFIED_COMP_FORMAT_R16F, 152 153 GMM_UNIFIED_COMP_FORMAT_R8U = 0x18, // 18h - bpc8 R U 154 GMM_UNIFIED_COMP_FORMAT_R8U1 = GMM_UNIFIED_COMP_FORMAT_R8U, 155 156 GMM_UNIFIED_COMP_FORMAT_R8S, // 19h - bpc8 R S 157 GMM_UNIFIED_COMP_FORMAT_R8S1 = GMM_UNIFIED_COMP_FORMAT_R8S, 158 GMM_UNIFIED_COMP_FORMAT_ML8 = 0x1F, 159 160 GMM_UNIFIED_COMP_MAX_RC_FORMAT = GMM_UNIFIED_COMP_FORMAT_ML8, 161 162 GMM_UNIFIED_COMP_MIN_MC_FORMAT = 0x21, //(0x1 <<5) ie Msb-5th bit turned on to identify MC encoding, to drop before SurfaceState usage 163 GMM_UNIFIED_COMP_FORMAT_RGBA16_MEDIA = GMM_UNIFIED_COMP_MIN_MC_FORMAT, //MC 1h 164 GMM_UNIFIED_COMP_FORMAT_Y210, //MC 2h 165 GMM_UNIFIED_COMP_FORMAT_YUY2, //MC 3h 166 GMM_UNIFIED_COMP_FORMAT_Y410, //MC 4h 167 GMM_UNIFIED_COMP_FORMAT_Y216, //MC 5h 168 GMM_UNIFIED_COMP_FORMAT_Y416, //MC 6h 169 GMM_UNIFIED_COMP_FORMAT_P010, //MC 7h 170 GMM_UNIFIED_COMP_FORMAT_P010_L = GMM_UNIFIED_COMP_FORMAT_P010, 171 GMM_UNIFIED_COMP_FORMAT_P010_C = GMM_UNIFIED_COMP_FORMAT_P010, 172 GMM_UNIFIED_COMP_FORMAT_P016, //MC 8h 173 GMM_UNIFIED_COMP_FORMAT_P016_L = GMM_UNIFIED_COMP_FORMAT_P016, 174 GMM_UNIFIED_COMP_FORMAT_P016_C = GMM_UNIFIED_COMP_FORMAT_P016, 175 GMM_UNIFIED_COMP_FORMAT_AYUV, //MC 9h 176 GMM_UNIFIED_COMP_FORMAT_ARGB8b, //MC Ah 177 GMM_UNIFIED_COMP_FORMAT_SWAPY, //MC Bh 178 GMM_UNIFIED_COMP_FORMAT_SWAPUV, //MC Ch 179 GMM_UNIFIED_COMP_FORMAT_SWAPUVY, //MC Dh 180 GMM_UNIFIED_COMP_FORMAT_RGB10b, //MC Eh --Which media format is it? 181 GMM_UNIFIED_COMP_FORMAT_NV12, //MC Fh 182 GMM_UNIFIED_COMP_FORMAT_NV12_L = GMM_UNIFIED_COMP_FORMAT_NV12, 183 GMM_UNIFIED_COMP_FORMAT_NV12_C = GMM_UNIFIED_COMP_FORMAT_NV12, 184 185 GMM_UNIFIED_COMP_FORMAT_YCRCB_SWAPUV = GMM_UNIFIED_COMP_FORMAT_SWAPUV, 186 GMM_UNIFIED_COMP_FORMAT_YCRCB_SWAPUVY = GMM_UNIFIED_COMP_FORMAT_SWAPUVY, 187 GMM_UNIFIED_COMP_FORMAT_YCRCB_SWAPY = GMM_UNIFIED_COMP_FORMAT_SWAPY, 188 189 GMM_UNIFIED_COMP_MAX_MC_FORMAT = GMM_UNIFIED_COMP_FORMAT_NV12, //should always be equal to last format encoding 190 191 GMM_UNIFIED_COMP_FORMAT_INVALID, //equal to last valid encoding plus one 192 } GMM_UNIFIED_COMP_FORMAT; 193 194 #ifdef __cplusplus 195 extern "C" { 196 #endif /*__cplusplus*/ 197 198 // Set packing alignment 199 #pragma pack(push, 8) 200 201 #ifndef __GMM_KMD__ 202 #ifdef _WIN32 203 #ifndef PHYSICAL_ADDRESS 204 #define PHYSICAL_ADDRESS LARGE_INTEGER 205 #endif 206 #endif 207 #ifndef PAGE_SIZE 208 #define PAGE_SIZE 4096 209 #endif 210 #endif /*__GMM_KMD__*/ 211 212 //=========================================================================== 213 // typedef: 214 // GMM_FORMAT_ENTRY 215 // 216 // Description: 217 // This struct is used to describe each surface format in the 218 // GMM_RESOURCE_FORMAT enum. Each surface format is desginated as a 219 // supported format on the running platform, as well as if the format is 220 // renderable. 221 // 222 //--------------------------------------------------------------------------- 223 typedef struct GMM_FORMAT_ENTRY_REC 224 { 225 struct 226 { 227 uint32_t ASTC : 1; 228 uint32_t Compressed : 1; 229 uint32_t RenderTarget : 1; 230 uint32_t Supported : 1; 231 }; 232 struct 233 { 234 uint16_t BitsPer; 235 uint8_t Depth; 236 uint8_t Height; 237 uint8_t Width; 238 } Element; 239 GMM_SURFACESTATE_FORMAT SurfaceStateFormat; 240 union { 241 GMM_E2ECOMP_FORMAT AuxL1eFormat; 242 uint8_t CompressionFormat; 243 } CompressionFormat; 244 }GMM_FORMAT_ENTRY; 245 246 //=========================================================================== 247 // typedef: 248 // GMM_TILE_MODE_ENUM 249 // 250 // Description: 251 // Enumeration of supported tile modes. 252 // 253 //-------------------------------------------------------------------------- 254 #define DEFINE_TILE_BPEs(TileName) \ 255 TILE_##TileName##_8bpe, \ 256 TILE_##TileName##_16bpe, \ 257 TILE_##TileName##_32bpe, \ 258 TILE_##TileName##_64bpe, \ 259 TILE_##TileName##_128bpe \ 260 261 typedef enum GMM_TILE_MODE_ENUM 262 { 263 TILE_NONE, 264 // Legacy Tile Modes 265 LEGACY_TILE_X, 266 LEGACY_TILE_Y, 267 // Tile-W is a 64x64 tile swizzled 268 // onto a 128x32 Tile-Y. 269 // For allocation purposes Tile-W 270 // can be treated like Tile-Y 271 // TILE_W 272 273 // Tiled Resource Modes (SKL+) 274 DEFINE_TILE_BPEs( YF_1D ), 275 DEFINE_TILE_BPEs( YS_1D ), 276 DEFINE_TILE_BPEs( YF_2D ), 277 DEFINE_TILE_BPEs( YF_2D_2X ), 278 DEFINE_TILE_BPEs( YF_2D_4X ), 279 DEFINE_TILE_BPEs( YF_2D_8X ), 280 DEFINE_TILE_BPEs( YF_2D_16X ), 281 DEFINE_TILE_BPEs( YF_3D ), 282 DEFINE_TILE_BPEs( YS_2D ), 283 DEFINE_TILE_BPEs( YS_2D_2X ), 284 DEFINE_TILE_BPEs( YS_2D_4X ), 285 DEFINE_TILE_BPEs( YS_2D_8X ), 286 DEFINE_TILE_BPEs( YS_2D_16X ), 287 DEFINE_TILE_BPEs( YS_3D ), 288 289 // XE-HP 290 TILE4, 291 DEFINE_TILE_BPEs( _64_1D ), 292 DEFINE_TILE_BPEs( _64_2D ), 293 DEFINE_TILE_BPEs( _64_2D_2X), 294 DEFINE_TILE_BPEs( _64_2D_4X), 295 DEFINE_TILE_BPEs( _64_3D), 296 297 GMM_TILE_MODES 298 }GMM_TILE_MODE; 299 300 #undef DEFINE_TILE_BPEs 301 302 typedef struct __TEX_ALIGNMENT 303 { 304 uint32_t Width; // pixels 305 uint32_t Height; // scanlines 306 uint32_t Depth; // pixels 307 } ALIGNMENT; 308 309 //=========================================================================== 310 // typedef: 311 // GMM_TEXTURE_ALIGN 312 // 313 // Description: 314 // The following struct describes the texture mip map unit alignment 315 // required for each map format. The alignment values are platform 316 // dependent. 317 // 318 //--------------------------------------------------------------------------- 319 typedef struct GMM_TEXTURE_ALIGN_REC 320 { 321 ALIGNMENT Compressed, Depth, Depth_D16_UNORM_1x_4x_16x, Depth_D16_UNORM_2x_8x, SeparateStencil, YUV422, XAdapter, AllOther; 322 323 struct 324 { 325 ALIGNMENT Align; 326 uint32_t MaxPitchinTiles; 327 } CCS; 328 }GMM_TEXTURE_ALIGN; 329 330 //=========================================================================== 331 // typedef: 332 // __GMM_BUFFER_TYPE_REC 333 // 334 // Description: 335 // This structure represents a buffer type. Common buffer types are 336 // Display buffers, Color buffers, Linear buffers and ring buffers. 337 // Each buffer type has platform specific size, dimension and alignment 338 // restricions that are stored here. 339 // 340 //--------------------------------------------------------------------------- 341 typedef struct __GMM_BUFFER_TYPE_REC 342 { 343 uint32_t Alignment; // Base Address Alignment 344 uint32_t PitchAlignment; // Pitch Alignment restriction. 345 uint32_t RenderPitchAlignment; // Pitch Alignment for render surface 346 uint32_t LockPitchAlignment; // Pitch Alignment for locked surface 347 uint32_t MinPitch; // Minimum pitch 348 GMM_GFX_SIZE_T MaxPitch; // Maximum pitch 349 GMM_GFX_SIZE_T MinAllocationSize; // Minimum Allocation size requirement 350 351 uint32_t MinHeight; // Mininum height in bytes 352 GMM_GFX_SIZE_T MinWidth; // Minimum width in bytes 353 uint32_t MinDepth; // Minimum depth (only for volume) 354 GMM_GFX_SIZE_T MaxHeight; // Maximum height in bytes 355 GMM_GFX_SIZE_T MaxWidth; // Maximum Width in bytes 356 uint32_t MaxDepth; // Maximum depth (only for volume) 357 uint32_t MaxArraySize; 358 uint8_t NeedPow2LockAlignment; // Locking surface need to be power of 2 aligned 359 } __GMM_BUFFER_TYPE; 360 361 //=========================================================================== 362 // typedef: 363 // __GMM_PLATFORM_RESOURCE 364 // 365 // Description: 366 // This structure represents various platform specific restrictions for 367 // - buffer types 368 // - tile dimensions 369 // - # of fences regisers platform supports 370 // - # of addressable bits 371 // - aperture size 372 // 373 //---------------------------------------------------------------------------- 374 typedef struct __GMM_PLATFORM_RESOURCE_REC 375 { 376 PLATFORM Platform; 377 // 378 // Define memory type req., alignment, min allocation size; 379 // 380 __GMM_BUFFER_TYPE Vertex; // Vertex Buffer restrictions 381 __GMM_BUFFER_TYPE Index; // Index Buffer restrictions 382 __GMM_BUFFER_TYPE Constant; // 383 __GMM_BUFFER_TYPE StateDx9ConstantBuffer; // Dx9 Constant Buffer pool restrictions 384 385 __GMM_BUFFER_TYPE Texture2DSurface; // 2D texture surface 386 __GMM_BUFFER_TYPE Texture2DLinearSurface; // 2D Linear media surface 387 __GMM_BUFFER_TYPE Texture3DSurface; // 3D texture surface 388 __GMM_BUFFER_TYPE CubeSurface; // cube texture surface 389 __GMM_BUFFER_TYPE BufferType; // Buffer type surface 390 391 __GMM_BUFFER_TYPE Color; // Color (Render Target) Buffer 392 __GMM_BUFFER_TYPE Depth; // Depth Buffer Restriction 393 __GMM_BUFFER_TYPE Stencil; // Stencil Buffer Restrictions 394 __GMM_BUFFER_TYPE HiZ; // Hierarchical Depth Buffer Resrictions 395 __GMM_BUFFER_TYPE Stream; // 396 397 __GMM_BUFFER_TYPE Video; // Video Planar surface restrictions 398 __GMM_BUFFER_TYPE MotionComp; // Motion Compensation buffer 399 400 __GMM_BUFFER_TYPE Overlay; // Overlay Buffer 401 __GMM_BUFFER_TYPE Nndi; // Non native display buffer restrictions 402 __GMM_BUFFER_TYPE ASyncFlipSurface; // ASync flip chain Buffers 403 404 __GMM_BUFFER_TYPE HardwareMBM; // Buffer Restrictions 405 406 __GMM_BUFFER_TYPE InterlacedScan; // 407 __GMM_BUFFER_TYPE TextApi; // 408 409 __GMM_BUFFER_TYPE Linear; // Linear(Generic) Buffer restrictions 410 __GMM_BUFFER_TYPE Cursor; // Cursor surface restrictions 411 __GMM_BUFFER_TYPE NoRestriction; // Motion Comp Buffer 412 413 __GMM_BUFFER_TYPE XAdapter; // Cross adapter linear buffer restrictions 414 415 GMM_TEXTURE_ALIGN TexAlign; // Alignment Units for Texture Maps 416 417 // 418 // various tile dimension based on platform 419 // 420 GMM_TILE_INFO TileInfo[GMM_TILE_MODES]; 421 422 // 423 // General platform Restriction 424 // 425 uint32_t NumberFenceRegisters; 426 uint32_t MinFenceSize; // 1 MB for Napa, 512 KB for Almador 427 428 uint32_t FenceLowBoundShift; 429 uint32_t FenceLowBoundMask; 430 431 uint32_t PageTableSteer; // Default for page table steer register 432 433 uint32_t PagingBufferPrivateDataSize; 434 uint32_t MaxLod; 435 uint32_t FBCRequiredStolenMemorySize; // Stolen Memory size required for FBC 436 437 GMM_FORMAT_ENTRY FormatTable[GMM_RESOURCE_FORMATS]; 438 439 uint32_t ResAllocTag[GMM_MAX_HW_RESOURCE_TYPE]; // uint32_t = 4 8-bit ASCII characters 440 441 uint32_t SurfaceStateYOffsetGranularity; 442 uint32_t SamplerFetchGranularityWidth; 443 uint32_t SamplerFetchGranularityHeight; 444 445 int64_t SurfaceMaxSize; // int64_t - Surface size is 64 bit for all configurations 446 uint32_t MaxGpuVirtualAddressBitsPerResource; 447 uint32_t MaxSLMSize; 448 449 uint8_t HiZPixelsPerByte; //HiZ-Bpp is < 1, keep inverse 450 uint64_t ReconMaxHeight; 451 uint64_t ReconMaxWidth; 452 uint8_t NoOfBitsSupported; // No of bits supported for System physcial address on GPU 453 uint64_t HighestAcceptablePhysicalAddress; // Highest acceptable System physical Address 454 }__GMM_PLATFORM_RESOURCE, GMM_PLATFORM_INFO; 455 456 //*************************************************************************** 457 // 458 // GMM_PLATFORM_INFO API 459 // 460 //*************************************************************************** 461 uint32_t GMM_STDCALL GmmPlatformGetBppFromGmmResourceFormat(void *pLibContext, GMM_RESOURCE_FORMAT Format); 462 463 // Reset packing alignment to project default 464 #pragma pack(pop) 465 466 #ifdef __cplusplus 467 } 468 #endif /*__cplusplus*/ 469