/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonCallingConvLower.h | 109 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { in getFirstUnallocated() 136 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { in AllocateReg() 148 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, in AllocateReg()
|
/minix/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/Disassembler/ |
H A D | SystemZDisassembler.cpp | 50 const unsigned *Regs) { in decodeRegisterClass() 188 const unsigned *Regs) { in decodeBDAddr12Operand() 198 const unsigned *Regs) { in decodeBDAddr20Operand() 208 const unsigned *Regs) { in decodeBDXAddr12Operand() 220 const unsigned *Regs) { in decodeBDXAddr20Operand() 232 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
|
/minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | CallingConvLower.h | 317 unsigned getFirstUnallocated(const MCPhysReg *Regs, unsigned NumRegs) const { in getFirstUnallocated() 344 unsigned AllocateReg(const MCPhysReg *Regs, unsigned NumRegs) { in AllocateReg() 358 unsigned AllocateRegBlock(ArrayRef<uint16_t> Regs, unsigned RegsRequired) { in AllocateRegBlock() 385 unsigned AllocateReg(const MCPhysReg *Regs, const MCPhysReg *ShadowRegs, in AllocateReg()
|
/minix/external/bsd/llvm/dist/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 183 const CodeGenRegister::Set &Regs = RC.getMembers(); in EmitRegUnitPressure() local 321 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() 444 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() 797 const auto &Regs = RegBank.getRegisters(); in runMCDesc() local 1323 const auto &Regs = RegBank.getRegisters(); in runTargetDesc() local 1421 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc() local
|
H A D | CodeGenRegisters.cpp | 160 RegUnitIterator(const CodeGenRegister::Set &Regs): in RegUnitIterator() 943 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); in CodeGenRegBank() local 1302 CodeGenRegister::Set Regs; member 1331 const CodeGenRegister::Set &Regs = RegClass.getMembers(); in computeUberSets() local 2072 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) { in computeCoveredRegisters()
|
H A D | CodeGenTarget.cpp | 223 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); in getRegisterByName() local
|
H A D | AsmMatcherEmitter.cpp | 2140 const auto &Regs = Target.getRegBank().getRegisters(); in emitMatchRegisterName() local
|
/minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 892 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple() 901 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() 910 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple() 948 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local 1117 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStore() local 1139 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStore() local 1192 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectLoadLane() local 1237 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostLoadLane() local 1295 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStoreLane() local 1328 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStoreLane() local
|
/minix/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/AsmParser/ |
H A D | SystemZAsmParser.cpp | 461 const unsigned *Regs, bool IsAddress) { in parseRegister() 478 const unsigned *Regs, RegisterKind Kind) { in parseRegister() 497 const unsigned *Regs, in parseAddress() 545 SystemZAsmParser::parseAddress(OperandVector &Operands, const unsigned *Regs, in parseAddress()
|
/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DbgValueHistoryCalculator.cpp | 169 BitVector &Regs) { in collectChangingRegs()
|
/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/ |
H A D | CallingConvLower.cpp | 194 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, in getRemainingRegParmsForType()
|
H A D | AggressiveAntiDepBreaker.cpp | 70 std::vector<unsigned> &Regs, in GetGroupRegs() 539 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
|
H A D | ExecutionDepsFix.cpp | 651 SmallVector<LiveReg, 4> Regs; in visitSoftInstr() local
|
H A D | RegisterPressure.cpp | 422 void RegPressureTracker::addLiveRegs(ArrayRef<unsigned> Regs) { in addLiveRegs()
|
/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMFrameLowering.cpp | 947 SmallVector<std::pair<unsigned,bool>, 4> Regs; in emitPushInst() local 1024 SmallVector<unsigned, 4> Regs; in emitPopInst() local
|
H A D | Thumb2SizeReduction.cpp | 214 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) in HasImplicitCPSRDef() local
|
H A D | ARMLoadStoreOptimizer.cpp | 472 ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB, in MergeOps() 743 SmallVector<std::pair<unsigned, bool>, 8> Regs; in MergeOpsUpdate() local
|
/minix/external/bsd/llvm/dist/llvm/lib/Transforms/Scalar/ |
H A D | LoopStrengthReduce.cpp | 922 SmallPtrSetImpl<const SCEV *> &Regs, in RateRegister() 970 SmallPtrSetImpl<const SCEV *> &Regs, in RatePrimaryRegister() 987 SmallPtrSetImpl<const SCEV *> &Regs, in RateFormula() 1253 SmallPtrSet<const SCEV *, 4> Regs; member in __anonbd2ddbdf0711::LSRUse 3918 SmallPtrSet<const SCEV *, 16> Regs; in FilterOutUndesirableDedicatedRegisters() local
|
/minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 1743 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, in DecodeRegListOperand() local 1765 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; in DecodeRegListOperand16() local
|
/minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 1007 CreateRegList(SmallVectorImpl<unsigned> &Regs, SMLoc StartLoc, SMLoc EndLoc, in CreateRegList() 2705 SmallVector<unsigned, 10> Regs; in parseRegisterList() local
|
/minix/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
H A D | SIISelLowering.cpp | 574 SmallVector<SDValue, 4> Regs; in LowerFormalArguments() local
|
/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.cpp | 610 SmallVector<unsigned, 4> Regs; member 6363 SmallVector<unsigned, 4> Regs; in GetRegistersForValue() local
|
/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 2681 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, in CreateRegList() argument
|