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Searched defs:SCE_VHDL_DEFAULT (Results 26 – 28 of 28) sorted by relevance

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/dports/editors/textadept/scintilla/include/
H A DSciLexer.h1062 #define SCE_VHDL_DEFAULT 0 macro
/dports/editors/scite/scintilla/include/
H A DSciLexer.h1062 #define SCE_VHDL_DEFAULT 0 macro
/dports/devel/codequery/codequery-0.24.0/scintilla/qt/ScintillaEditPy/
H A DScintillaConstants.py1696 SCE_VHDL_DEFAULT=0 variable

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