1 /* $NetBSD: sdmmcreg.h,v 1.34 2018/04/19 21:50:09 christos Exp $ */
2 /* $OpenBSD: sdmmcreg.h,v 1.4 2009/01/09 10:55:22 jsg Exp $ */
3
4 /*
5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #ifndef _SDMMCREG_H_
21 #define _SDMMCREG_H_
22
23 /* MMC commands */ /* response type */
24 #define MMC_GO_IDLE_STATE 0 /* R0 */
25 #define MMC_SEND_OP_COND 1 /* R3 */
26 #define MMC_ALL_SEND_CID 2 /* R2 */
27 #define MMC_SET_RELATIVE_ADDR 3 /* R1 */
28 #define MMC_SWITCH 6 /* R1b */
29 #define MMC_SELECT_CARD 7 /* R1 */
30 #define MMC_SEND_EXT_CSD 8 /* R1 */
31 #define MMC_SEND_CSD 9 /* R2 */
32 #define MMC_SEND_CID 10 /* R2 */
33 #define MMC_STOP_TRANSMISSION 12 /* R1b */
34 #define MMC_SEND_STATUS 13 /* R1 */
35 #define MMC_INACTIVE_STATE 15 /* R0 */
36 #define MMC_SET_BLOCKLEN 16 /* R1 */
37 #define MMC_READ_BLOCK_SINGLE 17 /* R1 */
38 #define MMC_READ_BLOCK_MULTIPLE 18 /* R1 */
39 #define MMC_SEND_TUNING_BLOCK 19 /* R1 */
40 #define MMC_SEND_TUNING_BLOCK_HS200 21 /* R1 */
41 #define MMC_SET_BLOCK_COUNT 23 /* R1 */
42 #define MMC_WRITE_BLOCK_SINGLE 24 /* R1 */
43 #define MMC_WRITE_BLOCK_MULTIPLE 25 /* R1 */
44 #define MMC_PROGRAM_CSD 27 /* R1 */
45 #define MMC_SET_WRITE_PROT 28 /* R1b */
46 #define MMC_SET_CLR_WRITE_PROT 29 /* R1b */
47 #define MMC_SET_SEND_WRITE_PROT 30 /* R1 */
48 #define MMC_TAG_SECTOR_START 32 /* R1 */
49 #define MMC_TAG_SECTOR_END 33 /* R1 */
50 #define MMC_UNTAG_SECTOR 34 /* R1 */
51 #define MMC_TAG_ERASE_GROUP_START 35 /* R1 */
52 #define MMC_TAG_ERASE_GROUP_END 36 /* R1 */
53 #define MMC_UNTAG_ERASE_GROUP 37 /* R1 */
54 #define MMC_ERASE 38 /* R1b */
55 #define MMC_LOCK_UNLOCK 42 /* R1b */
56 #define MMC_APP_CMD 55 /* R1 */
57 #define MMC_READ_OCR 58 /* R3 */
58
59 /* SD commands */ /* response type */
60 #define SD_SEND_RELATIVE_ADDR 3 /* R6 */
61 #define SD_SEND_SWITCH_FUNC 6 /* R1 */
62 #define SD_SEND_IF_COND 8 /* R7 */
63 #define SD_VOLTAGE_SWITCH 11 /* R1 */
64 #define SD_ERASE_WR_BLK_START 32 /* R1 */
65 #define SD_ERASE_WR_BLK_END 33 /* R1 */
66
67 /* SD application commands */ /* response type */
68 #define SD_APP_SET_BUS_WIDTH 6 /* R1 */
69 #define SD_APP_SD_STATUS 13 /* R1 */
70 #define SD_APP_SET_WR_BLK_ERASE_COUNT 23 /* R1 */
71 #define SD_APP_OP_COND 41 /* R3 */
72 #define SD_APP_SEND_SCR 51 /* R1 */
73
74 /* SD erase arguments */
75 #define SD_ERASE_DISCARD 0x00000001
76 #define SD_ERASE_FULE 0x00000002
77
78 /* OCR bits */
79 #define MMC_OCR_MEM_READY (1U<<31)/* memory power-up status bit */
80 #define MMC_OCR_HCS (1<<30) /* SD only */
81 #define MMC_OCR_ACCESS_MODE_MASK (3<<29) /* MMC only */
82 #define MMC_OCR_ACCESS_MODE_BYTE (0<<29) /* MMC only */
83 #define MMC_OCR_ACCESS_MODE_SECTOR (2<<29) /* MMC only */
84 #define MMC_OCR_S18A (1<<24)
85 #define MMC_OCR_3_5V_3_6V (1<<23)
86 #define MMC_OCR_3_4V_3_5V (1<<22)
87 #define MMC_OCR_3_3V_3_4V (1<<21)
88 #define MMC_OCR_3_2V_3_3V (1<<20)
89 #define MMC_OCR_3_1V_3_2V (1<<19)
90 #define MMC_OCR_3_0V_3_1V (1<<18)
91 #define MMC_OCR_2_9V_3_0V (1<<17)
92 #define MMC_OCR_2_8V_2_9V (1<<16)
93 #define MMC_OCR_2_7V_2_8V (1<<15)
94 #define MMC_OCR_2_6V_2_7V (1<<14)
95 #define MMC_OCR_2_5V_2_6V (1<<13)
96 #define MMC_OCR_2_4V_2_5V (1<<12)
97 #define MMC_OCR_2_3V_2_4V (1<<11)
98 #define MMC_OCR_2_2V_2_3V (1<<10)
99 #define MMC_OCR_2_1V_2_2V (1<<9)
100 #define MMC_OCR_2_0V_2_1V (1<<8)
101 #define MMC_OCR_1_65V_1_95V (1<<7)
102
103 /* R1 response type bits */
104 #define MMC_R1_READY_FOR_DATA (1<<8) /* ready for next transfer */
105 #define MMC_R1_SWITCH_ERROR (1<<7) /* switch command failed */
106 #define MMC_R1_APP_CMD (1<<5) /* app. commands supported */
107
108 /* 48-bit response decoding (32 bits w/o CRC) */
109 #define MMC_R1(resp) ((resp)[0])
110 #define MMC_R3(resp) ((resp)[0])
111 #define SD_R6(resp) ((resp)[0])
112 #define MMC_R7(resp) ((resp)[0])
113 #define MMC_SPI_R1(resp) ((resp)[0])
114 #define MMC_SPI_R7(resp) ((resp)[1])
115
116 /* RCA argument and response */
117 #define MMC_ARG_RCA(rca) ((rca) << 16)
118 #define SD_R6_RCA(resp) (SD_R6((resp)) >> 16)
119
120 /* bus width argument */
121 #define SD_ARG_BUS_WIDTH_1 0
122 #define SD_ARG_BUS_WIDTH_4 2
123
124 /* EXT_CSD fields */
125 #define EXT_CSD_FLUSH_CACHE 32 /* W/E_P */
126 #define EXT_CSD_CACHE_CTRL 33 /* R/W/E_P */
127 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
128 #define EXT_CSD_BUS_WIDTH 183 /* W/E_P */
129 #define EXT_CSD_HS_TIMING 185 /* R/W/E_P */
130 #define EXT_CSD_REV 192 /* R */
131 #define EXT_CSD_STRUCTURE 194 /* R */
132 #define EXT_CSD_CARD_TYPE 196 /* R */
133 #define EXT_CSD_SEC_COUNT 212 /* R */
134 #define EXT_CSD_CACHE_SIZE 249 /* R (4 bytes) */
135
136 /* EXT_CSD field definitions */
137 #define EXT_CSD_CMD_SET_NORMAL (1U << 0)
138 #define EXT_CSD_CMD_SET_SECURE (1U << 1)
139 #define EXT_CSD_CMD_SET_CPSECURE (1U << 2)
140
141 /* EXT_CSD_FLUSH_CACHE */
142 #define EXT_CSD_FLUSH_CACHE_FLUSH (1U << 0)
143 #define EXT_CSD_FLUSH_CACHE_BARRIER (1U << 1)
144
145 /* EXT_CSD_CACHE_CTRL */
146 #define EXT_CSD_CACHE_CTRL_CACHE_EN (1U << 0)
147
148 /* EXT_CSD_BUS_WIDTH */
149 #define EXT_CSD_BUS_WIDTH_1 0 /* 1 bit mode */
150 #define EXT_CSD_BUS_WIDTH_4 1 /* 4 bit mode */
151 #define EXT_CSD_BUS_WIDTH_8 2 /* 8 bit mode */
152 #define EXT_CSD_BUS_WIDTH_4_DDR 5 /* 4 bit mode (DDR) */
153 #define EXT_CSD_BUS_WIDTH_8_DDR 6 /* 8 bit mode (DDR) */
154
155 /* EXT_CSD_HS_TIMING */
156 #define EXT_CSD_HS_TIMING_LEGACY 0
157 #define EXT_CSD_HS_TIMING_HIGHSPEED 1
158 #define EXT_CSD_HS_TIMING_HS200 2
159 #define EXT_CSD_HS_TIMING_HS400 3
160
161 /* EXT_CSD_STRUCTURE */
162 #define EXT_CSD_STRUCTURE_VER_1_0 0 /* CSD Version No.1.0 */
163 #define EXT_CSD_STRUCTURE_VER_1_1 1 /* CSD Version No.1.1 */
164 #define EXT_CSD_STRUCTURE_VER_1_2 2 /* Version 4.1-4.2-4.3 */
165
166 /* EXT_CSD_CARD_TYPE */
167 #define EXT_CSD_CARD_TYPE_F_26M (1 << 0) /* HS 26 MHz */
168 #define EXT_CSD_CARD_TYPE_F_52M (1 << 1) /* HS 52 MHz */
169 #define EXT_CSD_CARD_TYPE_F_DDR52_1_8V (1 << 2) /* HS DDR 52 MHz 1.8V or 3V */
170 #define EXT_CSD_CARD_TYPE_F_DDR52_1_2V (1 << 3) /* HS DDR 52 MHz 1.2V */
171 #define EXT_CSD_CARD_TYPE_F_HS200_1_8V (1 << 4) /* HS200 SDR 200 MHz 1.8V */
172 #define EXT_CSD_CARD_TYPE_F_HS200_1_2V (1 << 5) /* HS200 SDR 200 MHz 1.2V */
173 #define EXT_CSD_CARD_TYPE_F_HS400_1_8V (1 << 6) /* HS400 DDR 200 MHz 1.8V */
174 #define EXT_CSD_CARD_TYPE_F_HS400_1_2V (1 << 7) /* HS400 DDR 200 MHz 1.2V */
175
176 /* EXT_CSD_RST_N_FUNCTION */
177 #define EXT_CSD_RST_N_TMP_DISABLED 0x00
178 #define EXT_CSD_RST_N_PERM_ENABLED 0x01
179 #define EXT_CSD_RST_N_PERM_DISABLED 0x02
180 #define EXT_CSD_RST_N_MASK 0x03
181
182 /* MMC_SWITCH access mode */
183 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
184 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in value */
185 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in value */
186 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
187
188 /* SPI mode reports R1/R2(SEND_STATUS) status. */
189 #define R1_SPI_IDLE (1 << 0)
190 #define R1_SPI_ERASE_RESET (1 << 1)
191 #define R1_SPI_ILLEGAL_COMMAND (1 << 2)
192 #define R1_SPI_COM_CRC (1 << 3)
193 #define R1_SPI_ERASE_SEQ (1 << 4)
194 #define R1_SPI_ADDRESS (1 << 5)
195 #define R1_SPI_PARAMETER (1 << 6)
196 /* R1 bit 7 is always zero */
197 #define R2_SPI_CARD_LOCKED (1 << 8)
198 #define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
199 #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
200 #define R2_SPI_ERROR (1 << 10)
201 #define R2_SPI_CC_ERROR (1 << 11)
202 #define R2_SPI_CARD_ECC_ERROR (1 << 12)
203 #define R2_SPI_WP_VIOLATION (1 << 13)
204 #define R2_SPI_ERASE_PARAM (1 << 14)
205 #define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
206 #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
207
208 /* MMC R2 response (CSD) */
209 #define MMC_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
210 #define MMC_CSD_CSDVER_1_0 0
211 #define MMC_CSD_CSDVER_1_1 1
212 #define MMC_CSD_CSDVER_1_2 2 /* MMC 4.1 - 4.2 - 4.3 */
213 #define MMC_CSD_CSDVER_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
214 #define MMC_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4)
215 #define MMC_CSD_MMCVER_1_0 0 /* MMC 1.0 - 1.2 */
216 #define MMC_CSD_MMCVER_1_4 1 /* MMC 1.4 */
217 #define MMC_CSD_MMCVER_2_0 2 /* MMC 2.0 - 2.2 */
218 #define MMC_CSD_MMCVER_3_1 3 /* MMC 3.1 - 3.3 */
219 #define MMC_CSD_MMCVER_4_0 4 /* MMC 4.1 - 4.2 - 4.3 */
220 #define MMC_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8)
221 #define MMC_CSD_TAAC_MANT(resp) MMC_RSP_BITS((resp), 115, 4)
222 #define MMC_CSD_TAAC_EXP(resp) MMC_RSP_BITS((resp), 112, 3)
223 #define MMC_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8)
224 #define MMC_CSD_TRAN_SPEED(resp) MMC_RSP_BITS((resp), 96, 8)
225 #define MMC_CSD_TRAN_SPEED_MANT(resp) MMC_RSP_BITS((resp), 99, 4)
226 #define MMC_CSD_TRAN_SPEED_EXP(resp) MMC_RSP_BITS((resp), 96, 3)
227 #define MMC_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
228 #define MMC_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
229 #define MMC_CSD_CAPACITY(resp) ((MMC_CSD_C_SIZE((resp))+1) << \
230 (MMC_CSD_C_SIZE_MULT((resp))+2))
231 #define MMC_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
232 #define MMC_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3)
233 #define MMC_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4)
234
235 /* MMC v1 R2 response (CID) */
236 #define MMC_CID_MID_V1(resp) MMC_RSP_BITS((resp), 104, 24)
237 #define MMC_CID_PNM_V1_CPY(resp, pnm) \
238 do { \
239 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
240 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
241 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
242 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
243 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
244 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
245 (pnm)[6] = MMC_RSP_BITS((resp), 48, 8); \
246 (pnm)[7] = '\0'; \
247 } while (/*CONSTCOND*/0)
248 #define MMC_CID_REV_V1(resp) MMC_RSP_BITS((resp), 40, 8)
249 #define MMC_CID_PSN_V1(resp) MMC_RSP_BITS((resp), 16, 24)
250 #define MMC_CID_MDT_V1(resp) MMC_RSP_BITS((resp), 8, 8)
251
252 /* MMC v2 R2 response (CID) */
253 #define MMC_CID_MID_V2(resp) MMC_RSP_BITS((resp), 120, 8)
254 #define MMC_CID_OID_V2(resp) MMC_RSP_BITS((resp), 104, 16)
255 #define MMC_CID_PNM_V2_CPY(resp, pnm) \
256 do { \
257 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
258 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
259 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
260 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
261 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
262 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
263 (pnm)[6] = '\0'; \
264 } while (/*CONSTCOND*/0)
265 #define MMC_CID_PSN_V2(resp) MMC_RSP_BITS((resp), 16, 32)
266
267 /* SD R2 response (CSD) */
268 #define SD_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
269 #define SD_CSD_CSDVER_1_0 0
270 #define SD_CSD_CSDVER_2_0 1
271 #define SD_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4)
272 #define SD_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8)
273 #define SD_CSD_TAAC_EXP(resp) MMC_RSP_BITS((resp), 115, 4)
274 #define SD_CSD_TAAC_MANT(resp) MMC_RSP_BITS((resp), 112, 3)
275 #define SD_CSD_TAAC_1_5_MSEC 0x26
276 #define SD_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8)
277 #define SD_CSD_SPEED(resp) MMC_RSP_BITS((resp), 96, 8)
278 #define SD_CSD_SPEED_MANT(resp) MMC_RSP_BITS((resp), 99, 4)
279 #define SD_CSD_SPEED_EXP(resp) MMC_RSP_BITS((resp), 96, 3)
280 #define SD_CSD_SPEED_25_MHZ 0x32
281 #define SD_CSD_SPEED_50_MHZ 0x5a
282 #define SD_CSD_CCC(resp) MMC_RSP_BITS((resp), 84, 12)
283 #define SD_CSD_CCC_BASIC (1 << 0) /* basic */
284 #define SD_CSD_CCC_BR (1 << 2) /* block read */
285 #define SD_CSD_CCC_BW (1 << 4) /* block write */
286 #define SD_CSD_CCC_ERACE (1 << 5) /* erase */
287 #define SD_CSD_CCC_WP (1 << 6) /* write protection */
288 #define SD_CSD_CCC_LC (1 << 7) /* lock card */
289 #define SD_CSD_CCC_AS (1 << 8) /*application specific*/
290 #define SD_CSD_CCC_IOM (1 << 9) /* I/O mode */
291 #define SD_CSD_CCC_SWITCH (1 << 10) /* switch */
292 #define SD_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
293 #define SD_CSD_READ_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 79, 1)
294 #define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1)
295 #define SD_CSD_READ_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 77, 1)
296 #define SD_CSD_DSR_IMP(resp) MMC_RSP_BITS((resp), 76, 1)
297 #define SD_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
298 #define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \
299 (SD_CSD_C_SIZE_MULT((resp))+2))
300 #define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3)
301 #define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3)
302 #define SD_CSD_VDD_W_CURR_MIN(resp) MMC_RSP_BITS((resp), 53, 3)
303 #define SD_CSD_VDD_W_CURR_MAX(resp) MMC_RSP_BITS((resp), 50, 3)
304 #define SD_CSD_VDD_RW_CURR_100mA 0x7
305 #define SD_CSD_VDD_RW_CURR_80mA 0x6
306 #define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22)
307 #define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10)
308 #define SD_CSD_V2_BL_LEN 0x9 /* 512 */
309 #define SD_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
310 #define SD_CSD_ERASE_BLK_EN(resp) MMC_RSP_BITS((resp), 46, 1)
311 #define SD_CSD_SECTOR_SIZE(resp) MMC_RSP_BITS((resp), 39, 7) /* +1 */
312 #define SD_CSD_WP_GRP_SIZE(resp) MMC_RSP_BITS((resp), 32, 7) /* +1 */
313 #define SD_CSD_WP_GRP_ENABLE(resp) MMC_RSP_BITS((resp), 31, 1)
314 #define SD_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3)
315 #define SD_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4)
316 #define SD_CSD_RW_BL_LEN_2G 0xa
317 #define SD_CSD_RW_BL_LEN_1G 0x9
318 #define SD_CSD_WRITE_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 21, 1)
319 #define SD_CSD_FILE_FORMAT_GRP(resp) MMC_RSP_BITS((resp), 15, 1)
320 #define SD_CSD_COPY(resp) MMC_RSP_BITS((resp), 14, 1)
321 #define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1)
322 #define SD_CSD_TMP_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 12, 1)
323 #define SD_CSD_FILE_FORMAT(resp) MMC_RSP_BITS((resp), 10, 2)
324
325 /* SD R2 response (CID) */
326 #define SD_CID_MID(resp) MMC_RSP_BITS((resp), 120, 8)
327 #define SD_CID_OID(resp) MMC_RSP_BITS((resp), 104, 16)
328 #define SD_CID_PNM_CPY(resp, pnm) \
329 do { \
330 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
331 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
332 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
333 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
334 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
335 (pnm)[5] = '\0'; \
336 } while (/*CONSTCOND*/0)
337 #define SD_CID_REV(resp) MMC_RSP_BITS((resp), 56, 8)
338 #define SD_CID_PSN(resp) MMC_RSP_BITS((resp), 24, 32)
339 #define SD_CID_MDT(resp) MMC_RSP_BITS((resp), 8, 12)
340
341 /* SCR (SD Configuration Register) */
342 #define SCR_STRUCTURE(scr) MMC_RSP_BITS((scr), 60, 4)
343 #define SCR_STRUCTURE_VER_1_0 0 /* Version 1.0 */
344 #define SCR_SD_SPEC(scr) MMC_RSP_BITS((scr), 56, 4)
345 #define SCR_SD_SPEC_VER_1_0 0 /* Version 1.0 and 1.01 */
346 #define SCR_SD_SPEC_VER_1_10 1 /* Version 1.10 */
347 #define SCR_SD_SPEC_VER_2 2 /* Version 2.00 or Version 3.0X */
348 #define SCR_DATA_STAT_AFTER_ERASE(scr) MMC_RSP_BITS((scr), 55, 1)
349 #define SCR_SD_SECURITY(scr) MMC_RSP_BITS((scr), 52, 3)
350 #define SCR_SD_SECURITY_NONE 0 /* no security */
351 #define SCR_SD_SECURITY_1_0 1 /* security protocol 1.0 */
352 #define SCR_SD_SECURITY_1_0_2 2 /* security protocol 1.0 */
353 #define SCR_SD_BUS_WIDTHS(scr) MMC_RSP_BITS((scr), 48, 4)
354 #define SCR_SD_BUS_WIDTHS_1BIT (1 << 0) /* 1bit (DAT0) */
355 #define SCR_SD_BUS_WIDTHS_4BIT (1 << 2) /* 4bit (DAT0-3) */
356 #define SCR_SD_SPEC3(scr) MMC_RSP_BITS((scr), 47, 1)
357 #define SCR_EX_SECURITY(scr) MMC_RSP_BITS((scr), 43, 4)
358 #define SCR_RESERVED(scr) MMC_RSP_BITS((scr), 34, 9)
359 #define SCR_CMD_SUPPORT_CMD23(scr) MMC_RSP_BITS((scr), 33, 1)
360 #define SCR_CMD_SUPPORT_CMD20(scr) MMC_RSP_BITS((scr), 32, 1)
361 #define SCR_RESERVED2(scr) MMC_RSP_BITS((scr), 0, 32)
362
363 /* SSR (SD Status Register) */
364 #define SSR_DAT_BUS_WIDTH(resp) __bitfield((resp), 510, 2)
365 #define SSR_DAT_BUS_WIDTH_1 0
366 #define SSR_DAT_BUS_WIDTH_4 2
367 #define SSR_SECURED_MODE(resp) __bitfield((resp), 509, 1)
368 #define SSR_SD_CARD_TYPE(resp) __bitfield((resp), 480, 16)
369 #define SSR_SD_CARD_TYPE_RDWR 0
370 #define SSR_SD_CARD_TYPE_ROM 1
371 #define SSR_SD_CARD_TYPE_OTP 2
372 #define SSR_SIZE_OF_PROTECTED_AREA(resp) __bitfield((resp), 448, 32)
373 #define SSR_SPEED_CLASS(resp) __bitfield((resp), 440, 8)
374 #define SSR_SPEED_CLASS_0 0
375 #define SSR_SPEED_CLASS_2 1
376 #define SSR_SPEED_CLASS_4 2
377 #define SSR_SPEED_CLASS_6 3
378 #define SSR_SPEED_CLASS_10 4
379 #define SSR_PERFORMANCE_MOVE(resp) __bitfield((resp), 432, 8)
380 #define SSR_AU_SIZE(resp) __bitfield((resp), 428, 4)
381 #define SSR_ERASE_SIZE(resp) __bitfield((resp), 408, 16)
382 #define SSR_ERASE_TIMEOUT(resp) __bitfield((resp), 402, 6)
383 #define SSR_ERASE_OFFSET(resp) __bitfield((resp), 400, 2)
384 #define SSR_UHS_SPEED_GRADE(resp) __bitfield((resp), 396, 4)
385 #define SSR_UHS_SPEED_GRADE_10MB 1
386 #define SSR_UHS_SPEED_GRADE_30MB 3
387 #define SSR_UHS_AU_SIZE(resp) __bitfield((resp), 392, 4)
388 #define SSR_VIDEO_SPEED_CLASS(resp) __bitfield((resp), 384, 8)
389 #define SSR_VSC_AU_SIZE(resp) __bitfield((resp), 368, 10)
390 #define SSR_SUS_ADDR(resp) __bitfield((resp), 346, 22)
391 #define SSR_APP_PERF_CLASS(resp) __bitfield((resp), 336, 4)
392 #define SSR_APP_PERF_CLASS_UNSUPPORTED 0
393 #define SSR_APP_PERF_CLASS_A1 1
394 #define SSR_APP_PERF_CLASS_A2 2
395 #define SSR_PERFORMANCE_ENHANCE(resp) __bitfield((resp), 328, 8)
396 #define SSR_DISCARD_SUPPORT(resp) __bitfield((resp), 313, 1)
397 #define SSR_FULE_SUPPORT(resp) __bitfield((resp), 312, 1)
398
399 /* Status of Switch Function */
400 #define SFUNC_STATUS_GROUP(status, group) \
401 (__bitfield((uint32_t *)(status), 400 + (group - 1) * 16, 16))
402
403 #define SD_ACCESS_MODE_SDR12 0
404 #define SD_ACCESS_MODE_SDR25 1
405 #define SD_ACCESS_MODE_SDR50 2
406 #define SD_ACCESS_MODE_SDR104 3
407 #define SD_ACCESS_MODE_DDR50 4
408
409 /* This assumes the response fields are in host byte order in 32-bit units. */
410 #define MMC_RSP_BITS(resp, start, len) __bitfield((resp), (start)-8, (len))
411 static __inline uint32_t
__bitfield(const uint32_t * src,size_t start,size_t len)412 __bitfield(const uint32_t *src, size_t start, size_t len)
413 {
414 if (start + len > 512 || len == 0 || len > 32)
415 return 0;
416
417 src += start / 32;
418 start %= 32;
419
420 uint32_t dst = src[0] >> start;
421
422 if (__predict_false((start + len - 1) / 32 != start / 32)) {
423 dst |= src[1] << (32 - start);
424 }
425
426 return dst & (__BIT(len) - 1);
427 }
428
429 #endif /* _SDMMCREG_H_ */
430