1 /* Definitions of target machine for GNU compiler. MIPS version. 2 Contributed by A. Lichnewsky, lich@inria.inria.fr 3 Copyright (C) 1989 Free Software Foundation, Inc. 4 5 This file is part of GNU CC. 6 7 GNU CC is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 1, or (at your option) 10 any later version. 11 12 GNU CC is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GNU CC; see the file COPYING. If not, write to 19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ 20 21 /* ??? This file needs to be reformatted so that it looks like the 22 rest of GCC. ??? */ 23 24 /* Currently we know of 2 MIPS machines: MIPS- M series, and DECStations. */ 25 /* Therefore we discriminate by declaring DECStations with */ 26 /* #define DECSTATION */ 27 28 /* Names to predefine in the preprocessor for this target machine. */ 29 30 #define CPP_PREDEFINES "-Dmips -Dunix" 31 #ifdef DECSTATION 32 #define CPP_SPEC "-DR3000 -DLANGUAGE_C -DMIPSEL -DSYSTYPE_BSD " 33 #else 34 #define CPP_SPEC "-DR3000 -Dhost_mips -DMIPSEB -DSYSTYPE_BSD -DLANGUAGE_C " 35 #endif 36 37 /*---------------------------------------------------------------------- 38 39 SWITCHES: 40 41 -O optimization. Implies -fstrength-reduce -fomit-frame-pointer 42 -O2 optimization. Implies -O 43 44 Tries to make use of short displacements using the 45 Sdata and Sbss sections. This uses the -G switches of as and ld. 46 47 -G <size> 48 Pass size to as and ld. Default -G 8. 49 50 -mG0 -mG1 -mG2 51 Construct a size to be passed to GCC for Data / Sdata selection. 52 53 Value is ( (i=G0 + 2 G1 + 4 G2) , (i < 6) ? ( 1<<i) :(1 <<(i+3))) 54 Same value should be passed to as + ld using -G. 55 56 Default = -mG1 -mG0 (Value = 8). 57 58 -G32 Implies -G 32 -mG2 -mnG1 -mG0. 59 60 61 -bestGnum 62 Pass -bestGnum flag to ld. This helps setting best value for 63 the -G parameter. 64 65 ----------------------------------------------------------------------*/ 66 67 68 69 /*********************************************************************** 70 71 WARNING: 72 73 No attempt to select (configure) the -B and -I parameters has been 74 made inside this version of gcc. They should be made (eg. thru a 75 shell script). 76 77 -I should be set in such a way that the include file "va-mips.h" 78 gets included (via "varargs.h") for varargs. Otherwise gcc will not 79 bootstrap -- and produce wrong code for varargs. 80 81 82 ***********************************************************************/ 83 84 85 /* Switch Recognition by gcc.c */ 86 87 #ifdef SWITCH_TAKES_ARG 88 #undef SWITCH_TAKES_ARG 89 #endif 90 91 #define SWITCH_TAKES_ARG(CHAR) \ 92 ((CHAR) == 'D' || (CHAR) == 'U' || (CHAR) == 'o' \ 93 || (CHAR) == 'e' || (CHAR) == 'T' || (CHAR) == 'u' \ 94 || (CHAR) == 'I' || (CHAR) == 'Y' || (CHAR) == 'm' \ 95 || (CHAR) == 'L' || (CHAR) == 'G') 96 97 98 99 100 /* Extra switches sometimes passed to the assembler. */ 101 102 #define ASM_SPEC "%{O:-O2} %{O2: -O2} %{!G32: %{G*}} \ 103 %{!G:%{!G32: -G 8}} %{G32: -G 32}" 104 105 106 /* Extra switches sometimes passed to the loader. */ 107 108 109 #define LINK_SPEC "%{!G32:%{G*} \ 110 %{!G:%{!G32:%{mG0:%eYou should include ld/as option -G} \ 111 %{mG1:%eYou should include ld/as option -G} \ 112 %{mG2:%eYou should include ld/as option -G} \ 113 -G 8}}} \ 114 %{G32: -G 32} \ 115 %{bestGnum: -bestGnum} " 116 117 /* CC1 SPECS */ 118 119 #define CC1_SPEC "%{!O2:%{O:-O -fstrength-reduce -fomit-frame-pointer}}\ 120 %{O2:-O -fstrength-reduce -fomit-frame-pointer -mgpOPT}\ 121 %{g:%eThis port of GCC does not support -g flag} \ 122 %{G32: -mG2 -mnG1 } \ 123 %{G32:%{!O2:%eOption -G32 may require -O2}}" 124 125 126 /* Print subsidiary information on the compiler version in use. */ 127 128 #ifdef DECSTATION 129 #define TARGET_VERSION printf (" (AL-MIPS 1.10) <DECStation>\n"); 130 /* Depends on MIPS ASM. */ 131 #else 132 #define TARGET_VERSION printf (" (AL-MIPS 1.10) <MIPS>\n"); 133 /* Depends on MIPS ASM. */ 134 #endif 135 #define TARGET_VERSNUM "1 10" 136 137 /* Do not Generate DBX debugging information. */ 138 139 /* #define DBX_DEBUGGING_INFO */ 140 141 /* Run-time compilation parameters selecting different hardware subsets. */ 142 143 extern int target_flags; 144 145 /* Macros used in the machine description to test the flags. */ 146 147 /* Nonzero if compiling code that Unix assembler can assemble. */ 148 #define TARGET_UNIX_ASM (target_flags & 1) 149 /* Debug Mode */ 150 #define TARGET_DEBUG_MODE (target_flags & 2) 151 #define TARGET_DEBUGA_MODE (target_flags & 4) 152 #define TARGET_DEBUGB_MODE (target_flags & 16) 153 #define TARGET_DEBUGC_MODE (target_flags & 32) 154 #define TARGET_DEBUGD_MODE (target_flags & 64) 155 /* Register Naming in .s ($21 vs. $a0) */ 156 #define TARGET_NAME_REGS (target_flags & 8) 157 /* Use addu / subbu or get FIXED_OVFL TRAPS */ 158 #define TARGET_NOFIXED_OVFL (target_flags & 128) 159 /* Optimize for Sdata/Sbss */ 160 #define TARGET_GP_OPT (target_flags & 4096) 161 #define TARGET_GVALUE ((target_flags >> 8 ) & 0xf) 162 163 164 165 /* Macro to define tables used to set the flags. 166 This is a list in braces of pairs in braces, 167 each pair being { "NAME", VALUE } 168 where VALUE is the bits to set or minus the bits to clear. 169 An empty string NAME is used to identify the default VALUE. */ 170 171 #define TARGET_SWITCHES \ 172 { {"unix", 1}, \ 173 {"gnu", -1}, \ 174 {"debug", 2 }, /* RELOAD and CONSTRAINTS Related DEBUG */\ 175 {"nodebug", -2 }, \ 176 {"debuga", 4 }, /* CALLING SEQUENCE RELATED DEBUG */ \ 177 {"nodebuga", -4 }, \ 178 {"debugb", 16 }, /* GLOBAL/LOCAL ALLOC DEBUG */ \ 179 {"nodebugb", -16 }, \ 180 {"debugc", 32 }, /* SPILL/RELOAD REGISTER ALLOCATOR DEBUG */\ 181 {"nodebugc", -32 }, \ 182 {"debugd", 64 }, /* CSE DEBUG */ \ 183 {"nodebugd", -64 }, \ 184 {"rnames", 8 }, /* Output register names like $a0 */ \ 185 {"nornames", -8 }, /* Output register numbers like $21 */ \ 186 {"nofixed-ovfl",128}, /* use addu and subu */ \ 187 {"fixed-ovfl", -128}, /* use add and sub */ \ 188 /* Following used to support the data/sdata */\ 189 /* feature */ \ 190 {"G0",256}, \ 191 {"nG0",-256}, \ 192 {"G1",512}, \ 193 {"nG1",-512}, \ 194 {"G2",1024}, \ 195 {"nG2",-1024}, \ 196 {"gpOPT", 4096}, /* DO the full GP optimization data/sdata.. */\ 197 {"ngpOPT", -4096},\ 198 { "", TARGET_DEFAULT}} 199 200 /* Default target_flags if no switches specified. */ 201 202 #define TARGET_DEFAULT 897 203 204 /* Default GVALUE (data item size threshold for selection of Sdata/data) 205 is computed : GVALUE == ( ((i=G0+2*G1+4*G2) < 6) 206 ? 1<<i 207 : 1<< (i+6)) 208 */ 209 #define MIPS_GVALUE_DEFAULT 8 210 211 /* Target machine storage layout */ 212 213 /* Define this if most significant bit is lowest numbered 214 in instructions that operate on numbered bit-fields. 215 */ 216 /* #define BITS_BIG_ENDIAN */ 217 218 /* Define this if most significant byte of a word is the lowest numbered. 219 */ 220 #ifndef DECSTATION 221 #define BYTES_BIG_ENDIAN 222 #endif 223 /* Define this if most significant word of a multiword number is numbered. 224 */ 225 #ifndef DECSTATION 226 #define WORDS_BIG_ENDIAN 227 #endif 228 /* Number of bits in an addressible storage unit */ 229 #define BITS_PER_UNIT 8 230 231 /* Width in bits of a "word", which is the contents of a machine register. 232 Note that this is not necessarily the width of data type `int'; 233 if using 16-bit ints on a 68000, this would still be 32. 234 But on a machine with 16-bit registers, this would be 16. */ 235 #define BITS_PER_WORD 32 236 237 /* Width of a word, in units (bytes). */ 238 #define UNITS_PER_WORD 4 239 240 /* Width in bits of a pointer. 241 See also the macro `Pmode' defined below. */ 242 #define POINTER_SIZE 32 243 244 /* Allocation boundary (in *bits*) for storing pointers in memory. */ 245 #define POINTER_BOUNDARY 32 246 247 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 248 #define PARM_BOUNDARY 32 249 250 /* Give parms extra alignment, up to this much, if their types want it. */ 251 #define MAX_PARM_BOUNDARY 64 252 253 /* Allocation boundary (in *bits*) for the code of a function. */ 254 #define FUNCTION_BOUNDARY 32 255 256 /* Alignment of field after `int : 0' in a structure. */ 257 #define EMPTY_FIELD_BOUNDARY 32 258 259 /* Every structure's size must be a multiple of this. */ 260 #define STRUCTURE_SIZE_BOUNDARY 16 261 262 /* There is no point aligning anything to a rounder boundary than this. */ 263 #define BIGGEST_ALIGNMENT 64 264 265 /* Define this if move instructions will actually fail to work 266 when given unaligned data. */ 267 #define STRICT_ALIGNMENT 268 269 /* Standard register usage. */ 270 271 /* Number of actual hardware registers. 272 The hardware registers are assigned numbers for the compiler 273 from 0 to just below FIRST_PSEUDO_REGISTER. 274 All registers that the compiler knows about must be given numbers, 275 even those that are not normally considered general registers. */ 276 #define FIRST_PSEUDO_REGISTER 64 277 278 /* 1 for registers that have pervasive standard uses 279 and are not available for the register allocator. 280 281 On the MIPS, see conventions, page D-2 282 283 I have chosen not to take Multiply/Divide HI,LO or PC into 284 account. 285 */ 286 #define FIXED_REGISTERS {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\ 287 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1,\ 288 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,\ 289 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \ 290 } 291 292 293 /* 1 for registers not available across function calls. 294 These must include the FIXED_REGISTERS and also any 295 registers that can be used without being saved. 296 The latter must include the registers where values are returned 297 and the register where structure-value addresses are passed. 298 Aside from that, you can include as many other registers as you like. */ 299 #define CALL_USED_REGISTERS {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\ 300 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1,\ 301 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\ 302 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0\ 303 } 304 305 306 /* Return number of consecutive hard regs needed starting at reg REGNO 307 to hold something of mode MODE. 308 This is ordinarily the length in words of a value of mode MODE 309 but can be less for certain modes in special long registers. 310 311 On the MIPS, all general registers are one word long. I have chosen to 312 use Floating point register pairs. 313 */ 314 #define HARD_REGNO_NREGS(REGNO, MODE) \ 315 (((MODE == SFmode) ||(MODE == DFmode)) ? 2 : \ 316 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 317 318 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 319 On the MIPS, all general registers can hold all modes, except 320 FLOATING POINT. */ 321 322 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 323 ((REGNO) < 32 ? (int) (((MODE) != SFmode) && ((MODE) != DFmode)) \ 324 : (int) (((MODE) == SFmode || (MODE) == DFmode) \ 325 && ((REGNO) & 1) == 0)) 326 327 328 /* Value is 1 if it is a good idea to tie two pseudo registers 329 when one has mode MODE1 and one has mode MODE2. 330 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 331 for any hard reg, then this must be 0 for correct output. */ 332 #define MODES_TIEABLE_P(MODE1, MODE2) \ 333 ( ((MODE1) == SFmode || (MODE1) == DFmode) \ 334 == ((MODE2) == SFmode || (MODE2) == DFmode)) 335 336 /* MIPS pc is apparently not overloaded on a register. */ 337 /* #define PC_REGNUM 15 */ 338 339 /* Register to use for pushing function arguments. */ 340 #define STACK_POINTER_REGNUM 29 341 342 /* Base register for access to local variables of the function. */ 343 #define FRAME_POINTER_REGNUM 30 344 345 /* Value should be nonzero if functions must have frame pointers. 346 Zero means the frame pointer need not be set up (and parms 347 may be accessed via the stack pointer) in functions that seem suitable. 348 This is computed in `reload', in reload1.c. */ 349 350 /* This is now 1 because we don't know until too late 351 whether the function is a varargs function. 352 Such functions currently require extra stack slots on the mips. */ 353 #define FRAME_POINTER_REQUIRED 1 354 355 /* Base register for access to arguments of the function. */ 356 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 357 358 /* Register in which static-chain is passed to a function. */ 359 #define STATIC_CHAIN_REGNUM 2 360 361 /* Register in which address to store a structure value 362 is passed to a function. */ 363 #define STRUCT_VALUE_REGNUM 3 364 365 /* Define the classes of registers for register constraints in the 366 machine description. Also define ranges of constants. 367 368 One of the classes must always be named ALL_REGS and include all hard regs. 369 If there is more than one class, another class must be named NO_REGS 370 and contain no registers. 371 372 The name GENERAL_REGS must be the name of a class (or an alias for 373 another name such as ALL_REGS). This is the class of registers 374 that is allowed by "g" or "r" in a register constraint. 375 Also, registers outside this class are allocated only when 376 instructions express preferences for them. 377 378 The classes must be numbered in nondecreasing order; that is, 379 a larger-numbered class must never be contained completely 380 in a smaller-numbered class. 381 382 For any two classes, it is very desirable that there be another 383 class that represents their union. */ 384 385 /* The MIPS has general and floating point registers, 386 */ 387 388 389 enum reg_class { NO_REGS, GR_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES } ; 390 391 #define N_REG_CLASSES (int) LIM_REG_CLASSES 392 393 #define GENERAL_REGS GR_REGS 394 395 /* Give names of register classes as strings for dump file. */ 396 397 #define REG_CLASS_NAMES \ 398 {"NO_REGS", "GR_REGS", "FP_REGS", "ALL_REGS" } 399 400 /* Define which registers fit in which classes. 401 This is an initializer for a vector of HARD_REG_SET 402 of length N_REG_CLASSES. */ 403 404 #define REG_CLASS_CONTENTS {{0x00000000, 0x00000000}, \ 405 {0xffffffff, 0x00000000}, \ 406 {0x00000000, 0xffffffff}, \ 407 {0xffffffff, 0xffffffff}} 408 409 410 /* The same information, inverted: 411 Return the class number of the smallest class containing 412 reg number REGNO. This could be a conditional expression 413 or could index an array. */ 414 415 #define REGNO_REG_CLASS(REGNO) \ 416 ( (REGNO >= 32) ? FP_REGS : GR_REGS) 417 418 /* Define a table that lets us find quickly all the reg classes 419 containing a given one. This is the initializer for an 420 N_REG_CLASSES x N_REG_CLASSES array of reg class codes. 421 Row N is a sequence containing all the class codes for 422 classes that contain all the regs in class N. Each row 423 contains no duplicates, and is terminated by LIM_REG_CLASSES. */ 424 425 /* We give just a dummy for the first element, which is for NO_REGS. */ 426 /* #define REG_CLASS_SUPERCLASSES {{LIM_REG_CLASSES}, \ 427 {GR_REGS,ALL_REGS,LIM_REG_CLASSES}, \ 428 {FP_REGS,ALL_REGS,LIM_REG_CLASSES}, \ 429 {ALL_REGS,LIM_REG_CLASSES} \ 430 } 431 */ 432 /* We give just a dummy for the first element, which is for NO_REGS. */ 433 #define REG_CLASS_SUPERCLASSES {{LIM_REG_CLASSES}, \ 434 {ALL_REGS,LIM_REG_CLASSES}, \ 435 {ALL_REGS,LIM_REG_CLASSES}, \ 436 {LIM_REG_CLASSES} \ 437 } 438 439 /* The inverse relationship: 440 for each class, a list of all reg classes contained in it. */ 441 #define REG_CLASS_SUBCLASSES \ 442 {{LIM_REG_CLASSES}, \ 443 {GR_REGS,LIM_REG_CLASSES}, \ 444 {FP_REGS,LIM_REG_CLASSES},\ 445 {GR_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES}\ 446 } 447 448 /* Define a table that lets us find quickly the class 449 for the subunion of any two classes. 450 451 We say "subunion" because the result need not be exactly 452 the union; it may instead be a subclass of the union 453 (though the closer to the union, the better). 454 But if it contains anything beyond union of the two classes, 455 you will lose! 456 457 This is an initializer for an N_REG_CLASSES x N_REG_CLASSES 458 array of reg class codes. The subunion of classes C1 and C2 459 is just element [C1, C2]. */ 460 461 #define REG_CLASS_SUBUNION {{NO_REGS, GR_REGS, FP_REGS, ALL_REGS}, \ 462 {GR_REGS, GR_REGS, ALL_REGS, ALL_REGS}, \ 463 {FP_REGS, ALL_REGS, FP_REGS, ALL_REGS}, \ 464 {ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS}} 465 466 /* The class value for index registers, and the one for base regs. */ 467 468 #define INDEX_REG_CLASS GR_REGS 469 #define BASE_REG_CLASS GR_REGS 470 471 472 /* REGISTER AND CONSTANT CLASSES 473 */ 474 475 /* Get reg_class from a letter such as appears in the machine 476 description. */ 477 /* DEFINED REGISTER CLASSES: 478 ** 479 ** 'f' : Floating point registers 480 ** 'y' : General register when used to 481 ** transfer chunks of Floating point 482 ** with mfc1 mtc1 insn 483 */ 484 485 #define REG_CLASS_FROM_LETTER(C) \ 486 ((C) == 'f' ? FP_REGS: \ 487 (C) == 'y' ? GR_REGS:NO_REGS) 488 489 /* The letters I, J, K, L and M in a register constraint string 490 can be used to stand for particular ranges of immediate operands. 491 This macro defines what the ranges are. 492 C is the letter, and VALUE is a constant value. 493 Return 1 if VALUE is in the range specified by C. */ 494 495 /* For MIPS, `I' is used for the range of constants an insn 496 can actually contain (16 bits signed integers). 497 `J' is used for the range which is just zero (since that is 498 available as $R0). 499 */ 500 501 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x10000) < 0x20000) 502 503 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 504 ((C) == 'I' ? (unsigned) ((VALUE) + 0x10000) < 0x20000 \ 505 : (C) == 'J' ? (VALUE) == 0 \ 506 : 0) 507 508 /* Similar, but for floating constants, and defining letters G and H. 509 Here VALUE is the CONST_DOUBLE rtx itself. */ 510 511 /* DEFINED FLOATING CONSTANT CLASSES: 512 ** 513 ** 'G' : Floating point 0 514 */ 515 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 516 ((C) == 'G' && XINT (VALUE, 0) == 0 && XINT (VALUE, 1) == 0) 517 518 /* Given an rtx X being reloaded into a reg required to be 519 in class CLASS, return the class of reg to actually use. 520 In general this is just CLASS; but on some machines 521 in some cases it is preferable to use a more restrictive class. */ 522 523 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 524 (((GET_MODE(X) == SFmode) || (GET_MODE(X) == DFmode))? FP_REGS : \ 525 ((GET_MODE(X) == VOIDmode) ? GR_REGS :(CLASS))) 526 527 /* Same but Mode has been extracted already 528 */ 529 530 #define PREFERRED_RELOAD_CLASS_FM(X,CLASS) \ 531 ((((X) == SFmode) || ((X) == DFmode))? FP_REGS : \ 532 (((X) == VOIDmode) ? GR_REGS :(CLASS))) 533 534 /* Return the maximum number of consecutive registers 535 needed to represent mode MODE in a register of class CLASS. */ 536 537 #define CLASS_MAX_NREGS(CLASS, MODE) \ 538 ((((MODE) == DFmode) || ((MODE) == SFmode)) ? 2 \ 539 : ((MODE) == VOIDmode)? ((CLASS) == FP_REGS ? 2 :1) \ 540 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 541 542 543 /* Stack layout; function entry, exit and calling. */ 544 545 /* Define this if pushing a word on the stack 546 makes the stack pointer a smaller address. */ 547 #define STACK_GROWS_DOWNWARD 548 549 /* Define this if the nominal address of the stack frame 550 is at the high-address end of the local variables; 551 that is, each additional local variable allocated 552 goes at a more negative offset in the frame. */ 553 #define FRAME_GROWS_DOWNWARD 554 555 /* Offset within stack frame to start allocating local variables at. 556 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 557 first local allocated. Otherwise, it is the offset to the BEGINNING 558 of the first local allocated. */ 559 #define STARTING_FRAME_OFFSET -4 560 561 /* If we generate an insn to push BYTES bytes, 562 this says how many the stack pointer really advances by. 563 On the vax, sp@- in a byte insn really pushes a word. */ 564 565 /* #define PUSH_ROUNDING(BYTES) 0 */ 566 567 568 /* Offset of first parameter from the argument pointer register value. */ 569 #define FIRST_PARM_OFFSET(FNDECL) 0 570 571 /* Offset from top-of-stack address to location to store the 572 function parameter if it can't go in a register. 573 Addresses for following parameters are computed relative to this one. */ 574 #define FIRST_PARM_CALLER_OFFSET(FNDECL) 0 575 576 /* When a parameter is passed in a register, stack space is still 577 allocated for it. */ 578 /* For the MIPS, stack space must be allocated, cf Asm Lang Prog Guide 579 page 7-8 580 581 BEWARE that some space is also allocated for non existing arguments 582 in register. In case an argument list is of form 583 GF used registers are a0 (a2,a3), but we should push over a1... not 584 used.. 585 */ 586 #define REG_PARM_STACK_SPACE 587 /* Align stack frames on 64 bits (Double Word ) 588 */ 589 590 #define STACK_BOUNDARY 64 591 592 /* For the MIPS, there seems to be a minimum to the amount of stack space 593 used... for varargs using functions. 594 evidence comes from the dis-assembled version of printf: 595 596 cc (cc) 597 Mips Computer Systems 1.31 598 /usr/lib/cpp1.31 599 600 601 printf: 602 [printf.c: 14] 0x400510: 27bdffe8 addiu sp,sp,-24 603 [printf.c: 14] 0x400514: afbf0014 sw ra,20(sp) 604 [printf.c: 14] 0x400518: afa5001c sw a1,28(sp) 605 [printf.c: 14] 0x40051c: afa60020 sw a2,32(sp) 606 [printf.c: 14] 0x400520: afa70024 sw a3,36(sp) 607 [printf.c: 18] 0x400524: 27a5001c addiu a1,sp,28 608 609 it is however OK for functions that do not take arguments to have 0 size 610 frames. 611 612 */ 613 614 #define STACK_ARGS_ADJUST(SIZE) \ 615 { \ 616 SIZE.constant += 4; \ 617 if (SIZE.var) \ 618 { \ 619 rtx size1 = ARGS_SIZE_RTX (SIZE); \ 620 rtx rounded = gen_reg_rtx (SImode); \ 621 rtx label = gen_label_rtx (); \ 622 emit_move_insn (rounded, size1); \ 623 /* Needed: insns to jump to LABEL if ROUNDED is < 16. */ \ 624 abort (); \ 625 emit_move_insn (rounded, gen_rtx (CONST_INT, VOIDmode, 16)); \ 626 emit_label (label); \ 627 SIZE.constant = 0; \ 628 SIZE.var = (tree) rounded; \ 629 } \ 630 else if (SIZE.constant < 16) \ 631 SIZE.constant = 16; \ 632 } 633 634 /* Value is 1 if returning from a function call automatically 635 pops the arguments described by the number-of-args field in the call. 636 FUNTYPE is the data type of the function (as a tree), 637 or for a library call it is an identifier node for the subroutine name. */ 638 639 #define RETURN_POPS_ARGS(FUNTYPE) 0 640 641 642 /* Define how to find the value returned by a function. 643 VALTYPE is the data type of the value (as a tree). 644 If the precise function being called is known, FUNC is its FUNCTION_DECL; 645 otherwise, FUNC is 0. */ 646 647 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 648 gen_rtx (REG, TYPE_MODE (VALTYPE), \ 649 (TYPE_MODE (VALTYPE) == SFmode) ||(TYPE_MODE (VALTYPE) == DFmode)?32 : 2) 650 651 /* Define how to find the value returned by a library function 652 assuming the value has mode MODE. */ 653 654 655 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, \ 656 ((MODE) == DFmode || ( MODE) == SFmode) ? 32 : 2) 657 658 /* 1 if N is a possible register number for a function value. 659 On the MIPS, R2 R3 and F0 F2 are the only register thus used. */ 660 /* Currently, R2 and F0 are only implemented here ( C has no complex type) 661 */ 662 663 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 32) 664 665 /* 1 if N is a possible register number for function argument passing. 666 */ 667 668 #define FUNCTION_ARG_REGNO_P(N) (((N) < 8 && (N) > 3) \ 669 ||((N) < 48 && (N) > 44 && (0 == (N) % 2))) 670 671 /* Define a data type for recording info about an argument list 672 during the scan of that argument list. This data type should 673 hold all necessary information about the function itself 674 and about the args processed so far, enough to enable macros 675 such as FUNCTION_ARG to determine where the next arg should go. 676 */ 677 /* On MIPS the following automaton decides */ 678 /* where to put things. */ 679 /* If you dont believe it, look at Gerry Kane*/ 680 /* 's book page D-22 */ 681 682 #define CUMULATIVE_ARGS struct { enum arg_state arg_rec_state;int restype,arg_num;} 683 684 enum arg_state { ARG_STA_INIT =0, 685 ARG_STA_F =1, /* $f12 */ 686 ARG_STA_FF =2, /* $f12 $f14 */ 687 ARG_STA_FG =3, /* $f12 $6 */ 688 ARG_STA_FGG =4, /* $f12 $6 $7 */ 689 ARG_STA_FGF =5, /* $f12 $6 STACK */ 690 ARG_STA_G =6, /* $4 */ 691 ARG_STA_GF =7, /* $4 ($6,$7) */ 692 ARG_STA_GG =8, /* $4 $5 */ 693 ARG_STA_GGF =9, /* $4 $5 ($6,$7) */ 694 ARG_STA_GGG =10,/* $4 $5 $6 */ 695 ARG_STA_GGGF =11,/* $4 $5 $6 STACK */ 696 ARG_STA_GGGG =12 /* $4 $5 $6 $7 */ 697 }; 698 #define ARG_STA_AUTOMA \ 699 { \ 700 {ARG_STA_F,ARG_STA_G,44,4 }, /* ARG_STA_INIT */ \ 701 {ARG_STA_FF,ARG_STA_FG,46,6 }, /* ARG_STA_F */ \ 702 {ARG_STA_FF,ARG_STA_FF,-1,-1 }, /* ARG_STA_FF */ \ 703 {ARG_STA_FGF,ARG_STA_FGG,-1,7 }, /* ARG_STA_FG */ \ 704 {ARG_STA_FGG,ARG_STA_FGG,-1,-1 }, /* ARG_STA_FGG */ \ 705 {ARG_STA_FGF,ARG_STA_FGF,-1,-1 }, /* ARG_STA_FGF */ \ 706 {ARG_STA_GF,ARG_STA_GG,-2,5 }, /* ARG_STA_G */ \ 707 {ARG_STA_GF,ARG_STA_GF,-1,-1 }, /* ARG_STA_GF */ \ 708 {ARG_STA_GGF,ARG_STA_GGG,-2,6 }, /* ARG_STA_GG */ \ 709 {ARG_STA_GGF,ARG_STA_GGF,-1,-1 }, /* ARG_STA_GGF */ \ 710 {ARG_STA_GGGF,ARG_STA_GGGG,-1,7 }, /* ARG_STA_GGG */ \ 711 {ARG_STA_GGGF,ARG_STA_GGGF,-1,-1 }, /* ARG_STA_GGGF */ \ 712 {ARG_STA_GGGG,ARG_STA_GGGG,-1,-1 } /* ARG_STA_GGGG */ \ 713 } 714 715 /* Initialize a variable CUM of type CUMULATIVE_ARGS 716 for a call to a function whose data type is FNTYPE. 717 For a library call, FNTYPE is 0. 718 719 */ 720 721 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE) ((CUM.arg_rec_state) = ARG_STA_INIT,\ 722 (CUM.arg_num) = 0, (CUM.restype = (int)VOIDmode)) 723 724 /* Update the data in CUM to advance over an argument 725 of mode MODE and data type TYPE. 726 (TYPE is null for libcalls where that information may not be available.) */ 727 728 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 729 ( function_arg_advance(&CUM,MODE,TYPE)); 730 731 extern enum arg_state function_arg_advance(); 732 733 /* Determine where to put an argument to a function. 734 Value is zero to push the argument on the stack, 735 or a hard register in which to store the argument. 736 737 MODE is the argument's machine mode. 738 TYPE is the data type of the argument (as a tree). 739 This is null for libcalls where that information may 740 not be available. 741 CUM is a variable of type CUMULATIVE_ARGS which gives info about 742 the preceding args and about the function being called. 743 NAMED is nonzero if this argument is a named parameter 744 (otherwise it is an extra parameter matching an ellipsis). */ 745 746 747 748 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 749 ( (rtx) function_arg(&CUM,MODE,TYPE,NAMED)) 750 751 /* For an arg passed partly in registers and partly in memory, 752 this is the number of registers used. 753 For args passed entirely in registers or entirely in memory, zero. 754 */ 755 756 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0) 757 758 759 /* This macro generates the assembly code for function entry. 760 FILE is a stdio stream to output the code to. 761 SIZE is an int: how many units of temporary storage to allocate. 762 Refer to the array `regs_ever_live' to determine which registers 763 to save; `regs_ever_live[I]' is nonzero if register number I 764 is ever used in the function. This macro is responsible for 765 knowing which registers should not be saved even if used. */ 766 767 768 /* ALIGN FRAMES on double word boundaries */ 769 770 #define AL_ADJUST_ALIGN(LOC) (((LOC)+7) & 0xfffffff8) 771 772 773 /* The problem of Varargs comes from the register passing conventions 774 for Floating Point data. There is a conflict when we send registers 775 back to stack between registers $4,$5 $6,$7 and $f12, $f14. 776 777 The current implementation: 778 a/ tries to figure out if the current routines uses varargs.(It becomes 779 ``suspect''.) This is currently done by looking for a special 780 static character string constant. 781 782 b/when a function is suspected of using varags, a larger reg 783 save_area is allocated which will hold regs f12 and f14. The varargs 784 macros then have to find where is the argument they are looking for. 785 This is made easier by a modification in stack frame layout for 786 these functions:the stack frame-size is accessible on stack at 787 location 4($30). 788 789 Total overhead in PROLOGUE: 2 inns to put stacksize on stack 790 2 sw.d to save floating registers. 791 (Only when Varargs suspected) 792 793 The only problem with ``thinking'', is that when functions are 794 thought using varargs and dont do it, they get the above entry 795 overhead.However the current method is quite precise, and is *safe*. 796 797 798 See va-mips.h for more information on varargs 799 800 */ 801 extern int varargs_suspect; 802 extern int this_varargs_suspect ; 803 804 #define VARARGS_SUSPECT(COND) varargs_suspect |= (COND) 805 #define VARARGS_NOTSUSPECT varargs_suspect = 0 806 #define VARARGS_SUSPECTED (varargs_suspect) 807 808 #define THIS_VARARGS_SUSPECT(COND) this_varargs_suspect |= (COND) 809 #define THIS_VARARGS_NOTSUSPECT this_varargs_suspect = 0 810 #define THIS_VARARGS_SUSPECTED (this_varargs_suspect) 811 812 813 #define FUNCTION_PROLOGUE(FILE, SIZE) \ 814 { register int regno; \ 815 register int mask = 0, fmask=0; \ 816 static char dont_save_regs[] = CALL_USED_REGISTERS; \ 817 register int push_loc = 0,tsize = SIZE+4; \ 818 char *fp_str; \ 819 extern char *reg_numchar[]; \ 820 extern int current_function_total_framesize; \ 821 this_varargs_suspect = VARARGS_SUSPECTED ; \ 822 fp_str = TARGET_NAME_REGS ? reg_names[STACK_POINTER_REGNUM] \ 823 : reg_numchar[STACK_POINTER_REGNUM]; \ 824 for (regno = 0; regno < 32; regno++) \ 825 if ( MUST_SAVE_REG_LOGUES \ 826 || (regs_ever_live[regno] && !dont_save_regs[regno])) \ 827 {tsize += 4; mask |= 1 << regno;} \ 828 for (regno = 32; regno < FIRST_PSEUDO_REGISTER; regno += 2) \ 829 if (regs_ever_live[regno] && !dont_save_regs[regno]) \ 830 {tsize += 8; fmask |= 1 << (regno-32);} \ 831 if (THIS_VARARGS_SUSPECTED) tsize += 16; \ 832 fprintf (FILE," #PROLOGUE\n"); \ 833 regno = STACK_POINTER_REGNUM; \ 834 tsize = AL_ADJUST_ALIGN (tsize); \ 835 \ 836 if (!frame_pointer_needed) \ 837 fprintf (FILE,"#define __0__gcc %d\n", \ 838 (!( regs_ever_live[29] || regs_ever_live[30] \ 839 || fmask || mask \ 840 || (SIZE > 0))) \ 841 ? 0:tsize); \ 842 \ 843 push_loc = 0; current_function_total_framesize = tsize; \ 844 fprintf (FILE, " #\t.mask\t0x%x\n", mask); \ 845 if (frame_pointer_needed || regs_ever_live[29] || regs_ever_live[30] \ 846 || fmask || mask \ 847 || (SIZE > 0)) \ 848 fprintf (FILE,"\tsubu\t%s,%d\t#temp=%5d,saveregs=%5d, sfo=%5d\n", \ 849 TARGET_NAME_REGS ? reg_names[29] \ 850 :reg_numchar[29],tsize,SIZE,tsize-SIZE, \ 851 STARTING_FRAME_OFFSET); \ 852 else fprintf (FILE," #NO STACK PUSH:\tSP %sused, FP %sused, FP %sneeded\n",\ 853 regs_ever_live[29]? "":"un", \ 854 regs_ever_live[30]? "":"un", \ 855 frame_pointer_needed ?"" : "not "); \ 856 for (regno = 31; regno >= 30; regno--) \ 857 { \ 858 if (MUST_SAVE_REG_LOGUES \ 859 || (regs_ever_live[regno] && !dont_save_regs[regno])) \ 860 { \ 861 push_loc += 4; \ 862 fprintf (FILE,"\tsw\t%s,%d(%s)\n", \ 863 TARGET_NAME_REGS ? reg_names[regno] \ 864 : reg_numchar[regno],push_loc,fp_str); \ 865 } \ 866 } \ 867 if (THIS_VARARGS_SUSPECTED) \ 868 { int fregno; \ 869 fprintf (FILE,"\taddi\t%s,$0,%d\t#Varargs suspicion\n", \ 870 TARGET_NAME_REGS ? reg_names[9] \ 871 : reg_numchar[9],tsize); \ 872 fprintf (FILE,"\tsw\t%s,-4(%s)\t#Varargs suspicion\n", \ 873 TARGET_NAME_REGS ? reg_names[9] \ 874 : reg_numchar[9], \ 875 TARGET_NAME_REGS ? reg_names[29] \ 876 : reg_numchar[29]); \ 877 for (fregno = 44; fregno< 48; fregno += 2) \ 878 {push_loc += 8; \ 879 fprintf (FILE,"\ts.d\t%s,%d(%s)\t#Varargs Suspicion\n", \ 880 ( (TARGET_NAME_REGS) \ 881 ?reg_names[fregno]: reg_numchar[fregno]), \ 882 push_loc,fp_str);} \ 883 } \ 884 for (regno = 29; regno >= 0; regno--) \ 885 { \ 886 if ( MUST_SAVE_REG_LOGUES \ 887 || (regs_ever_live[regno] && !dont_save_regs[regno])) \ 888 { \ 889 push_loc += 4; \ 890 fprintf (FILE, "\tsw\t%s,%d(%s)\n", \ 891 TARGET_NAME_REGS ? reg_names[regno] \ 892 : reg_numchar[regno],push_loc,fp_str); \ 893 } \ 894 } \ 895 fprintf (FILE, " #\t.fmask\t0x%x\n", fmask); \ 896 for (regno = 32; regno < FIRST_PSEUDO_REGISTER; regno += 2) \ 897 if (regs_ever_live[regno] && !dont_save_regs[regno]) \ 898 {push_loc += 8; \ 899 fprintf (FILE,"\ts.d\t%s,%d(%s)\n", \ 900 ( (TARGET_NAME_REGS) ? reg_names[regno] \ 901 : reg_numchar[regno]),push_loc,fp_str); \ 902 } \ 903 if (frame_pointer_needed) \ 904 fprintf (FILE,"\taddiu\t%s,%s,%d\t#Establish FramePTR\n", \ 905 (TARGET_NAME_REGS ? reg_names[FRAME_POINTER_REGNUM] : \ 906 reg_numchar[FRAME_POINTER_REGNUM]), \ 907 (TARGET_NAME_REGS ? reg_names[29] : reg_numchar[29]), \ 908 tsize); \ 909 fprintf (FILE," #END PROLOGUE\n"); \ 910 } 911 912 /* Output assembler code to FILE to increment profiler label # LABELNO 913 for profiling a function entry. */ 914 915 #define FUNCTION_PROFILER(FILE, LABELNO) \ 916 fprintf (FILE, "ERROR\t profiler LP%d,r0\n", (LABELNO)); 917 918 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 919 the stack pointer does not matter. The value is tested only in 920 functions that have frame pointers. 921 No definition is equivalent to always zero. */ 922 923 extern int may_call_alloca; 924 extern int current_function_pretend_args_size; 925 926 #define EXIT_IGNORE_STACK 0 927 928 929 /* This declaration is needed due to traditional/ANSI 930 incompatibilities which cannot be #ifdefed away 931 because they occur inside of macros. Sigh. */ 932 933 934 extern union tree_node *current_function_decl; 935 extern char *current_function_name; 936 937 /* Tell prologue and epilogue if Register containing return 938 address should be saved / restored 939 */ 940 941 #define MUST_SAVE_REG_LOGUES (( frame_pointer_needed && (regno == 30)) \ 942 ||( (regno == 31) && regs_ever_live[31]) \ 943 ) 944 945 946 /* This macro generates the assembly code for function exit, 947 on machines that need it. If FUNCTION_EPILOGUE is not defined 948 then individual return instructions are generated for each 949 return statement. Args are same as for FUNCTION_PROLOGUE. */ 950 951 952 #define FUNCTION_EPILOGUE(FILE, SIZE) \ 953 { register int regno; \ 954 register int mask = 0; \ 955 register int fmask = 0; \ 956 char *fp_str; \ 957 char *sp_str; \ 958 static char dont_save_regs[] = CALL_USED_REGISTERS; \ 959 register int push_loc ; \ 960 extern char *reg_numchar[]; \ 961 extern char *current_function_name; \ 962 extern int current_function_total_framesize; \ 963 push_loc = 0; \ 964 regno = STACK_POINTER_REGNUM; \ 965 sp_str = TARGET_NAME_REGS ? reg_names[STACK_POINTER_REGNUM] \ 966 : reg_numchar[STACK_POINTER_REGNUM]; \ 967 fp_str = TARGET_NAME_REGS ? reg_names[8] \ 968 :reg_numchar[8]; \ 969 fprintf (FILE," #EPILOGUE\n"); \ 970 if (!frame_pointer_needed) \ 971 fprintf (FILE,"#undef __0__gcc\n"); \ 972 else \ 973 fprintf (FILE,"\taddu\t%s,$0,%s\t# sp not trusted here \n", \ 974 fp_str, \ 975 TARGET_NAME_REGS ? reg_names[FRAME_POINTER_REGNUM] \ 976 :reg_numchar[FRAME_POINTER_REGNUM] \ 977 ); \ 978 for (regno = 0; regno < 32; regno++) \ 979 if ( MUST_SAVE_REG_LOGUES \ 980 || (regs_ever_live[regno] && !dont_save_regs[regno])) \ 981 mask |= 1 << regno; \ 982 fprintf (FILE, " #\t.mask\t0x%x\n", mask); \ 983 for (regno = 31; regno >= 0; regno--) \ 984 { if ( MUST_SAVE_REG_LOGUES \ 985 || (regs_ever_live[regno] && !dont_save_regs[regno])) \ 986 { \ 987 push_loc += 4; \ 988 fprintf (FILE,"\tlw\t%s,%d(%s)\n", \ 989 TARGET_NAME_REGS ? reg_names[regno] \ 990 : reg_numchar[regno], \ 991 (frame_pointer_needed ? \ 992 push_loc - current_function_total_framesize: \ 993 push_loc), \ 994 (frame_pointer_needed ? fp_str :sp_str)); \ 995 } \ 996 if ( THIS_VARARGS_SUSPECTED && (regno == 30)) push_loc += 16; \ 997 } \ 998 for (regno = 32; regno < FIRST_PSEUDO_REGISTER; regno += 2) \ 999 if (regs_ever_live[regno] && !dont_save_regs[regno]) \ 1000 fmask |= 1 << (regno-32); \ 1001 fprintf (FILE, " #\t.fmask\t0x%x\n", fmask); \ 1002 for (regno = 32; regno < FIRST_PSEUDO_REGISTER; regno += 2) \ 1003 { \ 1004 if (regs_ever_live[regno] && !dont_save_regs[regno]) \ 1005 { \ 1006 push_loc += 8; \ 1007 fprintf (FILE,"\tl.d\t%s,%d(%s)\n", \ 1008 ( ( TARGET_NAME_REGS) ? reg_names[regno] \ 1009 : reg_numchar[regno]), \ 1010 (frame_pointer_needed ? \ 1011 push_loc - current_function_total_framesize \ 1012 : push_loc), \ 1013 (frame_pointer_needed ? fp_str :sp_str)); \ 1014 } \ 1015 } \ 1016 if (frame_pointer_needed) \ 1017 fprintf (FILE,"\taddu\t%s,$0,%s\t# sp not trusted here \n", \ 1018 TARGET_NAME_REGS ? reg_names[STACK_POINTER_REGNUM] \ 1019 :reg_numchar[STACK_POINTER_REGNUM], \ 1020 TARGET_NAME_REGS ? reg_names[8] \ 1021 :reg_numchar[8] \ 1022 ); \ 1023 else \ 1024 if (regs_ever_live[29]|| regs_ever_live[30] \ 1025 || fmask || mask \ 1026 || (SIZE > 0)) \ 1027 fprintf (FILE,"\taddu\t%s,%d\t\n",TARGET_NAME_REGS ? reg_names[29]\ 1028 :reg_numchar[29],current_function_total_framesize); \ 1029 fprintf (FILE,"\tj\t$31\n"); \ 1030 fprintf (FILE," #END EPILOGUE\n"); \ 1031 fprintf (FILE," \t.end\t%s\n",current_function_name); \ 1032 THIS_VARARGS_NOTSUSPECT; VARARGS_NOTSUSPECT;} 1033 1034 /* If the memory Address ADDR is relative to the frame pointer, 1035 correct it to be relative to the stack pointer. This is for 1036 when we don't use a frame pointer. 1037 ADDR should be a variable name. */ 1038 1039 #define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH) \ 1040 { rtx newaddr; \ 1041 int frame_offset = -1; \ 1042 /* fprintf(stderr,"FIX_FRAME depth=%d\n",DEPTH); */ \ 1043 if(ADDR == frame_pointer_rtx) \ 1044 frame_offset = 0; \ 1045 else \ 1046 if (GET_CODE(ADDR) == PLUS) \ 1047 if(XEXP(ADDR,0) == frame_pointer_rtx) \ 1048 if(GET_CODE(XEXP(ADDR,1)) == CONST_INT) \ 1049 frame_offset = INTVAL(XEXP(ADDR,1)); \ 1050 else abort_with_insn(ADDR,"Unable to FIX"); \ 1051 else if (XEXP(ADDR,1) == frame_pointer_rtx) \ 1052 if(GET_CODE(XEXP(ADDR,0)) == CONST_INT) \ 1053 frame_offset = INTVAL(XEXP(ADDR,0)); \ 1054 else abort_with_insn(ADDR,"Unable to FIX"); \ 1055 else; \ 1056 if (frame_offset >= 0) \ 1057 { newaddr=gen_rtx(PLUS,Pmode,stack_pointer_rtx, \ 1058 gen_rtx(PLUS,Pmode, \ 1059 gen_rtx(CONST_INT,VOIDmode,frame_offset+(DEPTH)),\ 1060 gen_rtx(SYMBOL_REF,SImode,"__0__gcc"))); \ 1061 ADDR = newaddr; \ 1062 } \ 1063 } 1064 1065 1066 1067 /* Addressing modes, and classification of registers for them. */ 1068 1069 /* #define HAVE_POST_INCREMENT */ 1070 /* #define HAVE_POST_DECREMENT */ 1071 1072 /* #define HAVE_PRE_DECREMENT */ 1073 /* #define HAVE_PRE_INCREMENT */ 1074 1075 /* These assume that REGNO is a hard or pseudo reg number. 1076 They give nonzero only if REGNO is a hard reg of the suitable class 1077 or a pseudo reg currently allocated to a suitable hard reg. 1078 These definitions are NOT overridden anywhere. */ 1079 1080 #define REGNO_OK_FOR_INDEX_P(regno) \ 1081 ((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0) 1082 #define REGNO_OK_FOR_BASE_P(regno) \ 1083 ((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0) 1084 #define REGNO_OK_FOR_FP_P(REGNO) \ 1085 (((REGNO) ^ 0x20) < 32 || (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32) 1086 1087 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1088 and check its validity for a certain class. 1089 We have two alternate definitions for each of them. 1090 The usual definition accepts all pseudo regs; the other rejects them all. 1091 The symbol REG_OK_STRICT causes the latter definition to be used. 1092 1093 Most source files want to accept pseudo regs in the hope that 1094 they will get allocated to the class that the insn wants them to be in. 1095 Some source files that are used after register allocation 1096 need to be strict. */ 1097 1098 #ifndef REG_OK_STRICT 1099 1100 /* Nonzero if X is a hard reg that can be used as an index or if 1101 it is a pseudo reg. */ 1102 #define REG_OK_FOR_INDEX_P(X) 1 1103 /* Nonzero if X is a hard reg that can be used as a base reg 1104 of if it is a pseudo reg. */ 1105 #define REG_OK_FOR_BASE_P(X) 1 1106 1107 #else 1108 1109 /* Nonzero if X is a hard reg that can be used as an index. */ 1110 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1111 /* Nonzero if X is a hard reg that can be used as a base reg. */ 1112 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1113 1114 #endif 1115 1116 #define REG_OK_FOR_CLASS_P(X, C) 0 1117 1118 #define REGNO_OK_FOR_CLASS_P(X, C) 0 1119 1120 #define ADDRESS_REG_P(X) \ 1121 (GET_CODE (X) == REG ) 1122 1123 /* 1 if X is an fp register. */ 1124 1125 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 1126 1127 /* Maximum number of registers that can appear in a valid memory address. */ 1128 1129 #define MAX_REGS_PER_ADDRESS 1 1130 1131 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1132 that is a valid memory address for an instruction. 1133 The MODE argument is the machine mode for the MEM expression 1134 that wants to use this address. 1135 1136 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, 1137 except for CONSTANT_ADDRESS_P which is actually machine-independent. */ 1138 1139 /* 1 if X is an address that we could indirect through. */ 1140 #define INDIRECTABLE_ADDRESS_P(X) \ 1141 (CONSTANT_ADDRESS_P (X) \ 1142 || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 1143 || (GET_CODE (X) == PLUS \ 1144 && GET_CODE (XEXP (X, 0)) == REG \ 1145 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ 1146 && CONSTANT_ADDRESS_P (XEXP (X, 1)))) 1147 1148 1149 1150 /* 1 if X is an address which is (+ (reg) (+ (const_int) (symbol_ref) )) */ 1151 #define FIXED_FRAME_PTR_REL_P(X) \ 1152 ( (GET_CODE(X) == PLUS) \ 1153 && (GET_CODE(XEXP((X),0)) == REG) \ 1154 && (GET_CODE(XEXP((X),1)) == PLUS) \ 1155 && (GET_CODE(XEXP(XEXP((X),1),0)) == CONST_INT) \ 1156 && (GET_CODE(XEXP(XEXP((X),1),1)) == SYMBOL_REF)) 1157 1158 /* Go to ADDR if X is a valid address not using indexing. 1159 (This much is the easy part.) */ 1160 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1161 { register rtx xfoob = (X); \ 1162 if (GET_CODE (xfoob) == REG) goto ADDR; \ 1163 if (INDIRECTABLE_ADDRESS_P (xfoob)) goto ADDR; \ 1164 if (FIXED_FRAME_PTR_REL_P (xfoob)) goto ADDR; \ 1165 } 1166 1167 1168 1169 1170 #define CONSTANT_ADDRESS_P(X) \ 1171 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1172 || GET_CODE (X) == CONST_INT \ 1173 || GET_CODE (X) == CONST) 1174 1175 /* Nonzero if the constant value X is a legitimate general operand. 1176 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 1177 1178 Anything but a CONST_DOUBLE can be made to work. */ 1179 1180 #define LEGITIMATE_CONSTANT_P(X) \ 1181 (GET_CODE (X) != CONST_DOUBLE) 1182 1183 /* Try machine-dependent ways of modifying an illegitimate address 1184 to be legitimate. If we find one, return the new, valid address. 1185 This macro is used in only one place: `memory_address' in explow.c. 1186 1187 OLDX is the address as it was before break_out_memory_refs was called. 1188 In some cases it is useful to look at this to decide what needs to be done. 1189 1190 MODE and WIN are passed so that this macro can use 1191 GO_IF_LEGITIMATE_ADDRESS. 1192 1193 It is always safe for this macro to do nothing. It exists to recognize 1194 opportunities to optimize the output. 1195 1196 For the MIPS (so far ..), nothing needs to be done. 1197 1198 ACHTUNG this is actually used by the FLOW analysis to get rid 1199 of statements.... 1200 1201 */ 1202 1203 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {} 1204 1205 /* Go to LABEL if ADDR (a legitimate address expression) 1206 has an effect that depends on the machine mode it is used for. 1207 */ 1208 1209 /* See if this is of any use here */ 1210 1211 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1212 { } 1213 1214 1215 /* Specify the machine mode that this machine uses 1216 for the index in the tablejump instruction. */ 1217 #define CASE_VECTOR_MODE SImode 1218 1219 /* Define this if the tablejump instruction expects the table 1220 to contain offsets from the address of the table. 1221 Do not define this if the table should contain absolute addresses. */ 1222 /* #define CASE_VECTOR_PC_RELATIVE */ 1223 1224 /* Specify the tree operation to be used to convert reals to integers. */ 1225 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR 1226 1227 /* This is the kind of divide that is easiest to do in the general case. */ 1228 #define EASY_DIV_EXPR TRUNC_DIV_EXPR 1229 1230 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1231 #define DEFAULT_SIGNED_CHAR 1 1232 1233 /* Max number of bytes we can move from memory to memory 1234 in one reasonably fast instruction. */ 1235 #define MOVE_MAX 4 1236 1237 /* Nonzero if access to memory by bytes is slow and undesirable. */ 1238 #define SLOW_BYTE_ACCESS 0 1239 1240 /* On Sun 4, this limit is 2048. We use 1500 to be safe, 1241 since the length can run past this up to a continuation point. */ 1242 #define DBX_CONTIN_LENGTH 1500 1243 1244 /* We assume that the store-condition-codes instructions store 0 for false 1245 and some other value for true. This is the value stored for true. */ 1246 1247 #define STORE_FLAG_VALUE 1 1248 1249 /* Define this if zero-extension is slow (more than one real instruction). */ 1250 #define SLOW_ZERO_EXTEND 1251 1252 /* Define if shifts truncate the shift count 1253 which implies one can omit a sign-extension or zero-extension 1254 of a shift count. 1255 1256 Only 5 bits are used in SLLV and SRLV 1257 */ 1258 #define SHIFT_COUNT_TRUNCATED 1259 1260 1261 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1262 is done just by pretending it is already truncated. */ 1263 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1264 1265 /* Specify the machine mode that pointers have. 1266 After generation of rtl, the compiler makes no further distinction 1267 between pointers and any other objects of this machine mode. */ 1268 #define Pmode SImode 1269 1270 /* A function address in a call instruction 1271 is a word address (for indexing purposes) 1272 so give the MEM rtx a words's mode. */ 1273 1274 #define FUNCTION_MODE SImode 1275 1276 /* Compute the cost of computing a constant rtl expression RTX 1277 whose rtx-code is CODE. The body of this macro is a portion 1278 of a switch statement. If the code is computed here, 1279 return it with a return statement. Otherwise, break from the switch. */ 1280 1281 #define CONST_COSTS(RTX,CODE) \ 1282 case CONST_INT: \ 1283 /* Constant zero is super cheap due to register 0. */ \ 1284 if (RTX == const0_rtx) return 0; \ 1285 if ((INTVAL (RTX) < 0x7fff) && (- INTVAL(RTX) < 0x7fff)) return 1; \ 1286 case CONST: \ 1287 case LABEL_REF: \ 1288 case SYMBOL_REF: \ 1289 return 3; \ 1290 case CONST_DOUBLE: \ 1291 return 5; 1292 1293 /* Tell final.c how to eliminate redundant test instructions. */ 1294 1295 /* Here we define machine-dependent flags and fields in cc_status 1296 (see `conditions.h'). No extra ones are needed for the vax. */ 1297 /* Tell final.c how to eliminate redundant test instructions. */ 1298 1299 /* Tell final.c how to eliminate redundant test instructions. */ 1300 1301 /* Here we define machine-dependent flags and fields in cc_status 1302 (see `conditions.h'). No extra ones are needed for the vax. */ 1303 1304 /* Store in cc_status the expressions 1305 that the condition codes will describe 1306 after execution of an instruction whose pattern is EXP. 1307 Do not alter them if the instruction would not alter the cc's. */ 1308 1309 #define NOTICE_UPDATE_CC(EXP, INSN) \ 1310 CC_STATUS_INIT; 1311 1312 1313 /* Here we define machine-dependent flags and fields in cc_status 1314 (see `conditions.h'). */ 1315 1316 1317 /* Control the assembler format that we output. */ 1318 1319 /* Output at beginning of assembler file. */ 1320 1321 #define ASM_FILE_START(FILE) \ 1322 { \ 1323 if (TARGET_NAME_REGS) \ 1324 fprintf (FILE, "#include <regdef.h>\n\t.verstamp\t%s\n", TARGET_VERSNUM);\ 1325 else fprintf (FILE, " #\t.verstamp\t%s\n", TARGET_VERSNUM); \ 1326 /* print_options(FILE); */ \ 1327 if (TARGET_GP_OPT) \ 1328 fprintf (FILE, "#ifdef %sRESCAN_GCC\n", "__x_"); \ 1329 } 1330 1331 /* Output to assembler file text saying following lines 1332 may contain character constants, extra white space, comments, etc. */ 1333 1334 #define ASM_APP_ON " #APP\n" 1335 1336 /* Output to assembler file text saying following lines 1337 no longer contain unusual constructs. */ 1338 1339 #define ASM_APP_OFF " #NO_APP\n" 1340 1341 /* Output before read-only data. */ 1342 1343 #define TEXT_SECTION_ASM_OP ".text" 1344 1345 /* Output before writable data. */ 1346 1347 #define DATA_SECTION_ASM_OP ".data" 1348 1349 #define ASM_OUTPUT_MIPS_SECTIONS 1350 #define OUTPUT_MIPS_SECTION_THRESHOLD ((mips_section_threshold >= 0 )?\ 1351 mips_section_threshold : mips_section_get()) 1352 1353 /* Output before writable short data. */ 1354 1355 #define SDATA_SECTION_ASM_OP ".sdata" 1356 1357 /* How to refer to registers in assembler output. 1358 This sequence is indexed by compiler's hard-register-number (see above). */ 1359 1360 #define REGISTER_NAMES \ 1361 {"$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", \ 1362 "t1", "t2", "t3", "t4", "t5", "t6", "t7","s0", \ 1363 "s1","s2","s3","s4","s5","s6","s7","t8","t9", \ 1364 "k0","k1","gp","sp","fp","ra", \ 1365 "$f0","$f1","$f2","$f3","$f4","$f5","$f6","$f7","$f8","$f9", \ 1366 "$f10","$f11","$f12","$f13","$f14","$f15","$f16","$f17","$f18","$f19", \ 1367 "$f20","$f21","$f22","$f23","$f24","$f25","$f26","$f27","$f28","$f29", \ 1368 "$f30","$f31" \ 1369 } 1370 #define REGISTER_NUMCHAR \ 1371 { \ 1372 "$0","$1","$2","$3","$4","$5","$6","$7","$8","$9", \ 1373 "$10","$11","$12","$13","$14","$15","$16","$17","$18","$19", \ 1374 "$20","$21","$22","$23","$24","$25","$26","$27","$28","$29", \ 1375 "$30","$31", \ 1376 "$f0","$f1","$f2","$f3","$f4","$f5","$f6","$f7","$f8","$f9", \ 1377 "$f10","$f11","$f12","$f13","$f14","$f15","$f16","$f17","$f18","$f19", \ 1378 "$f20","$f21","$f22","$f23","$f24","$f25","$f26","$f27","$f28","$f29", \ 1379 "$f30","$f31" \ 1380 } 1381 1382 1383 /* How to renumber registers for dbx and gdb. 1384 MIPS needs no change in the numeration. */ 1385 1386 #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 1387 1388 /* Define results of standard character escape sequences. */ 1389 #define TARGET_BELL 007 1390 #define TARGET_BS 010 1391 #define TARGET_TAB 011 1392 #define TARGET_NEWLINE 012 1393 #define TARGET_VT 013 1394 #define TARGET_FF 014 1395 #define TARGET_CR 015 1396 1397 /* LIST OF PRINT OPERAND CODES 1398 1399 1400 ** 'x' X is CONST_INT, prints 16 bits in 1401 ** Hexadecimal format = "0x%4x", 1402 ** 'd' output integer constant in decimal, 1403 ** 'u' Prints an 'u' if flag -mnofixed-ovfl 1404 ** has been set, thus selecting addu 1405 ** instruction instead of add. 1406 */ 1407 1408 1409 /* Print an instruction operand X on file FILE. 1410 CODE is the code from the %-spec that requested printing this operand; 1411 if `%z3' was used to print operand 3, then CODE is 'z'. 1412 CODE is used as follows: 1413 1414 LIST OF PRINT OPERAND CODES 1415 1416 1417 'x' X is CONST_INT, prints 16 bits in 1418 ** Hexadecimal format = "0x%4x", 1419 ** 'd' output integer constant in decimal, 1420 ** ':' Prints an 'u' if flag -mnofixed-ovfl 1421 ** has been set, thus selecting addu 1422 ** instruction instead of add. 1423 */ 1424 1425 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 1426 ((CODE) == ':') 1427 1428 #define PRINT_OPERAND(FILE, X, CODE) \ 1429 { if ((CODE) == ':') \ 1430 {if (TARGET_NOFIXED_OVFL)fprintf(FILE,"u");} \ 1431 else if (GET_CODE (X) == REG) \ 1432 { extern char *reg_numchar[]; \ 1433 fprintf (FILE, "%s", TARGET_NAME_REGS ?reg_names[REGNO (X)] \ 1434 :reg_numchar[REGNO (X) ]); \ 1435 } \ 1436 else \ 1437 { \ 1438 if (GET_CODE (X) == MEM) \ 1439 output_address (XEXP (X, 0)); \ 1440 else if (GET_CODE (X) == CONST_DOUBLE) \ 1441 { union { double d; int i[2]; } u; \ 1442 union { float f; int i; } u1; \ 1443 u.i[0] = CONST_DOUBLE_LOW (X); \ 1444 u.i[1] = CONST_DOUBLE_HIGH (X); \ 1445 u1.f = u.d; \ 1446 if (GET_MODE (X) == SFmode) \ 1447 u.d = u1.f; \ 1448 fprintf (FILE, "%.20e", u.d); } \ 1449 else \ 1450 { if ((CODE == 'x') && (GET_CODE(X) == CONST_INT)) \ 1451 fprintf(FILE,"0x%x",0xffff & (INTVAL(X))); \ 1452 else { if ((CODE == 'd') && (GET_CODE(X) == CONST_INT)) \ 1453 fprintf(FILE,"%d",(INTVAL(X))); \ 1454 else \ 1455 { \ 1456 if ((CODE) == 'd') abort(); \ 1457 else output_addr_const (FILE, X);} \ 1458 }}}} 1459 1460 /* Print a memory operand whose address is X, on file FILE. */ 1461 1462 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 1463 { register rtx reg1, reg2, breg, ireg; \ 1464 register rtx addr = ADDR; \ 1465 rtx offset; \ 1466 extern char *reg_numchar[]; \ 1467 /* my_print_rtx(addr);*/ \ 1468 retry: \ 1469 switch (GET_CODE (addr)) \ 1470 { \ 1471 case REG: \ 1472 fprintf (FILE, "0(%s)", TARGET_NAME_REGS ? reg_names [REGNO (addr)]\ 1473 : reg_numchar[REGNO(addr)]); \ 1474 break; \ 1475 case MEM: \ 1476 case PRE_DEC: \ 1477 case POST_INC: \ 1478 abort(); \ 1479 break; \ 1480 case PLUS: \ 1481 if( (GET_CODE (XEXP(addr,0)) == REG) \ 1482 && (GET_CODE (XEXP(addr,1)) == PLUS) \ 1483 && (GET_CODE (XEXP(XEXP(addr,1),1)) == SYMBOL_REF) \ 1484 && (GET_CODE (XEXP(XEXP(addr,1),0)) == CONST_INT)) \ 1485 {output_address(XEXP(XEXP(addr,1),0)); \ 1486 fprintf(FILE,"+"); \ 1487 output_address(XEXP(XEXP(addr,1),1)); \ 1488 breg = XEXP(addr,0); \ 1489 fprintf(FILE,"(%s)", TARGET_NAME_REGS ? \ 1490 reg_names[REGNO (breg)]: reg_numchar[REGNO(breg)]); \ 1491 break; \ 1492 } \ 1493 \ 1494 reg1 = 0; reg2 = 0; \ 1495 ireg = 0; breg = 0; \ 1496 offset = 0; \ 1497 /*fprintf(stderr,"PRINT_OPERAND_ADDRESS"); */ \ 1498 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)) \ 1499 || GET_CODE (XEXP (addr, 0)) == MEM) \ 1500 { \ 1501 offset = XEXP (addr, 0); \ 1502 addr = XEXP (addr, 1); \ 1503 } \ 1504 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)) \ 1505 || GET_CODE (XEXP (addr, 1)) == MEM) \ 1506 { \ 1507 offset = XEXP (addr, 1); \ 1508 addr = XEXP (addr, 0); \ 1509 } \ 1510 if (GET_CODE (addr) != PLUS) ; \ 1511 else if (GET_CODE (XEXP (addr, 0)) == MULT) \ 1512 { \ 1513 reg1 = XEXP (addr, 0); \ 1514 addr = XEXP (addr, 1); \ 1515 } \ 1516 else if (GET_CODE (XEXP (addr, 1)) == MULT) \ 1517 { \ 1518 reg1 = XEXP (addr, 1); \ 1519 addr = XEXP (addr, 0); \ 1520 } \ 1521 else if (GET_CODE (XEXP (addr, 0)) == REG) \ 1522 { \ 1523 reg1 = XEXP (addr, 0); \ 1524 addr = XEXP (addr, 1); \ 1525 } \ 1526 else if (GET_CODE (XEXP (addr, 1)) == REG) \ 1527 { \ 1528 reg1 = XEXP (addr, 1); \ 1529 addr = XEXP (addr, 0); \ 1530 } \ 1531 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT) \ 1532 { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \ 1533 if (offset != 0) { if (addr != 0) abort (); addr = offset; } \ 1534 if (reg1 != 0 && GET_CODE (reg1) == MULT) \ 1535 { breg = reg2; ireg = reg1; } \ 1536 else if (reg2 != 0 && GET_CODE (reg2) == MULT) \ 1537 { breg = reg1; ireg = reg2; } \ 1538 else if (reg2 != 0 || GET_CODE (addr) == MEM) \ 1539 { breg = reg2; ireg = reg1; } \ 1540 else \ 1541 { breg = reg1; ireg = reg2; } \ 1542 if (addr != 0) \ 1543 output_address (offset); \ 1544 if (breg != 0) \ 1545 { if (GET_CODE (breg) != REG) abort (); \ 1546 fprintf (FILE, "(%s)", TARGET_NAME_REGS ? \ 1547 reg_names[REGNO (breg)]: reg_numchar[REGNO(breg)]); }\ 1548 if (ireg != 0) \ 1549 { if (GET_CODE (ireg) == MULT) ireg = XEXP (ireg, 0); \ 1550 if (GET_CODE (ireg) != REG) abort (); \ 1551 fprintf (FILE, "[%s]", TARGET_NAME_REGS ? \ 1552 reg_names[REGNO (ireg)]: reg_numchar[REGNO(ireg)]); }\ 1553 break; \ 1554 default: \ 1555 output_addr_const (FILE, addr); \ 1556 }} 1557 1558 1559 /* This is how to output a note to DBX telling it the line number 1560 to which the following sequence of instructions corresponds. 1561 1562 This is needed for SunOS 4.0, and should not hurt for 3.2 1563 versions either. */ 1564 #define ASM_OUTPUT_SOURCE_LINE(file, line) \ 1565 { static int sym_lineno = 1; \ 1566 fprintf (file, " #.stabn 68,0,%d,LM%d\nLM%d:\n", \ 1567 line, sym_lineno, sym_lineno); \ 1568 sym_lineno += 1; } 1569 1570 /* This is how to output the definition of a user-level label named NAME, 1571 such as the label on a static function or variable NAME. */ 1572 1573 #define ASM_OUTPUT_LABEL(FILE,NAME) \ 1574 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) 1575 1576 /* This is how to output a command to make the user-level label named NAME 1577 defined for reference from other files. */ 1578 1579 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ 1580 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); \ 1581 fputs ("\n", FILE); \ 1582 if(TARGET_GP_OPT) {fputs ("#define _gccx__",FILE); \ 1583 assemble_name(FILE,NAME); \ 1584 fputs ("\n", FILE); \ 1585 } \ 1586 } while (0) 1587 1588 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ 1589 fprintf(FILE,"\t.ent\t%s\n",NAME); \ 1590 current_function_name = NAME; \ 1591 ASM_OUTPUT_LABEL(FILE,NAME); 1592 1593 /* This is how to output a reference to a user-level label named NAME. 1594 `assemble_name' uses this. */ 1595 1596 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 1597 fprintf (FILE, "%s", NAME) 1598 1599 /* This is how to output an internal numbered label where 1600 PREFIX is the class of label and NUM is the number within the class. */ 1601 1602 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ 1603 fprintf (FILE, "%s%d:\n", PREFIX, NUM) 1604 1605 /* This is how to store into the string LABEL 1606 the symbol_ref name of an internal numbered label where 1607 PREFIX is the class of label and NUM is the number within the class. 1608 This is suitable for output with `assemble_name'. */ 1609 1610 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1611 sprintf (LABEL, "*%s%d", PREFIX, NUM) 1612 1613 /* This is how to output an assembler line defining a `double' constant. */ 1614 1615 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ 1616 fprintf (FILE, "\t.double %.20e\n", (VALUE)) 1617 1618 /* This is how to output an assembler line defining a `float' constant. */ 1619 1620 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ 1621 fprintf (FILE, "\t.float %.12e\n", (VALUE)) 1622 1623 /* This is how to output an assembler line defining an `int' constant. */ 1624 1625 #define ASM_OUTPUT_INT(FILE,VALUE) \ 1626 ( fprintf (FILE, "\t.word "), \ 1627 output_addr_const (FILE, (VALUE)), \ 1628 fprintf (FILE, "\n")) 1629 1630 /* Likewise for `char' and `short' constants. */ 1631 1632 #define ASM_OUTPUT_SHORT(FILE,VALUE) \ 1633 ( fprintf (FILE, "\t.half "), \ 1634 output_addr_const (FILE, (VALUE)), \ 1635 fprintf (FILE, "\n")) 1636 1637 #define ASM_OUTPUT_CHAR(FILE,VALUE) \ 1638 ( fprintf (FILE, "\t.byte "), \ 1639 output_addr_const (FILE, (VALUE)), \ 1640 fprintf (FILE, "\n")) 1641 1642 /* This is how to output an assembler line for a numeric constant byte. */ 1643 1644 #define ASM_OUTPUT_BYTE(FILE,VALUE) \ 1645 fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) 1646 1647 /* This is how to output an element of a case-vector that is absolute. */ 1648 1649 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1650 fprintf (FILE, "\t.word L%d\n", VALUE) 1651 1652 /* This is how to output an element of a case-vector that is relative. 1653 (We do not use such vectors, 1654 but we must define this macro anyway.) */ 1655 1656 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ 1657 fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL) 1658 1659 /* This is how to output an assembler line 1660 that says to advance the location counter 1661 to a multiple of 2**LOG bytes. */ 1662 1663 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1664 fprintf (FILE, "\t.align %d\n", (LOG)) 1665 1666 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1667 fprintf (FILE, "\t.space %d\n", (SIZE)) 1668 1669 /* The support of .comm and .extern below permits to take advantage 1670 of the SDATA/SBSS sections supported by the MIPS ASSEMBLER and LOADER 1671 However some problems have to be solved 1672 a/ externs should be included ONCE 1673 b/ the same external cannot appear both on an extern and .comm stmt 1674 in the same assembly 1675 c/ for the whole scheme to bring some benefit, .comm should appear 1676 in front of the source asm -- whereas GCC put them at the end 1677 */ 1678 1679 1680 /* ALL THESE PROBLEMS ARE PRESENTLY SOLVED */ 1681 /* USING CONDITIONAL ASSEMBLY + FILE RESCAN */ 1682 1683 #define EXTRA_SECTIONS in_sdata 1684 1685 /* Define the additional functions to select our additional sections. */ 1686 1687 /* on the MIPS it is not a good idea to put constants in the 1688 text section, since this defeats the sdata/data mechanism. This 1689 is especially true when -O2 is used. In this case an effort is 1690 made to address with faster (gp) register relative addressing, 1691 which can only get at sdata and sbss items (there is no stext !!) 1692 */ 1693 #define EXTRA_SECTION_FUNCTIONS \ 1694 void \ 1695 sdata_section () \ 1696 { \ 1697 if (in_section != in_sdata) \ 1698 { \ 1699 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \ 1700 in_section = in_sdata; \ 1701 } \ 1702 } 1703 1704 /* Given a decl node or constant node, choose the section to output it in 1705 and select that section. */ 1706 1707 /* following takes care of constants emitted from 1708 the hash table entries (see above comment) 1709 */ 1710 #define SELECT_SECTION_MODE(MODE,RTX) \ 1711 { \ 1712 extern int mips_section_threshold; \ 1713 if (( GET_MODE_SIZE(MODE)/ BITS_PER_UNIT) \ 1714 <= OUTPUT_MIPS_SECTION_THRESHOLD) \ 1715 sdata_section(); \ 1716 else \ 1717 data_section (); \ 1718 } \ 1719 1720 #define SELECT_SECTION(DECL) \ 1721 { \ 1722 extern int mips_section_threshold; \ 1723 if (int_size_in_bytes (TREE_TYPE (DECL)) \ 1724 <= OUTPUT_MIPS_SECTION_THRESHOLD) \ 1725 sdata_section (); \ 1726 else \ 1727 data_section (); \ 1728 } 1729 1730 /* This says how to output an assembler line 1731 to define a global common symbol. */ 1732 1733 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1734 ( ((TARGET_GP_OPT)? \ 1735 fprintf((FILE),"\n#else"),0 :0), \ 1736 fputs ("\n\t.comm ", (FILE)), \ 1737 assemble_name ((FILE), (NAME)), \ 1738 fprintf ((FILE), ",%d\n", (ROUNDED)), \ 1739 (TARGET_GP_OPT ? (fputs("\n#define _gccx__",(FILE)), \ 1740 assemble_name((FILE),NAME),0):0), \ 1741 ((TARGET_GP_OPT)? \ 1742 fprintf((FILE),"\n#endif\n#ifdef %sRESCAN_GCC","__x_"),0 :0) \ 1743 ) 1744 1745 1746 /* This says how to output an external */ 1747 /* It would be possible not to output anything and let undefined */ 1748 /* symbol become external. However the assembler uses length information on*/ 1749 /* externals to allocate in data/sdata bss/sbss, thereby saving exec time */ 1750 1751 #define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) \ 1752 mips_output_external(FILE,DECL,NAME) 1753 1754 1755 /* This says how to output an assembler line 1756 to define a local common symbol. */ 1757 1758 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1759 ( fputs ("\n\t.lcomm\t", (FILE)), \ 1760 assemble_name ((FILE), (NAME)), \ 1761 fprintf ((FILE), ",%d\n", (ROUNDED))) 1762 1763 /* This says what to print at the end of the assembly file */ 1764 #define ASM_FILE_END(FILE) \ 1765 mips_asm_file_end(FILE) 1766 1767 /* Store in OUTPUT a string (made with alloca) containing 1768 an assembler-name for a local static variable named NAME. 1769 LABELNO is an integer which is different for each call. */ 1770 1771 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 1772 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 1773 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 1774 1775 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 1776 (fprintf (FILE,"ERROR: ASM_OUTPUT_REG_POP\n")) 1777 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 1778 (fprintf (FILE,"ERROR: ASM_OUTPUT_REG_PUSH\n")) 1779 1780 /* The following macro is taken from the */ 1781 /* C-text of varasm.c. It has been modified */ 1782 /* to handle the VARARG_SUSPECTED hack */ 1783 #define ASM_OUTPUT_ASCII(FILE, P , SIZE) \ 1784 { int i; \ 1785 fprintf ((FILE), "\t.ascii \""); \ 1786 VARARGS_SUSPECT( 0 == strncmp((P),"__%%VARARGS",11)); \ 1787 for (i = 0; i < (SIZE); i++) \ 1788 { \ 1789 register int c = (P)[i]; \ 1790 if (i != 0 && (i / 200) * 200 == i) \ 1791 fprintf ((FILE), "\"\n\t.ascii \""); \ 1792 if (c == '\"' || c == '\\') \ 1793 putc ('\\', (FILE)); \ 1794 if (c >= ' ' && c < 0177) \ 1795 putc (c, (FILE)); \ 1796 else \ 1797 { \ 1798 fprintf ((FILE), "\\%o", c); \ 1799 /* After an octal-escape, if a digit follows, \ 1800 terminate one string constant and start another. \ 1801 The Vax assembler fails to stop reading the escape \ 1802 after three digits, so this is the only way we \ 1803 can get it to parse the data properly. */ \ 1804 if (i < (SIZE) - 1 && (P)[i + 1] >= '0' && (P)[i + 1] <= '9')\ 1805 fprintf ((FILE), "\"\n\t.ascii \""); \ 1806 } \ 1807 } \ 1808 fprintf ((FILE), "\"\n"); \ 1809 } 1810 1811 1812 1813 /* Define the parentheses used to group arithmetic operations 1814 in assembler code. */ 1815 1816 #define ASM_OPEN_PAREN "(" 1817 #define ASM_CLOSE_PAREN ")" 1818 1819 /* Specify what to precede various sizes of constant with 1820 in the output file. */ 1821 1822 #define ASM_INT_OP ".word " 1823 #define ASM_SHORT_OP ".half " 1824 #define ASM_CHAR_OP ".byte " 1825 1826 1827 #define DEBUG_LOG_INSN(X) { \ 1828 extern rtx al_log_insn_debug; \ 1829 al_log_insn_debug=(X); } 1830