1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #ifndef __RTW_FW_H_
6 #define __RTW_FW_H_
7
8 #define H2C_PKT_SIZE 32
9 #define H2C_PKT_HDR_SIZE 8
10
11 /* FW bin information */
12 #define FW_HDR_SIZE 64
13 #define FW_HDR_CHKSUM_SIZE 8
14
15 #define FW_NLO_INFO_CHECK_SIZE 4
16
17 #define FIFO_PAGE_SIZE_SHIFT 12
18 #define FIFO_PAGE_SIZE 4096
19 #define FIFO_DUMP_ADDR 0x8000
20
21 #define DLFW_PAGE_SIZE_SHIFT_LEGACY 12
22 #define DLFW_PAGE_SIZE_LEGACY 0x1000
23 #define DLFW_BLK_SIZE_SHIFT_LEGACY 2
24 #define DLFW_BLK_SIZE_LEGACY 4
25 #define FW_START_ADDR_LEGACY 0x1000
26
27 #define BCN_LOSS_CNT 10
28 #define BCN_FILTER_NOTIFY_SIGNAL_CHANGE 0
29 #define BCN_FILTER_CONNECTION_LOSS 1
30 #define BCN_FILTER_CONNECTED 2
31 #define BCN_FILTER_NOTIFY_BEACON_LOSS 3
32 #define RTW_DEFAULT_CQM_THOLD -70
33 #define RTW_DEFAULT_CQM_HYST 4
34
35 #define SCAN_NOTIFY_TIMEOUT msecs_to_jiffies(10)
36
37 #define RTW_CHANNEL_TIME 45
38 #define RTW_OFF_CHAN_TIME 100
39 #define RTW_PASS_CHAN_TIME 105
40 #define RTW_DFS_CHAN_TIME 20
41 #define RTW_CH_INFO_SIZE 4
42 #define RTW_EX_CH_INFO_SIZE 3
43 #define RTW_EX_CH_INFO_HDR_SIZE 2
44 #define RTW_SCAN_WIDTH 0
45 #define RTW_PRI_CH_IDX 1
46 #define RTW_OLD_PROBE_PG_CNT 2
47 #define RTW_PROBE_PG_CNT 4
48
49 #define RTW_DEBUG_DUMP_TIMES 10
50
51 enum rtw_c2h_cmd_id {
52 C2H_CCX_TX_RPT = 0x03,
53 C2H_BT_INFO = 0x09,
54 C2H_BT_MP_INFO = 0x0b,
55 C2H_BT_HID_INFO = 0x45,
56 C2H_RA_RPT = 0x0c,
57 C2H_HW_FEATURE_REPORT = 0x19,
58 C2H_WLAN_INFO = 0x27,
59 C2H_WLAN_RFON = 0x32,
60 C2H_BCN_FILTER_NOTIFY = 0x36,
61 C2H_ADAPTIVITY = 0x37,
62 C2H_SCAN_RESULT = 0x38,
63 C2H_HW_FEATURE_DUMP = 0xfd,
64 C2H_HALMAC = 0xff,
65 };
66
67 enum rtw_c2h_cmd_id_ext {
68 C2H_SCAN_STATUS_RPT = 0x3,
69 C2H_CCX_RPT = 0x0f,
70 C2H_CHAN_SWITCH = 0x22,
71 };
72
73 struct rtw_c2h_cmd {
74 u8 id;
75 u8 seq;
76 u8 payload[];
77 } __packed;
78
79 struct rtw_c2h_adaptivity {
80 u8 density;
81 u8 igi;
82 u8 l2h_th_init;
83 u8 l2h;
84 u8 h2l;
85 u8 option;
86 } __packed;
87
88 struct rtw_h2c_register {
89 u32 w0;
90 u32 w1;
91 } __packed;
92
93 #define RTW_H2C_W0_CMDID GENMASK(7, 0)
94
95 /* H2C_CMD_DEFAULT_PORT command */
96 #define RTW_H2C_DEFAULT_PORT_W0_PORTID GENMASK(15, 8)
97 #define RTW_H2C_DEFAULT_PORT_W0_MACID GENMASK(23, 16)
98
99 struct rtw_h2c_cmd {
100 __le32 msg;
101 __le32 msg_ext;
102 } __packed;
103
104 enum rtw_rsvd_packet_type {
105 RSVD_BEACON,
106 RSVD_DUMMY,
107 RSVD_PS_POLL,
108 RSVD_PROBE_RESP,
109 RSVD_NULL,
110 RSVD_QOS_NULL,
111 RSVD_LPS_PG_DPK,
112 RSVD_LPS_PG_INFO,
113 RSVD_PROBE_REQ,
114 RSVD_NLO_INFO,
115 RSVD_CH_INFO,
116 };
117
118 enum rtw_fw_rf_type {
119 FW_RF_1T2R = 0,
120 FW_RF_2T4R = 1,
121 FW_RF_2T2R = 2,
122 FW_RF_2T3R = 3,
123 FW_RF_1T1R = 4,
124 FW_RF_2T2R_GREEN = 5,
125 FW_RF_3T3R = 6,
126 FW_RF_3T4R = 7,
127 FW_RF_4T4R = 8,
128 FW_RF_MAX_TYPE = 0xF,
129 };
130
131 enum rtw_fw_feature {
132 FW_FEATURE_SIG = BIT(0),
133 FW_FEATURE_LPS_C2H = BIT(1),
134 FW_FEATURE_LCLK = BIT(2),
135 FW_FEATURE_PG = BIT(3),
136 FW_FEATURE_TX_WAKE = BIT(4),
137 FW_FEATURE_BCN_FILTER = BIT(5),
138 FW_FEATURE_NOTIFY_SCAN = BIT(6),
139 FW_FEATURE_ADAPTIVITY = BIT(7),
140 FW_FEATURE_SCAN_OFFLOAD = BIT(8),
141 FW_FEATURE_MAX = BIT(31),
142 };
143
144 enum rtw_fw_feature_ext {
145 FW_FEATURE_EXT_OLD_PAGE_NUM = BIT(0),
146 };
147
148 enum rtw_beacon_filter_offload_mode {
149 BCN_FILTER_OFFLOAD_MODE_0 = 0,
150 BCN_FILTER_OFFLOAD_MODE_1,
151 BCN_FILTER_OFFLOAD_MODE_2,
152 BCN_FILTER_OFFLOAD_MODE_3,
153
154 BCN_FILTER_OFFLOAD_MODE_DEFAULT = BCN_FILTER_OFFLOAD_MODE_0,
155 };
156
157 struct rtw_coex_info_req {
158 u8 seq;
159 u8 op_code;
160 u8 para1;
161 u8 para2;
162 u8 para3;
163 };
164
165 struct rtw_iqk_para {
166 u8 clear;
167 u8 segment_iqk;
168 };
169
170 struct rtw_lps_pg_dpk_hdr {
171 u16 dpk_path_ok;
172 u8 dpk_txagc[2];
173 u16 dpk_gs[2];
174 u32 coef[2][20];
175 u8 dpk_ch;
176 } __packed;
177
178 struct rtw_lps_pg_info_hdr {
179 u8 macid;
180 u8 mbssid;
181 u8 pattern_count;
182 u8 mu_tab_group_id;
183 u8 sec_cam_count;
184 u8 tx_bu_page_count;
185 u16 rsvd;
186 u8 sec_cam[MAX_PG_CAM_BACKUP_NUM];
187 } __packed;
188
189 struct rtw_rsvd_page {
190 /* associated with each vif */
191 struct list_head vif_list;
192 struct rtw_vif *rtwvif;
193
194 /* associated when build rsvd page */
195 struct list_head build_list;
196
197 struct sk_buff *skb;
198 enum rtw_rsvd_packet_type type;
199 u8 page;
200 u16 tim_offset;
201 bool add_txdesc;
202 struct cfg80211_ssid *ssid;
203 u16 probe_req_size;
204 };
205
206 enum rtw_keep_alive_pkt_type {
207 KEEP_ALIVE_NULL_PKT = 0,
208 KEEP_ALIVE_ARP_RSP = 1,
209 };
210
211 struct rtw_nlo_info_hdr {
212 u8 nlo_count;
213 u8 hidden_ap_count;
214 u8 rsvd1[2];
215 u8 pattern_check[FW_NLO_INFO_CHECK_SIZE];
216 u8 rsvd2[8];
217 u8 ssid_len[16];
218 u8 chiper[16];
219 u8 rsvd3[16];
220 u8 location[8];
221 } __packed;
222
223 enum rtw_packet_type {
224 RTW_PACKET_PROBE_REQ = 0x00,
225
226 RTW_PACKET_UNDEFINE = 0x7FFFFFFF,
227 };
228
229 struct rtw_fw_wow_keep_alive_para {
230 bool adopt;
231 u8 pkt_type;
232 u8 period; /* unit: sec */
233 };
234
235 struct rtw_fw_wow_disconnect_para {
236 bool adopt;
237 u8 period; /* unit: sec */
238 u8 retry_count;
239 };
240
241 enum rtw_channel_type {
242 RTW_CHANNEL_PASSIVE,
243 RTW_CHANNEL_ACTIVE,
244 RTW_CHANNEL_RADAR,
245 };
246
247 enum rtw_scan_extra_id {
248 RTW_SCAN_EXTRA_ID_DFS,
249 };
250
251 enum rtw_scan_extra_info {
252 RTW_SCAN_EXTRA_ACTION_SCAN,
253 };
254
255 enum rtw_scan_report_code {
256 RTW_SCAN_REPORT_SUCCESS = 0x00,
257 RTW_SCAN_REPORT_ERR_PHYDM = 0x01,
258 RTW_SCAN_REPORT_ERR_ID = 0x02,
259 RTW_SCAN_REPORT_ERR_TX = 0x03,
260 RTW_SCAN_REPORT_CANCELED = 0x10,
261 RTW_SCAN_REPORT_CANCELED_EXT = 0x11,
262 RTW_SCAN_REPORT_FW_DISABLED = 0xF0,
263 };
264
265 enum rtw_scan_notify_id {
266 RTW_SCAN_NOTIFY_ID_PRESWITCH = 0x00,
267 RTW_SCAN_NOTIFY_ID_POSTSWITCH = 0x01,
268 RTW_SCAN_NOTIFY_ID_PROBE_PRETX = 0x02,
269 RTW_SCAN_NOTIFY_ID_PROBE_ISSUETX = 0x03,
270 RTW_SCAN_NOTIFY_ID_NULL0_PRETX = 0x04,
271 RTW_SCAN_NOTIFY_ID_NULL0_ISSUETX = 0x05,
272 RTW_SCAN_NOTIFY_ID_NULL0_POSTTX = 0x06,
273 RTW_SCAN_NOTIFY_ID_NULL1_PRETX = 0x07,
274 RTW_SCAN_NOTIFY_ID_NULL1_ISSUETX = 0x08,
275 RTW_SCAN_NOTIFY_ID_NULL1_POSTTX = 0x09,
276 RTW_SCAN_NOTIFY_ID_DWELLEXT = 0x0A,
277 };
278
279 enum rtw_scan_notify_status {
280 RTW_SCAN_NOTIFY_STATUS_SUCCESS = 0x00,
281 RTW_SCAN_NOTIFY_STATUS_FAILURE = 0x01,
282 RTW_SCAN_NOTIFY_STATUS_RESOURCE = 0x02,
283 RTW_SCAN_NOTIFY_STATUS_TIMEOUT = 0x03,
284 };
285
286 struct rtw_ch_switch_option {
287 u8 periodic_option;
288 u32 tsf_high;
289 u32 tsf_low;
290 u8 dest_ch_en;
291 u8 absolute_time_en;
292 u8 dest_ch;
293 u8 normal_period;
294 u8 normal_period_sel;
295 u8 normal_cycle;
296 u8 slow_period;
297 u8 slow_period_sel;
298 u8 nlo_en;
299 bool switch_en;
300 bool back_op_en;
301 };
302
303 struct rtw_fw_hdr {
304 __le16 signature;
305 u8 category;
306 u8 function;
307 __le16 version; /* 0x04 */
308 u8 subversion;
309 u8 subindex;
310 __le32 rsvd; /* 0x08 */
311 __le32 feature; /* 0x0C */
312 u8 month; /* 0x10 */
313 u8 day;
314 u8 hour;
315 u8 min;
316 __le16 year; /* 0x14 */
317 __le16 rsvd3;
318 u8 mem_usage; /* 0x18 */
319 u8 rsvd4[3];
320 __le16 h2c_fmt_ver; /* 0x1C */
321 __le16 rsvd5;
322 __le32 dmem_addr; /* 0x20 */
323 __le32 dmem_size;
324 __le32 rsvd6;
325 __le32 rsvd7;
326 __le32 imem_size; /* 0x30 */
327 __le32 emem_size;
328 __le32 emem_addr;
329 __le32 imem_addr;
330 } __packed;
331
332 struct rtw_fw_hdr_legacy {
333 __le16 signature;
334 u8 category;
335 u8 function;
336 __le16 version; /* 0x04 */
337 u8 subversion1;
338 u8 subversion2;
339 u8 month; /* 0x08 */
340 u8 day;
341 u8 hour;
342 u8 minute;
343 __le16 size;
344 __le16 rsvd2;
345 __le32 idx; /* 0x10 */
346 __le32 rsvd3;
347 __le32 rsvd4; /* 0x18 */
348 __le32 rsvd5;
349 } __packed;
350
351 #define RTW_FW_VER_CODE(ver, sub_ver, idx) \
352 (((ver) << 16) | ((sub_ver) << 8) | (idx))
353 #define RTW_FW_SUIT_VER_CODE(s) \
354 RTW_FW_VER_CODE((s).version, (s).sub_version, (s).sub_index)
355
356 /* C2H */
357 #define GET_CCX_REPORT_SEQNUM_V0(c2h_payload) (c2h_payload[6] & 0xfc)
358 #define GET_CCX_REPORT_STATUS_V0(c2h_payload) (c2h_payload[0] & 0xc0)
359 #define GET_CCX_REPORT_SEQNUM_V1(c2h_payload) (c2h_payload[8] & 0xfc)
360 #define GET_CCX_REPORT_STATUS_V1(c2h_payload) (c2h_payload[9] & 0xc0)
361
362 #define GET_SCAN_REPORT_RETURN_CODE(c2h_payload) (c2h_payload[2] & 0xff)
363
364 #define GET_CHAN_SWITCH_CENTRAL_CH(c2h_payload) (c2h_payload[2])
365 #define GET_CHAN_SWITCH_ID(c2h_payload) (c2h_payload[3])
366 #define GET_CHAN_SWITCH_STATUS(c2h_payload) (c2h_payload[4])
367 #define GET_RA_REPORT_RATE(c2h_payload) (c2h_payload[0] & 0x7f)
368 #define GET_RA_REPORT_SGI(c2h_payload) ((c2h_payload[0] & 0x80) >> 7)
369 #define GET_RA_REPORT_BW(c2h_payload) (c2h_payload[6])
370 #define GET_RA_REPORT_MACID(c2h_payload) (c2h_payload[1])
371
372 #define GET_BCN_FILTER_NOTIFY_TYPE(c2h_payload) (c2h_payload[1] & 0xf)
373 #define GET_BCN_FILTER_NOTIFY_EVENT(c2h_payload) (c2h_payload[1] & 0x10)
374 #define GET_BCN_FILTER_NOTIFY_RSSI(c2h_payload) (c2h_payload[2] - 100)
375
376 /* PKT H2C */
377 #define H2C_PKT_CMD_ID 0xFF
378 #define H2C_PKT_CATEGORY 0x01
379
380 #define H2C_PKT_GENERAL_INFO 0x0D
381 #define H2C_PKT_PHYDM_INFO 0x11
382 #define H2C_PKT_IQK 0x0E
383
384 #define H2C_PKT_CH_SWITCH 0x02
385 #define H2C_PKT_UPDATE_PKT 0x0C
386 #define H2C_PKT_SCAN_OFFLOAD 0x19
387
388 #define H2C_PKT_CH_SWITCH_LEN 0x20
389 #define H2C_PKT_UPDATE_PKT_LEN 0x4
390
391 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \
392 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0))
393 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \
394 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
395 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \
396 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16))
397 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \
398 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0))
399
rtw_h2c_pkt_set_header(u8 * h2c_pkt,u8 sub_id)400 static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id)
401 {
402 SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY);
403 SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID);
404 SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id);
405 }
406
407 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \
408 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16))
409 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \
410 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
411
412 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \
413 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0))
414 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \
415 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
416 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \
417 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
418 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \
419 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24))
420 #define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \
421 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28))
422 #define IQK_SET_CLEAR(h2c_pkt, value) \
423 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
424 #define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \
425 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
426
427 #define CHSW_INFO_SET_CH(pkt, value) \
428 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(7, 0))
429 #define CHSW_INFO_SET_PRI_CH_IDX(pkt, value) \
430 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(11, 8))
431 #define CHSW_INFO_SET_BW(pkt, value) \
432 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(15, 12))
433 #define CHSW_INFO_SET_TIMEOUT(pkt, value) \
434 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(23, 16))
435 #define CHSW_INFO_SET_ACTION_ID(pkt, value) \
436 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(30, 24))
437 #define CHSW_INFO_SET_EXTRA_INFO(pkt, value) \
438 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, BIT(31))
439
440 #define CH_INFO_SET_CH(pkt, value) \
441 u8p_replace_bits((u8 *)(pkt) + 0x00, value, GENMASK(7, 0))
442 #define CH_INFO_SET_PRI_CH_IDX(pkt, value) \
443 u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(3, 0))
444 #define CH_INFO_SET_BW(pkt, value) \
445 u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(7, 4))
446 #define CH_INFO_SET_TIMEOUT(pkt, value) \
447 u8p_replace_bits((u8 *)(pkt) + 0x02, value, GENMASK(7, 0))
448 #define CH_INFO_SET_ACTION_ID(pkt, value) \
449 u8p_replace_bits((u8 *)(pkt) + 0x03, value, GENMASK(6, 0))
450 #define CH_INFO_SET_EXTRA_INFO(pkt, value) \
451 u8p_replace_bits((u8 *)(pkt) + 0x03, value, BIT(7))
452
453 #define EXTRA_CH_INFO_SET_ID(pkt, value) \
454 u8p_replace_bits((u8 *)(pkt) + 0x04, value, GENMASK(6, 0))
455 #define EXTRA_CH_INFO_SET_INFO(pkt, value) \
456 u8p_replace_bits((u8 *)(pkt) + 0x04, value, BIT(7))
457 #define EXTRA_CH_INFO_SET_SIZE(pkt, value) \
458 u8p_replace_bits((u8 *)(pkt) + 0x05, value, GENMASK(7, 0))
459 #define EXTRA_CH_INFO_SET_DFS_EXT_TIME(pkt, value) \
460 u8p_replace_bits((u8 *)(pkt) + 0x06, value, GENMASK(7, 0))
461
462 #define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \
463 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 0))
464 #define UPDATE_PKT_SET_PKT_ID(h2c_pkt, value) \
465 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
466 #define UPDATE_PKT_SET_LOCATION(h2c_pkt, value) \
467 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 24))
468
469 #define CH_SWITCH_SET_START(h2c_pkt, value) \
470 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
471 #define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \
472 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
473 #define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \
474 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2))
475 #define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \
476 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(4, 3))
477 #define CH_SWITCH_SET_SCAN_MODE(h2c_pkt, value) \
478 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(5))
479 #define CH_SWITCH_SET_BACK_OP_EN(h2c_pkt, value) \
480 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(6))
481 #define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \
482 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
483 #define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \
484 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
485 #define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \
486 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24))
487 #define CH_SWITCH_SET_DEST_BW(h2c_pkt, value) \
488 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28))
489 #define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \
490 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0))
491 #define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \
492 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(13, 8))
493 #define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \
494 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 14))
495 #define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \
496 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(21, 16))
497 #define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \
498 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 22))
499 #define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \
500 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(31, 24))
501 #define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \
502 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 0))
503 #define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \
504 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(31, 0))
505 #define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \
506 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x06, value, GENMASK(15, 0))
507
508 #define SCAN_OFFLOAD_SET_START(h2c_pkt, value) \
509 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
510 #define SCAN_OFFLOAD_SET_BACK_OP_EN(h2c_pkt, value) \
511 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
512 #define SCAN_OFFLOAD_SET_RANDOM_SEQ_EN(h2c_pkt, value) \
513 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2))
514 #define SCAN_OFFLOAD_SET_NO_CCK_EN(h2c_pkt, value) \
515 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(3))
516 #define SCAN_OFFLOAD_SET_VERBOSE(h2c_pkt, value) \
517 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(4))
518 #define SCAN_OFFLOAD_SET_CH_NUM(h2c_pkt, value) \
519 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
520 #define SCAN_OFFLOAD_SET_CH_INFO_SIZE(h2c_pkt, value) \
521 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 16))
522 #define SCAN_OFFLOAD_SET_CH_INFO_LOC(h2c_pkt, value) \
523 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0))
524 #define SCAN_OFFLOAD_SET_OP_CH(h2c_pkt, value) \
525 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 8))
526 #define SCAN_OFFLOAD_SET_OP_PRI_CH_IDX(h2c_pkt, value) \
527 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(19, 16))
528 #define SCAN_OFFLOAD_SET_OP_BW(h2c_pkt, value) \
529 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 20))
530 #define SCAN_OFFLOAD_SET_OP_PORT_ID(h2c_pkt, value) \
531 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(26, 24))
532 #define SCAN_OFFLOAD_SET_OP_DWELL_TIME(h2c_pkt, value) \
533 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(15, 0))
534 #define SCAN_OFFLOAD_SET_OP_GAP_TIME(h2c_pkt, value) \
535 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 16))
536 #define SCAN_OFFLOAD_SET_MODE(h2c_pkt, value) \
537 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(3, 0))
538 #define SCAN_OFFLOAD_SET_SSID_NUM(h2c_pkt, value) \
539 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(7, 4))
540 #define SCAN_OFFLOAD_SET_PKT_LOC(h2c_pkt, value) \
541 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(15, 8))
542
543 /* Command H2C */
544 #define H2C_CMD_RSVD_PAGE 0x0
545 #define H2C_CMD_MEDIA_STATUS_RPT 0x01
546 #define H2C_CMD_SET_PWR_MODE 0x20
547 #define H2C_CMD_LPS_PG_INFO 0x2b
548 #define H2C_CMD_DEFAULT_PORT 0x2c
549 #define H2C_CMD_RA_INFO 0x40
550 #define H2C_CMD_RSSI_MONITOR 0x42
551 #define H2C_CMD_BCN_FILTER_OFFLOAD_P0 0x56
552 #define H2C_CMD_BCN_FILTER_OFFLOAD_P1 0x57
553 #define H2C_CMD_WL_PHY_INFO 0x58
554 #define H2C_CMD_SCAN 0x59
555 #define H2C_CMD_ADAPTIVITY 0x5A
556
557 #define H2C_CMD_COEX_TDMA_TYPE 0x60
558 #define H2C_CMD_QUERY_BT_INFO 0x61
559 #define H2C_CMD_FORCE_BT_TX_POWER 0x62
560 #define H2C_CMD_IGNORE_WLAN_ACTION 0x63
561 #define H2C_CMD_WL_CH_INFO 0x66
562 #define H2C_CMD_QUERY_BT_MP_INFO 0x67
563 #define H2C_CMD_BT_WIFI_CONTROL 0x69
564 #define H2C_CMD_WIFI_CALIBRATION 0x6d
565 #define H2C_CMD_QUERY_BT_HID_INFO 0x73
566
567 #define H2C_CMD_KEEP_ALIVE 0x03
568 #define H2C_CMD_DISCONNECT_DECISION 0x04
569 #define H2C_CMD_WOWLAN 0x80
570 #define H2C_CMD_REMOTE_WAKE_CTRL 0x81
571 #define H2C_CMD_AOAC_GLOBAL_INFO 0x82
572 #define H2C_CMD_NLO_INFO 0x8C
573
574 #define H2C_CMD_RECOVER_BT_DEV 0xD1
575
576 #define SET_H2C_CMD_ID_CLASS(h2c_pkt, value) \
577 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0))
578
579 #define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \
580 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
581 #define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \
582 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
583
584 #define SET_WL_PHY_INFO_TX_TP(h2c_pkt, value) \
585 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(17, 8))
586 #define SET_WL_PHY_INFO_RX_TP(h2c_pkt, value) \
587 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(27, 18))
588 #define SET_WL_PHY_INFO_TX_RATE_DESC(h2c_pkt, value) \
589 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
590 #define SET_WL_PHY_INFO_RX_RATE_DESC(h2c_pkt, value) \
591 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
592 #define SET_WL_PHY_INFO_RX_EVM(h2c_pkt, value) \
593 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
594 #define SET_BCN_FILTER_OFFLOAD_P1_MACID(h2c_pkt, value) \
595 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
596 #define SET_BCN_FILTER_OFFLOAD_P1_ENABLE(h2c_pkt, value) \
597 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(16))
598 #define SET_BCN_FILTER_OFFLOAD_P1_HYST(h2c_pkt, value) \
599 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 17))
600 #define SET_BCN_FILTER_OFFLOAD_P1_OFFLOAD_MODE(h2c_pkt, value) \
601 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 21))
602 #define SET_BCN_FILTER_OFFLOAD_P1_THRESHOLD(h2c_pkt, value) \
603 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
604 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_LOSS_CNT(h2c_pkt, value) \
605 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(3, 0))
606 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_INTERVAL(h2c_pkt, value) \
607 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(13, 4))
608
609 #define SET_SCAN_START(h2c_pkt, value) \
610 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
611
612 #define SET_ADAPTIVITY_MODE(h2c_pkt, value) \
613 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(11, 8))
614 #define SET_ADAPTIVITY_OPTION(h2c_pkt, value) \
615 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))
616 #define SET_ADAPTIVITY_IGI(h2c_pkt, value) \
617 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
618 #define SET_ADAPTIVITY_L2H(h2c_pkt, value) \
619 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
620 #define SET_ADAPTIVITY_DENSITY(h2c_pkt, value) \
621 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
622
623 #define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \
624 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8))
625 #define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \
626 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16))
627 #define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \
628 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20))
629 #define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \
630 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
631 #define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \
632 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5))
633 #define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \
634 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
635 #define LPS_PG_INFO_LOC(h2c_pkt, value) \
636 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
637 #define LPS_PG_DPK_LOC(h2c_pkt, value) \
638 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
639 #define LPS_PG_SEC_CAM_EN(h2c_pkt, value) \
640 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
641 #define LPS_PG_PATTERN_CAM_EN(h2c_pkt, value) \
642 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
643 #define SET_RSSI_INFO_MACID(h2c_pkt, value) \
644 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
645 #define SET_RSSI_INFO_RSSI(h2c_pkt, value) \
646 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
647 #define SET_RSSI_INFO_STBC(h2c_pkt, value) \
648 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1))
649 #define SET_RA_INFO_MACID(h2c_pkt, value) \
650 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
651 #define SET_RA_INFO_RATE_ID(h2c_pkt, value) \
652 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16))
653 #define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value) \
654 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21))
655 #define SET_RA_INFO_SGI_EN(h2c_pkt, value) \
656 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23))
657 #define SET_RA_INFO_BW_MODE(h2c_pkt, value) \
658 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24))
659 #define SET_RA_INFO_LDPC(h2c_pkt, value) \
660 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26))
661 #define SET_RA_INFO_NO_UPDATE(h2c_pkt, value) \
662 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27))
663 #define SET_RA_INFO_VHT_EN(h2c_pkt, value) \
664 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28))
665 #define SET_RA_INFO_DIS_PT(h2c_pkt, value) \
666 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30))
667 #define SET_RA_INFO_RA_MASK0(h2c_pkt, value) \
668 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
669 #define SET_RA_INFO_RA_MASK1(h2c_pkt, value) \
670 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
671 #define SET_RA_INFO_RA_MASK2(h2c_pkt, value) \
672 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
673 #define SET_RA_INFO_RA_MASK3(h2c_pkt, value) \
674 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24))
675 #define SET_QUERY_BT_INFO(h2c_pkt, value) \
676 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
677 #define SET_WL_CH_INFO_LINK(h2c_pkt, value) \
678 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
679 #define SET_WL_CH_INFO_CHNL(h2c_pkt, value) \
680 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
681 #define SET_WL_CH_INFO_BW(h2c_pkt, value) \
682 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
683 #define SET_BT_MP_INFO_SEQ(h2c_pkt, value) \
684 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))
685 #define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value) \
686 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
687 #define SET_BT_MP_INFO_PARA1(h2c_pkt, value) \
688 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
689 #define SET_BT_MP_INFO_PARA2(h2c_pkt, value) \
690 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
691 #define SET_BT_MP_INFO_PARA3(h2c_pkt, value) \
692 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
693 #define SET_BT_TX_POWER_INDEX(h2c_pkt, value) \
694 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
695 #define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value) \
696 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
697 #define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value) \
698 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
699 #define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value) \
700 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
701 #define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value) \
702 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
703 #define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value) \
704 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
705 #define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value) \
706 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
707 #define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value) \
708 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
709 #define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value) \
710 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
711 #define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value) \
712 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
713 #define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value) \
714 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
715 #define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value) \
716 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
717 #define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value) \
718 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
719
720 #define SET_COEX_QUERY_HID_INFO_SUBID(h2c_pkt, value) \
721 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
722 #define SET_COEX_QUERY_HID_INFO_DATA1(h2c_pkt, value) \
723 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
724
725 #define SET_KEEP_ALIVE_ENABLE(h2c_pkt, value) \
726 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
727 #define SET_KEEP_ALIVE_ADOPT(h2c_pkt, value) \
728 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
729 #define SET_KEEP_ALIVE_PKT_TYPE(h2c_pkt, value) \
730 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
731 #define SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \
732 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
733
734 #define SET_DISCONNECT_DECISION_ENABLE(h2c_pkt, value) \
735 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
736 #define SET_DISCONNECT_DECISION_ADOPT(h2c_pkt, value) \
737 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
738 #define SET_DISCONNECT_DECISION_CHECK_PERIOD(h2c_pkt, value) \
739 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
740 #define SET_DISCONNECT_DECISION_TRY_PKT_NUM(h2c_pkt, value) \
741 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
742
743 #define SET_WOWLAN_FUNC_ENABLE(h2c_pkt, value) \
744 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
745 #define SET_WOWLAN_PATTERN_MATCH_ENABLE(h2c_pkt, value) \
746 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
747 #define SET_WOWLAN_MAGIC_PKT_ENABLE(h2c_pkt, value) \
748 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
749 #define SET_WOWLAN_UNICAST_PKT_ENABLE(h2c_pkt, value) \
750 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(11))
751 #define SET_WOWLAN_REKEY_WAKEUP_ENABLE(h2c_pkt, value) \
752 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(14))
753 #define SET_WOWLAN_DEAUTH_WAKEUP_ENABLE(h2c_pkt, value) \
754 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(15))
755
756 #define SET_REMOTE_WAKECTRL_ENABLE(h2c_pkt, value) \
757 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
758 #define SET_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(h2c_pkt, value) \
759 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(12))
760
761 #define SET_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(h2c_pkt, value) \
762 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
763 #define SET_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(h2c_pkt, value) \
764 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
765
766 #define SET_NLO_FUN_EN(h2c_pkt, value) \
767 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
768 #define SET_NLO_PS_32K(h2c_pkt, value) \
769 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
770 #define SET_NLO_IGNORE_SECURITY(h2c_pkt, value) \
771 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
772 #define SET_NLO_LOC_NLO_INFO(h2c_pkt, value) \
773 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
774
775 #define SET_RECOVER_BT_DEV_EN(h2c_pkt, value) \
776 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
777
778 #define GET_FW_DUMP_LEN(_header) \
779 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(15, 0))
780 #define GET_FW_DUMP_SEQ(_header) \
781 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(22, 16))
782 #define GET_FW_DUMP_MORE(_header) \
783 le32_get_bits(*((__le32 *)(_header) + 0x00), BIT(23))
784 #define GET_FW_DUMP_VERSION(_header) \
785 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(31, 24))
786 #define GET_FW_DUMP_TLV_TYPE(_header) \
787 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(15, 0))
788 #define GET_FW_DUMP_TLV_LEN(_header) \
789 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(31, 16))
790 #define GET_FW_DUMP_TLV_VAL(_header) \
791 le32_get_bits(*((__le32 *)(_header) + 0x02), GENMASK(31, 0))
792
793 #define RFK_SET_INFORM_START(h2c_pkt, value) \
794 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
get_c2h_from_skb(struct sk_buff * skb)795 static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb)
796 {
797 u32 pkt_offset;
798
799 pkt_offset = *((u32 *)skb->cb);
800 return (struct rtw_c2h_cmd *)(skb->data + pkt_offset);
801 }
802
rtw_fw_feature_check(struct rtw_fw_state * fw,enum rtw_fw_feature feature)803 static inline bool rtw_fw_feature_check(struct rtw_fw_state *fw,
804 enum rtw_fw_feature feature)
805 {
806 return !!(fw->feature & feature);
807 }
808
rtw_fw_feature_ext_check(struct rtw_fw_state * fw,enum rtw_fw_feature_ext feature)809 static inline bool rtw_fw_feature_ext_check(struct rtw_fw_state *fw,
810 enum rtw_fw_feature_ext feature)
811 {
812 return !!(fw->feature_ext & feature);
813 }
814
815 void rtw_fw_dump_dbg_info(struct rtw_dev *rtwdev);
816 void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset,
817 struct sk_buff *skb);
818 void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb);
819 void rtw_fw_send_general_info(struct rtw_dev *rtwdev);
820 void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev);
821 void rtw_fw_default_port(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif);
822
823 void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para);
824 void rtw_fw_inform_rfk_status(struct rtw_dev *rtwdev, bool start);
825 void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev);
826 void rtw_fw_set_pg_info(struct rtw_dev *rtwdev);
827 void rtw_fw_query_bt_info(struct rtw_dev *rtwdev);
828 void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw);
829 void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev,
830 struct rtw_coex_info_req *req);
831 void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl);
832 void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable);
833 void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev,
834 u8 para1, u8 para2, u8 para3, u8 para4, u8 para5);
835 void rtw_fw_coex_query_hid_info(struct rtw_dev *rtwdev, u8 sub_id, u8 data);
836
837 void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data);
838 void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
839 void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
840 bool reset_ra_mask);
841 void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn);
842 void rtw_fw_update_wl_phy_info(struct rtw_dev *rtwdev);
843 void rtw_fw_beacon_filter_config(struct rtw_dev *rtwdev, bool connect,
844 struct ieee80211_vif *vif);
845 int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
846 u8 *buf, u32 size);
847 void rtw_remove_rsvd_page(struct rtw_dev *rtwdev,
848 struct rtw_vif *rtwvif);
849 void rtw_add_rsvd_page_bcn(struct rtw_dev *rtwdev,
850 struct rtw_vif *rtwvif);
851 void rtw_add_rsvd_page_pno(struct rtw_dev *rtwdev,
852 struct rtw_vif *rtwvif);
853 void rtw_add_rsvd_page_sta(struct rtw_dev *rtwdev,
854 struct rtw_vif *rtwvif);
855 int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev);
856 void rtw_fw_update_beacon_work(struct work_struct *work);
857 void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev);
858 int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev,
859 u32 offset, u32 size, u32 *buf);
860 void rtw_fw_set_remote_wake_ctrl_cmd(struct rtw_dev *rtwdev, bool enable);
861 void rtw_fw_set_wowlan_ctrl_cmd(struct rtw_dev *rtwdev, bool enable);
862 void rtw_fw_set_keep_alive_cmd(struct rtw_dev *rtwdev, bool enable);
863 void rtw_fw_set_disconnect_decision_cmd(struct rtw_dev *rtwdev, bool enable);
864 void rtw_fw_set_aoac_global_info_cmd(struct rtw_dev *rtwdev,
865 u8 pairwise_key_enc,
866 u8 group_key_enc);
867
868 void rtw_fw_set_nlo_info(struct rtw_dev *rtwdev, bool enable);
869 void rtw_fw_set_recover_bt_device(struct rtw_dev *rtwdev);
870 void rtw_fw_update_pkt_probe_req(struct rtw_dev *rtwdev,
871 struct cfg80211_ssid *ssid);
872 void rtw_fw_channel_switch(struct rtw_dev *rtwdev, bool enable);
873 void rtw_fw_h2c_cmd_dbg(struct rtw_dev *rtwdev, u8 *h2c);
874 void rtw_fw_c2h_cmd_isr(struct rtw_dev *rtwdev);
875 int rtw_fw_dump_fifo(struct rtw_dev *rtwdev, u8 fifo_sel, u32 addr, u32 size,
876 u32 *buffer);
877 void rtw_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
878 void rtw_fw_adaptivity(struct rtw_dev *rtwdev);
879 void rtw_store_op_chan(struct rtw_dev *rtwdev, bool backup);
880 void rtw_clear_op_chan(struct rtw_dev *rtwdev);
881 void rtw_hw_scan_start(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
882 struct ieee80211_scan_request *req);
883 void rtw_hw_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
884 bool aborted);
885 int rtw_hw_scan_offload(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
886 bool enable);
887 void rtw_hw_scan_status_report(struct rtw_dev *rtwdev, struct sk_buff *skb);
888 void rtw_hw_scan_chan_switch(struct rtw_dev *rtwdev, struct sk_buff *skb);
889 void rtw_hw_scan_abort(struct rtw_dev *rtwdev);
890 #endif
891