1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright 2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  *  and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 #ifndef __DC_DIO_STREAM_ENCODER_DCN314_H__
28 #define __DC_DIO_STREAM_ENCODER_DCN314_H__
29 
30 #include "dcn30/dcn30_vpg.h"
31 #include "dcn30/dcn30_afmt.h"
32 #include "stream_encoder.h"
33 #include "dcn20/dcn20_stream_encoder.h"
34 
35 /* Register bit field name change */
36 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT                                        0x8
37 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT                                              0x9
38 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0xa
39 #define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT                                                      0xe
40 #define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT                                              0xf
41 
42 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK                                          0x00000100L
43 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK                                                0x00000200L
44 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000400L
45 #define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK                                                        0x00004000L
46 #define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK                                                0x00008000L
47 
48 
49 #define SE_DCN314_REG_LIST(id)\
50 	SRI(AFMT_CNTL, DIG, id), \
51 	SRI(DIG_FE_CNTL, DIG, id), \
52 	SRI(HDMI_CONTROL, DIG, id), \
53 	SRI(HDMI_DB_CONTROL, DIG, id), \
54 	SRI(HDMI_GC, DIG, id), \
55 	SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
56 	SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
57 	SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
58 	SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
59 	SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \
60 	SRI(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \
61 	SRI(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \
62 	SRI(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \
63 	SRI(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \
64 	SRI(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \
65 	SRI(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \
66 	SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
67 	SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
68 	SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
69 	SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
70 	SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
71 	SRI(HDMI_ACR_32_0, DIG, id),\
72 	SRI(HDMI_ACR_32_1, DIG, id),\
73 	SRI(HDMI_ACR_44_0, DIG, id),\
74 	SRI(HDMI_ACR_44_1, DIG, id),\
75 	SRI(HDMI_ACR_48_0, DIG, id),\
76 	SRI(HDMI_ACR_48_1, DIG, id),\
77 	SRI(DP_DB_CNTL, DP, id), \
78 	SRI(DP_MSA_MISC, DP, id), \
79 	SRI(DP_MSA_VBID_MISC, DP, id), \
80 	SRI(DP_MSA_COLORIMETRY, DP, id), \
81 	SRI(DP_MSA_TIMING_PARAM1, DP, id), \
82 	SRI(DP_MSA_TIMING_PARAM2, DP, id), \
83 	SRI(DP_MSA_TIMING_PARAM3, DP, id), \
84 	SRI(DP_MSA_TIMING_PARAM4, DP, id), \
85 	SRI(DP_MSE_RATE_CNTL, DP, id), \
86 	SRI(DP_MSE_RATE_UPDATE, DP, id), \
87 	SRI(DP_PIXEL_FORMAT, DP, id), \
88 	SRI(DP_SEC_CNTL, DP, id), \
89 	SRI(DP_SEC_CNTL1, DP, id), \
90 	SRI(DP_SEC_CNTL2, DP, id), \
91 	SRI(DP_SEC_CNTL5, DP, id), \
92 	SRI(DP_SEC_CNTL6, DP, id), \
93 	SRI(DP_STEER_FIFO, DP, id), \
94 	SRI(DP_VID_M, DP, id), \
95 	SRI(DP_VID_N, DP, id), \
96 	SRI(DP_VID_STREAM_CNTL, DP, id), \
97 	SRI(DP_VID_TIMING, DP, id), \
98 	SRI(DP_SEC_AUD_N, DP, id), \
99 	SRI(DP_SEC_TIMESTAMP, DP, id), \
100 	SRI(DP_DSC_CNTL, DP, id), \
101 	SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
102 	SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
103 	SRI(DP_SEC_FRAMING4, DP, id), \
104 	SRI(DP_GSP11_CNTL, DP, id), \
105 	SRI(DME_CONTROL, DME, id),\
106 	SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
107 	SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
108 	SRI(DIG_FE_CNTL, DIG, id), \
109 	SRI(DIG_CLOCK_PATTERN, DIG, id), \
110 	SRI(DIG_FIFO_CTRL0, DIG, id)
111 
112 
113 #define SE_COMMON_MASK_SH_LIST_DCN314(mask_sh)\
114 	SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
115 	SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
116 	SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, mask_sh),\
117 	SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
118 	SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
119 	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
120 	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
121 	SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
122 	SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\
123 	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
124 	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
125 	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
126 	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\
127 	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
128 	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
129 	SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
130 	SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
131 	SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
132 	SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
133 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
134 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
135 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
136 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
137 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
138 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
139 	SE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, mask_sh),\
140 	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND, mask_sh),\
141 	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, mask_sh),\
142 	SE_SF(DP0_DP_SEC_CNTL4, DP_SEC_GSP4_LINE_NUM, mask_sh),\
143 	SE_SF(DP0_DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM, mask_sh),\
144 	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, mask_sh),\
145 	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
146 	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
147 	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
148 	SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
149 	SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
150 	SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
151 	SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
152 	SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
153 	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
154 	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
155 	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
156 	SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
157 	SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
158 	SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
159 	SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
160 	SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
161 	SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
162 	SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
163 	SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
164 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
165 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
166 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
167 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
168 	SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
169 	SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
170 	SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
171 	SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
172 	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
173 	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
174 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
175 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
176 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
177 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
178 	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\
179 	SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\
180 	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP11_PPS, mask_sh),\
181 	SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, mask_sh),\
182 	SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, mask_sh),\
183 	SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
184 	SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
185 	SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
186 	SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
187 	SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
188 	SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
189 	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
190 	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
191 	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
192 	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
193 	SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
194 	SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
195 	SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
196 	SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
197 	SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh), \
198 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
199 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
200 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
201 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
202 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_CONT, mask_sh),\
203 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_SEND, mask_sh),\
204 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_CONT, mask_sh),\
205 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_SEND, mask_sh),\
206 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_CONT, mask_sh),\
207 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_SEND, mask_sh),\
208 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_CONT, mask_sh),\
209 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_SEND, mask_sh),\
210 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_CONT, mask_sh),\
211 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_SEND, mask_sh),\
212 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_CONT, mask_sh),\
213 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_SEND, mask_sh),\
214 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC8_CONT, mask_sh),\
215 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC8_SEND, mask_sh),\
216 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC9_CONT, mask_sh),\
217 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC9_SEND, mask_sh),\
218 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC10_CONT, mask_sh),\
219 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC10_SEND, mask_sh),\
220 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC11_CONT, mask_sh),\
221 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC11_SEND, mask_sh),\
222 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC12_CONT, mask_sh),\
223 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC12_SEND, mask_sh),\
224 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC13_CONT, mask_sh),\
225 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC13_SEND, mask_sh),\
226 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC14_CONT, mask_sh),\
227 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC14_SEND, mask_sh),\
228 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC0_LINE, mask_sh),\
229 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC1_LINE, mask_sh),\
230 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC2_LINE, mask_sh),\
231 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC3_LINE, mask_sh),\
232 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC4_LINE, mask_sh),\
233 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC5_LINE, mask_sh),\
234 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC6_LINE, mask_sh),\
235 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC7_LINE, mask_sh),\
236 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL7, HDMI_GENERIC8_LINE, mask_sh),\
237 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL7, HDMI_GENERIC9_LINE, mask_sh),\
238 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL8, HDMI_GENERIC10_LINE, mask_sh),\
239 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL8, HDMI_GENERIC11_LINE, mask_sh),\
240 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL9, HDMI_GENERIC12_LINE, mask_sh),\
241 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL9, HDMI_GENERIC13_LINE, mask_sh),\
242 	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL10, HDMI_GENERIC14_LINE, mask_sh),\
243 	SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\
244 	SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, mask_sh),\
245 	SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, mask_sh),\
246 	SE_SF(DME0_DME_CONTROL, METADATA_ENGINE_EN, mask_sh),\
247 	SE_SF(DME0_DME_CONTROL, METADATA_HUBP_REQUESTOR_ID, mask_sh),\
248 	SE_SF(DME0_DME_CONTROL, METADATA_STREAM_TYPE, mask_sh),\
249 	SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_ENABLE, mask_sh),\
250 	SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE_REFERENCE, mask_sh),\
251 	SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE, mask_sh),\
252 	SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_ENABLE, mask_sh),\
253 	SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE_REFERENCE, mask_sh),\
254 	SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE, mask_sh),\
255 	SE_SF(DIG0_DIG_FE_CNTL, DOLBY_VISION_EN, mask_sh),\
256 	SE_SF(DIG0_DIG_FE_CNTL, DIG_SYMCLK_FE_ON, mask_sh),\
257 	SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh),\
258 	SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\
259 	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, mask_sh),\
260 	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, mask_sh),\
261 	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, mask_sh),\
262 	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET, mask_sh),\
263 	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, mask_sh)
264 
265 void dcn314_dio_stream_encoder_construct(
266 	struct dcn10_stream_encoder *enc1,
267 	struct dc_context *ctx,
268 	struct dc_bios *bp,
269 	enum engine_id eng_id,
270 	struct vpg *vpg,
271 	struct afmt *afmt,
272 	const struct dcn10_stream_enc_registers *regs,
273 	const struct dcn10_stream_encoder_shift *se_shift,
274 	const struct dcn10_stream_encoder_mask *se_mask);
275 
276 void enc3_stream_encoder_update_hdmi_info_packets(
277 	struct stream_encoder *enc,
278 	const struct encoder_info_frame *info_frame);
279 
280 void enc3_stream_encoder_stop_hdmi_info_packets(
281 	struct stream_encoder *enc);
282 
283 void enc3_stream_encoder_update_dp_info_packets_sdp_line_num(
284 		struct stream_encoder *enc,
285 		struct encoder_info_frame *info_frame);
286 
287 void enc3_stream_encoder_update_dp_info_packets(
288 	struct stream_encoder *enc,
289 	const struct encoder_info_frame *info_frame);
290 
291 void enc3_audio_mute_control(
292 	struct stream_encoder *enc,
293 	bool mute);
294 
295 void enc3_se_dp_audio_setup(
296 	struct stream_encoder *enc,
297 	unsigned int az_inst,
298 	struct audio_info *info);
299 
300 void enc3_se_dp_audio_enable(
301 	struct stream_encoder *enc);
302 
303 void enc3_se_hdmi_audio_setup(
304 	struct stream_encoder *enc,
305 	unsigned int az_inst,
306 	struct audio_info *info,
307 	struct audio_crtc_info *audio_crtc_info);
308 
309 void enc3_dp_set_dsc_pps_info_packet(
310 	struct stream_encoder *enc,
311 	bool enable,
312 	uint8_t *dsc_packed_pps,
313 	bool immediate_update);
314 
315 void enc314_stream_encoder_dvi_set_stream_attribute(
316 	struct stream_encoder *enc,
317 	struct dc_crtc_timing *crtc_timing,
318 	bool is_dual_link);
319 
320 void enc314_stream_encoder_hdmi_set_stream_attribute(
321 	struct stream_encoder *enc,
322 	struct dc_crtc_timing *crtc_timing,
323 	int actual_pix_clk_khz,
324 	bool enable_audio);
325 
326 void enc314_stream_encoder_dp_blank(
327 	struct dc_link *link,
328 	struct stream_encoder *enc);
329 
330 void enc314_stream_encoder_dp_unblank(
331 		struct dc_link *link,
332 		struct stream_encoder *enc,
333 		const struct encoder_unblank_param *param);
334 
335 void enc314_reset_fifo(struct stream_encoder *enc, bool reset);
336 
337 void enc314_enable_fifo(struct stream_encoder *enc);
338 
339 void enc314_disable_fifo(struct stream_encoder *enc);
340 
341 void enc314_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container);
342 
343 void enc314_read_state(struct stream_encoder *enc, struct enc_state *s);
344 
345 void enc314_dp_set_odm_combine(
346 	struct stream_encoder *enc,
347 	bool odm_combine);
348 
349 void enc314_dp_set_dsc_config(
350 	struct stream_encoder *enc,
351 	enum optc_dsc_mode dsc_mode,
352 	uint32_t dsc_bytes_per_pixel,
353 	uint32_t dsc_slice_width);
354 
355 #endif /* __DC_DIO_STREAM_ENCODER_DCN314_H__ */
356