1 /* $OpenBSD: cache_sh3.h,v 1.2 2008/06/26 05:42:12 ray Exp $ */ 2 /* $NetBSD: cache_sh3.h,v 1.8 2006/03/04 01:55:03 uwe Exp $ */ 3 4 /*- 5 * Copyright (c) 2002 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by UCHIYAMA Yasushi. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * SH3: SH7708, SH7708S, SH7708R, SH7709, SH7709A 35 */ 36 #ifndef _SH_CACHE_SH3_H_ 37 #define _SH_CACHE_SH3_H_ 38 #include <sh/devreg.h> 39 #ifdef _KERNEL 40 41 #define SH3_CCR 0xffffffec 42 #define SH3_CCR_CE 0x00000001 43 #define SH3_CCR_WT 0x00000002 44 /* SH7708 don't have CB bit */ 45 #define SH3_CCR_CB 0x00000004 46 #define SH3_CCR_CF 0x00000008 47 /* SH7709A don't have RA bit */ 48 #define SH3_CCR_RA 0x00000020 49 50 /* SH7709A specific cache-lock control register */ 51 #define SH7709A_CCR2 0xa40000b0 52 #define SH7709A_CCR2_W2LOCK 0x00000001 53 #define SH7709A_CCR2_W2LOAD 0x00000002 54 #define SH7709A_CCR2_W3LOCK 0x00000100 55 #define SH7709A_CCR2_W3LOAD 0x00000200 56 57 #define SH3_CCA 0xf0000000 58 /* Address specification */ 59 #define CCA_A 0x00000008 60 #define CCA_ENTRY_SHIFT 4 61 /* 8KB cache (SH7708, SH7708S, SH7708R, SH7709) */ 62 #define CCA_8K_ENTRY 128 63 #define CCA_8K_ENTRY_MASK 0x000007f0 /* [10:4] */ 64 #define CCA_8K_WAY_SHIFT 11 65 #define CCA_8K_WAY_MASK 0x00001800 /* [12:11] */ 66 /* 16KB cache (SH7709A) */ 67 #define CCA_16K_ENTRY 256 68 #define CCA_16K_ENTRY_MASK 0x00000ff0 /* [11:4] */ 69 #define CCA_16K_WAY_SHIFT 12 70 #define CCA_16K_WAY_MASK 0x00003000 /* [13:12] */ 71 72 /* Data specification */ 73 #define CCA_V 0x00000001 74 #define CCA_U 0x00000002 75 #define CCA_LRU_SHIFT 4 76 #define CCA_LRU_MASK 0x000003f0 /* [9:4] */ 77 #define CCA_TAGADDR_SHIFT 10 78 #define CCA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 79 80 #define SH3_CCD 0xf1000000 81 /* Address specification */ 82 #define CCD_L_SHIFT 2 83 #define CCD_L_MASK 0x0000000c /* [3:2] */ 84 #define CCD_E_SHIFT 4 85 #define CCD_8K_E_MASK 0x000007f0 /* [10:4] */ 86 #define CCD_16K_E_MASK 0x00000ff0 /* [11:4] */ 87 #define CCD_8K_W_SHIFT 11 88 #define CCD_8K_W_MASK 0x00001800 /* [12:11] */ 89 #define CCD_16K_W_SHIFT 12 90 #define CCD_16K_W_MASK 0x00003000 /* [13:12] */ 91 /* Data specification */ 92 93 /* 94 * Configuration 95 */ 96 #define SH3_CACHE_LINESZ 16 97 #define SH3_CACHE_NORMAL_WAY 4 98 #define SH3_CACHE_RAMMODE_WAY 2 99 100 #define SH3_CACHE_8K_ENTRY 128 101 #define SH3_CACHE_8K_WAY_NORMAL 4 102 #define SH3_CACHE_8K_WAY_RAMMODE 2 103 104 #define SH3_CACHE_16K_ENTRY 256 105 #define SH3_CACHE_16K_WAY 4 106 107 /* 108 * cache flush macro for locore level code. 109 */ 110 #define SH3_CACHE_8K_FLUSH(maxway) \ 111 do { \ 112 uint32_t __e, __w, __wa, __a; \ 113 \ 114 for (__w = 0; __w < maxway; __w++) { \ 115 __wa = SH3_CCA | __w << CCA_8K_WAY_SHIFT; \ 116 for (__e = 0; __e < CCA_8K_ENTRY; __e++) { \ 117 __a = __wa |(__e << CCA_ENTRY_SHIFT); \ 118 (*(volatile uint32_t *)__a) &= \ 119 ~(CCA_U | CCA_V); \ 120 } \ 121 } \ 122 } while (/*CONSTCOND*/0) 123 124 #define SH3_CACHE_16K_FLUSH() \ 125 do { \ 126 uint32_t __e, __w, __wa, __a; \ 127 \ 128 for (__w = 0; __w < SH3_CACHE_16K_WAY; __w++) { \ 129 __wa = SH3_CCA | __w << CCA_16K_WAY_SHIFT; \ 130 for (__e = 0; __e < CCA_16K_ENTRY; __e++) { \ 131 __a = __wa |(__e << CCA_ENTRY_SHIFT); \ 132 (*(volatile uint32_t *)__a) &= \ 133 ~(CCA_U | CCA_V); \ 134 } \ 135 } \ 136 } while (/*CONSTCOND*/0) 137 138 #define SH7708_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4) 139 #define SH7708_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2) 140 #define SH7708S_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4) 141 #define SH7708S_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2) 142 #define SH7708R_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4) 143 #define SH7708R_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2) 144 #define SH7709_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4) 145 #define SH7709_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2) 146 #define SH7709A_CACHE_FLUSH() SH3_CACHE_16K_FLUSH() 147 148 #ifndef _LOCORE 149 extern void sh3_cache_config(void); 150 #endif 151 #endif /* _KERNEL */ 152 #endif /* !_SH_CACHE_SH3_H_ */ 153