1 //***************************************************************************** 2 // 3 // Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 4 // 5 // 6 // Redistribution and use in source and binary forms, with or without 7 // modification, are permitted provided that the following conditions 8 // are met: 9 // 10 // Redistributions of source code must retain the above copyright 11 // notice, this list of conditions and the following disclaimer. 12 // 13 // Redistributions in binary form must reproduce the above copyright 14 // notice, this list of conditions and the following disclaimer in the 15 // documentation and/or other materials provided with the 16 // distribution. 17 // 18 // Neither the name of Texas Instruments Incorporated nor the names of 19 // its contributors may be used to endorse or promote products derived 20 // from this software without specific prior written permission. 21 // 22 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 26 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 28 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 // 34 //***************************************************************************** 35 36 #ifndef __HW_SHAMD5_H__ 37 #define __HW_SHAMD5_H__ 38 39 //***************************************************************************** 40 // 41 // The following are defines for the SHAMD5_P register offsets. 42 // 43 //***************************************************************************** 44 #define SHAMD5_O_ODIGEST_A 0x00000000 // WRITE: Outer Digest [127:96] for 45 // MD5 [159:128] for SHA-1 [255:224] 46 // for SHA-2 / HMAC Key [31:0] for 47 // HMAC key proc READ: Outer Digest 48 // [127:96] for MD5 [159:128] for 49 // SHA-1 [255:224] for SHA-2 50 #define SHAMD5_O_ODIGEST_B 0x00000004 // WRITE: Outer Digest [95:64] for 51 // MD5 [127:96] for SHA-1 [223:192] 52 // for SHA-2 / HMAC Key [63:32] for 53 // HMAC key proc READ: Outer Digest 54 // [95:64] for MD5 [127:96] for 55 // SHA-1 [223:192] for SHA-2 56 #define SHAMD5_O_ODIGEST_C 0x00000008 // WRITE: Outer Digest [63:32] for 57 // MD5 [95:64] for SHA-1 [191:160] 58 // for SHA-2 / HMAC Key [95:64] for 59 // HMAC key proc READ: Outer Digest 60 // [63:32] for MD5 [95:64] for SHA-1 61 // [191:160] for SHA-2 62 #define SHAMD5_O_ODIGEST_D 0x0000000C // WRITE: Outer Digest [31:0] for 63 // MD5 [63:31] for SHA-1 [159:128] 64 // for SHA-2 / HMAC Key [127:96] for 65 // HMAC key proc READ: Outer Digest 66 // [31:0] for MD5 [63:32] for SHA-1 67 // [159:128] for SHA-2 68 #define SHAMD5_O_ODIGEST_E 0x00000010 // WRITE: Outer Digest [31:0] for 69 // SHA-1 [127:96] for SHA-2 / HMAC 70 // Key [159:128] for HMAC key proc 71 // READ: Outer Digest [31:0] for 72 // SHA-1 [127:96] for SHA-2 73 #define SHAMD5_O_ODIGEST_F 0x00000014 // WRITE: Outer Digest [95:64] for 74 // SHA-2 / HMAC Key [191:160] for 75 // HMAC key proc READ: Outer Digest 76 // [95:64] for SHA-2 77 #define SHAMD5_O_ODIGEST_G 0x00000018 // WRITE: Outer Digest [63:32] for 78 // SHA-2 / HMAC Key [223:192] for 79 // HMAC key proc READ: Outer Digest 80 // [63:32] for SHA-2 81 #define SHAMD5_O_ODIGEST_H 0x0000001C // WRITE: Outer Digest [31:0] for 82 // SHA-2 / HMAC Key [255:224] for 83 // HMAC key proc READ: Outer Digest 84 // [31:0] for SHA-2 85 #define SHAMD5_O_IDIGEST_A 0x00000020 // WRITE: Inner / Initial Digest 86 // [127:96] for MD5 [159:128] for 87 // SHA-1 [255:224] for SHA-2 / HMAC 88 // Key [287:256] for HMAC key proc 89 // READ: Intermediate / Inner Digest 90 // [127:96] for MD5 [159:128] for 91 // SHA-1 [255:224] for SHA-2 / 92 // Result Digest/MAC [127:96] for 93 // MD5 [159:128] for SHA-1 [223:192] 94 // for SHA-2 224 [255:224] for SHA-2 95 // 256 96 #define SHAMD5_O_IDIGEST_B 0x00000024 // WRITE: Inner / Initial Digest 97 // [95:64] for MD5 [127:96] for 98 // SHA-1 [223:192] for SHA-2 / HMAC 99 // Key [319:288] for HMAC key proc 100 // READ: Intermediate / Inner Digest 101 // [95:64] for MD5 [127:96] for 102 // SHA-1 [223:192] for SHA-2 / 103 // Result Digest/MAC [95:64] for MD5 104 // [127:96] for SHA-1 [191:160] for 105 // SHA-2 224 [223:192] for SHA-2 256 106 #define SHAMD5_O_IDIGEST_C 0x00000028 // WRITE: Inner / Initial Digest 107 // [63:32] for MD5 [95:64] for SHA-1 108 // [191:160] for SHA- 2 / HMAC Key 109 // [351:320] for HMAC key proc READ: 110 // Intermediate / Inner Digest 111 // [63:32] for MD5 [95:64] for SHA-1 112 // [191:160] for SHA-2 / Result 113 // Digest/MAC [63:32] for MD5 114 // [95:64] for SHA-1 [159:128] for 115 // SHA-2 224 [191:160] for SHA-2 256 116 #define SHAMD5_O_IDIGEST_D 0x0000002C // WRITE: Inner / Initial Digest 117 // [31:0] for MD5 [63:32] for SHA-1 118 // [159:128] for SHA-2 / HMAC Key 119 // [383:352] for HMAC key proc READ: 120 // Intermediate / Inner Digest 121 // [31:0] for MD5 [63:32] for SHA-1 122 // [159:128] for SHA-2 / Result 123 // Digest/MAC [31:0] for MD5 [63:32] 124 // for SHA-1 [127:96] for SHA-2 224 125 // [159:128] for SHA-2 256 126 #define SHAMD5_O_IDIGEST_E 0x00000030 // WRITE: Inner / Initial Digest 127 // [31:0] for SHA-1 [127:96] for 128 // SHA-2 / HMAC Key [415:384] for 129 // HMAC key proc READ: Intermediate 130 // / Inner Digest [31:0] for SHA-1 131 // [127:96] for SHA-2 / Result 132 // Digest/MAC [31:0] for SHA-1 133 // [95:64] for SHA-2 224 [127:96] 134 // for SHA-2 256 135 #define SHAMD5_O_IDIGEST_F 0x00000034 // WRITE: Inner / Initial Digest 136 // [95:64] for SHA-2 / HMAC Key 137 // [447:416] for HMAC key proc READ: 138 // Intermediate / Inner Digest 139 // [95:64] for SHA-2 / Result 140 // Digest/MAC [63:32] for SHA-2 224 141 // [95:64] for SHA-2 256 142 #define SHAMD5_O_IDIGEST_G 0x00000038 // WRITE: Inner / Initial Digest 143 // [63:32] for SHA-2 / HMAC Key 144 // [479:448] for HMAC key proc READ: 145 // Intermediate / Inner Digest 146 // [63:32] for SHA-2 / Result 147 // Digest/MAC [31:0] for SHA-2 224 148 // [63:32] for SHA-2 256 149 #define SHAMD5_O_IDIGEST_H 0x0000003C // WRITE: Inner / Initial Digest 150 // [31:0] for SHA-2 / HMAC Key 151 // [511:480] for HMAC key proc READ: 152 // Intermediate / Inner Digest 153 // [31:0] for SHA-2 / Result 154 // Digest/MAC [31:0] for SHA-2 256 155 #define SHAMD5_O_DIGEST_COUNT 0x00000040 // WRITE: Initial Digest Count 156 // ([31:6] only [5:0] assumed 0) 157 // READ: Result / IntermediateDigest 158 // Count The initial digest byte 159 // count for hash/HMAC continue 160 // operations (HMAC Key Processing = 161 // 0 and Use Algorithm Constants = 162 // 0) on the Secure World must be 163 // written to this register prior to 164 // starting the operation by writing 165 // to S_HASH_MODE. When either HMAC 166 // Key Processing is 1 or Use 167 // Algorithm Constants is 1 this 168 // register does not need to be 169 // written it will be overwritten 170 // with 64 (1 hash block of key XOR 171 // ipad) or 0 respectively 172 // automatically. When starting a 173 // HMAC operation from pre-computes 174 // (HMAC Key Processing is 0) then 175 // the value 64 must be written here 176 // to compensate for the appended 177 // key XOR ipad block. Note that the 178 // value written should always be a 179 // 64 byte multiple the lower 6 bits 180 // written are ignored. The updated 181 // digest byte count (initial digest 182 // byte count + bytes processed) can 183 // be read from this register when 184 // the status register indicates 185 // that the operation is done or 186 // suspended due to a context switch 187 // request or when a Secure World 188 // context out DMA is requested. In 189 // Advanced DMA mode when not 190 // suspended with a partial result 191 // reading the SHAMD5_DIGEST_COUNT 192 // register triggers the Hash/HMAC 193 // Engine to start the next context 194 // input DMA. Therefore reading the 195 // SHAMD5_DIGEST_COUNT register 196 // should always be the last 197 // context-read action if not 198 // suspended with a partial result 199 // (i.e. PartHashReady interrupt not 200 // pending). 201 #define SHAMD5_O_MODE 0x00000044 // Register SHAMD5_MODE 202 #define SHAMD5_O_LENGTH 0x00000048 // WRITE: Block Length / Remaining 203 // Byte Count (bytes) READ: 204 // Remaining Byte Count. The value 205 // programmed MUST be a 64-byte 206 // multiple if Close Hash is set to 207 // 0. This register is also the 208 // trigger to start processing: once 209 // this register is written the core 210 // will commence requesting input 211 // data via DMA or IRQ (if 212 // programmed length > 0) and start 213 // processing. The remaining byte 214 // count for the active operation 215 // can be read from this register 216 // when the interrupt status 217 // register indicates that the 218 // operation is suspended due to a 219 // context switch request. 220 #define SHAMD5_O_DATA0_IN 0x00000080 // Data input message 0 221 #define SHAMD5_O_DATA1_IN 0x00000084 // Data input message 1 222 #define SHAMD5_O_DATA2_IN 0x00000088 // Data input message 2 223 #define SHAMD5_O_DATA3_IN 0x0000008C // Data input message 3 224 #define SHAMD5_O_DATA4_IN 0x00000090 // Data input message 4 225 #define SHAMD5_O_DATA5_IN 0x00000094 // Data input message 5 226 #define SHAMD5_O_DATA6_IN 0x00000098 // Data input message 6 227 #define SHAMD5_O_DATA7_IN 0x0000009C // Data input message 7 228 #define SHAMD5_O_DATA8_IN 0x000000A0 // Data input message 8 229 #define SHAMD5_O_DATA9_IN 0x000000A4 // Data input message 9 230 #define SHAMD5_O_DATA10_IN 0x000000A8 // Data input message 10 231 #define SHAMD5_O_DATA11_IN 0x000000AC // Data input message 11 232 #define SHAMD5_O_DATA12_IN 0x000000B0 // Data input message 12 233 #define SHAMD5_O_DATA13_IN 0x000000B4 // Data input message 13 234 #define SHAMD5_O_DATA14_IN 0x000000B8 // Data input message 14 235 #define SHAMD5_O_DATA15_IN 0x000000BC // Data input message 15 236 #define SHAMD5_O_REVISION 0x00000100 // Register SHAMD5_REV 237 #define SHAMD5_O_SYSCONFIG 0x00000110 // Register SHAMD5_SYSCONFIG 238 #define SHAMD5_O_SYSSTATUS 0x00000114 // Register SHAMD5_SYSSTATUS 239 #define SHAMD5_O_IRQSTATUS 0x00000118 // Register SHAMD5_IRQSTATUS 240 #define SHAMD5_O_IRQENABLE 0x0000011C // Register SHAMD5_IRQENABLE. The 241 // SHAMD5_IRQENABLE register contains 242 // an enable bit for each unique 243 // interrupt for the public side. An 244 // interrupt is enabled when both 245 // the global enable in 246 // SHAMD5_SYSCONFIG (PIT_en) and the 247 // bit in this register are both set 248 // to 1. An interrupt that is 249 // enabled is propagated to the 250 // SINTREQUEST_P output. Please note 251 // that the dedicated partial hash 252 // output (SINTREQUEST_PART_P) is 253 // not affected by this register it 254 // is only affected by the global 255 // enable SHAMD5_SYSCONFIG (PIT_en). 256 #define SHAMD5_O_HASH512_ODIGEST_A \ 257 0x00000200 258 259 #define SHAMD5_O_HASH512_ODIGEST_B \ 260 0x00000204 261 262 #define SHAMD5_O_HASH512_ODIGEST_C \ 263 0x00000208 264 265 #define SHAMD5_O_HASH512_ODIGEST_D \ 266 0x0000020C 267 268 #define SHAMD5_O_HASH512_ODIGEST_E \ 269 0x00000210 270 271 #define SHAMD5_O_HASH512_ODIGEST_F \ 272 0x00000214 273 274 #define SHAMD5_O_HASH512_ODIGEST_G \ 275 0x00000218 276 277 #define SHAMD5_O_HASH512_ODIGEST_H \ 278 0x0000021C 279 280 #define SHAMD5_O_HASH512_ODIGEST_I \ 281 0x00000220 282 283 #define SHAMD5_O_HASH512_ODIGEST_J \ 284 0x00000224 285 286 #define SHAMD5_O_HASH512_ODIGEST_K \ 287 0x00000228 288 289 #define SHAMD5_O_HASH512_ODIGEST_L \ 290 0x0000022C 291 292 #define SHAMD5_O_HASH512_ODIGEST_M \ 293 0x00000230 294 295 #define SHAMD5_O_HASH512_ODIGEST_N \ 296 0x00000234 297 298 #define SHAMD5_O_HASH512_ODIGEST_O \ 299 0x00000238 300 301 #define SHAMD5_O_HASH512_ODIGEST_P \ 302 0x0000023C 303 304 #define SHAMD5_O_HASH512_IDIGEST_A \ 305 0x00000240 306 307 #define SHAMD5_O_HASH512_IDIGEST_B \ 308 0x00000244 309 310 #define SHAMD5_O_HASH512_IDIGEST_C \ 311 0x00000248 312 313 #define SHAMD5_O_HASH512_IDIGEST_D \ 314 0x0000024C 315 316 #define SHAMD5_O_HASH512_IDIGEST_E \ 317 0x00000250 318 319 #define SHAMD5_O_HASH512_IDIGEST_F \ 320 0x00000254 321 322 #define SHAMD5_O_HASH512_IDIGEST_G \ 323 0x00000258 324 325 #define SHAMD5_O_HASH512_IDIGEST_H \ 326 0x0000025C 327 328 #define SHAMD5_O_HASH512_IDIGEST_I \ 329 0x00000260 330 331 #define SHAMD5_O_HASH512_IDIGEST_J \ 332 0x00000264 333 334 #define SHAMD5_O_HASH512_IDIGEST_K \ 335 0x00000268 336 337 #define SHAMD5_O_HASH512_IDIGEST_L \ 338 0x0000026C 339 340 #define SHAMD5_O_HASH512_IDIGEST_M \ 341 0x00000270 342 343 #define SHAMD5_O_HASH512_IDIGEST_N \ 344 0x00000274 345 346 #define SHAMD5_O_HASH512_IDIGEST_O \ 347 0x00000278 348 349 #define SHAMD5_O_HASH512_IDIGEST_P \ 350 0x0000027C 351 352 #define SHAMD5_O_HASH512_DIGEST_COUNT \ 353 0x00000280 354 355 #define SHAMD5_O_HASH512_MODE 0x00000284 356 #define SHAMD5_O_HASH512_LENGTH 0x00000288 357 358 359 360 //****************************************************************************** 361 // 362 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A register. 363 // 364 //****************************************************************************** 365 #define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // data 366 #define SHAMD5_ODIGEST_A_DATA_S 0 367 //****************************************************************************** 368 // 369 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B register. 370 // 371 //****************************************************************************** 372 #define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // data 373 #define SHAMD5_ODIGEST_B_DATA_S 0 374 //****************************************************************************** 375 // 376 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C register. 377 // 378 //****************************************************************************** 379 #define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // data 380 #define SHAMD5_ODIGEST_C_DATA_S 0 381 //****************************************************************************** 382 // 383 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D register. 384 // 385 //****************************************************************************** 386 #define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // data 387 #define SHAMD5_ODIGEST_D_DATA_S 0 388 //****************************************************************************** 389 // 390 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E register. 391 // 392 //****************************************************************************** 393 #define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // data 394 #define SHAMD5_ODIGEST_E_DATA_S 0 395 //****************************************************************************** 396 // 397 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F register. 398 // 399 //****************************************************************************** 400 #define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // data 401 #define SHAMD5_ODIGEST_F_DATA_S 0 402 //****************************************************************************** 403 // 404 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G register. 405 // 406 //****************************************************************************** 407 #define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // data 408 #define SHAMD5_ODIGEST_G_DATA_S 0 409 //****************************************************************************** 410 // 411 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H register. 412 // 413 //****************************************************************************** 414 #define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // data 415 #define SHAMD5_ODIGEST_H_DATA_S 0 416 //****************************************************************************** 417 // 418 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A register. 419 // 420 //****************************************************************************** 421 #define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // data 422 #define SHAMD5_IDIGEST_A_DATA_S 0 423 //****************************************************************************** 424 // 425 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B register. 426 // 427 //****************************************************************************** 428 #define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // data 429 #define SHAMD5_IDIGEST_B_DATA_S 0 430 //****************************************************************************** 431 // 432 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C register. 433 // 434 //****************************************************************************** 435 #define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // data 436 #define SHAMD5_IDIGEST_C_DATA_S 0 437 //****************************************************************************** 438 // 439 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D register. 440 // 441 //****************************************************************************** 442 #define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // data 443 #define SHAMD5_IDIGEST_D_DATA_S 0 444 //****************************************************************************** 445 // 446 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E register. 447 // 448 //****************************************************************************** 449 #define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // data 450 #define SHAMD5_IDIGEST_E_DATA_S 0 451 //****************************************************************************** 452 // 453 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F register. 454 // 455 //****************************************************************************** 456 #define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // data 457 #define SHAMD5_IDIGEST_F_DATA_S 0 458 //****************************************************************************** 459 // 460 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G register. 461 // 462 //****************************************************************************** 463 #define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // data 464 #define SHAMD5_IDIGEST_G_DATA_S 0 465 //****************************************************************************** 466 // 467 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H register. 468 // 469 //****************************************************************************** 470 #define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // data 471 #define SHAMD5_IDIGEST_H_DATA_S 0 472 //****************************************************************************** 473 // 474 // The following are defines for the bit fields in the 475 // SHAMD5_O_DIGEST_COUNT register. 476 // 477 //****************************************************************************** 478 #define SHAMD5_DIGEST_COUNT_DATA_M \ 479 0xFFFFFFFF // data 480 481 #define SHAMD5_DIGEST_COUNT_DATA_S 0 482 //****************************************************************************** 483 // 484 // The following are defines for the bit fields in the SHAMD5_O_MODE register. 485 // 486 //****************************************************************************** 487 #define SHAMD5_MODE_HMAC_OUTER_HASH \ 488 0x00000080 // The HMAC Outer Hash is performed 489 // on the hash digest when the inner 490 // hash hash finished (block length 491 // exhausted and final hash 492 // performed if close_hash is 1). 493 // This bit should normally be set 494 // together with close_hash to 495 // finish the inner hash first or 496 // Block Length should be zero (HMAC 497 // continue with the just outer hash 498 // to be done). Auto cleared 499 // internally when outer hash 500 // performed. 0 No operation 1 hmac 501 // processing 502 503 #define SHAMD5_MODE_HMAC_KEY_PROC \ 504 0x00000020 // Performs HMAC key processing on 505 // the 512 bit HMAC key loaded into 506 // the SHAMD5_IDIGEST_{A to H} and 507 // SHAMD5_ODIGEST_{A to H} register 508 // block. Once HMAC key processing 509 // is finished this bit is 510 // automatically cleared and the 511 // resulting Inner and Outer digest 512 // is available from 513 // SHAMD5_IDIGEST_{A to H} and 514 // SHAMD5_ODIGEST_{A to H} 515 // respectively after which regular 516 // hash processing (using 517 // SHAMD5_IDIGEST_{A to H} as initial 518 // digest) will commence until the 519 // Block Length is exhausted. 0 No 520 // operation. 1 Hmac processing. 521 522 #define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding the 523 // hash/HMAC will be 'closed' at the 524 // end of the block as per 525 // MD5/SHA-1/SHA-2 specification 526 // (i.e. appropriate padding is 527 // added) or no padding is done 528 // allowing the hash to be continued 529 // later. However if the hash/HMAC 530 // is not closed then the Block 531 // Length MUST be a multiple of 64 532 // bytes to ensure correct 533 // operation. Auto cleared 534 // internally when hash closed. 0 No 535 // padding hash computation can be 536 // contimued. 1 Last packet will be 537 // padded. 538 #define SHAMD5_MODE_ALGO_CONSTANT \ 539 0x00000008 // The initial digest register will 540 // be overwritten with the algorithm 541 // constants for the selected 542 // algorithm when hashing and the 543 // initial digest count register 544 // will be reset to 0. This will 545 // start a normal hash operation. 546 // When continuing an existing hash 547 // or when performing an HMAC 548 // operation this register must be 549 // set to 0 and the 550 // intermediate/inner digest or HMAC 551 // key and digest count need to be 552 // written to the context input 553 // registers prior to writing 554 // SHAMD5_MODE. Auto cleared 555 // internally after first block 556 // processed. 0 Use pre-calculated 557 // digest (from an other operation) 558 // 1 Use constants of the selected 559 // algo. 560 561 #define SHAMD5_MODE_ALGO_M 0x00000006 // These bits select the hash 562 // algorithm to be used for 563 // processing: 0x0 md5_128 algorithm 564 // 0x1 sha1_160 algorithm 0x2 565 // sha2_224 algorithm 0x3 sha2_256 566 // algorithm 567 #define SHAMD5_MODE_ALGO_S 1 568 //****************************************************************************** 569 // 570 // The following are defines for the bit fields in the SHAMD5_O_LENGTH register. 571 // 572 //****************************************************************************** 573 #define SHAMD5_LENGTH_DATA_M 0xFFFFFFFF // data 574 #define SHAMD5_LENGTH_DATA_S 0 575 //****************************************************************************** 576 // 577 // The following are defines for the bit fields in the SHAMD5_O_DATA0_IN register. 578 // 579 //****************************************************************************** 580 #define SHAMD5_DATA0_IN_DATA0_IN_M \ 581 0xFFFFFFFF // data 582 583 #define SHAMD5_DATA0_IN_DATA0_IN_S 0 584 //****************************************************************************** 585 // 586 // The following are defines for the bit fields in the SHAMD5_O_DATA1_IN register. 587 // 588 //****************************************************************************** 589 #define SHAMD5_DATA1_IN_DATA1_IN_M \ 590 0xFFFFFFFF // data 591 592 #define SHAMD5_DATA1_IN_DATA1_IN_S 0 593 //****************************************************************************** 594 // 595 // The following are defines for the bit fields in the SHAMD5_O_DATA2_IN register. 596 // 597 //****************************************************************************** 598 #define SHAMD5_DATA2_IN_DATA2_IN_M \ 599 0xFFFFFFFF // data 600 601 #define SHAMD5_DATA2_IN_DATA2_IN_S 0 602 //****************************************************************************** 603 // 604 // The following are defines for the bit fields in the SHAMD5_O_DATA3_IN register. 605 // 606 //****************************************************************************** 607 #define SHAMD5_DATA3_IN_DATA3_IN_M \ 608 0xFFFFFFFF // data 609 610 #define SHAMD5_DATA3_IN_DATA3_IN_S 0 611 //****************************************************************************** 612 // 613 // The following are defines for the bit fields in the SHAMD5_O_DATA4_IN register. 614 // 615 //****************************************************************************** 616 #define SHAMD5_DATA4_IN_DATA4_IN_M \ 617 0xFFFFFFFF // data 618 619 #define SHAMD5_DATA4_IN_DATA4_IN_S 0 620 //****************************************************************************** 621 // 622 // The following are defines for the bit fields in the SHAMD5_O_DATA5_IN register. 623 // 624 //****************************************************************************** 625 #define SHAMD5_DATA5_IN_DATA5_IN_M \ 626 0xFFFFFFFF // data 627 628 #define SHAMD5_DATA5_IN_DATA5_IN_S 0 629 //****************************************************************************** 630 // 631 // The following are defines for the bit fields in the SHAMD5_O_DATA6_IN register. 632 // 633 //****************************************************************************** 634 #define SHAMD5_DATA6_IN_DATA6_IN_M \ 635 0xFFFFFFFF // data 636 637 #define SHAMD5_DATA6_IN_DATA6_IN_S 0 638 //****************************************************************************** 639 // 640 // The following are defines for the bit fields in the SHAMD5_O_DATA7_IN register. 641 // 642 //****************************************************************************** 643 #define SHAMD5_DATA7_IN_DATA7_IN_M \ 644 0xFFFFFFFF // data 645 646 #define SHAMD5_DATA7_IN_DATA7_IN_S 0 647 //****************************************************************************** 648 // 649 // The following are defines for the bit fields in the SHAMD5_O_DATA8_IN register. 650 // 651 //****************************************************************************** 652 #define SHAMD5_DATA8_IN_DATA8_IN_M \ 653 0xFFFFFFFF // data 654 655 #define SHAMD5_DATA8_IN_DATA8_IN_S 0 656 //****************************************************************************** 657 // 658 // The following are defines for the bit fields in the SHAMD5_O_DATA9_IN register. 659 // 660 //****************************************************************************** 661 #define SHAMD5_DATA9_IN_DATA9_IN_M \ 662 0xFFFFFFFF // data 663 664 #define SHAMD5_DATA9_IN_DATA9_IN_S 0 665 //****************************************************************************** 666 // 667 // The following are defines for the bit fields in the SHAMD5_O_DATA10_IN register. 668 // 669 //****************************************************************************** 670 #define SHAMD5_DATA10_IN_DATA10_IN_M \ 671 0xFFFFFFFF // data 672 673 #define SHAMD5_DATA10_IN_DATA10_IN_S 0 674 //****************************************************************************** 675 // 676 // The following are defines for the bit fields in the SHAMD5_O_DATA11_IN register. 677 // 678 //****************************************************************************** 679 #define SHAMD5_DATA11_IN_DATA11_IN_M \ 680 0xFFFFFFFF // data 681 682 #define SHAMD5_DATA11_IN_DATA11_IN_S 0 683 //****************************************************************************** 684 // 685 // The following are defines for the bit fields in the SHAMD5_O_DATA12_IN register. 686 // 687 //****************************************************************************** 688 #define SHAMD5_DATA12_IN_DATA12_IN_M \ 689 0xFFFFFFFF // data 690 691 #define SHAMD5_DATA12_IN_DATA12_IN_S 0 692 //****************************************************************************** 693 // 694 // The following are defines for the bit fields in the SHAMD5_O_DATA13_IN register. 695 // 696 //****************************************************************************** 697 #define SHAMD5_DATA13_IN_DATA13_IN_M \ 698 0xFFFFFFFF // data 699 700 #define SHAMD5_DATA13_IN_DATA13_IN_S 0 701 //****************************************************************************** 702 // 703 // The following are defines for the bit fields in the SHAMD5_O_DATA14_IN register. 704 // 705 //****************************************************************************** 706 #define SHAMD5_DATA14_IN_DATA14_IN_M \ 707 0xFFFFFFFF // data 708 709 #define SHAMD5_DATA14_IN_DATA14_IN_S 0 710 //****************************************************************************** 711 // 712 // The following are defines for the bit fields in the SHAMD5_O_DATA15_IN register. 713 // 714 //****************************************************************************** 715 #define SHAMD5_DATA15_IN_DATA15_IN_M \ 716 0xFFFFFFFF // data 717 718 #define SHAMD5_DATA15_IN_DATA15_IN_S 0 719 //****************************************************************************** 720 // 721 // The following are defines for the bit fields in the SHAMD5_O_REVISION register. 722 // 723 //****************************************************************************** 724 #define SHAMD5_REVISION_SCHEME_M 0xC0000000 725 #define SHAMD5_REVISION_SCHEME_S 30 726 #define SHAMD5_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software 727 // compatible module family. If 728 // there is no level of software 729 // compatibility a new Func number 730 // (and hence REVISION) should be 731 // assigned. 732 #define SHAMD5_REVISION_FUNC_S 16 733 #define SHAMD5_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP 734 // design owner. RTL follows a 735 // numbering such as X.Y.R.Z which 736 // are explained in this table. R 737 // changes ONLY when: (1) PDS 738 // uploads occur which may have been 739 // due to spec changes (2) Bug fixes 740 // occur (3) Resets to '0' when X or 741 // Y changes. Design team has an 742 // internal 'Z' (customer invisible) 743 // number which increments on every 744 // drop that happens due to DV and 745 // RTL updates. Z resets to 0 when R 746 // increments. 747 #define SHAMD5_REVISION_R_RTL_S 11 748 #define SHAMD5_REVISION_X_MAJOR_M \ 749 0x00000700 // Major Revision (X) maintained by 750 // IP specification owner. X changes 751 // ONLY when: (1) There is a major 752 // feature addition. An example 753 // would be adding Master Mode to 754 // Utopia Level2. The Func field (or 755 // Class/Type in old PID format) 756 // will remain the same. X does NOT 757 // change due to: (1) Bug fixes (2) 758 // Change in feature parameters. 759 760 #define SHAMD5_REVISION_X_MAJOR_S 8 761 #define SHAMD5_REVISION_CUSTOM_M 0x000000C0 762 #define SHAMD5_REVISION_CUSTOM_S 6 763 #define SHAMD5_REVISION_Y_MINOR_M \ 764 0x0000003F // Minor Revision (Y) maintained by 765 // IP specification owner. Y changes 766 // ONLY when: (1) Features are 767 // scaled (up or down). Flexibility 768 // exists in that this feature 769 // scalability may either be 770 // represented in the Y change or a 771 // specific register in the IP that 772 // indicates which features are 773 // exactly available. (2) When 774 // feature creeps from Is-Not list 775 // to Is list. But this may not be 776 // the case once it sees silicon; in 777 // which case X will change. Y does 778 // NOT change due to: (1) Bug fixes 779 // (2) Typos or clarifications (3) 780 // major functional/feature 781 // change/addition/deletion. Instead 782 // these changes may be reflected 783 // via R S X as applicable. Spec 784 // owner maintains a 785 // customer-invisible number 'S' 786 // which changes due to: (1) 787 // Typos/clarifications (2) Bug 788 // documentation. Note that this bug 789 // is not due to a spec change but 790 // due to implementation. 791 // Nevertheless the spec tracks the 792 // IP bugs. An RTL release (say for 793 // silicon PG1.1) that occurs due to 794 // bug fix should document the 795 // corresponding spec number (X.Y.S) 796 // in its release notes. 797 798 #define SHAMD5_REVISION_Y_MINOR_S 0 799 //****************************************************************************** 800 // 801 // The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG register. 802 // 803 //****************************************************************************** 804 #define SHAMD5_SYSCONFIG_PADVANCED \ 805 0x00000080 // If set to 1 Advanced mode is 806 // enabled for the Secure World. If 807 // set to 0 Legacy mode is enabled 808 // for the Secure World. 809 810 #define SHAMD5_SYSCONFIG_PCONT_SWT \ 811 0x00000040 // Finish all pending data and 812 // context DMA input requests (but 813 // will not assert any new requests) 814 // finish processing all data in the 815 // module and provide a saved 816 // context (partial hash result 817 // updated digest count remaining 818 // length updated mode information 819 // where applicable) for the last 820 // operation that was interrupted so 821 // that it can be resumed later. 822 823 #define SHAMD5_SYSCONFIG_PDMA_EN 0x00000008 824 #define SHAMD5_SYSCONFIG_PIT_EN 0x00000004 825 //****************************************************************************** 826 // 827 // The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS register. 828 // 829 //****************************************************************************** 830 #define SHAMD5_SYSSTATUS_RESETDONE \ 831 0x00000001 // data 832 833 //****************************************************************************** 834 // 835 // The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS register. 836 // 837 //****************************************************************************** 838 #define SHAMD5_IRQSTATUS_CONTEXT_READY \ 839 0x00000008 // indicates that the secure side 840 // context input registers are 841 // available for a new context for 842 // the next packet to be processed. 843 844 #define SHAMD5_IRQSTATUS_PARTHASH_READY \ 845 0x00000004 // After a secure side context 846 // switch request this bit will read 847 // as 1 indicating that the saved 848 // context is available from the 849 // secure side context output 850 // registers. Note that if the 851 // context switch request coincides 852 // with a final hash (when hashing) 853 // or an outer hash (when doing 854 // HMAC) that PartHashReady will not 855 // become active but a regular 856 // Output Ready will occur instead 857 // (indicating that the result is 858 // final and therefore no 859 // continuation is required). 860 861 #define SHAMD5_IRQSTATUS_INPUT_READY \ 862 0x00000002 // indicates that the secure side 863 // data FIFO is ready to receive the 864 // next 64 byte data block. 865 866 #define SHAMD5_IRQSTATUS_OUTPUT_READY \ 867 0x00000001 // Indicates that a (partial) 868 // result or saved context is 869 // available from the secure side 870 // context output registers. 871 872 //****************************************************************************** 873 // 874 // The following are defines for the bit fields in the SHAMD5_O_IRQENABLE register. 875 // 876 //****************************************************************************** 877 #define SHAMD5_IRQENABLE_M_CONTEXT_READY \ 878 0x00000008 // mask for context ready 879 880 #define SHAMD5_IRQENABLE_M_PARTHASH_READY \ 881 0x00000004 // mask for partial hash 882 883 #define SHAMD5_IRQENABLE_M_INPUT_READY \ 884 0x00000002 // mask for input_ready 885 886 #define SHAMD5_IRQENABLE_M_OUTPUT_READY \ 887 0x00000001 // mask for output_ready 888 889 //****************************************************************************** 890 // 891 // The following are defines for the bit fields in the 892 // SHAMD5_O_HASH512_ODIGEST_A register. 893 // 894 //****************************************************************************** 895 #define SHAMD5_HASH512_ODIGEST_A_DATA_M \ 896 0xFFFFFFFF 897 898 #define SHAMD5_HASH512_ODIGEST_A_DATA_S 0 899 //****************************************************************************** 900 // 901 // The following are defines for the bit fields in the 902 // SHAMD5_O_HASH512_ODIGEST_B register. 903 // 904 //****************************************************************************** 905 #define SHAMD5_HASH512_ODIGEST_B_DATA_M \ 906 0xFFFFFFFF 907 908 #define SHAMD5_HASH512_ODIGEST_B_DATA_S 0 909 //****************************************************************************** 910 // 911 // The following are defines for the bit fields in the 912 // SHAMD5_O_HASH512_ODIGEST_C register. 913 // 914 //****************************************************************************** 915 #define SHAMD5_HASH512_ODIGEST_C_DATA_M \ 916 0xFFFFFFFF 917 918 #define SHAMD5_HASH512_ODIGEST_C_DATA_S 0 919 //****************************************************************************** 920 // 921 // The following are defines for the bit fields in the 922 // SHAMD5_O_HASH512_ODIGEST_D register. 923 // 924 //****************************************************************************** 925 #define SHAMD5_HASH512_ODIGEST_D_DATA_M \ 926 0xFFFFFFFF 927 928 #define SHAMD5_HASH512_ODIGEST_D_DATA_S 0 929 //****************************************************************************** 930 // 931 // The following are defines for the bit fields in the 932 // SHAMD5_O_HASH512_ODIGEST_E register. 933 // 934 //****************************************************************************** 935 #define SHAMD5_HASH512_ODIGEST_E_DATA_M \ 936 0xFFFFFFFF 937 938 #define SHAMD5_HASH512_ODIGEST_E_DATA_S 0 939 //****************************************************************************** 940 // 941 // The following are defines for the bit fields in the 942 // SHAMD5_O_HASH512_ODIGEST_F register. 943 // 944 //****************************************************************************** 945 #define SHAMD5_HASH512_ODIGEST_F_DATA_M \ 946 0xFFFFFFFF 947 948 #define SHAMD5_HASH512_ODIGEST_F_DATA_S 0 949 //****************************************************************************** 950 // 951 // The following are defines for the bit fields in the 952 // SHAMD5_O_HASH512_ODIGEST_G register. 953 // 954 //****************************************************************************** 955 #define SHAMD5_HASH512_ODIGEST_G_DATA_M \ 956 0xFFFFFFFF 957 958 #define SHAMD5_HASH512_ODIGEST_G_DATA_S 0 959 //****************************************************************************** 960 // 961 // The following are defines for the bit fields in the 962 // SHAMD5_O_HASH512_ODIGEST_H register. 963 // 964 //****************************************************************************** 965 #define SHAMD5_HASH512_ODIGEST_H_DATA_M \ 966 0xFFFFFFFF 967 968 #define SHAMD5_HASH512_ODIGEST_H_DATA_S 0 969 //****************************************************************************** 970 // 971 // The following are defines for the bit fields in the 972 // SHAMD5_O_HASH512_ODIGEST_I register. 973 // 974 //****************************************************************************** 975 #define SHAMD5_HASH512_ODIGEST_I_DATA_M \ 976 0xFFFFFFFF 977 978 #define SHAMD5_HASH512_ODIGEST_I_DATA_S 0 979 //****************************************************************************** 980 // 981 // The following are defines for the bit fields in the 982 // SHAMD5_O_HASH512_ODIGEST_J register. 983 // 984 //****************************************************************************** 985 #define SHAMD5_HASH512_ODIGEST_J_DATA_M \ 986 0xFFFFFFFF 987 988 #define SHAMD5_HASH512_ODIGEST_J_DATA_S 0 989 //****************************************************************************** 990 // 991 // The following are defines for the bit fields in the 992 // SHAMD5_O_HASH512_ODIGEST_K register. 993 // 994 //****************************************************************************** 995 #define SHAMD5_HASH512_ODIGEST_K_DATA_M \ 996 0xFFFFFFFF 997 998 #define SHAMD5_HASH512_ODIGEST_K_DATA_S 0 999 //****************************************************************************** 1000 // 1001 // The following are defines for the bit fields in the 1002 // SHAMD5_O_HASH512_ODIGEST_L register. 1003 // 1004 //****************************************************************************** 1005 #define SHAMD5_HASH512_ODIGEST_L_DATA_M \ 1006 0xFFFFFFFF 1007 1008 #define SHAMD5_HASH512_ODIGEST_L_DATA_S 0 1009 //****************************************************************************** 1010 // 1011 // The following are defines for the bit fields in the 1012 // SHAMD5_O_HASH512_ODIGEST_M register. 1013 // 1014 //****************************************************************************** 1015 #define SHAMD5_HASH512_ODIGEST_M_DATA_M \ 1016 0xFFFFFFFF 1017 1018 #define SHAMD5_HASH512_ODIGEST_M_DATA_S 0 1019 //****************************************************************************** 1020 // 1021 // The following are defines for the bit fields in the 1022 // SHAMD5_O_HASH512_ODIGEST_N register. 1023 // 1024 //****************************************************************************** 1025 #define SHAMD5_HASH512_ODIGEST_N_DATA_M \ 1026 0xFFFFFFFF 1027 1028 #define SHAMD5_HASH512_ODIGEST_N_DATA_S 0 1029 //****************************************************************************** 1030 // 1031 // The following are defines for the bit fields in the 1032 // SHAMD5_O_HASH512_ODIGEST_O register. 1033 // 1034 //****************************************************************************** 1035 #define SHAMD5_HASH512_ODIGEST_O_DATA_M \ 1036 0xFFFFFFFF 1037 1038 #define SHAMD5_HASH512_ODIGEST_O_DATA_S 0 1039 //****************************************************************************** 1040 // 1041 // The following are defines for the bit fields in the 1042 // SHAMD5_O_HASH512_ODIGEST_P register. 1043 // 1044 //****************************************************************************** 1045 #define SHAMD5_HASH512_ODIGEST_DATA_M \ 1046 0xFFFFFFFF 1047 1048 #define SHAMD5_HASH512_ODIGEST_DATA_S 0 1049 //****************************************************************************** 1050 // 1051 // The following are defines for the bit fields in the 1052 // SHAMD5_O_HASH512_IDIGEST_A register. 1053 // 1054 //****************************************************************************** 1055 #define SHAMD5_HASH512_IDIGEST_A_DATA_M \ 1056 0xFFFFFFFF 1057 1058 #define SHAMD5_HASH512_IDIGEST_A_DATA_S 0 1059 //****************************************************************************** 1060 // 1061 // The following are defines for the bit fields in the 1062 // SHAMD5_O_HASH512_IDIGEST_B register. 1063 // 1064 //****************************************************************************** 1065 #define SHAMD5_HASH512_IDIGEST_B_DATA_M \ 1066 0xFFFFFFFF 1067 1068 #define SHAMD5_HASH512_IDIGEST_B_DATA_S 0 1069 //****************************************************************************** 1070 // 1071 // The following are defines for the bit fields in the 1072 // SHAMD5_O_HASH512_IDIGEST_C register. 1073 // 1074 //****************************************************************************** 1075 #define SHAMD5_HASH512_IDIGEST_C_DATA_M \ 1076 0xFFFFFFFF 1077 1078 #define SHAMD5_HASH512_IDIGEST_C_DATA_S 0 1079 //****************************************************************************** 1080 // 1081 // The following are defines for the bit fields in the 1082 // SHAMD5_O_HASH512_IDIGEST_D register. 1083 // 1084 //****************************************************************************** 1085 #define SHAMD5_HASH512_IDIGEST_D_DATA_M \ 1086 0xFFFFFFFF 1087 1088 #define SHAMD5_HASH512_IDIGEST_D_DATA_S 0 1089 //****************************************************************************** 1090 // 1091 // The following are defines for the bit fields in the 1092 // SHAMD5_O_HASH512_IDIGEST_E register. 1093 // 1094 //****************************************************************************** 1095 #define SHAMD5_HASH512_IDIGEST_E_DATA_M \ 1096 0xFFFFFFFF 1097 1098 #define SHAMD5_HASH512_IDIGEST_E_DATA_S 0 1099 //****************************************************************************** 1100 // 1101 // The following are defines for the bit fields in the 1102 // SHAMD5_O_HASH512_IDIGEST_F register. 1103 // 1104 //****************************************************************************** 1105 #define SHAMD5_HASH512_IDIGEST_F_DATA_M \ 1106 0xFFFFFFFF 1107 1108 #define SHAMD5_HASH512_IDIGEST_F_DATA_S 0 1109 //****************************************************************************** 1110 // 1111 // The following are defines for the bit fields in the 1112 // SHAMD5_O_HASH512_IDIGEST_G register. 1113 // 1114 //****************************************************************************** 1115 #define SHAMD5_HASH512_IDIGEST_G_DATA_M \ 1116 0xFFFFFFFF 1117 1118 #define SHAMD5_HASH512_IDIGEST_G_DATA_S 0 1119 //****************************************************************************** 1120 // 1121 // The following are defines for the bit fields in the 1122 // SHAMD5_O_HASH512_IDIGEST_H register. 1123 // 1124 //****************************************************************************** 1125 #define SHAMD5_HASH512_IDIGEST_H_DATA_M \ 1126 0xFFFFFFFF 1127 1128 #define SHAMD5_HASH512_IDIGEST_H_DATA_S 0 1129 //****************************************************************************** 1130 // 1131 // The following are defines for the bit fields in the 1132 // SHAMD5_O_HASH512_IDIGEST_I register. 1133 // 1134 //****************************************************************************** 1135 #define SHAMD5_HASH512_IDIGEST_I_DATA_M \ 1136 0xFFFFFFFF 1137 1138 #define SHAMD5_HASH512_IDIGEST_I_DATA_S 0 1139 //****************************************************************************** 1140 // 1141 // The following are defines for the bit fields in the 1142 // SHAMD5_O_HASH512_IDIGEST_J register. 1143 // 1144 //****************************************************************************** 1145 #define SHAMD5_HASH512_IDIGEST_J_DATA_M \ 1146 0xFFFFFFFF 1147 1148 #define SHAMD5_HASH512_IDIGEST_J_DATA_S 0 1149 //****************************************************************************** 1150 // 1151 // The following are defines for the bit fields in the 1152 // SHAMD5_O_HASH512_IDIGEST_K register. 1153 // 1154 //****************************************************************************** 1155 #define SHAMD5_HASH512_IDIGEST_K_DATA_M \ 1156 0xFFFFFFFF 1157 1158 #define SHAMD5_HASH512_IDIGEST_K_DATA_S 0 1159 //****************************************************************************** 1160 // 1161 // The following are defines for the bit fields in the 1162 // SHAMD5_O_HASH512_IDIGEST_L register. 1163 // 1164 //****************************************************************************** 1165 #define SHAMD5_HASH512_IDIGEST_L_DATA_M \ 1166 0xFFFFFFFF 1167 1168 #define SHAMD5_HASH512_IDIGEST_L_DATA_S 0 1169 //****************************************************************************** 1170 // 1171 // The following are defines for the bit fields in the 1172 // SHAMD5_O_HASH512_IDIGEST_M register. 1173 // 1174 //****************************************************************************** 1175 #define SHAMD5_HASH512_IDIGEST_M_DATA_M \ 1176 0xFFFFFFFF 1177 1178 #define SHAMD5_HASH512_IDIGEST_M_DATA_S 0 1179 //****************************************************************************** 1180 // 1181 // The following are defines for the bit fields in the 1182 // SHAMD5_O_HASH512_IDIGEST_N register. 1183 // 1184 //****************************************************************************** 1185 #define SHAMD5_HASH512_IDIGEST_N_DATA_M \ 1186 0xFFFFFFFF 1187 1188 #define SHAMD5_HASH512_IDIGEST_N_DATA_S 0 1189 //****************************************************************************** 1190 // 1191 // The following are defines for the bit fields in the 1192 // SHAMD5_O_HASH512_IDIGEST_O register. 1193 // 1194 //****************************************************************************** 1195 #define SHAMD5_HASH512_IDIGEST_O_DATA_M \ 1196 0xFFFFFFFF 1197 1198 #define SHAMD5_HASH512_IDIGEST_O_DATA_S 0 1199 //****************************************************************************** 1200 // 1201 // The following are defines for the bit fields in the 1202 // SHAMD5_O_HASH512_IDIGEST_P register. 1203 // 1204 //****************************************************************************** 1205 #define SHAMD5_HASH512_IDIGEST_DATA_M \ 1206 0xFFFFFFFF 1207 1208 #define SHAMD5_HASH512_IDIGEST_DATA_S 0 1209 //****************************************************************************** 1210 // 1211 // The following are defines for the bit fields in the 1212 // SHAMD5_O_HASH512_DIGEST_COUNT register. 1213 // 1214 //****************************************************************************** 1215 #define SHAMD5_HASH512_DIGEST_COUNT_DATA_M \ 1216 0xFFFFFFFF 1217 1218 #define SHAMD5_HASH512_DIGEST_COUNT_DATA_S 0 1219 //****************************************************************************** 1220 // 1221 // The following are defines for the bit fields in the 1222 // SHAMD5_O_HASH512_MODE register. 1223 // 1224 //****************************************************************************** 1225 #define SHAMD5_HASH512_MODE_DATA_M \ 1226 0xFFFFFFFF 1227 1228 #define SHAMD5_HASH512_MODE_DATA_S 0 1229 //****************************************************************************** 1230 // 1231 // The following are defines for the bit fields in the 1232 // SHAMD5_O_HASH512_LENGTH register. 1233 // 1234 //****************************************************************************** 1235 #define SHAMD5_HASH512_LENGTH_DATA_M \ 1236 0xFFFFFFFF 1237 1238 #define SHAMD5_HASH512_LENGTH_DATA_S 0 1239 1240 1241 1242 #endif // __HW_SHAMD5_H__ 1243