1 /* $OpenBSD: rtcreg.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $ */ 2 /* $NetBSD: rtcreg.h,v 1.10 2006/09/03 12:38:34 uwe Exp $ */ 3 4 /*- 5 * Copyright (C) 1999 SAITOH Masanobu. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef _SH_RTCREG_H_ 31 #define _SH_RTCREG_H_ 32 #include <sh/devreg.h> 33 34 /* 35 * RTC 36 */ 37 #define SH3_R64CNT 0xfffffec0 38 #define SH3_RSECCNT 0xfffffec2 39 #define SH3_RMINCNT 0xfffffec4 40 #define SH3_RHRCNT 0xfffffec6 41 #define SH3_RWKCNT 0xfffffec8 42 #define SH3_RDAYCNT 0xfffffeca 43 #define SH3_RMONCNT 0xfffffecc 44 #define SH3_RYRCNT 0xfffffece 45 #define SH3_RSECAR 0xfffffed0 46 #define SH3_RMINAR 0xfffffed2 47 #define SH3_RHRAR 0xfffffed4 48 #define SH3_RWKAR 0xfffffed6 49 #define SH3_RDAYAR 0xfffffed8 50 #define SH3_RMONAR 0xfffffeda 51 #define SH3_RCR1 0xfffffedc 52 #define SH3_RCR2 0xfffffede 53 54 #define SH4_R64CNT 0xffc80000 55 #define SH4_RSECCNT 0xffc80004 56 #define SH4_RMINCNT 0xffc80008 57 #define SH4_RHRCNT 0xffc8000c 58 #define SH4_RWKCNT 0xffc80010 59 #define SH4_RDAYCNT 0xffc80014 60 #define SH4_RMONCNT 0xffc80018 61 #define SH4_RYRCNT 0xffc8001c /* 16 bit */ 62 #define SH4_RSECAR 0xffc80020 63 #define SH4_RMINAR 0xffc80024 64 #define SH4_RHRAR 0xffc80028 65 #define SH4_RWKAR 0xffc8002c 66 #define SH4_RDAYAR 0xffc80030 67 #define SH4_RMONAR 0xffc80034 68 #define SH4_RCR1 0xffc80038 69 #define SH4_RCR2 0xffc8003c 70 71 #define SH_RCR1_CF 0x80 /* carry flag */ 72 #define SH_RCR1_CIE 0x10 /* carry interrupt enable */ 73 #define SH_RCR1_AIE 0x08 /* alarm interrupt enable */ 74 #define SH_RCR1_AF 0x01 /* alarm flag */ 75 76 #define SH_RCR2_PEF 0x80 /* periodic interrupt flag */ 77 #define SH_RCR2_PES2 0x40 /* periodic interrupt freq */ 78 #define SH_RCR2_PES1 0x20 /* -//- */ 79 #define SH_RCR2_PES0 0x10 /* -//- */ 80 #define SH_RCR2_ENABLE 0x08 81 #define SH_RCR2_ADJ 0x04 /* second adjustment */ 82 #define SH_RCR2_RESET 0x02 83 #define SH_RCR2_START 0x01 84 85 #ifndef _LOCORE 86 #if defined(SH3) && defined(SH4) 87 extern uint32_t __sh_R64CNT; 88 extern uint32_t __sh_RSECCNT; 89 extern uint32_t __sh_RMINCNT; 90 extern uint32_t __sh_RHRCNT; 91 extern uint32_t __sh_RWKCNT; 92 extern uint32_t __sh_RDAYCNT; 93 extern uint32_t __sh_RMONCNT; 94 extern uint32_t __sh_RYRCNT; 95 extern uint32_t __sh_RSECAR; 96 extern uint32_t __sh_RMINAR; 97 extern uint32_t __sh_RHRAR; 98 extern uint32_t __sh_RWKAR; 99 extern uint32_t __sh_RDAYAR; 100 extern uint32_t __sh_RMONAR; 101 extern uint32_t __sh_RCR1; 102 extern uint32_t __sh_RCR2; 103 #endif /* SH3 && SH4 */ 104 #endif /* !_LOCORE */ 105 106 #endif /* !_SH_RTCREG_H_ */ 107