1 /* -*- tab-width: 4 -*- 2 * 3 * Electric(tm) VLSI Design System 4 * 5 * File: sim.h 6 * Simulation tool: header file 7 * Written by: Steven M. Rubin, Static Free Software 8 * 9 * Copyright (c) 2000 Static Free Software. 10 * 11 * Electric(tm) is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * Electric(tm) is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with Electric(tm); see the file COPYING. If not, write to 23 * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, 24 * Boston, Mass 02111-1307, USA. 25 * 26 * Static Free Software 27 * 4119 Alpine Road 28 * Portola Valley, California 94028 29 * info@staticfreesoft.com 30 */ 31 32 #if defined(__cplusplus) && !defined(ALLCPLUSPLUS) 33 extern "C" 34 { 35 #endif 36 37 /********************* for all simulators *********************/ 38 39 #define ESIM 0 /* ESIM from MIT (SIM format) */ 40 #define RSIM 1 /* RSIM from MIT (SIM format) */ 41 #define RNL 2 /* RNL from MIT (SIM format) */ 42 #define COSMOS 3 /* COSMOS from CMU (SIM format) */ 43 #define SPICE 4 /* SPICE from Berkeley (SPICE format) */ 44 #define MOSSIM 5 /* MOSSIM from CalTech (NTK format) */ 45 #define TEXSIM 6 /* TEGAS from Calma (TDL format) */ 46 #define ABEL 7 /* ABEL from Data I/O (PAL programmer) */ 47 #define VERILOG 8 /* VERILOG from Gateway (VER format) */ 48 #define SILOS 9 /* SILOS from Simucad */ 49 #define ALS 10 /* ALS (NET format) */ 50 #define FASTHENRY 11 /* FastHenry (INP format) */ 51 #define IRSIM 12 /* IRSIM from Stanford (SIM format) */ 52 #define CDL 13 /* CDL (SPICE with no headers or parameters) */ 53 #define MAXWELL 14 /* MAXWELL (electromagnetic simulation) */ 54 55 /* the meaning of "SIM_dontrun" */ 56 #define SIMRUNYES -1 /* run simulation, show output */ 57 #define SIMRUNYESPARSE 0 /* run simulation, show output, parse output */ 58 #define SIMRUNNO 1 /* do not runs simulation */ 59 #define SIMRUNYESQPARSE 2 /* run simulation, parse output */ 60 #define SIMRUNYESQ 3 /* run simulation */ 61 62 extern TOOL *sim_tool; /* the Simulator tool object */ 63 extern INTBIG sim_formatkey; /* key for "SIM_format" (ESIM, etc) */ 64 extern INTBIG sim_netfilekey; /* key for "SIM_netfile" */ 65 extern INTBIG sim_dontrunkey; /* key for "SIM_dontrun" */ 66 extern INTBIG sim_weaknodekey; /* key for "SIM_weak_node" */ 67 extern INTBIG sim_spice_partskey; /* key for "SIM_spice_parts" */ 68 extern CHAR *sim_spice_parts; /* cached value for "SIM_spice_parts" */ 69 extern NODEPROTO *sim_simnt; /* cell being simulated */ 70 #if defined(__cplusplus) 71 extern EProcess *sim_process; /* process of simulator */ 72 #endif 73 extern INTBIG sim_filetypeesim; /* ESIM netlist disk file descriptor */ 74 extern INTBIG sim_filetypefasthenry;/* FastHenry netlist disk file descriptor */ 75 extern INTBIG sim_filetypemossim; /* MOSSIM netlist disk file descriptor */ 76 extern INTBIG sim_filetypepal; /* PAL netlist disk file descriptor */ 77 extern INTBIG sim_filetypeals; /* ALS netlist disk file descriptor */ 78 extern INTBIG sim_filetypealsvec; /* ALS vectors disk file descriptor */ 79 extern INTBIG sim_filetypeirsimcmd; /* IRSIM command (vectors) file descriptor */ 80 extern INTBIG sim_filetypenetlisp; /* Netlisp netlist disk file descriptor */ 81 extern INTBIG sim_filetypequisc; /* QUISC netlist disk file descriptor */ 82 extern INTBIG sim_filetypersim; /* RSIM netlist disk file descriptor */ 83 extern INTBIG sim_filetypeirsim; /* IRSIM netlist disk file descriptor */ 84 extern INTBIG sim_filetypesilos; /* Silos netlist disk file descriptor */ 85 extern INTBIG sim_filetypespice; /* SPICE input disk file descriptor */ 86 extern INTBIG sim_filetypespicecmd; /* SPICE command disk file descriptor */ 87 extern INTBIG sim_filetypespiceout; /* SPICE output disk file descriptor */ 88 extern INTBIG sim_filetypehspiceout;/* HSPICE output file descriptor */ 89 extern INTBIG sim_filetyperawspiceout; /* SPICE raw output disk file descriptor */ 90 extern INTBIG sim_filetypesrawspiceout; /* SmartSPICE raw output disk file descriptor */ 91 extern INTBIG sim_filetypecdl; /* CDL output file descriptor */ 92 extern INTBIG sim_filetypectemp; /* CDL template disk file descriptor */ 93 extern INTBIG sim_filetypemaxwell; /* MAXWELL output file descriptor */ 94 extern INTBIG sim_filetypetegas; /* Tegas netlist disk file descriptor */ 95 extern INTBIG sim_filetypetegastab; /* Tegas table disk file descriptor */ 96 extern INTBIG sim_filetypeverilog; /* Verilog disk file descriptor */ 97 extern INTBIG sim_filetypeverilogvcd; /* Verilog VCD dump file descriptor */ 98 99 /********************* for Simulation Window *********************/ 100 101 /* the bits returned by "sim_window_isactive()" */ 102 #define SIMWINDOWWAVEFORM 1 /* set if waveform window is active */ 103 #define SIMWINDOWSCHEMATIC 2 /* set if schematic window is active */ 104 105 #define MAXSIMWINDOWBUSWIDTH 300 /* maximum width of a bus in thw waveform window */ 106 107 /* logic levels and signal strengths in the window */ 108 #define LOGIC_LOW -1 109 #define LOGIC_X -2 110 #define LOGIC_HIGH -3 111 #define LOGIC_Z -4 112 #define OFF_STRENGTH 0 113 #define NODE_STRENGTH 2 114 #define GATE_STRENGTH 4 115 #define VDD_STRENGTH 6 116 117 /* the meaning of "SIM_window_state" */ 118 #define FULLSTATE 01 /* set for full 12-state simulation */ 119 #define SHOWWAVEFORM 02 /* set to show waveform window */ 120 #define ADVANCETIME 04 /* set to advance time to end of simulation */ 121 #define BUSBASEBITS 070 /* base to use for bus display */ 122 #define BUSBASE10 0 /* use base 10 for bus display */ 123 #define BUSBASE2 010 /* use base 2 for bus display */ 124 #define BUSBASE8 020 /* use base 8 for bus display */ 125 #define BUSBASE16 040 /* use base 16 for bus display */ 126 #define WAVEPLACE 0300 /* location of waveform windows */ 127 #define WAVEPLACECAS 0 /* cascade waveform windows */ 128 #define WAVEPLACETHOR 0100 /* cascade waveform windows */ 129 #define WAVEPLACETVER 0200 /* cascade waveform windows */ 130 #define SIMENGINE 01400 /* simulation engine to use for "simulate" command */ 131 #define SIMENGINEALS 0 /* use ALS simulation engine */ 132 #define SIMENGINEIRSIM 0400 /* use IRSIM simulation engine */ 133 #define SIMENGINECUR 016000 /* simulation in this window */ 134 #define SIMENGINECURALS 0 /* current window has ALS simulation */ 135 #define SIMENGINECURIRSIM 02000 /* current window has IRSIM simulation */ 136 #define SIMENGINECURVERILOG 04000 /* current window has Verilog simulation */ 137 #define SIMENGINECURSPICE 010000 /* current window has SPICE simulation */ 138 139 extern INTBIG sim_window_statekey; /* key for "SIM_window_state" */ 140 extern INTBIG sim_window_state; /* cached value of "SIM_window_state" */ 141 extern INTBIG sim_window_signalorder_key; /* key for "SIM_window_signalorder" */ 142 extern INTBIG sim_window_hierpos_key; /* key for "SIM_window_hierarchy_pos" */ 143 extern INTBIG sim_window_format; /* type of simulation in window */ 144 extern INTBIG sim_colorstrengthoff; /* color of off-strength */ 145 extern INTBIG sim_colorstrengthnode; /* color of node-strength */ 146 extern INTBIG sim_colorstrengthgate; /* color of gate-strength */ 147 extern INTBIG sim_colorstrengthpower; /* color of power-strength */ 148 extern INTBIG sim_colorlevellow; /* color of low-levels */ 149 extern INTBIG sim_colorlevelhigh; /* color of high-levels */ 150 extern INTBIG sim_colorlevelundef; /* color of undefined levels */ 151 extern INTBIG sim_colorlevelzdef; /* color of Z levels */ 152 extern INTBIG sim_colorstrengthoff_key; /* key for "SIM_window_color_str0" */ 153 extern INTBIG sim_colorstrengthnode_key; /* key for "SIM_window_color_str1" */ 154 extern INTBIG sim_colorstrengthgate_key; /* key for "SIM_window_color_str2" */ 155 extern INTBIG sim_colorstrengthpower_key; /* key for "SIM_window_color_str3" */ 156 extern INTBIG sim_colorlevellow_key; /* key for "SIM_window_color_low" */ 157 extern INTBIG sim_colorlevelhigh_key; /* key for "SIM_window_color_high" */ 158 extern INTBIG sim_colorlevelundef_key; /* key for "SIM_window_color_X" */ 159 extern INTBIG sim_colorlevelzdef_key; /* key for "SIM_window_color_Z" */ 160 161 /* prototypes */ 162 void sim_window_init(void); 163 BOOLEAN sim_window_create(INTBIG, NODEPROTO*, BOOLEAN(*)(WINDOWPART*, INTSML, INTBIG), 164 BOOLEAN(*)(WINDOWPART*, INTSML, INTBIG), INTBIG); 165 void sim_window_titleinfo(CHAR *title); 166 void sim_window_stopsimulation(void); 167 void sim_window_setvdd(float vdd); 168 INTBIG sim_window_isactive(NODEPROTO **np); 169 void sim_window_redraw(void); 170 void sim_window_setnumframes(INTBIG); 171 INTBIG sim_window_getnumframes(void); 172 INTBIG sim_window_getnumvisframes(void); 173 INTBIG sim_window_getcurframe(void); 174 void sim_window_settopvisframe(INTBIG count); 175 INTBIG sim_window_gettopvisframe(void); 176 void sim_window_savegraph(void); 177 void sim_window_writespicecmd(void); 178 void sim_window_setdisplaycolor(INTBIG strength, INTBIG color); 179 INTBIG sim_window_getdisplaycolor(INTBIG strength); 180 INTBIG sim_window_newtrace(INTBIG, CHAR*, INTBIG); 181 BOOLEAN sim_window_buscommand(void); 182 INTBIG sim_window_makebus(INTBIG count, INTBIG *traces, CHAR *busname); 183 void sim_window_loaddigtrace(INTBIG, INTBIG, double*, INTSML*); 184 void sim_window_loadanatrace(INTBIG, INTBIG, double*, float*); 185 void sim_window_settraceframe(INTBIG, INTBIG); 186 void sim_window_killtrace(INTBIG); 187 void sim_window_killalltraces(BOOLEAN); 188 INTBIG *sim_window_getbustraces(INTBIG); 189 INTBIG sim_window_gettraceframe(INTBIG); 190 CHAR *sim_window_gettracename(INTBIG); 191 INTBIG sim_window_gettracedata(INTBIG); 192 float sim_window_getanatracevalue(INTBIG, double); 193 CHAR *sim_window_getbustracevalue(INTBIG tri, double time); 194 void sim_window_getdigtracevalue(INTBIG tri, double time, INTBIG *level, INTBIG *strength); 195 INTBIG *sim_window_findtrace(CHAR*, INTBIG*); 196 void sim_window_inittraceloop(void); 197 void sim_window_inittraceloop2(void); 198 INTBIG sim_window_nexttraceloop(void); 199 INTBIG sim_window_nexttraceloop2(void); 200 void sim_window_cleartracehighlight(void); 201 void sim_window_addhighlighttrace(INTBIG); 202 void sim_window_deletehighlighttrace(INTBIG); 203 INTBIG sim_window_gethighlighttrace(void); 204 INTBIG *sim_window_gethighlighttraces(void); 205 void sim_window_showhighlightedtraces(void); 206 void sim_window_setmaincursor(double); 207 double sim_window_getmaincursor(void); 208 void sim_window_setextensioncursor(double); 209 double sim_window_getextensioncursor(void); 210 void sim_window_settimerange(INTBIG, double, double); 211 void sim_window_gettimerange(INTBIG, double*, double*); 212 void sim_window_getaveragetimerange(double *avgmintime, double *avgmaxtime); 213 void sim_window_gettimeextents(double*, double*); 214 void sim_window_updatelayoutwindow(void); 215 CHAR *sim_windowconvertengineeringnotation(double); 216 void sim_window_setstate(INTBIG); 217 INTBIG sim_window_getwidevalue(INTBIG **bits); 218 void sim_window_auto_anarange(void); 219 void sim_window_zoom_frame(INTBIG frameno); 220 void sim_window_zoomout_frame(INTBIG frameno); 221 void sim_window_shiftup_frame(INTBIG frameno); 222 void sim_window_shiftdown_frame(INTBIG frameno); 223 void sim_window_grabcachedsignalsoncell(NODEPROTO *cell); 224 INTBIG sim_window_getcachedsignals(CHAR ***strings); 225 void sim_window_supresstraceprefix(CHAR *prefix); 226 void sim_window_renumberlines(void); 227 void sim_window_advancetime(void); 228 229 /********************* for ESIM *********************/ 230 231 #define ESIMNAME x_("esim") 232 233 /********************* for RSIM *********************/ 234 235 #define RSIMPRENAME x_("presim") 236 #define RSIMNAME x_("rsim") 237 #define RSIMIN x_("rsim.in") /* name of file with binary network */ 238 239 /********************* for ALS *********************/ 240 241 #define NET_EXT x_(".net") 242 #define PLOT_EXT x_(".hpgl") 243 244 /********************* for RNL *********************/ 245 246 #define RNLPRENAME x_("presim") 247 #define RNLNAME x_("rnl") 248 #define RNLIN x_("rnl.in") /* name of file with binary network */ 249 #define RNLCOMM x_("nl.l") /* file with simulator initialization */ 250 251 /********************* for VERILOG *********************/ 252 253 /* Meaning of bits in "SIM_verilog_state" */ 254 #define VERILOGUSEASSIGN 01 /* set to use "assign" construct */ 255 #define VERILOGUSETRIREG 02 /* set to use "trireg" wire by default */ 256 257 extern INTBIG sim_verilog_statekey; /* key for "SIM_verilog_state" */ 258 259 void sim_verlevel_up(NODEPROTO *cell); 260 void sim_verlevel_set(CHAR *instname, NODEPROTO *cell); 261 void sim_verparsefile(CHAR*, NODEPROTO *cell); 262 BOOLEAN sim_vertopofinstances(CHAR **c); 263 CHAR *sim_vernextinstance(void); 264 CHAR *sim_verlevel_cur(void); 265 void sim_verreportsignals(WINDOWPART *simwin, void *(*addbranch)(CHAR*, void*), 266 void *(*findbranch)(CHAR*, void*), void *(*addleaf)(CHAR*, void*), CHAR *(*nodename)(void*)); 267 void sim_veraddhighlightednet(CHAR *signame); 268 269 /********************* for SPICE *********************/ 270 271 #define MAXSPICELEVEL 3 /* levels 1, 2, and 3 */ 272 273 /* Meaning of bits in sim_spice_state */ 274 #define SPICERESISTANCE 01 /* set for resistances */ 275 #define SPICEPLOT 02 /* set for plots (vs prints) */ 276 #define SPICENODENAMES 010 /* set for node names (vs numbers) */ 277 #define SPICETYPE 0160 /* mask for spice type */ 278 #define SPICE2 000 /* spice 2 */ 279 #define SPICE3 020 /* spice 3 */ 280 #define SPICEHSPICE 040 /* hspice */ 281 #define SPICEPSPICE 060 /* pspice */ 282 #define SPICEGNUCAP 0100 /* gnucap */ 283 #define SPICESMARTSPICE 0120 /* smartspice */ 284 #define SPICEGLOBALPG 0200 /* set to use global power and ground */ 285 #define SPICECELLPARAM 01000 /* set to use cell parameters */ 286 #define SPICEUSELAMBDAS 02000 /* set to use lambdas instead of microns for transistor sizes */ 287 #define SPICEOUTPUT 034000 /* mask for output format */ 288 #define SPICEOUTPUTNORM 0 /* normal */ 289 #define SPICEOUTPUTRAW 04000 /* raw */ 290 #define SPICEOUTPUTRAWSMART 010000 /* raw for smartspice */ 291 292 extern INTBIG sim_spice_levelkey; /* key for "SIM_spice_level" */ 293 extern INTBIG sim_spice_statekey; /* key for "SIM_spice_state" */ 294 extern INTBIG sim_spice_state; /* value of "SIM_spice_state" */ 295 extern INTBIG sim_spice_nameuniqueid; /* key for "SIM_spice_nameuniqueid" */ 296 extern INTBIG sim_spice_listingfilekey; /* key for "SIM_listingfile" */ 297 extern INTBIG sim_spice_runargskey; /* key for "SIM_spice_runarguments" */ 298 299 void sim_spicereportsignals(WINDOWPART *simwin, void *(*addbranch)(CHAR*, void*), 300 void *(*findbranch)(CHAR*, void*), void *(*addleaf)(CHAR*, void*), CHAR *(*nodename)(void*)); 301 void sim_spice_addhighlightednet(CHAR *name, BOOLEAN); 302 303 /********************* for FASTHENRY *********************/ 304 305 /* the meaning of "tool:sim.SIM_fasthenry_state" */ 306 #define FHUSESINGLEFREQ 01 /* use single frequency */ 307 #define FHMAKEMULTIPOLECKT 02 /* make multipole circuit */ 308 #define FHMAKEPOSTSCRIPTVIEW 04 /* make PostScript view */ 309 #define FHMAKESPICESUBCKT 010 /* make SPICE subcircuit */ 310 #define FHEXECUTETYPE 0160 /* what to do after writing the deck */ 311 #define FHEXECUTENONE 0 /* no simulator run */ 312 #define FHEXECUTERUNFH 020 /* run fasthenry */ 313 #define FHEXECUTERUNFHMUL 040 /* run fasthenry for every group */ 314 315 extern INTBIG sim_fasthenrystatekey; /* variable key for "SIM_fasthenry_state" */ 316 extern INTBIG sim_fasthenryfreqstartkey; /* variable key for "SIM_fasthenry_freqstart" */ 317 extern INTBIG sim_fasthenryfreqendkey; /* variable key for "SIM_fasthenry_freqend" */ 318 extern INTBIG sim_fasthenryrunsperdecadekey;/* variable key for "SIM_fasthenry_runsperdecade" */ 319 extern INTBIG sim_fasthenrynumpoleskey; /* variable key for "SIM_fasthenry_numpoles" */ 320 extern INTBIG sim_fasthenryseglimitkey; /* variable key for "SIM_fasthenry_seglimit" */ 321 extern INTBIG sim_fasthenrythicknesskey; /* variable key for "SIM_fasthenry_thickness" */ 322 extern INTBIG sim_fasthenrywidthsubdivkey; /* variable key for "SIM_fasthenry_width_subdivs" */ 323 extern INTBIG sim_fasthenryheightsubdivkey; /* variable key for "SIM_fasthenry_height_subdivs" */ 324 extern INTBIG sim_fasthenryzheadkey; /* variable key for "SIM_fasthenry_z_head" */ 325 extern INTBIG sim_fasthenryztailkey; /* variable key for "SIM_fasthenry_z_tail" */ 326 extern INTBIG sim_fasthenrygroupnamekey; /* variable key for "SIM_fasthenry_group_name" */ 327 328 /* prototypes for tool interface */ 329 void sim_init(INTBIG*, CHAR1*[], TOOL*); 330 void sim_done(void); 331 void sim_set(INTBIG, CHAR*[]); 332 INTBIG sim_request(CHAR *command, va_list ap); 333 void sim_slice(void); 334 void sim_startbatch(TOOL*, BOOLEAN); 335 void sim_modifynodeinst(NODEINST*,INTBIG,INTBIG,INTBIG,INTBIG,INTBIG,INTBIG); 336 void sim_modifyarcinst(ARCINST*,INTBIG,INTBIG,INTBIG,INTBIG,INTBIG,INTBIG); 337 void sim_modifyportproto(PORTPROTO*, NODEINST*, PORTPROTO*); 338 void sim_newobject(INTBIG, INTBIG); 339 void sim_killobject(INTBIG, INTBIG); 340 void sim_newvariable(INTBIG, INTBIG, INTBIG, INTBIG); 341 void sim_killvariable(INTBIG, INTBIG, INTBIG, INTBIG, INTBIG, UINTBIG*); 342 void sim_modifyvariable(INTBIG, INTBIG, INTBIG, INTBIG, INTBIG, INTBIG); 343 void sim_insertvariable(INTBIG, INTBIG, INTBIG, INTBIG, INTBIG); 344 void sim_deletevariable(INTBIG, INTBIG, INTBIG, INTBIG, INTBIG, INTBIG); 345 void sim_readlibrary(LIBRARY*); 346 347 /* prototypes for intratool interface */ 348 void sim_freewindowmemory(void); 349 void sim_freespicememory(void); 350 void sim_freespicerun_memory(void); 351 void sim_freeirsimmemory(void); 352 void sim_freemaxwellmemory(void); 353 void sim_freeverilogmemory(void); 354 void sim_spice_xprintf(FILE*, BOOLEAN, CHAR*, ...); 355 NETWORK *sim_spice_networkfromname(CHAR *name); 356 CHAR *sim_spice_signalname(NETWORK *net); 357 void sim_simpointout(CHAR*, INTBIG); 358 void sim_spice_execute(CHAR*, CHAR*, NODEPROTO*); 359 void sim_writefasthenrynetlist(NODEPROTO*); 360 void sim_fasthenryinit(void); 361 void sim_writesim(NODEPROTO*, INTBIG); 362 void sim_writeirsim(NODEPROTO*); 363 void sim_writepalnetlist(NODEPROTO*); 364 void sim_writemaxwell(NODEPROTO*); 365 void sim_writemossim(NODEPROTO*); 366 void sim_writetexnetlist(NODEPROTO*); 367 void sim_writespice(NODEPROTO*, BOOLEAN); 368 void sim_writevernetlist(NODEPROTO*); 369 void sim_writesilnetlist(NODEPROTO*); 370 void sim_resumesim(BOOLEAN); 371 INTBIG sim_alsclockdlog(CHAR *paramstart[]); 372 void sim_initbussignals(void); 373 void sim_addbussignal(INTBIG signal); 374 INTBIG sim_getbussignals(INTBIG **signallist); 375 void sim_reportsignals(WINDOWPART *simwin, void *(*addbranch)(CHAR*, void*), 376 void *(*findbranch)(CHAR*, void*), void *(*addleaf)(CHAR*, void*), CHAR *(*nodename)(void*)); 377 void sim_addsignal(WINDOWPART *simwin, CHAR *sig, BOOLEAN overlay); 378 CHAR *sim_signalseparator(void); 379 380 #if defined(__cplusplus) && !defined(ALLCPLUSPLUS) 381 } 382 #endif 383 384 #if defined(__cplusplus) 385 386 class SpiceCell; 387 class SpiceInst; 388 class SpiceBind; 389 class SpiceParam; 390 class SpiceNet; 391 392 class SpiceCell 393 { 394 friend class SpiceInst; 395 friend class SpiceNet; 396 public: 397 SpiceCell( CHAR *name = "" ); 398 ~SpiceCell(); name()399 CHAR *name() { return _name; } 400 static SpiceCell *findByName( CHAR *name ); 401 void setup(); 402 static void traverseAll(); 403 static void clearAll(); 404 void printSpice(); 405 private: 406 void traverse(); 407 CHAR *_name; 408 static SpiceCell *_firstCell; 409 SpiceCell *_nextCell; 410 SpiceInst *_firstInst, *_lastInst; 411 SpiceNet *_firstNet; 412 INTBIG _pathlen; 413 INTBIG _totalnets; 414 static CHAR *_path; 415 static CHAR *_pathend; 416 static CHAR *_rpath; 417 static CHAR *_rpathbeg; 418 }; 419 420 class SpiceInst 421 { 422 friend class SpiceCell; 423 friend class SpiceBind; 424 public: 425 SpiceInst( SpiceCell *parentCell, CHAR *name ); 426 ~SpiceInst(); name()427 CHAR *name() { return _name; } 428 void setInstCell( SpiceCell *instCell ); 429 void addParam( SpiceParam *param ); 430 void addParamM( NODEINST *ni ); 431 void addError( CHAR *error ); 432 private: 433 void addBind( SpiceBind *bind ); 434 void printSpice(); 435 void traverse(); 436 CHAR *_name; 437 SpiceCell *_parentCell; 438 SpiceCell *_instCell; 439 SpiceBind *_firstBind, *_lastBind; 440 SpiceParam *_firstParam, *_lastParam; 441 CHAR *_error; 442 SpiceInst *_nextInst; 443 }; 444 445 class SpiceBind 446 { 447 friend class SpiceInst; 448 public: 449 SpiceBind( SpiceInst *inst, SpiceNet *net = 0 ); 450 ~SpiceBind(); 451 private: 452 void printSpice(); 453 SpiceInst *_inst; 454 SpiceNet *_net; 455 SpiceBind *_nextBind; 456 }; 457 458 class SpiceParam 459 { 460 friend class SpiceInst; 461 public: 462 SpiceParam( CHAR *str ); 463 ~SpiceParam(); str()464 CHAR *str() { return _str; } 465 private: 466 CHAR *_str; 467 SpiceParam *_nextParam; 468 }; 469 470 class SpiceNet 471 { 472 friend class SpiceCell; 473 friend class SpiceBind; 474 public: 475 SpiceNet( SpiceCell *parentCell, INTBIG netnumber, NETWORK *netw = 0 ); 476 ~SpiceNet(); 477 private: 478 void printSpice(); 479 INTBIG _netnumber; 480 NETWORK *_netw; 481 SpiceCell *_parentCell; 482 SpiceNet *_nextNet; 483 }; 484 485 extern CHAR **sim_spice_printlist; 486 extern INTBIG sim_spice_printlistlen; 487 488 #endif 489