1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30 #include "util/u_dynarray.h"
31 #include "util/u_idalloc.h"
32 #include "util/u_suballoc.h"
33 #include "util/u_threaded_context.h"
34 #include "util/u_vertex_state_cache.h"
35 #include "ac_sqtt.h"
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 #if UTIL_ARCH_BIG_ENDIAN
42 #define SI_BIG_ENDIAN 1
43 #else
44 #define SI_BIG_ENDIAN 0
45 #endif
46
47 #define ATI_VENDOR_ID 0x1002
48 #define SI_NOT_QUERY 0xffffffff
49
50 /* The base vertex and primitive restart can be any number, but we must pick
51 * one which will mean "unknown" for the purpose of state tracking and
52 * the number shouldn't be a commonly-used one. */
53 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
54 #define SI_START_INSTANCE_UNKNOWN ((unsigned)INT_MIN)
55 #define SI_DRAW_ID_UNKNOWN ((unsigned)INT_MIN)
56 #define SI_RESTART_INDEX_UNKNOWN ((unsigned)INT_MIN)
57 #define SI_INSTANCE_COUNT_UNKNOWN ((unsigned)INT_MIN)
58 #define SI_NUM_SMOOTH_AA_SAMPLES 4
59 #define SI_MAX_POINT_SIZE 2048
60 #define SI_GS_PER_ES 128
61 /* Alignment for optimal CP DMA performance. */
62 #define SI_CPDMA_ALIGNMENT 32
63
64 /* We don't want to evict buffers from VRAM by mapping them for CPU access,
65 * because they might never be moved back again. If a buffer is large enough,
66 * upload data by copying from a temporary GTT buffer. 8K might not seem much,
67 * but there can be 100000 buffers.
68 *
69 * This tweak improves performance for viewperf creo & snx.
70 */
71 #define SI_MAX_VRAM_MAP_SIZE 8196
72
73 /* Tunables for compute-based clear_buffer and copy_buffer: */
74 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
75 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
76 /* L2 LRU is recommended because the compute shader can finish sooner due to fewer L2 evictions. */
77 #define SI_COMPUTE_DST_CACHE_POLICY L2_LRU
78
79 /* Pipeline & streamout query controls. */
80 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
81 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
82 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
83 /* Instruction cache. */
84 #define SI_CONTEXT_INV_ICACHE (1 << 3)
85 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
86 * GFX10: This also invalidates the L1 shader array cache. */
87 #define SI_CONTEXT_INV_SCACHE (1 << 4)
88 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
89 * GFX10: This also invalidates the L1 shader array cache. */
90 #define SI_CONTEXT_INV_VCACHE (1 << 5)
91 /* L2 cache + L2 metadata cache writeback & invalidate.
92 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
93 #define SI_CONTEXT_INV_L2 (1 << 6)
94 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
95 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
96 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
97 #define SI_CONTEXT_WB_L2 (1 << 7)
98 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
99 * a CB or DB flush. */
100 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
101 /* Framebuffer caches. */
102 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
103 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
104 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
105 /* Engine synchronization. */
106 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
107 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
108 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
109 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
110 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
111 /* PFP waits for ME to finish. Used to sync for index and indirect buffers and render
112 * condition. It's typically set when doing a VS/PS/CS partial flush for buffers. */
113 #define SI_CONTEXT_PFP_SYNC_ME (1 << 17)
114
115 #define SI_PREFETCH_LS (1 << 1)
116 #define SI_PREFETCH_HS (1 << 2)
117 #define SI_PREFETCH_ES (1 << 3)
118 #define SI_PREFETCH_GS (1 << 4)
119 #define SI_PREFETCH_VS (1 << 5)
120 #define SI_PREFETCH_PS (1 << 6)
121
122 #define SI_MAX_BORDER_COLORS 4096
123 #define SI_MAX_VIEWPORTS 16
124 #define SIX_BITS 0x3F
125 #define SI_MAP_BUFFER_ALIGNMENT 64
126 /* We only support the minimum allowed value (512), so that we can pack a 3D block size
127 * in 1 SGPR. */
128 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 512
129
130 #define SI_CONTEXT_FLAG_AUX (1u << 31)
131
132 #define SI_RESOURCE_FLAG_FORCE_LINEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
133 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
134 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
135 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
136 #define SI_RESOURCE_FLAG_DRIVER_INTERNAL (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
137 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
138 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
139 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
140 #define SI_RESOURCE_AUX_PLANE (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
141 /* Set a micro tile mode: */
142 #define SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE (PIPE_RESOURCE_FLAG_DRV_PRIV << 9)
143 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT (util_logbase2(PIPE_RESOURCE_FLAG_DRV_PRIV) + 10)
144 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(x) \
145 (((x)&0x3) << SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT)
146 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(x) \
147 (((x) >> SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) & 0x3)
148 #define SI_RESOURCE_FLAG_UNCACHED (PIPE_RESOURCE_FLAG_DRV_PRIV << 12)
149
150 enum si_has_gs {
151 GS_OFF,
152 GS_ON,
153 };
154
155 enum si_has_tess {
156 TESS_OFF,
157 TESS_ON,
158 };
159
160 enum si_has_ngg {
161 NGG_OFF,
162 NGG_ON,
163 };
164
165 enum si_clear_code
166 {
167 DCC_CLEAR_COLOR_0000 = 0x00000000,
168 DCC_CLEAR_COLOR_0001 = 0x40404040,
169 DCC_CLEAR_COLOR_1110 = 0x80808080,
170 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
171 DCC_CLEAR_COLOR_REG = 0x20202020,
172 DCC_UNCOMPRESSED = 0xFFFFFFFF,
173 };
174
175 #define SI_IMAGE_ACCESS_DCC_OFF (1 << 8)
176 #define SI_IMAGE_ACCESS_ALLOW_DCC_STORE (1 << 9)
177
178 /* Debug flags. */
179 enum
180 {
181 /* Shader logging options: */
182 DBG_VS = MESA_SHADER_VERTEX,
183 DBG_TCS = MESA_SHADER_TESS_CTRL,
184 DBG_TES = MESA_SHADER_TESS_EVAL,
185 DBG_GS = MESA_SHADER_GEOMETRY,
186 DBG_PS = MESA_SHADER_FRAGMENT,
187 DBG_CS = MESA_SHADER_COMPUTE,
188 DBG_NO_IR,
189 DBG_NO_NIR,
190 DBG_NO_ASM,
191 DBG_PREOPT_IR,
192
193 /* Shader compiler options the shader cache should be aware of: */
194 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
195 DBG_GISEL,
196 DBG_W32_GE,
197 DBG_W32_PS,
198 DBG_W32_PS_DISCARD,
199 DBG_W32_CS,
200 DBG_W64_GE,
201 DBG_W64_PS,
202 DBG_W64_CS,
203
204 /* Shader compiler options (with no effect on the shader cache): */
205 DBG_CHECK_IR,
206 DBG_MONOLITHIC_SHADERS,
207 DBG_NO_OPT_VARIANT,
208
209 /* Information logging options: */
210 DBG_INFO,
211 DBG_TEX,
212 DBG_COMPUTE,
213 DBG_VM,
214 DBG_CACHE_STATS,
215 DBG_IB,
216
217 /* Driver options: */
218 DBG_NO_WC,
219 DBG_CHECK_VM,
220 DBG_RESERVE_VMID,
221 DBG_SHADOW_REGS,
222 DBG_NO_FAST_DISPLAY_LIST,
223
224 /* Multimedia options: */
225 DBG_NO_EFC,
226
227 /* 3D engine options: */
228 DBG_NO_GFX,
229 DBG_NO_NGG,
230 DBG_ALWAYS_NGG_CULLING_ALL,
231 DBG_NO_NGG_CULLING,
232 DBG_SWITCH_ON_EOP,
233 DBG_NO_OUT_OF_ORDER,
234 DBG_NO_DPBB,
235 DBG_DPBB,
236 DBG_NO_HYPERZ,
237 DBG_NO_2D_TILING,
238 DBG_NO_TILING,
239 DBG_NO_DISPLAY_TILING,
240 DBG_NO_DISPLAY_DCC,
241 DBG_NO_EXPORTED_DCC,
242 DBG_NO_DCC,
243 DBG_NO_DCC_CLEAR,
244 DBG_NO_DCC_STORE,
245 DBG_DCC_STORE,
246 DBG_NO_DCC_MSAA,
247 DBG_NO_FMASK,
248 DBG_NO_DMA,
249
250 DBG_TMZ,
251 DBG_SQTT,
252
253 DBG_COUNT
254 };
255
256 enum
257 {
258 /* Tests: */
259 DBG_TEST_BLIT,
260 DBG_TEST_VMFAULT_CP,
261 DBG_TEST_VMFAULT_SHADER,
262 DBG_TEST_DMA_PERF,
263 DBG_TEST_GDS,
264 DBG_TEST_GDS_MM,
265 DBG_TEST_GDS_OA_MM,
266 };
267
268 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
269 #define DBG(name) (1ull << DBG_##name)
270
271 enum si_cache_policy
272 {
273 L2_BYPASS,
274 L2_STREAM, /* same as SLC=1 */
275 L2_LRU, /* same as SLC=0 */
276 };
277
278 enum si_coherency
279 {
280 SI_COHERENCY_NONE, /* no cache flushes needed */
281 SI_COHERENCY_SHADER,
282 SI_COHERENCY_CB_META,
283 SI_COHERENCY_DB_META,
284 SI_COHERENCY_CP,
285 };
286
287 #define SI_BIND_CONSTANT_BUFFER_SHIFT 0
288 #define SI_BIND_SHADER_BUFFER_SHIFT 6
289 #define SI_BIND_IMAGE_BUFFER_SHIFT 12
290 #define SI_BIND_SAMPLER_BUFFER_SHIFT 18
291 #define SI_BIND_OTHER_BUFFER_SHIFT 24
292
293 /* Bind masks for all 6 shader stages. */
294 #define SI_BIND_CONSTANT_BUFFER_ALL (0x3f << SI_BIND_CONSTANT_BUFFER_SHIFT)
295 #define SI_BIND_SHADER_BUFFER_ALL (0x3f << SI_BIND_SHADER_BUFFER_SHIFT)
296 #define SI_BIND_IMAGE_BUFFER_ALL (0x3f << SI_BIND_IMAGE_BUFFER_SHIFT)
297 #define SI_BIND_SAMPLER_BUFFER_ALL (0x3f << SI_BIND_SAMPLER_BUFFER_SHIFT)
298
299 #define SI_BIND_CONSTANT_BUFFER(shader) ((1 << (shader)) << SI_BIND_CONSTANT_BUFFER_SHIFT)
300 #define SI_BIND_SHADER_BUFFER(shader) ((1 << (shader)) << SI_BIND_SHADER_BUFFER_SHIFT)
301 #define SI_BIND_IMAGE_BUFFER(shader) ((1 << (shader)) << SI_BIND_IMAGE_BUFFER_SHIFT)
302 #define SI_BIND_SAMPLER_BUFFER(shader) ((1 << (shader)) << SI_BIND_SAMPLER_BUFFER_SHIFT)
303 #define SI_BIND_VERTEX_BUFFER (1 << (SI_BIND_OTHER_BUFFER_SHIFT + 0))
304 #define SI_BIND_STREAMOUT_BUFFER (1 << (SI_BIND_OTHER_BUFFER_SHIFT + 1))
305
306 struct si_compute;
307 struct si_shader_context;
308 struct hash_table;
309
310 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
311 * at the moment.
312 */
313 struct si_resource {
314 struct threaded_resource b;
315
316 /* Winsys objects. */
317 struct pb_buffer *buf;
318 uint64_t gpu_address;
319 /* Memory usage if the buffer placement is optimal. */
320 uint32_t memory_usage_kb;
321
322 /* Resource properties. */
323 uint64_t bo_size;
324 uint8_t bo_alignment_log2;
325 enum radeon_bo_domain domains:8;
326 enum radeon_bo_flag flags:16;
327 unsigned bind_history; /* bitmask of SI_BIND_xxx_BUFFER */
328
329 /* The buffer range which is initialized (with a write transfer,
330 * streamout, DMA, or as a random access target). The rest of
331 * the buffer is considered invalid and can be mapped unsynchronized.
332 *
333 * This allows unsynchronized mapping of a buffer range which hasn't
334 * been used yet. It's for applications which forget to use
335 * the unsynchronized map flag and expect the driver to figure it out.
336 */
337 struct util_range valid_buffer_range;
338
339 /* For buffers only. This indicates that a write operation has been
340 * performed by TC L2, but the cache hasn't been flushed.
341 * Any hw block which doesn't use or bypasses TC L2 should check this
342 * flag and flush the cache before using the buffer.
343 *
344 * For example, TC L2 must be flushed if a buffer which has been
345 * modified by a shader store instruction is about to be used as
346 * an index buffer. The reason is that VGT DMA index fetching doesn't
347 * use TC L2.
348 */
349 bool TC_L2_dirty;
350
351 /* Whether this resource is referenced by bindless handles. */
352 bool texture_handle_allocated;
353 bool image_handle_allocated;
354
355 /* Whether the resource has been exported via resource_get_handle. */
356 uint8_t external_usage; /* PIPE_HANDLE_USAGE_* */
357 };
358
359 struct si_transfer {
360 struct threaded_transfer b;
361 struct si_resource *staging;
362 };
363
364 struct si_texture {
365 struct si_resource buffer;
366
367 struct radeon_surf surface;
368 struct si_texture *flushed_depth_texture;
369
370 /* One texture allocation can contain these buffers:
371 * - image (pixel data)
372 * - FMASK buffer (MSAA compression)
373 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
374 * - HTILE buffer (Z/S compression and fast Z/S clear)
375 * - DCC buffer (color compression and new fast color clear)
376 * - displayable DCC buffer (if the DCC buffer is not displayable)
377 */
378 uint64_t cmask_base_address_reg;
379 struct si_resource *cmask_buffer;
380 unsigned cb_color_info; /* fast clear enable bit */
381 unsigned color_clear_value[2];
382 unsigned last_msaa_resolve_target_micro_mode;
383 bool swap_rgb_to_bgr_on_next_clear;
384 bool swap_rgb_to_bgr;
385 unsigned num_level0_transfers;
386 unsigned plane_index; /* other planes are different pipe_resources */
387 unsigned num_planes;
388
389 /* Depth buffer compression and fast clear. */
390 float depth_clear_value[RADEON_SURF_MAX_LEVELS];
391 uint8_t stencil_clear_value[RADEON_SURF_MAX_LEVELS];
392 uint16_t depth_cleared_level_mask_once; /* if it was cleared at least once */
393 uint16_t depth_cleared_level_mask; /* track if it's cleared (can be false negative) */
394 uint16_t stencil_cleared_level_mask_once; /* if it was cleared at least once */
395 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
396 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
397 enum pipe_format db_render_format : 16;
398 bool fmask_is_identity : 1;
399 bool tc_compatible_htile : 1;
400 bool enable_tc_compatible_htile_next_clear : 1;
401 bool htile_stencil_disabled : 1;
402 bool upgraded_depth : 1; /* upgraded from unorm to Z32_FLOAT */
403 bool is_depth : 1;
404 bool db_compatible : 1;
405 bool can_sample_z : 1;
406 bool can_sample_s : 1;
407 bool need_flush_after_depth_decompression: 1;
408
409 /* We need to track DCC dirtiness, because st/dri usually calls
410 * flush_resource twice per frame (not a bug) and we don't wanna
411 * decompress DCC twice.
412 */
413 bool displayable_dcc_dirty : 1;
414
415 /* Counter that should be non-zero if the texture is bound to a
416 * framebuffer.
417 */
418 unsigned framebuffers_bound;
419 };
420
421 /* State trackers create separate textures in a next-chain for extra planes
422 * even if those are planes created purely for modifiers. Because the linking
423 * of the chain happens outside of the driver, and NULL is interpreted as
424 * failure, let's create some dummy texture structs. We could use these
425 * later to use the offsets for linking if we really wanted to.
426 *
427 * For now just create a dummy struct and completely ignore it.
428 *
429 * Potentially in the future we could store stride/offset and use it during
430 * creation, though we might want to change how linking is done first.
431 */
432 struct si_auxiliary_texture {
433 struct threaded_resource b;
434 struct pb_buffer *buffer;
435 uint32_t offset;
436 uint32_t stride;
437 };
438
439 struct si_surface {
440 struct pipe_surface base;
441
442 /* These can vary with block-compressed textures. */
443 uint16_t width0;
444 uint16_t height0;
445
446 bool color_initialized : 1;
447 bool depth_initialized : 1;
448
449 /* Misc. color flags. */
450 bool color_is_int8 : 1;
451 bool color_is_int10 : 1;
452 bool dcc_incompatible : 1;
453
454 /* Color registers. */
455 unsigned cb_color_info;
456 unsigned cb_color_view;
457 unsigned cb_color_attrib;
458 unsigned cb_color_attrib2; /* GFX9 and later */
459 unsigned cb_color_attrib3; /* GFX10 and later */
460 unsigned cb_dcc_control; /* GFX8 and later */
461 unsigned spi_shader_col_format : 8; /* no blending, no alpha-to-coverage. */
462 unsigned spi_shader_col_format_alpha : 8; /* alpha-to-coverage */
463 unsigned spi_shader_col_format_blend : 8; /* blending without alpha. */
464 unsigned spi_shader_col_format_blend_alpha : 8; /* blending with alpha. */
465
466 /* DB registers. */
467 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
468 uint64_t db_stencil_base;
469 uint64_t db_htile_data_base;
470 unsigned db_depth_info;
471 unsigned db_z_info;
472 unsigned db_z_info2; /* GFX9 only */
473 unsigned db_depth_view;
474 unsigned db_depth_size;
475 unsigned db_depth_slice;
476 unsigned db_stencil_info;
477 unsigned db_stencil_info2; /* GFX9 only */
478 unsigned db_htile_surface;
479 };
480
481 struct si_mmio_counter {
482 unsigned busy;
483 unsigned idle;
484 };
485
486 union si_mmio_counters {
487 struct si_mmio_counters_named {
488 /* For global GPU load including SDMA. */
489 struct si_mmio_counter gpu;
490
491 /* GRBM_STATUS */
492 struct si_mmio_counter spi;
493 struct si_mmio_counter gui;
494 struct si_mmio_counter ta;
495 struct si_mmio_counter gds;
496 struct si_mmio_counter vgt;
497 struct si_mmio_counter ia;
498 struct si_mmio_counter sx;
499 struct si_mmio_counter wd;
500 struct si_mmio_counter bci;
501 struct si_mmio_counter sc;
502 struct si_mmio_counter pa;
503 struct si_mmio_counter db;
504 struct si_mmio_counter cp;
505 struct si_mmio_counter cb;
506
507 /* SRBM_STATUS2 */
508 struct si_mmio_counter sdma;
509
510 /* CP_STAT */
511 struct si_mmio_counter pfp;
512 struct si_mmio_counter meq;
513 struct si_mmio_counter me;
514 struct si_mmio_counter surf_sync;
515 struct si_mmio_counter cp_dma;
516 struct si_mmio_counter scratch_ram;
517 } named;
518
519 unsigned array[sizeof(struct si_mmio_counters_named) / sizeof(unsigned)];
520 };
521
522 struct si_memory_object {
523 struct pipe_memory_object b;
524 struct pb_buffer *buf;
525 uint32_t stride;
526 };
527
528 /* Saved CS data for debugging features. */
529 struct radeon_saved_cs {
530 uint32_t *ib;
531 unsigned num_dw;
532
533 struct radeon_bo_list_item *bo_list;
534 unsigned bo_count;
535 };
536
537 struct si_screen {
538 struct pipe_screen b;
539 struct radeon_winsys *ws;
540 struct disk_cache *disk_shader_cache;
541
542 struct radeon_info info;
543 struct nir_shader_compiler_options nir_options;
544 uint64_t debug_flags;
545 char renderer_string[183];
546
547 void (*make_texture_descriptor)(struct si_screen *screen, struct si_texture *tex, bool sampler,
548 enum pipe_texture_target target, enum pipe_format pipe_format,
549 const unsigned char state_swizzle[4], unsigned first_level,
550 unsigned last_level, unsigned first_layer, unsigned last_layer,
551 unsigned width, unsigned height, unsigned depth, uint32_t *state,
552 uint32_t *fmask_state);
553
554 unsigned max_memory_usage_kb;
555 unsigned pa_sc_raster_config;
556 unsigned pa_sc_raster_config_1;
557 unsigned se_tile_repeat;
558 unsigned gs_table_depth;
559 unsigned tess_offchip_block_dw_size;
560 unsigned tess_offchip_ring_size;
561 unsigned tess_factor_ring_size;
562 unsigned vgt_hs_offchip_param;
563 unsigned eqaa_force_coverage_samples;
564 unsigned eqaa_force_z_samples;
565 unsigned eqaa_force_color_samples;
566 unsigned pbb_context_states_per_bin;
567 unsigned pbb_persistent_states_per_bin;
568 bool has_draw_indirect_multi;
569 bool has_out_of_order_rast;
570 bool assume_no_z_fights;
571 bool commutative_blend_add;
572 bool allow_draw_out_of_order;
573 bool dpbb_allowed;
574 bool use_ngg;
575 bool use_ngg_culling;
576 bool use_ngg_streamout;
577 bool allow_dcc_msaa_clear_to_reg_for_bpp[5]; /* indexed by log2(Bpp) */
578 bool always_allow_dcc_stores;
579
580 struct {
581 #define OPT_BOOL(name, dflt, description) bool name : 1;
582 #define OPT_INT(name, dflt, description) int name;
583 #include "si_debug_options.h"
584 } options;
585
586 /* Whether shaders are monolithic (1-part) or separate (3-part). */
587 bool use_monolithic_shaders;
588 bool record_llvm_ir;
589
590 struct slab_parent_pool pool_transfers;
591
592 /* Texture filter settings. */
593 int force_aniso; /* -1 = disabled */
594
595 /* Auxiliary context. Mainly used to initialize resources.
596 * It must be locked prior to using and flushed before unlocking. */
597 struct pipe_context *aux_context;
598 simple_mtx_t aux_context_lock;
599
600 /* Async compute context for DRI_PRIME copies. */
601 struct pipe_context *async_compute_context;
602 simple_mtx_t async_compute_context_lock;
603
604 /* This must be in the screen, because UE4 uses one context for
605 * compilation and another one for rendering.
606 */
607 unsigned num_compilations;
608 /* Along with ST_DEBUG=precompile, this should show if applications
609 * are loading shaders on demand. This is a monotonic counter.
610 */
611 unsigned num_shaders_created;
612 unsigned num_memory_shader_cache_hits;
613 unsigned num_memory_shader_cache_misses;
614 unsigned num_disk_shader_cache_hits;
615 unsigned num_disk_shader_cache_misses;
616
617 /* GPU load thread. */
618 simple_mtx_t gpu_load_mutex;
619 thrd_t gpu_load_thread;
620 union si_mmio_counters mmio_counters;
621 volatile unsigned gpu_load_stop_thread; /* bool */
622
623 /* Performance counters. */
624 struct si_perfcounters *perfcounters;
625
626 /* If pipe_screen wants to recompute and re-emit the framebuffer,
627 * sampler, and image states of all contexts, it should atomically
628 * increment this.
629 *
630 * Each context will compare this with its own last known value of
631 * the counter before drawing and re-emit the states accordingly.
632 */
633 unsigned dirty_tex_counter;
634 unsigned dirty_buf_counter;
635
636 /* Atomically increment this counter when an existing texture's
637 * metadata is enabled or disabled in a way that requires changing
638 * contexts' compressed texture binding masks.
639 */
640 unsigned compressed_colortex_counter;
641
642 struct {
643 /* Context flags to set so that all writes from earlier jobs
644 * in the CP are seen by L2 clients.
645 */
646 unsigned cp_to_L2;
647
648 /* Context flags to set so that all writes from earlier jobs
649 * that end in L2 are seen by CP.
650 */
651 unsigned L2_to_cp;
652 } barrier_flags;
653
654 simple_mtx_t shader_parts_mutex;
655 struct si_shader_part *vs_prologs;
656 struct si_shader_part *tcs_epilogs;
657 struct si_shader_part *ps_prologs;
658 struct si_shader_part *ps_epilogs;
659
660 /* Shader cache in memory.
661 *
662 * Design & limitations:
663 * - The shader cache is per screen (= per process), never saved to
664 * disk, and skips redundant shader compilations from NIR to bytecode.
665 * - It can only be used with one-variant-per-shader support, in which
666 * case only the main (typically middle) part of shaders is cached.
667 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
668 * variants of VS and TES are cached, so LS and ES aren't.
669 * - GS and CS aren't cached, but it's certainly possible to cache
670 * those as well.
671 */
672 simple_mtx_t shader_cache_mutex;
673 struct hash_table *shader_cache;
674 /* Maximum and current size */
675 uint32_t shader_cache_size;
676 uint32_t shader_cache_max_size;
677
678 /* Shader cache of live shaders. */
679 struct util_live_shader_cache live_shader_cache;
680
681 /* Shader compiler queue for multithreaded compilation. */
682 struct util_queue shader_compiler_queue;
683 /* Use at most 3 normal compiler threads on quadcore and better.
684 * Hyperthreaded CPUs report the number of threads, but we want
685 * the number of cores. We only need this many threads for shader-db. */
686 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
687
688 struct util_queue shader_compiler_queue_low_priority;
689 /* Use at most 2 low priority threads on quadcore and better.
690 * We want to minimize the impact on multithreaded Mesa. */
691 struct ac_llvm_compiler compiler_lowp[10];
692
693 unsigned ngg_subgroup_size;
694
695 struct util_idalloc_mt buffer_ids;
696 struct util_vertex_state_cache vertex_state_cache;
697 };
698
699 struct si_sampler_view {
700 struct pipe_sampler_view base;
701 /* [0..7] = image descriptor
702 * [4..7] = buffer descriptor */
703 uint32_t state[8];
704 uint32_t fmask_state[8];
705 const struct legacy_surf_level *base_level_info;
706 ubyte base_level;
707 ubyte block_width;
708 bool is_stencil_sampler;
709 bool dcc_incompatible;
710 };
711
712 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
713
714 struct si_sampler_state {
715 #ifndef NDEBUG
716 unsigned magic;
717 #endif
718 uint32_t val[4];
719 uint32_t upgraded_depth_val[4];
720 };
721
722 struct si_cs_shader_state {
723 struct si_compute *program;
724 struct si_compute *emitted_program;
725 unsigned offset;
726 bool initialized;
727 bool uses_scratch;
728 };
729
730 struct si_samplers {
731 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
732 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
733
734 /* The i-th bit is set if that element is enabled (non-NULL resource). */
735 unsigned enabled_mask;
736 uint32_t has_depth_tex_mask;
737 uint32_t needs_depth_decompress_mask;
738 uint32_t needs_color_decompress_mask;
739 };
740
741 struct si_images {
742 struct pipe_image_view views[SI_NUM_IMAGES];
743 uint32_t needs_color_decompress_mask;
744 unsigned enabled_mask;
745 unsigned display_dcc_store_mask;
746 };
747
748 struct si_framebuffer {
749 struct pipe_framebuffer_state state;
750 unsigned colorbuf_enabled_4bit;
751 unsigned spi_shader_col_format;
752 unsigned spi_shader_col_format_alpha;
753 unsigned spi_shader_col_format_blend;
754 unsigned spi_shader_col_format_blend_alpha;
755 ubyte nr_samples : 5; /* at most 16xAA */
756 ubyte log_samples : 3; /* at most 4 = 16xAA */
757 ubyte nr_color_samples; /* at most 8xAA */
758 ubyte compressed_cb_mask;
759 ubyte uncompressed_cb_mask;
760 ubyte color_is_int8;
761 ubyte color_is_int10;
762 ubyte dirty_cbufs;
763 ubyte dcc_overwrite_combiner_watermark;
764 ubyte min_bytes_per_pixel;
765 bool dirty_zsbuf;
766 bool any_dst_linear;
767 bool CB_has_shader_readable_metadata;
768 bool DB_has_shader_readable_metadata;
769 bool all_DCC_pipe_aligned;
770 bool has_dcc_msaa;
771 };
772
773 enum si_quant_mode
774 {
775 /* This is the list we want to support. */
776 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
777 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
778 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
779 };
780
781 struct si_signed_scissor {
782 int minx;
783 int miny;
784 int maxx;
785 int maxy;
786 enum si_quant_mode quant_mode;
787 };
788
789 struct si_viewports {
790 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
791 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
792 };
793
794 struct si_streamout_target {
795 struct pipe_stream_output_target b;
796
797 /* The buffer where BUFFER_FILLED_SIZE is stored. */
798 struct si_resource *buf_filled_size;
799 unsigned buf_filled_size_offset;
800 bool buf_filled_size_valid;
801
802 unsigned stride_in_dw;
803 };
804
805 struct si_streamout {
806 bool begin_emitted;
807
808 unsigned enabled_mask;
809 unsigned num_targets;
810 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
811
812 unsigned append_bitmask;
813 bool suspended;
814
815 /* External state which comes from the vertex shader,
816 * it must be set explicitly when binding a shader. */
817 uint16_t *stride_in_dw;
818 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
819
820 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
821 unsigned hw_enabled_mask;
822
823 /* The state of VGT_STRMOUT_(CONFIG|EN). */
824 bool streamout_enabled;
825 bool prims_gen_query_enabled;
826 int num_prims_gen_queries;
827 };
828
829 /* A shader state consists of the shader selector, which is a constant state
830 * object shared by multiple contexts and shouldn't be modified, and
831 * the current shader variant selected for this context.
832 */
833 struct si_shader_ctx_state {
834 struct si_shader_selector *cso;
835 struct si_shader *current;
836 /* The shader variant key representing the current state. */
837 union si_shader_key key;
838 };
839
840 #define SI_NUM_VGT_PARAM_KEY_BITS 12
841 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
842
843 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
844 * Some fields are set by state-change calls, most are set by draw_vbo.
845 */
846 union si_vgt_param_key {
847 struct {
848 #if UTIL_ARCH_LITTLE_ENDIAN
849 uint16_t prim : 4;
850 uint16_t uses_instancing : 1;
851 uint16_t multi_instances_smaller_than_primgroup : 1;
852 uint16_t primitive_restart : 1;
853 uint16_t count_from_stream_output : 1;
854 uint16_t line_stipple_enabled : 1;
855 uint16_t uses_tess : 1;
856 uint16_t tess_uses_prim_id : 1;
857 uint16_t uses_gs : 1;
858 uint16_t _pad : 16 - SI_NUM_VGT_PARAM_KEY_BITS;
859 #else /* UTIL_ARCH_BIG_ENDIAN */
860 uint16_t _pad : 16 - SI_NUM_VGT_PARAM_KEY_BITS;
861 uint16_t uses_gs : 1;
862 uint16_t tess_uses_prim_id : 1;
863 uint16_t uses_tess : 1;
864 uint16_t line_stipple_enabled : 1;
865 uint16_t count_from_stream_output : 1;
866 uint16_t primitive_restart : 1;
867 uint16_t multi_instances_smaller_than_primgroup : 1;
868 uint16_t uses_instancing : 1;
869 uint16_t prim : 4;
870 #endif
871 } u;
872 uint16_t index;
873 };
874
875 struct si_texture_handle {
876 unsigned desc_slot;
877 bool desc_dirty;
878 struct pipe_sampler_view *view;
879 struct si_sampler_state sstate;
880 };
881
882 struct si_image_handle {
883 unsigned desc_slot;
884 bool desc_dirty;
885 struct pipe_image_view view;
886 };
887
888 struct si_saved_cs {
889 struct pipe_reference reference;
890 struct si_context *ctx;
891 struct radeon_saved_cs gfx;
892 struct radeon_saved_cs compute;
893 struct si_resource *trace_buf;
894 unsigned trace_id;
895
896 unsigned gfx_last_dw;
897 bool flushed;
898 int64_t time_flush;
899 };
900
901 struct si_small_prim_cull_info {
902 float scale[2], translate[2];
903 float scale_no_aa[2], translate_no_aa[2];
904 float clip_half_line_width[2]; /* line_width * 0.5 in clip space in X and Y directions */
905 float small_prim_precision_no_aa; /* same as the small prim precision, but ignores MSAA */
906 /* The above fields are uploaded to memory. The below fields are passed via user SGPRs. */
907 float small_prim_precision;
908 };
909
910 struct si_vertex_state {
911 struct pipe_vertex_state b;
912 struct si_vertex_elements velems;
913 uint32_t descriptors[4 * SI_MAX_ATTRIBS];
914 };
915
916 typedef void (*pipe_draw_vbo_func)(struct pipe_context *pipe,
917 const struct pipe_draw_info *info,
918 unsigned drawid_offset,
919 const struct pipe_draw_indirect_info *indirect,
920 const struct pipe_draw_start_count_bias *draws,
921 unsigned num_draws);
922 typedef void (*pipe_draw_vertex_state_func)(struct pipe_context *ctx,
923 struct pipe_vertex_state *vstate,
924 uint32_t partial_velem_mask,
925 struct pipe_draw_vertex_state_info info,
926 const struct pipe_draw_start_count_bias *draws,
927 unsigned num_draws);
928
929 struct si_context {
930 struct pipe_context b; /* base class */
931
932 enum radeon_family family;
933 enum chip_class chip_class;
934
935 struct radeon_winsys *ws;
936 struct radeon_winsys_ctx *ctx;
937 struct radeon_cmdbuf gfx_cs; /* compute IB if graphics is disabled */
938 struct radeon_cmdbuf *sdma_cs;
939 struct pipe_fence_handle *last_gfx_fence;
940 struct si_resource *eop_bug_scratch;
941 struct si_resource *eop_bug_scratch_tmz;
942 struct u_upload_mgr *cached_gtt_allocator;
943 struct threaded_context *tc;
944 struct u_suballocator allocator_zeroed_memory;
945 struct slab_child_pool pool_transfers;
946 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
947 struct pipe_device_reset_callback device_reset_callback;
948 struct u_log_context *log;
949 void *query_result_shader;
950 void *sh_query_result_shader;
951 struct si_resource *shadowed_regs;
952
953 void (*emit_cache_flush)(struct si_context *ctx, struct radeon_cmdbuf *cs);
954
955 struct blitter_context *blitter;
956 void *noop_blend;
957 void *noop_dsa;
958 void *no_velems_state;
959 void *discard_rasterizer_state;
960 void *custom_dsa_flush;
961 void *custom_blend_resolve;
962 void *custom_blend_fmask_decompress;
963 void *custom_blend_eliminate_fastclear;
964 void *custom_blend_dcc_decompress;
965 void *vs_blit_pos;
966 void *vs_blit_pos_layered;
967 void *vs_blit_color;
968 void *vs_blit_color_layered;
969 void *vs_blit_texcoord;
970 void *cs_clear_buffer;
971 void *cs_clear_buffer_rmw;
972 void *cs_copy_buffer;
973 void *cs_copy_image_1D;
974 void *cs_copy_image_2D;
975 void *cs_clear_render_target;
976 void *cs_clear_render_target_1d_array;
977 void *cs_clear_12bytes_buffer;
978 void *cs_dcc_decompress;
979 void *cs_dcc_retile[32];
980 void *cs_fmask_expand[3][2]; /* [log2(samples)-1][is_array] */
981 struct si_screen *screen;
982 struct pipe_debug_callback debug;
983 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
984 struct si_shader_ctx_state fixed_func_tcs_shader;
985 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
986 struct si_resource *wait_mem_scratch;
987 struct si_resource *wait_mem_scratch_tmz;
988 unsigned wait_mem_number;
989 uint16_t prefetch_L2_mask;
990
991 bool blitter_running;
992 bool in_update_ps_colorbuf0_slot;
993 bool is_noop:1;
994 bool has_graphics:1;
995 bool gfx_flush_in_progress : 1;
996 bool gfx_last_ib_is_busy : 1;
997 bool compute_is_busy : 1;
998 int8_t pipeline_stats_enabled; /* -1 = unknown, 0 = disabled, 1 = enabled */
999
1000 unsigned num_gfx_cs_flushes;
1001 unsigned initial_gfx_cs_size;
1002 unsigned last_dirty_tex_counter;
1003 unsigned last_dirty_buf_counter;
1004 unsigned last_compressed_colortex_counter;
1005 unsigned last_num_draw_calls;
1006 unsigned flags; /* flush flags */
1007 /* Current unaccounted memory usage. */
1008 uint32_t memory_usage_kb;
1009
1010 /* NGG streamout. */
1011 struct pb_buffer *gds;
1012 struct pb_buffer *gds_oa;
1013
1014 /* Atoms (direct states). */
1015 union si_state_atoms atoms;
1016 unsigned dirty_atoms; /* mask */
1017 /* PM4 states (precomputed immutable states) */
1018 unsigned dirty_states;
1019 union si_state queued;
1020 union si_state emitted;
1021
1022 /* Atom declarations. */
1023 struct si_framebuffer framebuffer;
1024 unsigned sample_locs_num_samples;
1025 uint16_t sample_mask;
1026 unsigned last_cb_target_mask;
1027 struct pipe_blend_color blend_color;
1028 struct pipe_clip_state clip_state;
1029 struct si_shader_data shader_pointers;
1030 struct si_stencil_ref stencil_ref;
1031 bool blend_color_any_nonzeros:1;
1032 bool clip_state_any_nonzeros:1;
1033 bool viewport0_y_inverted;
1034 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
1035 struct si_streamout streamout;
1036 struct si_viewports viewports;
1037 unsigned num_window_rectangles;
1038 bool window_rectangles_include;
1039 struct pipe_scissor_state window_rectangles[4];
1040
1041 /* Precomputed states. */
1042 struct si_pm4_state *cs_preamble_state;
1043 struct si_pm4_state *cs_preamble_tess_rings;
1044 struct si_pm4_state *cs_preamble_tess_rings_tmz;
1045 struct si_pm4_state *cs_preamble_gs_rings;
1046 bool cs_preamble_has_vgt_flush;
1047 struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
1048
1049 /* shaders */
1050 union {
1051 struct {
1052 struct si_shader_ctx_state vs;
1053 struct si_shader_ctx_state ps;
1054 struct si_shader_ctx_state gs;
1055 struct si_shader_ctx_state tcs;
1056 struct si_shader_ctx_state tes;
1057 } shader;
1058 /* indexed access using pipe_shader_type (not by MESA_SHADER_*) */
1059 struct si_shader_ctx_state shaders[SI_NUM_GRAPHICS_SHADERS];
1060 };
1061 struct si_cs_shader_state cs_shader_state;
1062
1063 /* shader information */
1064 uint64_t ps_inputs_read_or_disabled;
1065 struct si_vertex_elements *vertex_elements;
1066 unsigned num_vertex_elements;
1067 unsigned cs_max_waves_per_sh;
1068 bool uses_nontrivial_vs_prolog;
1069 bool force_trivial_vs_prolog;
1070 bool do_update_shaders;
1071 bool compute_shaderbuf_sgprs_dirty;
1072 bool compute_image_sgprs_dirty;
1073 bool vs_uses_base_instance;
1074 bool vs_uses_draw_id;
1075 uint8_t patch_vertices;
1076
1077 /* shader descriptors */
1078 struct si_descriptors descriptors[SI_NUM_DESCS];
1079 unsigned descriptors_dirty;
1080 unsigned shader_pointers_dirty;
1081 unsigned shader_needs_decompress_mask;
1082 unsigned shader_has_depth_tex;
1083 struct si_buffer_resources internal_bindings;
1084 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1085 struct si_samplers samplers[SI_NUM_SHADERS];
1086 struct si_images images[SI_NUM_SHADERS];
1087 bool bo_list_add_all_resident_resources;
1088 bool bo_list_add_all_gfx_resources;
1089 bool bo_list_add_all_compute_resources;
1090
1091 /* other shader resources */
1092 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1093 struct pipe_resource *esgs_ring;
1094 struct pipe_resource *gsvs_ring;
1095 struct pipe_resource *tess_rings;
1096 struct pipe_resource *tess_rings_tmz;
1097 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1098 struct si_resource *border_color_buffer;
1099 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1100 unsigned border_color_count;
1101 unsigned num_vs_blit_sgprs;
1102 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
1103 uint32_t cs_user_data[4];
1104
1105 /* Vertex buffers. */
1106 bool vertex_buffers_dirty;
1107 bool vertex_buffer_pointer_dirty;
1108 bool vertex_buffer_user_sgprs_dirty;
1109 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1110 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1111 uint32_t *vb_descriptors_gpu_list;
1112 struct si_resource *vb_descriptors_buffer;
1113 unsigned vb_descriptors_offset;
1114 unsigned vb_descriptor_user_sgprs[5 * 4];
1115
1116 /* MSAA config state. */
1117 int ps_iter_samples;
1118 bool ps_uses_fbfetch;
1119 bool smoothing_enabled;
1120
1121 /* DB render state. */
1122 unsigned ps_db_shader_control;
1123 unsigned dbcb_copy_sample;
1124 bool dbcb_depth_copy_enabled : 1;
1125 bool dbcb_stencil_copy_enabled : 1;
1126 bool db_flush_depth_inplace : 1;
1127 bool db_flush_stencil_inplace : 1;
1128 bool db_depth_clear : 1;
1129 bool db_depth_disable_expclear : 1;
1130 bool db_stencil_clear : 1;
1131 bool db_stencil_disable_expclear : 1;
1132 bool occlusion_queries_disabled : 1;
1133 bool generate_mipmap_for_depth : 1;
1134 bool allow_flat_shading : 1;
1135
1136 /* Emitted draw state. */
1137 bool ngg : 1;
1138 uint16_t ngg_culling;
1139 unsigned last_index_size;
1140 int last_base_vertex;
1141 unsigned last_start_instance;
1142 unsigned last_instance_count;
1143 unsigned last_drawid;
1144 unsigned last_sh_base_reg;
1145 int last_primitive_restart_en;
1146 unsigned last_restart_index;
1147 unsigned last_prim;
1148 unsigned last_multi_vgt_param;
1149 unsigned last_gs_out_prim;
1150 unsigned current_vs_state;
1151 unsigned last_vs_state;
1152 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
1153
1154 struct si_small_prim_cull_info last_small_prim_cull_info;
1155 struct si_resource *small_prim_cull_info_buf;
1156 uint64_t small_prim_cull_info_address;
1157
1158 /* Scratch buffer */
1159 struct si_resource *scratch_buffer;
1160 unsigned scratch_waves;
1161 unsigned spi_tmpring_size;
1162 unsigned max_seen_scratch_bytes_per_wave;
1163 unsigned max_seen_compute_scratch_bytes_per_wave;
1164
1165 struct si_resource *compute_scratch_buffer;
1166
1167 /* Emitted derived tessellation state. */
1168 /* Local shader (VS), or HS if LS-HS are merged. */
1169 struct si_shader *last_ls;
1170 struct si_shader_selector *last_tcs;
1171 unsigned last_num_tcs_input_cp;
1172 unsigned last_tes_sh_base;
1173 bool last_tess_uses_primid;
1174 unsigned last_num_patches;
1175 unsigned last_ls_hs_config;
1176
1177 /* Debug state. */
1178 bool is_debug;
1179 struct si_saved_cs *current_saved_cs;
1180 uint64_t dmesg_timestamp;
1181 unsigned apitrace_call_number;
1182
1183 /* Other state */
1184 bool need_check_render_feedback;
1185 bool decompression_enabled;
1186 bool dpbb_force_off;
1187 bool dpbb_force_off_profile_vs;
1188 bool dpbb_force_off_profile_ps;
1189 bool vs_writes_viewport_index;
1190 bool vs_disables_clipping_viewport;
1191
1192 /* Precomputed IA_MULTI_VGT_PARAM */
1193 union si_vgt_param_key ia_multi_vgt_param_key;
1194 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1195
1196 /* Bindless descriptors. */
1197 struct si_descriptors bindless_descriptors;
1198 struct util_idalloc bindless_used_slots;
1199 unsigned num_bindless_descriptors;
1200 bool bindless_descriptors_dirty;
1201 bool graphics_bindless_pointer_dirty;
1202 bool compute_bindless_pointer_dirty;
1203
1204 /* Allocated bindless handles */
1205 struct hash_table *tex_handles;
1206 struct hash_table *img_handles;
1207
1208 /* Resident bindless handles */
1209 struct util_dynarray resident_tex_handles;
1210 struct util_dynarray resident_img_handles;
1211
1212 /* Resident bindless handles which need decompression */
1213 struct util_dynarray resident_tex_needs_color_decompress;
1214 struct util_dynarray resident_img_needs_color_decompress;
1215 struct util_dynarray resident_tex_needs_depth_decompress;
1216
1217 /* Bindless state */
1218 bool uses_bindless_samplers;
1219 bool uses_bindless_images;
1220
1221 /* MSAA sample locations.
1222 * The first index is the sample index.
1223 * The second index is the coordinate: X, Y. */
1224 struct {
1225 float x1[1][2];
1226 float x2[2][2];
1227 float x4[4][2];
1228 float x8[8][2];
1229 float x16[16][2];
1230 } sample_positions;
1231 struct pipe_resource *sample_pos_buffer;
1232
1233 /* Misc stats. */
1234 unsigned num_draw_calls;
1235 unsigned num_decompress_calls;
1236 unsigned num_prim_restart_calls;
1237 unsigned num_compute_calls;
1238 unsigned num_cp_dma_calls;
1239 unsigned num_vs_flushes;
1240 unsigned num_ps_flushes;
1241 unsigned num_cs_flushes;
1242 unsigned num_cb_cache_flushes;
1243 unsigned num_db_cache_flushes;
1244 unsigned num_L2_invalidates;
1245 unsigned num_L2_writebacks;
1246 unsigned num_resident_handles;
1247 uint64_t num_alloc_tex_transfer_bytes;
1248 unsigned last_tex_ps_draw_ratio; /* for query */
1249 unsigned context_roll;
1250
1251 /* Queries. */
1252 /* Maintain the list of active queries for pausing between IBs. */
1253 int num_occlusion_queries;
1254 int num_perfect_occlusion_queries;
1255 int num_pipeline_stat_queries;
1256 struct list_head active_queries;
1257 unsigned num_cs_dw_queries_suspend;
1258
1259 /* Render condition. */
1260 struct pipe_query *render_cond;
1261 unsigned render_cond_mode;
1262 bool render_cond_invert;
1263 bool render_cond_enabled; /* for u_blitter */
1264
1265 /* Shader-based queries. */
1266 struct list_head shader_query_buffers;
1267 unsigned num_active_shader_queries;
1268
1269 bool force_cb_shader_coherent;
1270
1271 struct si_tracked_regs tracked_regs;
1272
1273 /* Resources that need to be flushed, but will not get an explicit
1274 * flush_resource from the frontend and that will need to get flushed during
1275 * a context flush.
1276 */
1277 struct hash_table *dirty_implicit_resources;
1278
1279 pipe_draw_vbo_func draw_vbo[2][2][2];
1280 pipe_draw_vertex_state_func draw_vertex_state[2][2][2];
1281 /* When b.draw_vbo is a wrapper, real_draw_vbo is the real draw_vbo function */
1282 pipe_draw_vbo_func real_draw_vbo;
1283 pipe_draw_vertex_state_func real_draw_vertex_state;
1284 void (*emit_spi_map[33])(struct si_context *sctx);
1285
1286 /* SQTT */
1287 struct ac_thread_trace_data *thread_trace;
1288 struct pipe_fence_handle *last_sqtt_fence;
1289 enum rgp_sqtt_marker_event_type sqtt_next_event;
1290 bool thread_trace_enabled;
1291
1292 unsigned context_flags;
1293
1294 /* Shaders. */
1295 /* TODO: move other shaders here too */
1296 /* Only used for DCC MSAA clears with 4-8 fragments and 4-16 samples. */
1297 void *cs_clear_dcc_msaa[32][5][2][3][2]; /* [swizzle_mode][log2(bpe)][fragments == 8][log2(samples)-2][is_array] */
1298 };
1299
1300 /* si_blit.c */
1301 enum si_blitter_op /* bitmask */
1302 {
1303 SI_SAVE_TEXTURES = 1,
1304 SI_SAVE_FRAMEBUFFER = 2,
1305 SI_SAVE_FRAGMENT_STATE = 4,
1306 SI_DISABLE_RENDER_COND = 8,
1307 };
1308
1309 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1310 void si_blitter_end(struct si_context *sctx);
1311 void si_init_blit_functions(struct si_context *sctx);
1312 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1313 void si_decompress_subresource(struct pipe_context *ctx, struct pipe_resource *tex, unsigned planes,
1314 unsigned level, unsigned first_layer, unsigned last_layer);
1315 void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst,
1316 unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
1317 struct pipe_resource *src, unsigned src_level,
1318 const struct pipe_box *src_box);
1319 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1320 void si_flush_implicit_resources(struct si_context *sctx);
1321
1322 /* si_nir_optim.c */
1323 bool si_nir_is_output_const_if_tex_is_const(nir_shader *shader, float *in, float *out, int *texunit);
1324
1325 /* si_buffer.c */
1326 bool si_cs_is_buffer_referenced(struct si_context *sctx, struct pb_buffer *buf,
1327 unsigned usage);
1328 void *si_buffer_map(struct si_context *sctx, struct si_resource *resource,
1329 unsigned usage);
1330 void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size,
1331 unsigned alignment);
1332 bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res);
1333 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
1334 unsigned usage, unsigned size, unsigned alignment);
1335 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
1336 unsigned usage, unsigned size, unsigned alignment);
1337 struct pipe_resource *si_buffer_from_winsys_buffer(struct pipe_screen *screen,
1338 const struct pipe_resource *templ,
1339 struct pb_buffer *imported_buf,
1340 uint64_t offset);
1341 void si_replace_buffer_storage(struct pipe_context *ctx, struct pipe_resource *dst,
1342 struct pipe_resource *src, unsigned num_rebinds,
1343 uint32_t rebind_mask, uint32_t delete_buffer_id);
1344 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1345 void si_init_buffer_functions(struct si_context *sctx);
1346
1347 /* si_clear.c */
1348 #define SI_CLEAR_TYPE_CMASK (1 << 0)
1349 #define SI_CLEAR_TYPE_DCC (1 << 1)
1350 #define SI_CLEAR_TYPE_HTILE (1 << 2)
1351
1352 struct si_clear_info {
1353 struct pipe_resource *resource;
1354 uint64_t offset;
1355 uint32_t size;
1356 uint32_t clear_value;
1357 uint32_t writemask;
1358 bool is_dcc_msaa; /* Clear it as a DCC MSAA image. */
1359 };
1360
1361 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1362 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1363 bool vi_dcc_get_clear_info(struct si_context *sctx, struct si_texture *tex, unsigned level,
1364 unsigned clear_value, struct si_clear_info *out);
1365 void si_init_buffer_clear(struct si_clear_info *info,
1366 struct pipe_resource *resource, uint64_t offset,
1367 uint32_t size, uint32_t clear_value);
1368 void si_execute_clears(struct si_context *sctx, struct si_clear_info *info,
1369 unsigned num_clears, unsigned types);
1370 void si_init_clear_functions(struct si_context *sctx);
1371
1372 /* si_compute_blit.c */
1373 #define SI_OP_SYNC_CS_BEFORE (1 << 0)
1374 #define SI_OP_SYNC_PS_BEFORE (1 << 1)
1375 #define SI_OP_SYNC_CPDMA_BEFORE (1 << 2) /* only affects CP DMA calls */
1376 #define SI_OP_SYNC_BEFORE (SI_OP_SYNC_CS_BEFORE | SI_OP_SYNC_PS_BEFORE | SI_OP_SYNC_CPDMA_BEFORE)
1377 #define SI_OP_SYNC_AFTER (1 << 3)
1378 #define SI_OP_SYNC_BEFORE_AFTER (SI_OP_SYNC_BEFORE | SI_OP_SYNC_AFTER)
1379 #define SI_OP_SKIP_CACHE_INV_BEFORE (1 << 4) /* don't invalidate caches */
1380 #define SI_OP_CS_IMAGE (1 << 5)
1381 #define SI_OP_CS_RENDER_COND_ENABLE (1 << 6)
1382 #define SI_OP_CPDMA_SKIP_CHECK_CS_SPACE (1 << 7) /* don't call need_cs_space */
1383 #define SI_OP_SYNC_GE_BEFORE (1 << 8) /* only sync VS, TCS, TES, GS */
1384
1385 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1386 enum si_cache_policy cache_policy);
1387 void si_launch_grid_internal(struct si_context *sctx, struct pipe_grid_info *info,
1388 void *shader, unsigned flags);
1389 void si_launch_grid_internal_ssbos(struct si_context *sctx, struct pipe_grid_info *info,
1390 void *shader, unsigned flags, enum si_coherency coher,
1391 unsigned num_buffers, const struct pipe_shader_buffer *buffers,
1392 unsigned writeable_bitmask);
1393 enum si_clear_method {
1394 SI_CP_DMA_CLEAR_METHOD,
1395 SI_COMPUTE_CLEAR_METHOD,
1396 SI_AUTO_SELECT_CLEAR_METHOD
1397 };
1398 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1399 uint64_t offset, uint64_t size, uint32_t *clear_value,
1400 uint32_t clear_value_size, unsigned flags,
1401 enum si_coherency coher, enum si_clear_method method);
1402 void si_compute_clear_buffer_rmw(struct si_context *sctx, struct pipe_resource *dst,
1403 unsigned dst_offset, unsigned size,
1404 uint32_t clear_value, uint32_t writebitmask,
1405 unsigned flags, enum si_coherency coher);
1406 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst, uint64_t offset,
1407 uint64_t size, unsigned value, unsigned flags);
1408 void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
1409 uint64_t dst_offset, uint64_t src_offset, unsigned size, unsigned flags);
1410 void si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, unsigned dst_level,
1411 struct pipe_resource *src, unsigned src_level, unsigned dstx,
1412 unsigned dsty, unsigned dstz, const struct pipe_box *src_box,
1413 bool is_dcc_decompress, unsigned flags);
1414 void si_compute_clear_render_target(struct pipe_context *ctx, struct pipe_surface *dstsurf,
1415 const union pipe_color_union *color, unsigned dstx,
1416 unsigned dsty, unsigned width, unsigned height,
1417 bool render_condition_enabled);
1418 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1419 void gfx9_clear_dcc_msaa(struct si_context *sctx, struct pipe_resource *res, uint32_t clear_value,
1420 unsigned flags, enum si_coherency coher);
1421 void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex);
1422 void si_init_compute_blit_functions(struct si_context *sctx);
1423
1424 /* si_cp_dma.c */
1425 void si_cp_dma_wait_for_idle(struct si_context *sctx, struct radeon_cmdbuf *cs);
1426 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1427 struct pipe_resource *dst, uint64_t offset, uint64_t size,
1428 unsigned value, unsigned user_flags, enum si_coherency coher,
1429 enum si_cache_policy cache_policy);
1430 void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
1431 struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset,
1432 unsigned size, unsigned user_flags, enum si_coherency coher,
1433 enum si_cache_policy cache_policy);
1434 void si_cp_dma_prefetch(struct si_context *sctx, struct pipe_resource *buf,
1435 unsigned offset, unsigned size);
1436 void si_test_gds(struct si_context *sctx);
1437 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset,
1438 unsigned size, unsigned dst_sel, unsigned engine, const void *data);
1439 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,
1440 struct si_resource *dst, unsigned dst_offset, unsigned src_sel,
1441 struct si_resource *src, unsigned src_offset);
1442
1443 /* si_cp_reg_shadowing.c */
1444 void si_init_cp_reg_shadowing(struct si_context *sctx);
1445
1446 /* si_debug.c */
1447 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved,
1448 bool get_buffer_list);
1449 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1450 void si_destroy_saved_cs(struct si_saved_cs *scs);
1451 void si_auto_log_cs(void *data, struct u_log_context *log);
1452 void si_log_hw_flush(struct si_context *sctx);
1453 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1454 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1455 void si_init_debug_functions(struct si_context *sctx);
1456 void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved,
1457 enum ring_type ring);
1458 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1459 void si_print_current_ib(struct si_context *sctx, FILE *f);
1460
1461 /* si_fence.c */
1462 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigned event,
1463 unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1464 struct si_resource *buf, uint64_t va, uint32_t new_fence,
1465 unsigned query_type);
1466 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1467 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, uint64_t va, uint32_t ref,
1468 uint32_t mask, unsigned flags);
1469 void si_init_fence_functions(struct si_context *ctx);
1470 void si_init_screen_fence_functions(struct si_screen *screen);
1471 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1472 struct tc_unflushed_batch_token *tc_token);
1473
1474 /* si_get.c */
1475 void si_init_screen_get_functions(struct si_screen *sscreen);
1476
1477 bool si_sdma_copy_image(struct si_context *ctx, struct si_texture *dst, struct si_texture *src);
1478
1479 /* si_gfx_cs.c */
1480 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_handle **fence);
1481 void si_allocate_gds(struct si_context *ctx);
1482 void si_set_tracked_regs_to_clear_state(struct si_context *ctx);
1483 void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs);
1484 void si_trace_emit(struct si_context *sctx);
1485 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
1486 unsigned cp_coher_cntl);
1487 void gfx10_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs);
1488 void si_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs);
1489 /* Replace the sctx->b.draw_vbo function with a wrapper. This can be use to implement
1490 * optimizations without affecting the normal draw_vbo functions perf.
1491 */
1492 void si_install_draw_wrapper(struct si_context *sctx, pipe_draw_vbo_func wrapper,
1493 pipe_draw_vertex_state_func vstate_wrapper);
1494
1495 /* si_gpu_load.c */
1496 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1497 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1498 unsigned si_end_counter(struct si_screen *sscreen, unsigned type, uint64_t begin);
1499
1500 /* si_compute.c */
1501 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1502 void si_init_compute_functions(struct si_context *sctx);
1503
1504 /* si_pipe.c */
1505 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler);
1506 void si_init_aux_async_compute_ctx(struct si_screen *sscreen);
1507
1508 /* si_perfcounters.c */
1509 void si_init_perfcounters(struct si_screen *screen);
1510 void si_destroy_perfcounters(struct si_screen *screen);
1511 void si_inhibit_clockgating(struct si_context *sctx, struct radeon_cmdbuf *cs, bool inhibit);
1512
1513 /* si_query.c */
1514 void si_init_screen_query_functions(struct si_screen *sscreen);
1515 void si_init_query_functions(struct si_context *sctx);
1516 void si_suspend_queries(struct si_context *sctx);
1517 void si_resume_queries(struct si_context *sctx);
1518
1519 /* si_shaderlib_nir.c */
1520 void *si_create_copy_image_cs(struct si_context *sctx, bool is_1D);
1521 void *si_create_dcc_retile_cs(struct si_context *sctx, struct radeon_surf *surf);
1522 void *gfx9_create_clear_dcc_msaa_cs(struct si_context *sctx, struct si_texture *tex);
1523
1524 /* si_shaderlib_tgsi.c */
1525 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1526 unsigned num_layers);
1527 void *si_create_fixed_func_tcs(struct si_context *sctx);
1528 void *si_create_dma_compute_shader(struct pipe_context *ctx, unsigned num_dwords_per_thread,
1529 bool dst_stream_cache_policy, bool is_copy);
1530 void *si_create_clear_buffer_rmw_cs(struct si_context *sctx);
1531 void *si_create_dcc_decompress_cs(struct pipe_context *ctx);
1532 void *si_clear_render_target_shader(struct pipe_context *ctx);
1533 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1534 void *si_clear_12bytes_buffer_shader(struct pipe_context *ctx);
1535 void *si_create_fmask_expand_cs(struct pipe_context *ctx, unsigned num_samples, bool is_array);
1536 void *si_create_query_result_cs(struct si_context *sctx);
1537 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1538
1539 /* gfx10_query.c */
1540 void gfx10_init_query(struct si_context *sctx);
1541 void gfx10_destroy_query(struct si_context *sctx);
1542
1543 /* si_test_blit.c */
1544 void si_test_blit(struct si_screen *sscreen);
1545
1546 /* si_test_clearbuffer.c */
1547 void si_test_dma_perf(struct si_screen *sscreen);
1548
1549 /* si_uvd.c */
1550 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1551 const struct pipe_video_codec *templ);
1552
1553 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1554 const struct pipe_video_buffer *tmpl);
1555 struct pipe_video_buffer *si_video_buffer_create_with_modifiers(struct pipe_context *pipe,
1556 const struct pipe_video_buffer *tmpl,
1557 const uint64_t *modifiers,
1558 unsigned int modifiers_count);
1559
1560 /* si_viewport.c */
1561 void si_update_vs_viewport_state(struct si_context *ctx);
1562 void si_init_viewport_functions(struct si_context *ctx);
1563
1564 /* si_texture.c */
1565 void si_eliminate_fast_color_clear(struct si_context *sctx, struct si_texture *tex,
1566 bool *ctx_flushed);
1567 void si_texture_discard_cmask(struct si_screen *sscreen, struct si_texture *tex);
1568 bool si_init_flushed_depth_texture(struct pipe_context *ctx, struct pipe_resource *texture);
1569 void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
1570 struct u_log_context *log);
1571 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1572 const struct pipe_resource *templ);
1573 bool si_texture_commit(struct si_context *ctx, struct si_resource *res, unsigned level,
1574 struct pipe_box *box, bool commit);
1575 bool vi_dcc_formats_compatible(struct si_screen *sscreen, enum pipe_format format1,
1576 enum pipe_format format2);
1577 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex, unsigned level,
1578 enum pipe_format view_format);
1579 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx, struct pipe_resource *tex,
1580 unsigned level, enum pipe_format view_format);
1581 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1582 struct pipe_resource *texture,
1583 const struct pipe_surface *templ, unsigned width0,
1584 unsigned height0, unsigned width, unsigned height);
1585 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1586 bool si_texture_disable_dcc(struct si_context *sctx, struct si_texture *tex);
1587 void si_init_screen_texture_functions(struct si_screen *sscreen);
1588 void si_init_context_texture_functions(struct si_context *sctx);
1589
1590 /* si_sqtt.c */
1591 void si_sqtt_write_event_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
1592 enum rgp_sqtt_marker_event_type api_type,
1593 uint32_t vertex_offset_user_data,
1594 uint32_t instance_offset_user_data,
1595 uint32_t draw_index_user_data);
1596 bool si_sqtt_register_pipeline(struct si_context* sctx, uint64_t pipeline_hash, uint64_t base_address, bool is_compute);
1597 bool si_sqtt_pipeline_is_registered(struct ac_thread_trace_data *thread_trace_data,
1598 uint64_t pipeline_hash);
1599 void si_sqtt_describe_pipeline_bind(struct si_context* sctx, uint64_t pipeline_hash, int bind_point);
1600 void
1601 si_write_event_with_dims_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
1602 enum rgp_sqtt_marker_event_type api_type,
1603 uint32_t x, uint32_t y, uint32_t z);
1604 void
1605 si_write_user_event(struct si_context* sctx, struct radeon_cmdbuf *rcs,
1606 enum rgp_sqtt_marker_user_event_type type,
1607 const char *str, int len);
1608 void
1609 si_sqtt_describe_barrier_start(struct si_context* sctx, struct radeon_cmdbuf *rcs);
1610 void
1611 si_sqtt_describe_barrier_end(struct si_context* sctx, struct radeon_cmdbuf *rcs, unsigned flags);
1612 bool si_init_thread_trace(struct si_context *sctx);
1613 void si_destroy_thread_trace(struct si_context *sctx);
1614 void si_handle_thread_trace(struct si_context *sctx, struct radeon_cmdbuf *rcs);
1615
1616 /*
1617 * common helpers
1618 */
1619
si_resource(struct pipe_resource * r)1620 static inline struct si_resource *si_resource(struct pipe_resource *r)
1621 {
1622 return (struct si_resource *)r;
1623 }
1624
si_resource_reference(struct si_resource ** ptr,struct si_resource * res)1625 static inline void si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1626 {
1627 pipe_resource_reference((struct pipe_resource **)ptr, (struct pipe_resource *)res);
1628 }
1629
si_texture_reference(struct si_texture ** ptr,struct si_texture * res)1630 static inline void si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1631 {
1632 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1633 }
1634
1635 static inline void
si_shader_selector_reference(struct si_context * sctx,struct si_shader_selector ** dst,struct si_shader_selector * src)1636 si_shader_selector_reference(struct si_context *sctx, /* sctx can optionally be NULL */
1637 struct si_shader_selector **dst, struct si_shader_selector *src)
1638 {
1639 if (*dst == src)
1640 return;
1641
1642 struct si_screen *sscreen = src ? src->screen : (*dst)->screen;
1643 util_shader_reference(&sctx->b, &sscreen->live_shader_cache, (void **)dst, src);
1644 }
1645
vi_dcc_enabled(struct si_texture * tex,unsigned level)1646 static inline bool vi_dcc_enabled(struct si_texture *tex, unsigned level)
1647 {
1648 return !tex->is_depth && tex->surface.meta_offset && level < tex->surface.num_meta_levels;
1649 }
1650
si_tile_mode_index(struct si_texture * tex,unsigned level,bool stencil)1651 static inline unsigned si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1652 {
1653 if (stencil)
1654 return tex->surface.u.legacy.zs.stencil_tiling_index[level];
1655 else
1656 return tex->surface.u.legacy.tiling_index[level];
1657 }
1658
si_get_minimum_num_gfx_cs_dwords(struct si_context * sctx,unsigned num_draws)1659 static inline unsigned si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx,
1660 unsigned num_draws)
1661 {
1662 /* Don't count the needed CS space exactly and just use an upper bound.
1663 *
1664 * Also reserve space for stopping queries at the end of IB, because
1665 * the number of active queries is unlimited in theory.
1666 */
1667 return 2048 + sctx->num_cs_dw_queries_suspend + num_draws * 10;
1668 }
1669
si_context_add_resource_size(struct si_context * sctx,struct pipe_resource * r)1670 static inline void si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1671 {
1672 if (r) {
1673 /* Add memory usage for need_gfx_cs_space */
1674 sctx->memory_usage_kb += si_resource(r)->memory_usage_kb;
1675 }
1676 }
1677
si_invalidate_draw_sh_constants(struct si_context * sctx)1678 static inline void si_invalidate_draw_sh_constants(struct si_context *sctx)
1679 {
1680 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1681 sctx->last_start_instance = SI_START_INSTANCE_UNKNOWN;
1682 sctx->last_drawid = SI_DRAW_ID_UNKNOWN;
1683 }
1684
si_invalidate_draw_constants(struct si_context * sctx)1685 static inline void si_invalidate_draw_constants(struct si_context *sctx)
1686 {
1687 si_invalidate_draw_sh_constants(sctx);
1688 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1689 }
1690
si_get_atom_bit(struct si_context * sctx,struct si_atom * atom)1691 static inline unsigned si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1692 {
1693 return 1 << (atom - sctx->atoms.array);
1694 }
1695
si_set_atom_dirty(struct si_context * sctx,struct si_atom * atom,bool dirty)1696 static inline void si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1697 {
1698 unsigned bit = si_get_atom_bit(sctx, atom);
1699
1700 if (dirty)
1701 sctx->dirty_atoms |= bit;
1702 else
1703 sctx->dirty_atoms &= ~bit;
1704 }
1705
si_is_atom_dirty(struct si_context * sctx,struct si_atom * atom)1706 static inline bool si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1707 {
1708 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1709 }
1710
si_mark_atom_dirty(struct si_context * sctx,struct si_atom * atom)1711 static inline void si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1712 {
1713 si_set_atom_dirty(sctx, atom, true);
1714 }
1715
1716 /* This should be evaluated at compile time if all parameters except sctx are constants. */
1717 static ALWAYS_INLINE struct si_shader_ctx_state *
si_get_vs_inline(struct si_context * sctx,enum si_has_tess has_tess,enum si_has_gs has_gs)1718 si_get_vs_inline(struct si_context *sctx, enum si_has_tess has_tess, enum si_has_gs has_gs)
1719 {
1720 if (has_gs)
1721 return &sctx->shader.gs;
1722 if (has_tess)
1723 return &sctx->shader.tes;
1724
1725 return &sctx->shader.vs;
1726 }
1727
si_get_vs(struct si_context * sctx)1728 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1729 {
1730 return si_get_vs_inline(sctx, sctx->shader.tes.cso ? TESS_ON : TESS_OFF,
1731 sctx->shader.gs.cso ? GS_ON : GS_OFF);
1732 }
1733
si_get_vs_info(struct si_context * sctx)1734 static inline struct si_shader_info *si_get_vs_info(struct si_context *sctx)
1735 {
1736 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1737
1738 return vs->cso ? &vs->cso->info : NULL;
1739 }
1740
si_can_dump_shader(struct si_screen * sscreen,gl_shader_stage stage)1741 static inline bool si_can_dump_shader(struct si_screen *sscreen, gl_shader_stage stage)
1742 {
1743 return sscreen->debug_flags & (1 << stage);
1744 }
1745
si_get_strmout_en(struct si_context * sctx)1746 static inline bool si_get_strmout_en(struct si_context *sctx)
1747 {
1748 return sctx->streamout.streamout_enabled || sctx->streamout.prims_gen_query_enabled;
1749 }
1750
si_optimal_tcc_alignment(struct si_context * sctx,unsigned upload_size)1751 static inline unsigned si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1752 {
1753 unsigned alignment, tcc_cache_line_size;
1754
1755 /* If the upload size is less than the cache line size (e.g. 16, 32),
1756 * the whole thing will fit into a cache line if we align it to its size.
1757 * The idea is that multiple small uploads can share a cache line.
1758 * If the upload size is greater, align it to the cache line size.
1759 */
1760 alignment = util_next_power_of_two(upload_size);
1761 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1762 return MIN2(alignment, tcc_cache_line_size);
1763 }
1764
si_saved_cs_reference(struct si_saved_cs ** dst,struct si_saved_cs * src)1765 static inline void si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1766 {
1767 if (pipe_reference(&(*dst)->reference, &src->reference))
1768 si_destroy_saved_cs(*dst);
1769
1770 *dst = src;
1771 }
1772
si_make_CB_shader_coherent(struct si_context * sctx,unsigned num_samples,bool shaders_read_metadata,bool dcc_pipe_aligned)1773 static inline void si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1774 bool shaders_read_metadata, bool dcc_pipe_aligned)
1775 {
1776 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_INV_VCACHE;
1777 sctx->force_cb_shader_coherent = false;
1778
1779 if (sctx->chip_class >= GFX10) {
1780 if (sctx->screen->info.tcc_rb_non_coherent)
1781 sctx->flags |= SI_CONTEXT_INV_L2;
1782 else if (shaders_read_metadata)
1783 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1784 } else if (sctx->chip_class == GFX9) {
1785 /* Single-sample color is coherent with shaders on GFX9, but
1786 * L2 metadata must be flushed if shaders read metadata.
1787 * (DCC, CMASK).
1788 */
1789 if (num_samples >= 2 || (shaders_read_metadata && !dcc_pipe_aligned))
1790 sctx->flags |= SI_CONTEXT_INV_L2;
1791 else if (shaders_read_metadata)
1792 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1793 } else {
1794 /* GFX6-GFX8 */
1795 sctx->flags |= SI_CONTEXT_INV_L2;
1796 }
1797 }
1798
si_make_DB_shader_coherent(struct si_context * sctx,unsigned num_samples,bool include_stencil,bool shaders_read_metadata)1799 static inline void si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1800 bool include_stencil, bool shaders_read_metadata)
1801 {
1802 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_INV_VCACHE;
1803
1804 if (sctx->chip_class >= GFX10) {
1805 if (sctx->screen->info.tcc_rb_non_coherent)
1806 sctx->flags |= SI_CONTEXT_INV_L2;
1807 else if (shaders_read_metadata)
1808 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1809 } else if (sctx->chip_class == GFX9) {
1810 /* Single-sample depth (not stencil) is coherent with shaders
1811 * on GFX9, but L2 metadata must be flushed if shaders read
1812 * metadata.
1813 */
1814 if (num_samples >= 2 || include_stencil)
1815 sctx->flags |= SI_CONTEXT_INV_L2;
1816 else if (shaders_read_metadata)
1817 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1818 } else {
1819 /* GFX6-GFX8 */
1820 sctx->flags |= SI_CONTEXT_INV_L2;
1821 }
1822 }
1823
si_can_sample_zs(struct si_texture * tex,bool stencil_sampler)1824 static inline bool si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1825 {
1826 return (stencil_sampler && tex->can_sample_s) || (!stencil_sampler && tex->can_sample_z);
1827 }
1828
si_htile_enabled(struct si_texture * tex,unsigned level,unsigned zs_mask)1829 static inline bool si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1830 {
1831 if (zs_mask == PIPE_MASK_S && (tex->htile_stencil_disabled || !tex->surface.has_stencil))
1832 return false;
1833
1834 if (!tex->is_depth || !tex->surface.meta_offset)
1835 return false;
1836
1837 struct si_screen *sscreen = (struct si_screen *)tex->buffer.b.b.screen;
1838 if (sscreen->info.chip_class >= GFX8) {
1839 return level < tex->surface.num_meta_levels;
1840 } else {
1841 /* GFX6-7 don't have TC-compatible HTILE, which means they have to run
1842 * a decompression pass for every mipmap level before texturing, so compress
1843 * only one level to reduce the number of decompression passes to a minimum.
1844 */
1845 return level == 0;
1846 }
1847 }
1848
vi_tc_compat_htile_enabled(struct si_texture * tex,unsigned level,unsigned zs_mask)1849 static inline bool vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level,
1850 unsigned zs_mask)
1851 {
1852 assert(!tex->tc_compatible_htile || tex->surface.meta_offset);
1853 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1854 }
1855
si_get_ps_iter_samples(struct si_context * sctx)1856 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1857 {
1858 if (sctx->ps_uses_fbfetch)
1859 return sctx->framebuffer.nr_color_samples;
1860
1861 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1862 }
1863
si_get_total_colormask(struct si_context * sctx)1864 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1865 {
1866 if (sctx->queued.named.rasterizer->rasterizer_discard)
1867 return 0;
1868
1869 struct si_shader_selector *ps = sctx->shader.ps.cso;
1870 if (!ps)
1871 return 0;
1872
1873 unsigned colormask =
1874 sctx->framebuffer.colorbuf_enabled_4bit & sctx->queued.named.blend->cb_target_mask;
1875
1876 if (!ps->info.color0_writes_all_cbufs)
1877 colormask &= ps->colors_written_4bit;
1878 else if (!ps->colors_written_4bit)
1879 colormask = 0; /* color0 writes all cbufs, but it's not written */
1880
1881 return colormask;
1882 }
1883
1884 #define UTIL_ALL_PRIM_LINE_MODES \
1885 ((1 << PIPE_PRIM_LINES) | (1 << PIPE_PRIM_LINE_LOOP) | (1 << PIPE_PRIM_LINE_STRIP) | \
1886 (1 << PIPE_PRIM_LINES_ADJACENCY) | (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1887
1888 #define UTIL_ALL_PRIM_TRIANGLE_MODES \
1889 ((1 << PIPE_PRIM_TRIANGLES) | (1 << PIPE_PRIM_TRIANGLE_STRIP) | \
1890 (1 << PIPE_PRIM_TRIANGLE_FAN) | (1 << PIPE_PRIM_QUADS) | (1 << PIPE_PRIM_QUAD_STRIP) | \
1891 (1 << PIPE_PRIM_POLYGON) | (1 << PIPE_PRIM_TRIANGLES_ADJACENCY) | \
1892 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY))
1893
util_prim_is_lines(unsigned prim)1894 static inline bool util_prim_is_lines(unsigned prim)
1895 {
1896 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1897 }
1898
util_prim_is_points_or_lines(unsigned prim)1899 static inline bool util_prim_is_points_or_lines(unsigned prim)
1900 {
1901 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES | (1 << PIPE_PRIM_POINTS))) != 0;
1902 }
1903
util_rast_prim_is_triangles(unsigned prim)1904 static inline bool util_rast_prim_is_triangles(unsigned prim)
1905 {
1906 return ((1 << prim) & UTIL_ALL_PRIM_TRIANGLE_MODES) != 0;
1907 }
1908
util_rast_prim_is_lines_or_triangles(unsigned prim)1909 static inline bool util_rast_prim_is_lines_or_triangles(unsigned prim)
1910 {
1911 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES | UTIL_ALL_PRIM_TRIANGLE_MODES)) != 0;
1912 }
1913
1914 /**
1915 * Return true if there is enough memory in VRAM and GTT for the buffers
1916 * added so far.
1917 *
1918 * \param vram VRAM memory size not added to the buffer list yet
1919 * \param gtt GTT memory size not added to the buffer list yet
1920 */
radeon_cs_memory_below_limit(struct si_screen * screen,struct radeon_cmdbuf * cs,uint32_t kb)1921 static inline bool radeon_cs_memory_below_limit(struct si_screen *screen, struct radeon_cmdbuf *cs,
1922 uint32_t kb)
1923 {
1924 return kb + cs->used_vram_kb + cs->used_gart_kb < screen->max_memory_usage_kb;
1925 }
1926
si_need_gfx_cs_space(struct si_context * ctx,unsigned num_draws)1927 static inline void si_need_gfx_cs_space(struct si_context *ctx, unsigned num_draws)
1928 {
1929 struct radeon_cmdbuf *cs = &ctx->gfx_cs;
1930
1931 /* There are two memory usage counters in the winsys for all buffers
1932 * that have been added (cs_add_buffer) and one counter in the pipe
1933 * driver for those that haven't been added yet.
1934 */
1935 uint32_t kb = ctx->memory_usage_kb;
1936 ctx->memory_usage_kb = 0;
1937
1938 if (radeon_cs_memory_below_limit(ctx->screen, &ctx->gfx_cs, kb) &&
1939 ctx->ws->cs_check_space(cs, si_get_minimum_num_gfx_cs_dwords(ctx, num_draws)))
1940 return;
1941
1942 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1943 }
1944
1945 /**
1946 * Add a buffer to the buffer list for the given command stream (CS).
1947 *
1948 * All buffers used by a CS must be added to the list. This tells the kernel
1949 * driver which buffers are used by GPU commands. Other buffers can
1950 * be swapped out (not accessible) during execution.
1951 *
1952 * The buffer list becomes empty after every context flush and must be
1953 * rebuilt.
1954 */
radeon_add_to_buffer_list(struct si_context * sctx,struct radeon_cmdbuf * cs,struct si_resource * bo,unsigned usage)1955 static inline void radeon_add_to_buffer_list(struct si_context *sctx, struct radeon_cmdbuf *cs,
1956 struct si_resource *bo, unsigned usage)
1957 {
1958 assert(usage);
1959 sctx->ws->cs_add_buffer(cs, bo->buf, usage | RADEON_USAGE_SYNCHRONIZED,
1960 bo->domains);
1961 }
1962
1963 /**
1964 * Same as above, but also checks memory usage and flushes the context
1965 * accordingly.
1966 *
1967 * When this SHOULD NOT be used:
1968 *
1969 * - if si_context_add_resource_size has been called for the buffer
1970 * followed by *_need_cs_space for checking the memory usage
1971 *
1972 * - when emitting state packets and draw packets (because preceding packets
1973 * can't be re-emitted at that point)
1974 *
1975 * - if shader resource "enabled_mask" is not up-to-date or there is
1976 * a different constraint disallowing a context flush
1977 */
radeon_add_to_gfx_buffer_list_check_mem(struct si_context * sctx,struct si_resource * bo,unsigned usage,bool check_mem)1978 static inline void radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1979 struct si_resource *bo,
1980 unsigned usage,
1981 bool check_mem)
1982 {
1983 if (check_mem &&
1984 !radeon_cs_memory_below_limit(sctx->screen, &sctx->gfx_cs, sctx->memory_usage_kb + bo->memory_usage_kb))
1985 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1986
1987 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, bo, usage);
1988 }
1989
si_select_draw_vbo(struct si_context * sctx)1990 static inline void si_select_draw_vbo(struct si_context *sctx)
1991 {
1992 pipe_draw_vbo_func draw_vbo = sctx->draw_vbo[!!sctx->shader.tes.cso]
1993 [!!sctx->shader.gs.cso]
1994 [sctx->ngg];
1995 pipe_draw_vertex_state_func draw_vertex_state =
1996 sctx->draw_vertex_state[!!sctx->shader.tes.cso]
1997 [!!sctx->shader.gs.cso]
1998 [sctx->ngg];
1999 assert(draw_vbo);
2000 assert(draw_vertex_state);
2001
2002 if (unlikely(sctx->real_draw_vbo)) {
2003 assert(sctx->real_draw_vertex_state);
2004 sctx->real_draw_vbo = draw_vbo;
2005 sctx->real_draw_vertex_state = draw_vertex_state;
2006 } else {
2007 assert(!sctx->real_draw_vertex_state);
2008 sctx->b.draw_vbo = draw_vbo;
2009 sctx->b.draw_vertex_state = draw_vertex_state;
2010 }
2011 }
2012
2013 /* Return the number of samples that the rasterizer uses. */
si_get_num_coverage_samples(struct si_context * sctx)2014 static inline unsigned si_get_num_coverage_samples(struct si_context *sctx)
2015 {
2016 if (sctx->framebuffer.nr_samples > 1 &&
2017 sctx->queued.named.rasterizer->multisample_enable)
2018 return sctx->framebuffer.nr_samples;
2019
2020 /* Note that smoothing_enabled is set by si_update_shaders. */
2021 if (sctx->smoothing_enabled)
2022 return SI_NUM_SMOOTH_AA_SAMPLES;
2023
2024 return 1;
2025 }
2026
2027 static unsigned ALWAYS_INLINE
si_num_vbos_in_user_sgprs_inline(enum chip_class chip_class)2028 si_num_vbos_in_user_sgprs_inline(enum chip_class chip_class)
2029 {
2030 /* This decreases CPU overhead if all descriptors are in user SGPRs because we don't
2031 * have to allocate and count references for the upload buffer.
2032 */
2033 return chip_class >= GFX9 ? 5 : 1;
2034 }
2035
si_num_vbos_in_user_sgprs(struct si_screen * sscreen)2036 static inline unsigned si_num_vbos_in_user_sgprs(struct si_screen *sscreen)
2037 {
2038 return si_num_vbos_in_user_sgprs_inline(sscreen->info.chip_class);
2039 }
2040
2041 #define PRINT_ERR(fmt, args...) \
2042 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
2043
2044 #ifdef __cplusplus
2045 }
2046 #endif
2047
2048 #endif
2049