1 /*
2 * Xilinx Zynq Baseboard System emulation.
3 *
4 * Copyright (c) 2010 Xilinx.
5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
6 * Copyright (c) 2012 Petalogix Pty Ltd.
7 * Written by Haibing Ma
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qemu/units.h"
20 #include "qapi/error.h"
21 #include "hw/sysbus.h"
22 #include "hw/arm/boot.h"
23 #include "net/net.h"
24 #include "sysemu/sysemu.h"
25 #include "hw/boards.h"
26 #include "hw/block/flash.h"
27 #include "hw/loader.h"
28 #include "hw/adc/zynq-xadc.h"
29 #include "hw/ssi/ssi.h"
30 #include "hw/usb/chipidea.h"
31 #include "qemu/error-report.h"
32 #include "hw/sd/sdhci.h"
33 #include "hw/char/cadence_uart.h"
34 #include "hw/net/cadence_gem.h"
35 #include "hw/cpu/a9mpcore.h"
36 #include "hw/qdev-clock.h"
37 #include "sysemu/reset.h"
38 #include "qom/object.h"
39 #include "exec/tswap.h"
40 #include "target/arm/cpu-qom.h"
41 #include "qapi/visitor.h"
42
43 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
44 OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE)
45
46 /* board base frequency: 33.333333 MHz */
47 #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3)
48
49 #define NUM_SPI_FLASHES 4
50 #define NUM_QSPI_FLASHES 2
51 #define NUM_QSPI_BUSSES 2
52
53 #define FLASH_SIZE (64 * 1024 * 1024)
54 #define FLASH_SECTOR_SIZE (128 * 1024)
55
56 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
57
58 #define MPCORE_PERIPHBASE 0xF8F00000
59 #define ZYNQ_BOARD_MIDR 0x413FC090
60
61 static const int dma_irqs[8] = {
62 46, 47, 48, 49, 72, 73, 74, 75
63 };
64
65 #define BOARD_SETUP_ADDR 0x100
66
67 #define SLCR_LOCK_OFFSET 0x004
68 #define SLCR_UNLOCK_OFFSET 0x008
69 #define SLCR_ARM_PLL_OFFSET 0x100
70
71 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d
72 #define SLCR_XILINX_LOCK_KEY 0x767b
73
74 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
75
76 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
77 extract32((x), 12, 4) << 16)
78
79 /* Write immediate val to address r0 + addr. r0 should contain base offset
80 * of the SLCR block. Clobbers r1.
81 */
82
83 #define SLCR_WRITE(addr, val) \
84 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \
85 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
86 0xe5801000 + (addr)
87
88 #define ZYNQ_MAX_CPUS 2
89
90 struct ZynqMachineState {
91 MachineState parent;
92 Clock *ps_clk;
93 ARMCPU *cpu[ZYNQ_MAX_CPUS];
94 uint8_t boot_mode;
95 };
96
zynq_write_board_setup(ARMCPU * cpu,const struct arm_boot_info * info)97 static void zynq_write_board_setup(ARMCPU *cpu,
98 const struct arm_boot_info *info)
99 {
100 int n;
101 uint32_t board_setup_blob[] = {
102 0xe3a004f8, /* mov r0, #0xf8000000 */
103 SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
104 SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
105 SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
106 0xe12fff1e, /* bx lr */
107 };
108 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
109 board_setup_blob[n] = tswap32(board_setup_blob[n]);
110 }
111 rom_add_blob_fixed("board-setup", board_setup_blob,
112 sizeof(board_setup_blob), BOARD_SETUP_ADDR);
113 }
114
115 static struct arm_boot_info zynq_binfo = {};
116
gem_init(uint32_t base,qemu_irq irq)117 static void gem_init(uint32_t base, qemu_irq irq)
118 {
119 DeviceState *dev;
120 SysBusDevice *s;
121
122 dev = qdev_new(TYPE_CADENCE_GEM);
123 qemu_configure_nic_device(dev, true, NULL);
124 object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort);
125 s = SYS_BUS_DEVICE(dev);
126 sysbus_realize_and_unref(s, &error_fatal);
127 sysbus_mmio_map(s, 0, base);
128 sysbus_connect_irq(s, 0, irq);
129 }
130
zynq_init_spi_flashes(uint32_t base_addr,qemu_irq irq,bool is_qspi,int unit0)131 static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
132 bool is_qspi, int unit0)
133 {
134 int unit = unit0;
135 DeviceState *dev;
136 SysBusDevice *busdev;
137 SSIBus *spi;
138 DeviceState *flash_dev;
139 int i, j;
140 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
141 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
142
143 dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
144 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
145 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
146 qdev_prop_set_uint8(dev, "num-busses", num_busses);
147 busdev = SYS_BUS_DEVICE(dev);
148 sysbus_realize_and_unref(busdev, &error_fatal);
149 sysbus_mmio_map(busdev, 0, base_addr);
150 if (is_qspi) {
151 sysbus_mmio_map(busdev, 1, 0xFC000000);
152 }
153 sysbus_connect_irq(busdev, 0, irq);
154
155 for (i = 0; i < num_busses; ++i) {
156 char bus_name[16];
157 qemu_irq cs_line;
158
159 snprintf(bus_name, 16, "spi%d", i);
160 spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
161
162 for (j = 0; j < num_ss; ++j) {
163 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit++);
164 flash_dev = qdev_new("n25q128");
165 if (dinfo) {
166 qdev_prop_set_drive_err(flash_dev, "drive",
167 blk_by_legacy_dinfo(dinfo),
168 &error_fatal);
169 }
170 qdev_prop_set_uint8(flash_dev, "cs", j);
171 qdev_realize_and_unref(flash_dev, BUS(spi), &error_fatal);
172
173 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
174 sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
175 }
176 }
177
178 return unit;
179 }
180
zynq_set_boot_mode(Object * obj,const char * str,Error ** errp)181 static void zynq_set_boot_mode(Object *obj, const char *str,
182 Error **errp)
183 {
184 ZynqMachineState *m = ZYNQ_MACHINE(obj);
185 uint8_t mode = 0;
186
187 if (!strncasecmp(str, "qspi", 4)) {
188 mode = 1;
189 } else if (!strncasecmp(str, "sd", 2)) {
190 mode = 5;
191 } else if (!strncasecmp(str, "nor", 3)) {
192 mode = 2;
193 } else if (!strncasecmp(str, "jtag", 4)) {
194 mode = 0;
195 } else {
196 error_setg(errp, "%s boot mode not supported", str);
197 return;
198 }
199 m->boot_mode = mode;
200 }
201
zynq_init(MachineState * machine)202 static void zynq_init(MachineState *machine)
203 {
204 ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine);
205 MemoryRegion *address_space_mem = get_system_memory();
206 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
207 DeviceState *dev, *slcr;
208 SysBusDevice *busdev;
209 qemu_irq pic[64];
210 int n;
211 unsigned int smp_cpus = machine->smp.cpus;
212
213 /* max 2GB ram */
214 if (machine->ram_size > 2 * GiB) {
215 error_report("RAM size more than 2 GiB is not supported");
216 exit(EXIT_FAILURE);
217 }
218
219 for (n = 0; n < smp_cpus; n++) {
220 Object *cpuobj = object_new(machine->cpu_type);
221
222 /*
223 * By default A9 CPUs have EL3 enabled. This board does not currently
224 * support EL3 so the CPU EL3 property is disabled before realization.
225 */
226 if (object_property_find(cpuobj, "has_el3")) {
227 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
228 }
229
230 object_property_set_int(cpuobj, "midr", ZYNQ_BOARD_MIDR,
231 &error_fatal);
232 object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE,
233 &error_fatal);
234
235 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
236
237 zynq_machine->cpu[n] = ARM_CPU(cpuobj);
238 }
239
240 /* DDR remapped to address zero. */
241 memory_region_add_subregion(address_space_mem, 0, machine->ram);
242
243 /* 256K of on-chip memory */
244 memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB,
245 &error_fatal);
246 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
247
248 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
249
250 /* AMD */
251 pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE,
252 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
253 FLASH_SECTOR_SIZE, 1,
254 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
255 0);
256
257 /* Create the main clock source, and feed slcr with it */
258 zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));
259 object_property_add_child(OBJECT(zynq_machine), "ps_clk",
260 OBJECT(zynq_machine->ps_clk));
261 object_unref(OBJECT(zynq_machine->ps_clk));
262 clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
263
264 /* Create slcr, keep a pointer to connect clocks */
265 slcr = qdev_new("xilinx-zynq_slcr");
266 qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
267 qdev_prop_set_uint8(slcr, "boot-mode", zynq_machine->boot_mode);
268 sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
269 sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
270
271 dev = qdev_new(TYPE_A9MPCORE_PRIV);
272 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
273 busdev = SYS_BUS_DEVICE(dev);
274 sysbus_realize_and_unref(busdev, &error_fatal);
275 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
276 zynq_binfo.gic_cpu_if_addr = MPCORE_PERIPHBASE + 0x100;
277 sysbus_create_varargs("l2x0", MPCORE_PERIPHBASE + 0x2000, NULL);
278 for (n = 0; n < smp_cpus; n++) {
279 /* See "hw/intc/arm_gic.h" for the IRQ line association */
280 DeviceState *cpudev = DEVICE(zynq_machine->cpu[n]);
281 sysbus_connect_irq(busdev, n,
282 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
283 sysbus_connect_irq(busdev, smp_cpus + n,
284 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
285 }
286
287 for (n = 0; n < 64; n++) {
288 pic[n] = qdev_get_gpio_in(dev, n);
289 }
290
291 n = zynq_init_spi_flashes(0xE0006000, pic[58 - IRQ_OFFSET], false, 0);
292 n = zynq_init_spi_flashes(0xE0007000, pic[81 - IRQ_OFFSET], false, n);
293 n = zynq_init_spi_flashes(0xE000D000, pic[51 - IRQ_OFFSET], true, n);
294
295 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
296 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
297
298 dev = qdev_new(TYPE_CADENCE_UART);
299 busdev = SYS_BUS_DEVICE(dev);
300 qdev_prop_set_chr(dev, "chardev", serial_hd(0));
301 qdev_connect_clock_in(dev, "refclk",
302 qdev_get_clock_out(slcr, "uart0_ref_clk"));
303 sysbus_realize_and_unref(busdev, &error_fatal);
304 sysbus_mmio_map(busdev, 0, 0xE0000000);
305 sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);
306 dev = qdev_new(TYPE_CADENCE_UART);
307 busdev = SYS_BUS_DEVICE(dev);
308 qdev_prop_set_chr(dev, "chardev", serial_hd(1));
309 qdev_connect_clock_in(dev, "refclk",
310 qdev_get_clock_out(slcr, "uart1_ref_clk"));
311 sysbus_realize_and_unref(busdev, &error_fatal);
312 sysbus_mmio_map(busdev, 0, 0xE0001000);
313 sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);
314
315 sysbus_create_varargs("cadence_ttc", 0xF8001000,
316 pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
317 sysbus_create_varargs("cadence_ttc", 0xF8002000,
318 pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
319
320 gem_init(0xE000B000, pic[54 - IRQ_OFFSET]);
321 gem_init(0xE000C000, pic[77 - IRQ_OFFSET]);
322
323 for (n = 0; n < 2; n++) {
324 int hci_irq = n ? 79 : 56;
325 hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
326 DriveInfo *di;
327 BlockBackend *blk;
328 DeviceState *carddev;
329
330 /* Compatible with:
331 * - SD Host Controller Specification Version 2.0 Part A2
332 * - SDIO Specification Version 2.0
333 * - MMC Specification Version 3.31
334 */
335 dev = qdev_new(TYPE_SYSBUS_SDHCI);
336 qdev_prop_set_uint8(dev, "sd-spec-version", 2);
337 qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
338 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
339 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
340 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
341
342 di = drive_get(IF_SD, 0, n);
343 blk = di ? blk_by_legacy_dinfo(di) : NULL;
344 carddev = qdev_new(TYPE_SD_CARD);
345 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
346 qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
347 &error_fatal);
348 }
349
350 dev = qdev_new(TYPE_ZYNQ_XADC);
351 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
352 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
353 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
354
355 dev = qdev_new("pl330");
356 object_property_set_link(OBJECT(dev), "memory",
357 OBJECT(address_space_mem),
358 &error_fatal);
359 qdev_prop_set_uint8(dev, "num_chnls", 8);
360 qdev_prop_set_uint8(dev, "num_periph_req", 4);
361 qdev_prop_set_uint8(dev, "num_events", 16);
362
363 qdev_prop_set_uint8(dev, "data_width", 64);
364 qdev_prop_set_uint8(dev, "wr_cap", 8);
365 qdev_prop_set_uint8(dev, "wr_q_dep", 16);
366 qdev_prop_set_uint8(dev, "rd_cap", 8);
367 qdev_prop_set_uint8(dev, "rd_q_dep", 16);
368 qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
369
370 busdev = SYS_BUS_DEVICE(dev);
371 sysbus_realize_and_unref(busdev, &error_fatal);
372 sysbus_mmio_map(busdev, 0, 0xF8003000);
373 sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
374 for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */
375 sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
376 }
377
378 dev = qdev_new("xlnx.ps7-dev-cfg");
379 busdev = SYS_BUS_DEVICE(dev);
380 sysbus_realize_and_unref(busdev, &error_fatal);
381 sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
382 sysbus_mmio_map(busdev, 0, 0xF8007000);
383
384 zynq_binfo.ram_size = machine->ram_size;
385 zynq_binfo.board_id = 0xd32;
386 zynq_binfo.loader_start = 0;
387 zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
388 zynq_binfo.write_board_setup = zynq_write_board_setup;
389
390 arm_load_kernel(zynq_machine->cpu[0], machine, &zynq_binfo);
391 }
392
zynq_machine_class_init(ObjectClass * oc,void * data)393 static void zynq_machine_class_init(ObjectClass *oc, void *data)
394 {
395 static const char * const valid_cpu_types[] = {
396 ARM_CPU_TYPE_NAME("cortex-a9"),
397 NULL
398 };
399 MachineClass *mc = MACHINE_CLASS(oc);
400 ObjectProperty *prop;
401 mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
402 mc->init = zynq_init;
403 mc->max_cpus = ZYNQ_MAX_CPUS;
404 mc->no_sdcard = 1;
405 mc->ignore_memory_transaction_failures = true;
406 mc->valid_cpu_types = valid_cpu_types;
407 mc->default_ram_id = "zynq.ext_ram";
408 prop = object_class_property_add_str(oc, "boot-mode", NULL,
409 zynq_set_boot_mode);
410 object_class_property_set_description(oc, "boot-mode",
411 "Supported boot modes:"
412 " jtag qspi sd nor");
413 object_property_set_default_str(prop, "qspi");
414 }
415
416 static const TypeInfo zynq_machine_type = {
417 .name = TYPE_ZYNQ_MACHINE,
418 .parent = TYPE_MACHINE,
419 .class_init = zynq_machine_class_init,
420 .instance_size = sizeof(ZynqMachineState),
421 };
422
zynq_machine_register_types(void)423 static void zynq_machine_register_types(void)
424 {
425 type_register_static(&zynq_machine_type);
426 }
427
428 type_init(zynq_machine_register_types)
429