xref: /linux/arch/x86/include/asm/mce.h (revision 5ad21a24)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_MCE_H
3 #define _ASM_X86_MCE_H
4 
5 #include <uapi/asm/mce.h>
6 
7 /*
8  * Machine Check support for x86
9  */
10 
11 /* MCG_CAP register defines */
12 #define MCG_BANKCNT_MASK	0xff         /* Number of Banks */
13 #define MCG_CTL_P		BIT_ULL(8)   /* MCG_CTL register available */
14 #define MCG_EXT_P		BIT_ULL(9)   /* Extended registers available */
15 #define MCG_CMCI_P		BIT_ULL(10)  /* CMCI supported */
16 #define MCG_SEAM_NR		BIT_ULL(12)  /* MCG_STATUS_SEAM_NR supported */
17 #define MCG_EXT_CNT_MASK	0xff0000     /* Number of Extended registers */
18 #define MCG_EXT_CNT_SHIFT	16
19 #define MCG_EXT_CNT(c)		(((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
20 #define MCG_SER_P		BIT_ULL(24)  /* MCA recovery/new status bits */
21 #define MCG_ELOG_P		BIT_ULL(26)  /* Extended error log supported */
22 #define MCG_LMCE_P		BIT_ULL(27)  /* Local machine check supported */
23 
24 /* MCG_STATUS register defines */
25 #define MCG_STATUS_RIPV		BIT_ULL(0)   /* restart ip valid */
26 #define MCG_STATUS_EIPV		BIT_ULL(1)   /* ip points to correct instruction */
27 #define MCG_STATUS_MCIP		BIT_ULL(2)   /* machine check in progress */
28 #define MCG_STATUS_LMCES	BIT_ULL(3)   /* LMCE signaled */
29 #define MCG_STATUS_SEAM_NR	BIT_ULL(12)  /* Machine check inside SEAM non-root mode */
30 
31 /* MCG_EXT_CTL register defines */
32 #define MCG_EXT_CTL_LMCE_EN	BIT_ULL(0) /* Enable LMCE */
33 
34 /* MCi_STATUS register defines */
35 #define MCI_STATUS_VAL		BIT_ULL(63)  /* valid error */
36 #define MCI_STATUS_OVER		BIT_ULL(62)  /* previous errors lost */
37 #define MCI_STATUS_UC		BIT_ULL(61)  /* uncorrected error */
38 #define MCI_STATUS_EN		BIT_ULL(60)  /* error enabled */
39 #define MCI_STATUS_MISCV	BIT_ULL(59)  /* misc error reg. valid */
40 #define MCI_STATUS_ADDRV	BIT_ULL(58)  /* addr reg. valid */
41 #define MCI_STATUS_PCC		BIT_ULL(57)  /* processor context corrupt */
42 #define MCI_STATUS_S		BIT_ULL(56)  /* Signaled machine check */
43 #define MCI_STATUS_AR		BIT_ULL(55)  /* Action required */
44 #define MCI_STATUS_CEC_SHIFT	38           /* Corrected Error Count */
45 #define MCI_STATUS_CEC_MASK	GENMASK_ULL(52,38)
46 #define MCI_STATUS_CEC(c)	(((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)
47 #define MCI_STATUS_MSCOD(m)	(((m) >> 16) & 0xffff)
48 
49 /* AMD-specific bits */
50 #define MCI_STATUS_TCC		BIT_ULL(55)  /* Task context corrupt */
51 #define MCI_STATUS_SYNDV	BIT_ULL(53)  /* synd reg. valid */
52 #define MCI_STATUS_DEFERRED	BIT_ULL(44)  /* uncorrected error, deferred exception */
53 #define MCI_STATUS_POISON	BIT_ULL(43)  /* access poisonous data */
54 #define MCI_STATUS_SCRUB	BIT_ULL(40)  /* Error detected during scrub operation */
55 
56 /*
57  * McaX field if set indicates a given bank supports MCA extensions:
58  *  - Deferred error interrupt type is specifiable by bank.
59  *  - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
60  *    But should not be used to determine MSR numbers.
61  *  - TCC bit is present in MCx_STATUS.
62  */
63 #define MCI_CONFIG_MCAX		0x1
64 #define MCI_IPID_MCATYPE	0xFFFF0000
65 #define MCI_IPID_HWID		0xFFF
66 
67 /*
68  * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
69  * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
70  * errors to indicate that errors are being filtered by hardware.
71  * We should mask out bit 12 when looking for specific signatures
72  * of uncorrected errors - so the F bit is deliberately skipped
73  * in this #define.
74  */
75 #define MCACOD		  0xefff     /* MCA Error Code */
76 
77 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
78 #define MCACOD_SCRUB	0x00C0	/* 0xC0-0xCF Memory Scrubbing */
79 #define MCACOD_SCRUBMSK	0xeff0	/* Skip bit 12 ('F' bit) */
80 #define MCACOD_L3WB	0x017A	/* L3 Explicit Writeback */
81 #define MCACOD_DATA	0x0134	/* Data Load */
82 #define MCACOD_INSTR	0x0150	/* Instruction Fetch */
83 
84 /* MCi_MISC register defines */
85 #define MCI_MISC_ADDR_LSB(m)	((m) & 0x3f)
86 #define MCI_MISC_ADDR_MODE(m)	(((m) >> 6) & 7)
87 #define  MCI_MISC_ADDR_SEGOFF	0	/* segment offset */
88 #define  MCI_MISC_ADDR_LINEAR	1	/* linear address */
89 #define  MCI_MISC_ADDR_PHYS	2	/* physical address */
90 #define  MCI_MISC_ADDR_MEM	3	/* memory address */
91 #define  MCI_MISC_ADDR_GENERIC	7	/* generic */
92 
93 /* MCi_ADDR register defines */
94 #define MCI_ADDR_PHYSADDR	GENMASK_ULL(boot_cpu_data.x86_phys_bits - 1, 0)
95 
96 /* CTL2 register defines */
97 #define MCI_CTL2_CMCI_EN		BIT_ULL(30)
98 #define MCI_CTL2_CMCI_THRESHOLD_MASK	0x7fffULL
99 
100 #define MCJ_CTX_MASK		3
101 #define MCJ_CTX(flags)		((flags) & MCJ_CTX_MASK)
102 #define MCJ_CTX_RANDOM		0    /* inject context: random */
103 #define MCJ_CTX_PROCESS		0x1  /* inject context: process */
104 #define MCJ_CTX_IRQ		0x2  /* inject context: IRQ */
105 #define MCJ_NMI_BROADCAST	0x4  /* do NMI broadcasting */
106 #define MCJ_EXCEPTION		0x8  /* raise as exception */
107 #define MCJ_IRQ_BROADCAST	0x10 /* do IRQ broadcasting */
108 
109 #define MCE_OVERFLOW 0		/* bit 0 in flags means overflow */
110 
111 #define MCE_LOG_MIN_LEN 32U
112 #define MCE_LOG_SIGNATURE	"MACHINECHECK"
113 
114 /* AMD Scalable MCA */
115 #define MSR_AMD64_SMCA_MC0_CTL		0xc0002000
116 #define MSR_AMD64_SMCA_MC0_STATUS	0xc0002001
117 #define MSR_AMD64_SMCA_MC0_ADDR		0xc0002002
118 #define MSR_AMD64_SMCA_MC0_MISC0	0xc0002003
119 #define MSR_AMD64_SMCA_MC0_CONFIG	0xc0002004
120 #define MSR_AMD64_SMCA_MC0_IPID		0xc0002005
121 #define MSR_AMD64_SMCA_MC0_SYND		0xc0002006
122 #define MSR_AMD64_SMCA_MC0_DESTAT	0xc0002008
123 #define MSR_AMD64_SMCA_MC0_DEADDR	0xc0002009
124 #define MSR_AMD64_SMCA_MC0_MISC1	0xc000200a
125 #define MSR_AMD64_SMCA_MCx_CTL(x)	(MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
126 #define MSR_AMD64_SMCA_MCx_STATUS(x)	(MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
127 #define MSR_AMD64_SMCA_MCx_ADDR(x)	(MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
128 #define MSR_AMD64_SMCA_MCx_MISC(x)	(MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
129 #define MSR_AMD64_SMCA_MCx_CONFIG(x)	(MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
130 #define MSR_AMD64_SMCA_MCx_IPID(x)	(MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
131 #define MSR_AMD64_SMCA_MCx_SYND(x)	(MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))
132 #define MSR_AMD64_SMCA_MCx_DESTAT(x)	(MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
133 #define MSR_AMD64_SMCA_MCx_DEADDR(x)	(MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
134 #define MSR_AMD64_SMCA_MCx_MISCy(x, y)	((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
135 
136 #define XEC(x, mask)			(((x) >> 16) & mask)
137 
138 /* mce.kflags flag bits for logging etc. */
139 #define	MCE_HANDLED_CEC		BIT_ULL(0)
140 #define	MCE_HANDLED_UC		BIT_ULL(1)
141 #define	MCE_HANDLED_EXTLOG	BIT_ULL(2)
142 #define	MCE_HANDLED_NFIT	BIT_ULL(3)
143 #define	MCE_HANDLED_EDAC	BIT_ULL(4)
144 #define	MCE_HANDLED_MCELOG	BIT_ULL(5)
145 
146 /*
147  * Indicates an MCE which has happened in kernel space but from
148  * which the kernel can recover simply by executing fixup_exception()
149  * so that an error is returned to the caller of the function that
150  * hit the machine check.
151  */
152 #define MCE_IN_KERNEL_RECOV	BIT_ULL(6)
153 
154 /*
155  * Indicates an MCE that happened in kernel space while copying data
156  * from user. In this case fixup_exception() gets the kernel to the
157  * error exit for the copy function. Machine check handler can then
158  * treat it like a fault taken in user mode.
159  */
160 #define MCE_IN_KERNEL_COPYIN	BIT_ULL(7)
161 
162 /*
163  * This structure contains all data related to the MCE log.  Also
164  * carries a signature to make it easier to find from external
165  * debugging tools.  Each entry is only valid when its finished flag
166  * is set.
167  */
168 struct mce_log_buffer {
169 	char signature[12]; /* "MACHINECHECK" */
170 	unsigned len;	    /* = elements in .mce_entry[] */
171 	unsigned next;
172 	unsigned flags;
173 	unsigned recordlen;	/* length of struct mce */
174 	struct mce entry[];
175 };
176 
177 /* Highest last */
178 enum mce_notifier_prios {
179 	MCE_PRIO_LOWEST,
180 	MCE_PRIO_MCELOG,
181 	MCE_PRIO_EDAC,
182 	MCE_PRIO_NFIT,
183 	MCE_PRIO_EXTLOG,
184 	MCE_PRIO_UC,
185 	MCE_PRIO_EARLY,
186 	MCE_PRIO_CEC,
187 	MCE_PRIO_HIGHEST = MCE_PRIO_CEC
188 };
189 
190 struct notifier_block;
191 extern void mce_register_decode_chain(struct notifier_block *nb);
192 extern void mce_unregister_decode_chain(struct notifier_block *nb);
193 
194 #include <linux/percpu.h>
195 #include <linux/atomic.h>
196 
197 extern int mce_p5_enabled;
198 
199 #ifdef CONFIG_ARCH_HAS_COPY_MC
200 extern void enable_copy_mc_fragile(void);
201 unsigned long __must_check copy_mc_fragile(void *dst, const void *src, unsigned cnt);
202 #else
enable_copy_mc_fragile(void)203 static inline void enable_copy_mc_fragile(void)
204 {
205 }
206 #endif
207 
208 struct cper_ia_proc_ctx;
209 
210 #ifdef CONFIG_X86_MCE
211 int mcheck_init(void);
212 void mcheck_cpu_init(struct cpuinfo_x86 *c);
213 void mcheck_cpu_clear(struct cpuinfo_x86 *c);
214 int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
215 			       u64 lapic_id);
216 #else
mcheck_init(void)217 static inline int mcheck_init(void) { return 0; }
mcheck_cpu_init(struct cpuinfo_x86 * c)218 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
mcheck_cpu_clear(struct cpuinfo_x86 * c)219 static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
apei_smca_report_x86_error(struct cper_ia_proc_ctx * ctx_info,u64 lapic_id)220 static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
221 					     u64 lapic_id) { return -EINVAL; }
222 #endif
223 
224 void mce_prep_record(struct mce *m);
225 void mce_log(struct mce *m);
226 DECLARE_PER_CPU(struct device *, mce_device);
227 
228 /* Maximum number of MCA banks per CPU. */
229 #define MAX_NR_BANKS 64
230 
231 #ifdef CONFIG_X86_MCE_INTEL
232 void mce_intel_feature_init(struct cpuinfo_x86 *c);
233 void mce_intel_feature_clear(struct cpuinfo_x86 *c);
234 void cmci_clear(void);
235 void cmci_reenable(void);
236 void cmci_rediscover(void);
237 void cmci_recheck(void);
238 #else
mce_intel_feature_init(struct cpuinfo_x86 * c)239 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
mce_intel_feature_clear(struct cpuinfo_x86 * c)240 static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
cmci_clear(void)241 static inline void cmci_clear(void) {}
cmci_reenable(void)242 static inline void cmci_reenable(void) {}
cmci_rediscover(void)243 static inline void cmci_rediscover(void) {}
cmci_recheck(void)244 static inline void cmci_recheck(void) {}
245 #endif
246 
247 int mce_available(struct cpuinfo_x86 *c);
248 bool mce_is_memory_error(struct mce *m);
249 bool mce_is_correctable(struct mce *m);
250 bool mce_usable_address(struct mce *m);
251 
252 DECLARE_PER_CPU(unsigned, mce_exception_count);
253 DECLARE_PER_CPU(unsigned, mce_poll_count);
254 
255 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
256 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
257 
258 enum mcp_flags {
259 	MCP_TIMESTAMP	= BIT(0),	/* log time stamp */
260 	MCP_UC		= BIT(1),	/* log uncorrected errors */
261 	MCP_DONTLOG	= BIT(2),	/* only clear, don't log */
262 	MCP_QUEUE_LOG	= BIT(3),	/* only queue to genpool */
263 };
264 
265 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
266 
267 int mce_notify_irq(void);
268 
269 DECLARE_PER_CPU(struct mce, injectm);
270 
271 /* Disable CMCI/polling for MCA bank claimed by firmware */
272 extern void mce_disable_bank(int bank);
273 
274 /*
275  * Exception handler
276  */
277 void do_machine_check(struct pt_regs *pt_regs);
278 
279 /*
280  * Threshold handler
281  */
282 extern void (*mce_threshold_vector)(void);
283 
284 /* Deferred error interrupt handler */
285 extern void (*deferred_error_int_vector)(void);
286 
287 /*
288  * Used by APEI to report memory error via /dev/mcelog
289  */
290 
291 struct cper_sec_mem_err;
292 extern void apei_mce_report_mem_error(int corrected,
293 				      struct cper_sec_mem_err *mem_err);
294 
295 /*
296  * Enumerate new IP types and HWID values in AMD processors which support
297  * Scalable MCA.
298  */
299 #ifdef CONFIG_X86_MCE_AMD
300 
301 /* These may be used by multiple smca_hwid_mcatypes */
302 enum smca_bank_types {
303 	SMCA_LS = 0,	/* Load Store */
304 	SMCA_LS_V2,
305 	SMCA_IF,	/* Instruction Fetch */
306 	SMCA_L2_CACHE,	/* L2 Cache */
307 	SMCA_DE,	/* Decoder Unit */
308 	SMCA_RESERVED,	/* Reserved */
309 	SMCA_EX,	/* Execution Unit */
310 	SMCA_FP,	/* Floating Point */
311 	SMCA_L3_CACHE,	/* L3 Cache */
312 	SMCA_CS,	/* Coherent Slave */
313 	SMCA_CS_V2,
314 	SMCA_PIE,	/* Power, Interrupts, etc. */
315 	SMCA_UMC,	/* Unified Memory Controller */
316 	SMCA_UMC_V2,
317 	SMCA_MA_LLC,	/* Memory Attached Last Level Cache */
318 	SMCA_PB,	/* Parameter Block */
319 	SMCA_PSP,	/* Platform Security Processor */
320 	SMCA_PSP_V2,
321 	SMCA_SMU,	/* System Management Unit */
322 	SMCA_SMU_V2,
323 	SMCA_MP5,	/* Microprocessor 5 Unit */
324 	SMCA_MPDMA,	/* MPDMA Unit */
325 	SMCA_NBIO,	/* Northbridge IO Unit */
326 	SMCA_PCIE,	/* PCI Express Unit */
327 	SMCA_PCIE_V2,
328 	SMCA_XGMI_PCS,	/* xGMI PCS Unit */
329 	SMCA_NBIF,	/* NBIF Unit */
330 	SMCA_SHUB,	/* System HUB Unit */
331 	SMCA_SATA,	/* SATA Unit */
332 	SMCA_USB,	/* USB Unit */
333 	SMCA_USR_DP,	/* Ultra Short Reach Data Plane Controller */
334 	SMCA_USR_CP,	/* Ultra Short Reach Control Plane Controller */
335 	SMCA_GMI_PCS,	/* GMI PCS Unit */
336 	SMCA_XGMI_PHY,	/* xGMI PHY Unit */
337 	SMCA_WAFL_PHY,	/* WAFL PHY Unit */
338 	SMCA_GMI_PHY,	/* GMI PHY Unit */
339 	N_SMCA_BANK_TYPES
340 };
341 
342 extern bool amd_mce_is_memory_error(struct mce *m);
343 
344 extern int mce_threshold_create_device(unsigned int cpu);
345 extern int mce_threshold_remove_device(unsigned int cpu);
346 
347 void mce_amd_feature_init(struct cpuinfo_x86 *c);
348 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank);
349 #else
350 
mce_threshold_create_device(unsigned int cpu)351 static inline int mce_threshold_create_device(unsigned int cpu)		{ return 0; };
mce_threshold_remove_device(unsigned int cpu)352 static inline int mce_threshold_remove_device(unsigned int cpu)		{ return 0; };
amd_mce_is_memory_error(struct mce * m)353 static inline bool amd_mce_is_memory_error(struct mce *m)		{ return false; };
mce_amd_feature_init(struct cpuinfo_x86 * c)354 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c)		{ }
355 #endif
356 
mce_hygon_feature_init(struct cpuinfo_x86 * c)357 static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c)	{ return mce_amd_feature_init(c); }
358 
359 unsigned long copy_mc_fragile_handle_tail(char *to, char *from, unsigned len);
360 
361 #endif /* _ASM_X86_MCE_H */
362