1 /* $NetBSD: if_smscreg.h,v 1.5 2014/08/21 14:02:10 reinoud Exp $ */ 2 3 /* $OpenBSD: if_smscreg.h,v 1.2 2012/09/27 12:38:11 jsg Exp $ */ 4 /*- 5 * Copyright (c) 2012 6 * Ben Gray <bgray@freebsd.org>. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: src/sys/dev/usb/net/if_smscreg.h,v 1.1 2012/08/15 04:03:55 gonzo Exp $ 31 */ 32 #ifndef _IF_SMSCREG_H_ 33 #define _IF_SMSCREG_H_ 34 35 /* 36 * Definitions for the SMSC LAN9514 and LAN9514 USB to ethernet controllers. 37 * 38 * This information was gleaned from the SMSC driver in the linux kernel, where 39 * it is Copyrighted (C) 2007-2008 SMSC. 40 * 41 */ 42 43 /* 44 * TRANSMIT FRAMES 45 * --------------- 46 * Tx frames are prefixed with an 8-byte header which describes the frame 47 * 48 * 4 bytes 4 bytes variable 49 * +------------+------------+--- . . . . . . . . . . . . ---+ 50 * | TX_CTRL_0 | TX_CTRL_1 | Ethernet frame data | 51 * +------------+------------+--- . . . . . . . . . . . . ---+ 52 * 53 * Where the headers have the following fields: 54 * 55 * TX_CTRL_0 <31:18> Reserved 56 * TX_CTRL_0 <17:16> Data offset (alignment padding 0-3) 57 * TX_CTRL_0 <13> First segment of frame indicator 58 * TX_CTRL_0 <12> Last segment of frame indicator 59 * TX_CTRL_0 <10:0> Buffer size (payload size) 60 * 61 * TX_CTRL_1 <14> Perform H/W checksuming on IP packets 62 * TX_CTRL_1 <13> Disable automatic ethernet CRC generation 63 * TX_CTRL_1 <12> Disable ethernet frame padding upto 64 bytes 64 * TX_CTRL_1 <10:0> Packet byte length 65 * 66 */ 67 #define SMSC_TX_CTRL_0_OFFSET(x) (((x) & 0x3UL) << 16) 68 #define SMSC_TX_CTRL_0_FIRST_SEG (0x1UL << 13) 69 #define SMSC_TX_CTRL_0_LAST_SEG (0x1UL << 12) 70 #define SMSC_TX_CTRL_0_BUF_SIZE(x) ((x) & 0x000007FFUL) 71 72 #define SMSC_TX_CTRL_1_CSUM_ENABLE (0x1UL << 14) 73 #define SMSC_TX_CTRL_1_CRC_DISABLE (0x1UL << 13) 74 #define SMSC_TX_CTRL_1_PADDING_DISABLE (0x1UL << 12) 75 #define SMSC_TX_CTRL_1_PKT_LENGTH(x) ((x) & 0x000007FFUL) 76 77 /* 78 * RECEIVE FRAMES 79 * -------------- 80 * Rx frames are prefixed with an 4-byte status header which describes any 81 * errors with the frame as well as things like the length 82 * 83 * 4 bytes variable 84 * +------------+--- . . . . . . . . . . . . ---+ 85 * | RX_STAT | Ethernet frame data | 86 * +------------+--- . . . . . . . . . . . . ---+ 87 * 88 * Where the status header has the following fields: 89 * 90 * RX_STAT <30> Filter Fail 91 * RX_STAT <29:16> Frame Length 92 * RX_STAT <15> Error Summary 93 * RX_STAT <13> Broadcast Frame 94 * RX_STAT <12> Length Error 95 * RX_STAT <11> Runt Frame 96 * RX_STAT <10> Multicast Frame 97 * RX_STAT <7> Frame too long 98 * RX_STAT <6> Collision Seen 99 * RX_STAT <5> Frame Type 100 * RX_STAT <4> Receive Watchdog 101 * RX_STAT <3> Mii Error 102 * RX_STAT <2> Dribbling 103 * RX_STAT <1> CRC Error 104 * 105 */ 106 #define SMSC_RX_STAT_FILTER_FAIL (0x1UL << 30) 107 #define SMSC_RX_STAT_FRM_LENGTH(x) (((x) >> 16) & 0x3FFFUL) 108 #define SMSC_RX_STAT_ERROR (0x1UL << 15) 109 #define SMSC_RX_STAT_BROADCAST (0x1UL << 13) 110 #define SMSC_RX_STAT_LENGTH_ERROR (0x1UL << 12) 111 #define SMSC_RX_STAT_RUNT (0x1UL << 11) 112 #define SMSC_RX_STAT_MULTICAST (0x1UL << 10) 113 #define SMSC_RX_STAT_FRM_TOO_LONG (0x1UL << 7) 114 #define SMSC_RX_STAT_COLLISION (0x1UL << 6) 115 #define SMSC_RX_STAT_FRM_TYPE (0x1UL << 5) 116 #define SMSC_RX_STAT_WATCHDOG (0x1UL << 4) 117 #define SMSC_RX_STAT_MII_ERROR (0x1UL << 3) 118 #define SMSC_RX_STAT_DRIBBLING (0x1UL << 2) 119 #define SMSC_RX_STAT_CRC_ERROR (0x1UL << 1) 120 121 /* 122 * REGISTERS 123 */ 124 #define SMSC_ID_REV 0x000 125 #define SMSC_INTR_STATUS 0x008 126 #define SMSC_RX_CFG 0x00C 127 #define SMSC_TX_CFG 0x010 128 #define SMSC_HW_CFG 0x014 129 #define SMSC_PM_CTRL 0x020 130 #define SMSC_LED_GPIO_CFG 0x024 131 #define SMSC_GPIO_CFG 0x028 132 #define SMSC_AFC_CFG 0x02C 133 #define SMSC_EEPROM_CMD 0x030 134 #define SMSC_EEPROM_DATA 0x034 135 #define SMSC_BURST_CAP 0x038 136 #define SMSC_GPIO_WAKE 0x064 137 #define SMSC_INTR_CFG 0x068 138 #define SMSC_BULK_IN_DLY 0x06C 139 #define SMSC_MAC_CSR 0x100 140 #define SMSC_MAC_ADDRH 0x104 141 #define SMSC_MAC_ADDRL 0x108 142 #define SMSC_HASHH 0x10C 143 #define SMSC_HASHL 0x110 144 #define SMSC_MII_ADDR 0x114 145 #define SMSC_MII_DATA 0x118 146 #define SMSC_FLOW 0x11C 147 #define SMSC_VLAN1 0x120 148 #define SMSC_VLAN2 0x124 149 #define SMSC_WUFF 0x128 150 #define SMSC_WUCSR 0x12C 151 #define SMSC_COE_CTRL 0x130 152 153 /* ID / Revision register */ 154 #define SMSC_ID_REV_CHIP_ID_MASK 0xFFFF0000UL 155 #define SMSC_ID_REV_CHIP_REV_MASK 0x0000FFFFUL 156 157 #define SMSC_RX_FIFO_FLUSH (0x1UL << 0) 158 159 #define SMSC_TX_CFG_ON (0x1UL << 2) 160 #define SMSC_TX_CFG_STOP (0x1UL << 1) 161 #define SMSC_TX_CFG_FIFO_FLUSH (0x1UL << 0) 162 163 #define SMSC_HW_CFG_BIR (0x1UL << 12) 164 #define SMSC_HW_CFG_LEDB (0x1UL << 11) 165 #define SMSC_HW_CFG_RXDOFF_SHIFT (9) 166 #define SMSC_HW_CFG_RXDOFF (0x3UL << 9) /* RX pkt alignment */ 167 #define SMSC_HW_CFG_DRP (0x1UL << 6) 168 #define SMSC_HW_CFG_MEF (0x1UL << 5) 169 #define SMSC_HW_CFG_LRST (0x1UL << 3) /* Lite reset */ 170 #define SMSC_HW_CFG_PSEL (0x1UL << 2) 171 #define SMSC_HW_CFG_BCE (0x1UL << 1) 172 #define SMSC_HW_CFG_SRST (0x1UL << 0) 173 174 #define SMSC_PM_CTRL_PHY_RST (0x1UL << 4) /* PHY reset */ 175 176 #define SMSC_LED_GPIO_CFG_SPD_LED (0x1UL << 24) 177 #define SMSC_LED_GPIO_CFG_LNK_LED (0x1UL << 20) 178 #define SMSC_LED_GPIO_CFG_FDX_LED (0x1UL << 16) 179 180 /* Hi watermark = 15.5Kb (~10 mtu pkts) */ 181 /* low watermark = 3k (~2 mtu pkts) */ 182 /* backpressure duration = ~ 350us */ 183 /* Apply FC on any frame. */ 184 #define AFC_CFG_DEFAULT (0x00F830A1) 185 186 #define SMSC_EEPROM_CMD_BUSY (0x1UL << 31) 187 #define SMSC_EEPROM_CMD_MASK (0x7UL << 28) 188 #define SMSC_EEPROM_CMD_READ (0x0UL << 28) 189 #define SMSC_EEPROM_CMD_WRITE (0x3UL << 28) 190 #define SMSC_EEPROM_CMD_ERASE (0x5UL << 28) 191 #define SMSC_EEPROM_CMD_RELOAD (0x7UL << 28) 192 #define SMSC_EEPROM_CMD_TIMEOUT (0x1UL << 10) 193 #define SMSC_EEPROM_CMD_ADDR_MASK 0x000001FFUL 194 195 /* MAC Control and Status Register */ 196 #define SMSC_MAC_CSR_RCVOWN (0x1UL << 23) /* Half duplex */ 197 #define SMSC_MAC_CSR_LOOPBK (0x1UL << 21) /* Loopback */ 198 #define SMSC_MAC_CSR_FDPX (0x1UL << 20) /* Full duplex */ 199 #define SMSC_MAC_CSR_MCPAS (0x1UL << 19) /* Multicast mode */ 200 #define SMSC_MAC_CSR_PRMS (0x1UL << 18) /* Promiscuous mode */ 201 #define SMSC_MAC_CSR_INVFILT (0x1UL << 17) /* Inverse filtering */ 202 #define SMSC_MAC_CSR_PASSBAD (0x1UL << 16) /* Pass on bad frames */ 203 #define SMSC_MAC_CSR_HPFILT (0x1UL << 13) /* Hash filtering */ 204 #define SMSC_MAC_CSR_BCAST (0x1UL << 11) /* Broadcast */ 205 #define SMSC_MAC_CSR_DISRTY (0x1UL << 10) /* Disable Retry */ 206 #define SMSC_MAC_CSR_PADSTR (0x1UL << 8) /* PAD stripping */ 207 #define SMSC_MAC_CSR_TXEN (0x1UL << 3) /* TX enable */ 208 #define SMSC_MAC_CSR_RXEN (0x1UL << 2) /* RX enable */ 209 210 /* Interrupt control register */ 211 #define SMSC_INTR_NTEP (0x1UL << 31) 212 #define SMSC_INTR_MACRTO (0x1UL << 19) /* MAC reset timeout */ 213 #define SMSC_INTR_TX_STOP (0x1UL << 17) /* Transmittor halted */ 214 #define SMSC_INTR_RX_STOP (0x1UL << 16) /* Receiver halted */ 215 #define SMSC_INTR_PHY_INT (0x1UL << 15) /* PHY interrupt event */ 216 #define SMSC_INTR_TXE (0x1UL << 14) /* Transmittor error */ 217 #define SMSC_INTR_TDFU (0x1UL << 13) /* TX FIFO underrun */ 218 #define SMSC_INTR_TDFO (0x1UL << 12) /* TX FIFO overrun */ 219 #define SMSC_INTR_RXDF (0x1UL << 11) /* RX dropped frame */ 220 #define SMSC_INTR_GPIOS 0x000007FFUL 221 222 /* Phy MII interface register */ 223 #define SMSC_MII_WRITE (0x1UL << 1) 224 #define SMSC_MII_READ (0x0UL << 1) 225 #define SMSC_MII_BUSY (0x1UL << 0) 226 227 /* H/W checksum register */ 228 #define SMSC_COE_CTRL_TX_EN (0x1UL << 16) /* Tx H/W csum enable */ 229 #define SMSC_COE_CTRL_RX_MODE (0x1UL << 1) 230 #define SMSC_COE_CTRL_RX_EN (0x1UL << 0) /* Rx H/W csum enable */ 231 232 /* Registers on the phy, accessed via MII/MDIO */ 233 #define SMSC_PHY_INTR_STAT (29) 234 #define SMSC_PHY_INTR_MASK (30) 235 236 #define SMSC_PHY_INTR_ENERGY_ON (0x1U << 7) 237 #define SMSC_PHY_INTR_ANEG_COMP (0x1U << 6) 238 #define SMSC_PHY_INTR_REMOTE_FAULT (0x1U << 5) 239 #define SMSC_PHY_INTR_LINK_DOWN (0x1U << 4) 240 241 /* USB Vendor Requests */ 242 #define SMSC_UR_WRITE_REG 0xA0 243 #define SMSC_UR_READ_REG 0xA1 244 #define SMSC_UR_GET_STATS 0xA2 245 246 #define SMSC_RX_LIST_CNT 1 247 #define SMSC_TX_LIST_CNT 1 248 249 #define SMSC_CONFIG_INDEX 1 /* config number 1 */ 250 #define SMSC_IFACE_IDX 0 251 252 #define SMSC_ENDPT_RX 0 253 #define SMSC_ENDPT_TX 1 254 #define SMSC_ENDPT_INTR 2 255 #define SMSC_ENDPT_MAX 3 256 257 #define SMSC_MIN_BUFSZ 2048 258 #define SMSC_MAX_BUFSZ 18944 259 260 #endif /* _IF_SMSCREG_H_ */ 261