1 /* $NetBSD: smu74.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 27 #ifndef SMU74_H 28 #define SMU74_H 29 30 #pragma pack(push, 1) 31 32 #define SMU__DGPU_ONLY 33 34 #define SMU__NUM_SCLK_DPM_STATE 8 35 #define SMU__NUM_MCLK_DPM_LEVELS 4 36 #define SMU__NUM_LCLK_DPM_LEVELS 8 37 #define SMU__NUM_PCIE_DPM_LEVELS 8 38 39 #define EXP_M1 35 40 #define EXP_M2 92821 41 #define EXP_B 66629747 42 43 #define EXP_M1_1 365 44 #define EXP_M2_1 658700 45 #define EXP_B_1 305506134 46 47 #define EXP_M1_2 189 48 #define EXP_M2_2 379692 49 #define EXP_B_2 194609469 50 51 #define EXP_M1_3 99 52 #define EXP_M2_3 217915 53 #define EXP_B_3 122255994 54 55 #define EXP_M1_4 51 56 #define EXP_M2_4 122643 57 #define EXP_B_4 74893384 58 59 #define EXP_M1_5 423 60 #define EXP_M2_5 1103326 61 #define EXP_B_5 728122621 62 63 enum SID_OPTION { 64 SID_OPTION_HI, 65 SID_OPTION_LO, 66 SID_OPTION_COUNT 67 }; 68 69 enum Poly3rdOrderCoeff { 70 LEAKAGE_TEMPERATURE_SCALAR, 71 LEAKAGE_VOLTAGE_SCALAR, 72 DYNAMIC_VOLTAGE_SCALAR, 73 POLY_3RD_ORDER_COUNT 74 }; 75 76 struct SMU7_Poly3rdOrder_Data { 77 int32_t a; 78 int32_t b; 79 int32_t c; 80 int32_t d; 81 uint8_t a_shift; 82 uint8_t b_shift; 83 uint8_t c_shift; 84 uint8_t x_shift; 85 }; 86 87 typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data; 88 89 struct Power_Calculator_Data { 90 uint16_t NoLoadVoltage; 91 uint16_t LoadVoltage; 92 uint16_t Resistance; 93 uint16_t Temperature; 94 uint16_t BaseLeakage; 95 uint16_t LkgTempScalar; 96 uint16_t LkgVoltScalar; 97 uint16_t LkgAreaScalar; 98 uint16_t LkgPower; 99 uint16_t DynVoltScalar; 100 uint32_t Cac; 101 uint32_t DynPower; 102 uint32_t TotalCurrent; 103 uint32_t TotalPower; 104 }; 105 106 typedef struct Power_Calculator_Data PowerCalculatorData_t; 107 108 struct Gc_Cac_Weight_Data { 109 uint8_t index; 110 uint32_t value; 111 }; 112 113 typedef struct Gc_Cac_Weight_Data GcCacWeight_Data; 114 115 116 typedef struct { 117 uint32_t high; 118 uint32_t low; 119 } data_64_t; 120 121 typedef struct { 122 data_64_t high; 123 data_64_t low; 124 } data_128_t; 125 126 #define SMU7_CONTEXT_ID_SMC 1 127 #define SMU7_CONTEXT_ID_VBIOS 2 128 129 #define SMU74_MAX_LEVELS_VDDC 16 130 #define SMU74_MAX_LEVELS_VDDGFX 16 131 #define SMU74_MAX_LEVELS_VDDCI 8 132 #define SMU74_MAX_LEVELS_MVDD 4 133 134 #define SMU_MAX_SMIO_LEVELS 4 135 136 #define SMU74_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */ 137 #define SMU74_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS /* MCLK Levels DPM */ 138 #define SMU74_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS /* LCLK Levels */ 139 #define SMU74_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes */ 140 #define SMU74_MAX_LEVELS_UVD 8 /* VCLK/DCLK levels for UVD */ 141 #define SMU74_MAX_LEVELS_VCE 8 /* ECLK levels for VCE */ 142 #define SMU74_MAX_LEVELS_ACP 8 /* ACLK levels for ACP */ 143 #define SMU74_MAX_LEVELS_SAMU 8 /* SAMCLK levels for SAMU */ 144 #define SMU74_MAX_ENTRIES_SMIO 32 /* Number of entries in SMIO table */ 145 146 #define DPM_NO_LIMIT 0 147 #define DPM_NO_UP 1 148 #define DPM_GO_DOWN 2 149 #define DPM_GO_UP 3 150 151 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 152 #define SMU7_FIRST_DPM_MEMORY_LEVEL 0 153 154 #define GPIO_CLAMP_MODE_VRHOT 1 155 #define GPIO_CLAMP_MODE_THERM 2 156 #define GPIO_CLAMP_MODE_DC 4 157 158 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 159 #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) 160 #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 161 #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) 162 #define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 163 #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) 164 #define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 165 #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) 166 #define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 167 #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) 168 #define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 169 #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) 170 #define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 171 #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) 172 #define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 173 #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) 174 #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 175 #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) 176 #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 177 #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) 178 179 /* Virtualization Defines */ 180 #define CG_XDMA_MASK 0x1 181 #define CG_XDMA_SHIFT 0 182 #define CG_UVD_MASK 0x2 183 #define CG_UVD_SHIFT 1 184 #define CG_VCE_MASK 0x4 185 #define CG_VCE_SHIFT 2 186 #define CG_SAMU_MASK 0x8 187 #define CG_SAMU_SHIFT 3 188 #define CG_GFX_MASK 0x10 189 #define CG_GFX_SHIFT 4 190 #define CG_SDMA_MASK 0x20 191 #define CG_SDMA_SHIFT 5 192 #define CG_HDP_MASK 0x40 193 #define CG_HDP_SHIFT 6 194 #define CG_MC_MASK 0x80 195 #define CG_MC_SHIFT 7 196 #define CG_DRM_MASK 0x100 197 #define CG_DRM_SHIFT 8 198 #define CG_ROM_MASK 0x200 199 #define CG_ROM_SHIFT 9 200 #define CG_BIF_MASK 0x400 201 #define CG_BIF_SHIFT 10 202 203 204 #define SMU74_DTE_ITERATIONS 5 205 #define SMU74_DTE_SOURCES 3 206 #define SMU74_DTE_SINKS 1 207 #define SMU74_NUM_CPU_TES 0 208 #define SMU74_NUM_GPU_TES 1 209 #define SMU74_NUM_NON_TES 2 210 #define SMU74_DTE_FAN_SCALAR_MIN 0x100 211 #define SMU74_DTE_FAN_SCALAR_MAX 0x166 212 #define SMU74_DTE_FAN_TEMP_MAX 93 213 #define SMU74_DTE_FAN_TEMP_MIN 83 214 215 216 #if defined SMU__FUSION_ONLY 217 #define SMU7_DTE_ITERATIONS 5 218 #define SMU7_DTE_SOURCES 5 219 #define SMU7_DTE_SINKS 3 220 #define SMU7_NUM_CPU_TES 2 221 #define SMU7_NUM_GPU_TES 1 222 #define SMU7_NUM_NON_TES 2 223 #endif 224 225 struct SMU7_HystController_Data { 226 uint8_t waterfall_up; 227 uint8_t waterfall_down; 228 uint8_t waterfall_limit; 229 uint8_t spare; 230 uint16_t release_cnt; 231 uint16_t release_limit; 232 }; 233 234 typedef struct SMU7_HystController_Data SMU7_HystController_Data; 235 236 struct SMU74_PIDController { 237 uint32_t Ki; 238 int32_t LFWindupUpperLim; 239 int32_t LFWindupLowerLim; 240 uint32_t StatePrecision; 241 uint32_t LfPrecision; 242 uint32_t LfOffset; 243 uint32_t MaxState; 244 uint32_t MaxLfFraction; 245 uint32_t StateShift; 246 }; 247 248 typedef struct SMU74_PIDController SMU74_PIDController; 249 250 struct SMU7_LocalDpmScoreboard { 251 uint32_t PercentageBusy; 252 253 int32_t PIDError; 254 int32_t PIDIntegral; 255 int32_t PIDOutput; 256 257 uint32_t SigmaDeltaAccum; 258 uint32_t SigmaDeltaOutput; 259 uint32_t SigmaDeltaLevel; 260 261 uint32_t UtilizationSetpoint; 262 263 uint8_t TdpClampMode; 264 uint8_t TdcClampMode; 265 uint8_t ThermClampMode; 266 uint8_t VoltageBusy; 267 268 int8_t CurrLevel; 269 int8_t TargLevel; 270 uint8_t LevelChangeInProgress; 271 uint8_t UpHyst; 272 273 uint8_t DownHyst; 274 uint8_t VoltageDownHyst; 275 uint8_t DpmEnable; 276 uint8_t DpmRunning; 277 278 uint8_t DpmForce; 279 uint8_t DpmForceLevel; 280 uint8_t DisplayWatermark; 281 uint8_t McArbIndex; 282 283 uint32_t MinimumPerfSclk; 284 285 uint8_t AcpiReq; 286 uint8_t AcpiAck; 287 uint8_t GfxClkSlow; 288 uint8_t GpioClampMode; 289 290 uint8_t spare2; 291 uint8_t EnabledLevelsChange; 292 uint8_t DteClampMode; 293 uint8_t FpsClampMode; 294 295 uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_GRAPHICS]; 296 uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_GRAPHICS]; 297 298 void (*TargetStateCalculator)(uint8_t); 299 void (*SavedTargetStateCalculator)(uint8_t); 300 301 uint16_t AutoDpmInterval; 302 uint16_t AutoDpmRange; 303 304 uint8_t FpsEnabled; 305 uint8_t MaxPerfLevel; 306 uint8_t AllowLowClkInterruptToHost; 307 uint8_t FpsRunning; 308 309 uint32_t MaxAllowedFrequency; 310 311 uint32_t FilteredSclkFrequency; 312 uint32_t LastSclkFrequency; 313 uint32_t FilteredSclkFrequencyCnt; 314 315 uint8_t MinPerfLevel; 316 uint8_t padding[3]; 317 318 uint16_t FpsAlpha; 319 uint16_t DeltaTime; 320 uint32_t CurrentFps; 321 uint32_t FilteredFps; 322 uint32_t FrameCount; 323 uint32_t FrameCountLast; 324 uint16_t FpsTargetScalar; 325 uint16_t FpsWaterfallLimitScalar; 326 uint16_t FpsAlphaScalar; 327 uint16_t spare8; 328 SMU7_HystController_Data HystControllerData; 329 }; 330 331 typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard; 332 333 #define SMU7_MAX_VOLTAGE_CLIENTS 12 334 335 typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t); 336 337 #define VDDC_MASK 0x00007FFF 338 #define VDDC_SHIFT 0 339 #define VDDCI_MASK 0x3FFF8000 340 #define VDDCI_SHIFT 15 341 #define PHASES_MASK 0xC0000000 342 #define PHASES_SHIFT 30 343 344 typedef uint32_t SMU_VoltageLevel; 345 346 struct SMU7_VoltageScoreboard { 347 348 SMU_VoltageLevel TargetVoltage; 349 uint16_t MaxVid; 350 uint8_t HighestVidOffset; 351 uint8_t CurrentVidOffset; 352 353 uint16_t CurrentVddc; 354 uint16_t CurrentVddci; 355 356 357 uint8_t ControllerBusy; 358 uint8_t CurrentVid; 359 uint8_t CurrentVddciVid; 360 uint8_t padding; 361 362 SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS]; 363 SMU_VoltageLevel TargetVoltageState; 364 uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS]; 365 366 uint8_t padding2; 367 uint8_t padding3; 368 uint8_t ControllerEnable; 369 uint8_t ControllerRunning; 370 uint16_t CurrentStdVoltageHiSidd; 371 uint16_t CurrentStdVoltageLoSidd; 372 uint8_t OverrideVoltage; 373 uint8_t padding4; 374 uint8_t padding5; 375 uint8_t CurrentPhases; 376 377 VoltageChangeHandler_t ChangeVddc; 378 379 VoltageChangeHandler_t ChangeVddci; 380 VoltageChangeHandler_t ChangePhase; 381 VoltageChangeHandler_t ChangeMvdd; 382 383 VoltageChangeHandler_t functionLinks[6]; 384 385 uint16_t *VddcFollower1; 386 387 int16_t Driver_OD_RequestedVidOffset1; 388 int16_t Driver_OD_RequestedVidOffset2; 389 }; 390 391 typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard; 392 393 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ 394 395 struct SMU7_PCIeLinkSpeedScoreboard { 396 uint8_t DpmEnable; 397 uint8_t DpmRunning; 398 uint8_t DpmForce; 399 uint8_t DpmForceLevel; 400 401 uint8_t CurrentLinkSpeed; 402 uint8_t EnabledLevelsChange; 403 uint16_t AutoDpmInterval; 404 405 uint16_t AutoDpmRange; 406 uint16_t AutoDpmCount; 407 408 uint8_t DpmMode; 409 uint8_t AcpiReq; 410 uint8_t AcpiAck; 411 uint8_t CurrentLinkLevel; 412 413 }; 414 415 typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard; 416 417 #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 418 #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 419 420 #define SMU7_SCALE_I 7 421 #define SMU7_SCALE_R 12 422 423 struct SMU7_PowerScoreboard { 424 PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT]; 425 426 uint32_t TotalGpuPower; 427 uint32_t TdcCurrent; 428 429 uint16_t VddciTotalPower; 430 uint16_t sparesasfsdfd; 431 uint16_t Vddr1Power; 432 uint16_t RocPower; 433 434 uint16_t CalcMeasPowerBlend; 435 uint8_t SidOptionPower; 436 uint8_t SidOptionCurrent; 437 438 uint32_t WinTime; 439 440 uint16_t Telemetry_1_slope; 441 uint16_t Telemetry_2_slope; 442 int32_t Telemetry_1_offset; 443 int32_t Telemetry_2_offset; 444 445 uint32_t VddcCurrentTelemetry; 446 uint32_t VddGfxCurrentTelemetry; 447 uint32_t VddcPowerTelemetry; 448 uint32_t VddGfxPowerTelemetry; 449 uint32_t VddciPowerTelemetry; 450 451 uint32_t VddcPower; 452 uint32_t VddGfxPower; 453 uint32_t VddciPower; 454 455 uint32_t TelemetryCurrent[2]; 456 uint32_t TelemetryVoltage[2]; 457 uint32_t TelemetryPower[2]; 458 }; 459 460 typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard; 461 462 struct SMU7_ThermalScoreboard { 463 int16_t GpuLimit; 464 int16_t GpuHyst; 465 uint16_t CurrGnbTemp; 466 uint16_t FilteredGnbTemp; 467 468 uint8_t ControllerEnable; 469 uint8_t ControllerRunning; 470 uint8_t AutoTmonCalInterval; 471 uint8_t AutoTmonCalEnable; 472 473 uint8_t ThermalDpmEnabled; 474 uint8_t SclkEnabledMask; 475 uint8_t spare[2]; 476 int32_t temperature_gradient; 477 478 SMU7_HystController_Data HystControllerData; 479 int32_t WeightedSensorTemperature; 480 uint16_t TemperatureLimit[SMU74_MAX_LEVELS_GRAPHICS]; 481 uint32_t Alpha; 482 }; 483 484 typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard; 485 486 #define SMU7_SCLK_DPM_CONFIG_MASK 0x01 487 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 488 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 489 #define SMU7_MCLK_DPM_CONFIG_MASK 0x08 490 #define SMU7_UVD_DPM_CONFIG_MASK 0x10 491 #define SMU7_VCE_DPM_CONFIG_MASK 0x20 492 #define SMU7_ACP_DPM_CONFIG_MASK 0x40 493 #define SMU7_SAMU_DPM_CONFIG_MASK 0x80 494 #define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 495 496 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 497 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 498 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 499 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 500 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 501 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 502 503 /* All 'soft registers' should be uint32_t. */ 504 struct SMU74_SoftRegisters { 505 uint32_t RefClockFrequency; 506 uint32_t PmTimerPeriod; 507 uint32_t FeatureEnables; 508 509 uint32_t PreVBlankGap; 510 uint32_t VBlankTimeout; 511 uint32_t TrainTimeGap; 512 513 uint32_t MvddSwitchTime; 514 uint32_t LongestAcpiTrainTime; 515 uint32_t AcpiDelay; 516 uint32_t G5TrainTime; 517 uint32_t DelayMpllPwron; 518 uint32_t VoltageChangeTimeout; 519 520 uint32_t HandshakeDisables; 521 522 uint8_t DisplayPhy1Config; 523 uint8_t DisplayPhy2Config; 524 uint8_t DisplayPhy3Config; 525 uint8_t DisplayPhy4Config; 526 527 uint8_t DisplayPhy5Config; 528 uint8_t DisplayPhy6Config; 529 uint8_t DisplayPhy7Config; 530 uint8_t DisplayPhy8Config; 531 532 uint32_t AverageGraphicsActivity; 533 uint32_t AverageMemoryActivity; 534 uint32_t AverageGioActivity; 535 536 uint8_t SClkDpmEnabledLevels; 537 uint8_t MClkDpmEnabledLevels; 538 uint8_t LClkDpmEnabledLevels; 539 uint8_t PCIeDpmEnabledLevels; 540 541 uint8_t UVDDpmEnabledLevels; 542 uint8_t SAMUDpmEnabledLevels; 543 uint8_t ACPDpmEnabledLevels; 544 uint8_t VCEDpmEnabledLevels; 545 546 uint32_t DRAM_LOG_ADDR_H; 547 uint32_t DRAM_LOG_ADDR_L; 548 uint32_t DRAM_LOG_PHY_ADDR_H; 549 uint32_t DRAM_LOG_PHY_ADDR_L; 550 uint32_t DRAM_LOG_BUFF_SIZE; 551 uint32_t UlvEnterCount; 552 uint32_t UlvTime; 553 uint32_t UcodeLoadStatus; 554 uint32_t AllowMvddSwitch; 555 uint8_t Activity_Weight; 556 uint8_t Reserved8[3]; 557 }; 558 559 typedef struct SMU74_SoftRegisters SMU74_SoftRegisters; 560 561 struct SMU74_Firmware_Header { 562 uint32_t Digest[5]; 563 uint32_t Version; 564 uint32_t HeaderSize; 565 uint32_t Flags; 566 uint32_t EntryPoint; 567 uint32_t CodeSize; 568 uint32_t ImageSize; 569 570 uint32_t Rtos; 571 uint32_t SoftRegisters; 572 uint32_t DpmTable; 573 uint32_t FanTable; 574 uint32_t CacConfigTable; 575 uint32_t CacStatusTable; 576 577 uint32_t mcRegisterTable; 578 579 uint32_t mcArbDramTimingTable; 580 581 uint32_t PmFuseTable; 582 uint32_t Globals; 583 uint32_t ClockStretcherTable; 584 uint32_t VftTable; 585 uint32_t Reserved1; 586 uint32_t AvfsTable; 587 uint32_t AvfsCksOffGbvTable; 588 uint32_t AvfsMeanNSigma; 589 uint32_t AvfsSclkOffsetTable; 590 uint32_t Reserved[16]; 591 uint32_t Signature; 592 }; 593 594 typedef struct SMU74_Firmware_Header SMU74_Firmware_Header; 595 596 #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000 597 598 enum DisplayConfig { 599 PowerDown = 1, 600 DP54x4, 601 DP54x2, 602 DP54x1, 603 DP27x4, 604 DP27x2, 605 DP27x1, 606 HDMI297, 607 HDMI162, 608 LVDS, 609 DP324x4, 610 DP324x2, 611 DP324x1 612 }; 613 614 615 #define MC_BLOCK_COUNT 1 616 #define CPL_BLOCK_COUNT 5 617 #define SE_BLOCK_COUNT 15 618 #define GC_BLOCK_COUNT 24 619 620 struct SMU7_Local_Cac { 621 uint8_t BlockId; 622 uint8_t SignalId; 623 uint8_t Threshold; 624 uint8_t Padding; 625 }; 626 627 typedef struct SMU7_Local_Cac SMU7_Local_Cac; 628 629 struct SMU7_Local_Cac_Table { 630 631 SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT]; 632 SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT]; 633 SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT]; 634 SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT]; 635 }; 636 637 typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table; 638 639 #pragma pack(pop) 640 641 /* Description of Clock Gating bitmask for Tonga: 642 * System Clock Gating 643 */ 644 #define CG_SYS_BITMASK_FIRST_BIT 0 /* First bit of Sys CG bitmask */ 645 #define CG_SYS_BITMASK_LAST_BIT 9 /* Last bit of Sys CG bitmask */ 646 #define CG_SYS_BIF_MGLS_SHIFT 0 647 #define CG_SYS_ROM_SHIFT 1 648 #define CG_SYS_MC_MGCG_SHIFT 2 649 #define CG_SYS_MC_MGLS_SHIFT 3 650 #define CG_SYS_SDMA_MGCG_SHIFT 4 651 #define CG_SYS_SDMA_MGLS_SHIFT 5 652 #define CG_SYS_DRM_MGCG_SHIFT 6 653 #define CG_SYS_HDP_MGCG_SHIFT 7 654 #define CG_SYS_HDP_MGLS_SHIFT 8 655 #define CG_SYS_DRM_MGLS_SHIFT 9 656 #define CG_SYS_BIF_MGCG_SHIFT 10 657 658 #define CG_SYS_BIF_MGLS_MASK 0x1 659 #define CG_SYS_ROM_MASK 0x2 660 #define CG_SYS_MC_MGCG_MASK 0x4 661 #define CG_SYS_MC_MGLS_MASK 0x8 662 #define CG_SYS_SDMA_MGCG_MASK 0x10 663 #define CG_SYS_SDMA_MGLS_MASK 0x20 664 #define CG_SYS_DRM_MGCG_MASK 0x40 665 #define CG_SYS_HDP_MGCG_MASK 0x80 666 #define CG_SYS_HDP_MGLS_MASK 0x100 667 #define CG_SYS_DRM_MGLS_MASK 0x200 668 #define CG_SYS_BIF_MGCG_MASK 0x400 669 670 /* Graphics Clock Gating */ 671 #define CG_GFX_BITMASK_FIRST_BIT 16 /* First bit of Gfx CG bitmask */ 672 #define CG_GFX_BITMASK_LAST_BIT 24 /* Last bit of Gfx CG bitmask */ 673 674 #define CG_GFX_CGCG_SHIFT 16 675 #define CG_GFX_CGLS_SHIFT 17 676 #define CG_CPF_MGCG_SHIFT 18 677 #define CG_RLC_MGCG_SHIFT 19 678 #define CG_GFX_OTHERS_MGCG_SHIFT 20 679 #define CG_GFX_3DCG_SHIFT 21 680 #define CG_GFX_3DLS_SHIFT 22 681 #define CG_GFX_RLC_LS_SHIFT 23 682 #define CG_GFX_CP_LS_SHIFT 24 683 684 #define CG_GFX_CGCG_MASK 0x00010000 685 #define CG_GFX_CGLS_MASK 0x00020000 686 #define CG_CPF_MGCG_MASK 0x00040000 687 #define CG_RLC_MGCG_MASK 0x00080000 688 #define CG_GFX_OTHERS_MGCG_MASK 0x00100000 689 #define CG_GFX_3DCG_MASK 0x00200000 690 #define CG_GFX_3DLS_MASK 0x00400000 691 #define CG_GFX_RLC_LS_MASK 0x00800000 692 #define CG_GFX_CP_LS_MASK 0x01000000 693 694 695 /* Voltage Regulator Configuration 696 VR Config info is contained in dpmTable.VRConfig */ 697 698 #define VRCONF_VDDC_MASK 0x000000FF 699 #define VRCONF_VDDC_SHIFT 0 700 #define VRCONF_VDDGFX_MASK 0x0000FF00 701 #define VRCONF_VDDGFX_SHIFT 8 702 #define VRCONF_VDDCI_MASK 0x00FF0000 703 #define VRCONF_VDDCI_SHIFT 16 704 #define VRCONF_MVDD_MASK 0xFF000000 705 #define VRCONF_MVDD_SHIFT 24 706 707 #define VR_MERGED_WITH_VDDC 0 708 #define VR_SVI2_PLANE_1 1 709 #define VR_SVI2_PLANE_2 2 710 #define VR_SMIO_PATTERN_1 3 711 #define VR_SMIO_PATTERN_2 4 712 #define VR_STATIC_VOLTAGE 5 713 714 /* Clock Stretcher Configuration */ 715 716 #define CLOCK_STRETCHER_MAX_ENTRIES 0x4 717 #define CKS_LOOKUPTable_MAX_ENTRIES 0x4 718 719 /* The 'settings' field is subdivided in the following way: */ 720 #define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01 721 #define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0 722 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E 723 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1 724 #define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80 725 #define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7 726 727 struct SMU_ClockStretcherDataTableEntry { 728 uint8_t minVID; 729 uint8_t maxVID; 730 uint16_t setting; 731 }; 732 typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry; 733 734 struct SMU_ClockStretcherDataTable { 735 SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES]; 736 }; 737 typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable; 738 739 struct SMU_CKS_LOOKUPTableEntry { 740 uint16_t minFreq; 741 uint16_t maxFreq; 742 743 uint8_t setting; 744 uint8_t padding[3]; 745 }; 746 typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry; 747 748 struct SMU_CKS_LOOKUPTable { 749 SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES]; 750 }; 751 typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable; 752 753 struct AgmAvfsData_t { 754 uint16_t avgPsmCount[28]; 755 uint16_t minPsmCount[28]; 756 }; 757 758 typedef struct AgmAvfsData_t AgmAvfsData_t; 759 760 enum VFT_COLUMNS { 761 SCLK0, 762 SCLK1, 763 SCLK2, 764 SCLK3, 765 SCLK4, 766 SCLK5, 767 SCLK6, 768 SCLK7, 769 770 NUM_VFT_COLUMNS 771 }; 772 773 #define VFT_TABLE_DEFINED 774 775 #define TEMP_RANGE_MAXSTEPS 12 776 777 struct VFT_CELL_t { 778 uint16_t Voltage; 779 }; 780 781 typedef struct VFT_CELL_t VFT_CELL_t; 782 783 struct VFT_TABLE_t { 784 VFT_CELL_t Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS]; 785 uint16_t AvfsGbv[NUM_VFT_COLUMNS]; 786 uint16_t BtcGbv[NUM_VFT_COLUMNS]; 787 uint16_t Temperature[TEMP_RANGE_MAXSTEPS]; 788 789 uint8_t NumTemperatureSteps; 790 uint8_t padding[3]; 791 }; 792 793 typedef struct VFT_TABLE_t VFT_TABLE_t; 794 795 796 /* Total margin, root mean square of Fmax + DC + Platform */ 797 struct AVFS_Margin_t { 798 VFT_CELL_t Cell[NUM_VFT_COLUMNS]; 799 }; 800 typedef struct AVFS_Margin_t AVFS_Margin_t; 801 802 #define BTCGB_VDROOP_TABLE_MAX_ENTRIES 2 803 #define AVFSGB_VDROOP_TABLE_MAX_ENTRIES 2 804 805 struct GB_VDROOP_TABLE_t { 806 int32_t a0; 807 int32_t a1; 808 int32_t a2; 809 uint32_t spare; 810 }; 811 typedef struct GB_VDROOP_TABLE_t GB_VDROOP_TABLE_t; 812 813 struct AVFS_CksOff_Gbv_t { 814 VFT_CELL_t Cell[NUM_VFT_COLUMNS]; 815 }; 816 typedef struct AVFS_CksOff_Gbv_t AVFS_CksOff_Gbv_t; 817 818 struct AVFS_meanNsigma_t { 819 uint32_t Aconstant[3]; 820 uint16_t DC_tol_sigma; 821 uint16_t Platform_mean; 822 uint16_t Platform_sigma; 823 uint16_t PSM_Age_CompFactor; 824 uint8_t Static_Voltage_Offset[NUM_VFT_COLUMNS]; 825 }; 826 typedef struct AVFS_meanNsigma_t AVFS_meanNsigma_t; 827 828 struct AVFS_Sclk_Offset_t { 829 uint16_t Sclk_Offset[8]; 830 }; 831 typedef struct AVFS_Sclk_Offset_t AVFS_Sclk_Offset_t; 832 833 #endif 834 835 836