xref: /netbsd/sys/arch/hpcsh/dev/hd64465/hd64465reg.h (revision cd1f8754)
1 /*	$NetBSD: hd64465reg.h,v 1.3 2021/12/27 23:04:20 andvar Exp $	*/
2 
3 /*-
4  * Copyright (c) 2002 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by UCHIYAMA Yasushi.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 /*
33  * HD64465 power management and system configuration register.
34  */
35 /* System Module Standby Register */
36 #define HD64465_SMSCR		0xb0000000
37 #define   SMSCR_PS2ST		  0x4000
38 #define   SMSCR_ADCST		  0x1000
39 #define   SMSCR_UARTST		  0x0800
40 #define   SMSCR_SCDIST		  0x0200
41 #define   SMSCR_PPST		  0x0100
42 #define   SMSCR_PC0ST		  0x0040
43 #define   SMSCR_PC1ST		  0x0020
44 #define   SMSCR_AFEST		  0x0010
45 #define   SMSCR_TM0ST		  0x0008
46 #define   SMSCR_TM1ST		  0x0004
47 #define   SMSCR_IRDAST		  0x0002
48 #define   SMSCR_KBCST		  0x0001
49 
50 /* System Configuration Register */
51 #define HD64465_SCONFR		0xb0000002
52 /* System Bus Control Register */
53 #define HD64465_SBCR		0xb0000004
54 /* System Peripheral Clock Control Register */
55 #define HD64465_SPCCR		0xb0000006
56 #define   SPCCR_ADCCLK		  0x8000
57 #define   SPCCR_UARTCLK		  0x2000
58 #define   SPCCR_PPCLK		  0x1000
59 #define   SPCCR_FIRCLK		  0x0800
60 #define   SPCCR_SIRCLK		  0x0400
61 #define   SPCCR_SCDICLK		  0x0200
62 #define   SPCCR_KBCCLK		  0x0100
63 #define   SPCCR_USBCLK		  0x0080
64 #define   SPCCR_AFECLK		  0x0040
65 #define   SPCCR_UCKOSC		  0x0002
66 #define   SPCCR_AFEOSC		  0x0001
67 
68 /* System Peripheral S/W Reset Control Register */
69 #define HD64465_SPSRCR		0xb0000008
70 /* System PLL Control Register */
71 #define HD64465_SPLLCR		0xb000000a
72 /* System Revision Register */
73 #define HD64465_SRR		0xb000000c
74 /* System Test Mode Control Register */
75 #define HD64465_STMCR		0xb000000e
76 /* System Device ID Register */
77 #define HD64465_SDIDR		0xb0000010	/* ro 0x8122 */
78 /* System Debug Port Control Register */
79 #define HD64465_SDPCR		0xb0000ff0
80