/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/ |
H A D | NorFlash.h | 300 #define SPINOR_OP_WRSR 0x01 // Write status register 1 byte macro
|
/dports/multimedia/libv4l/linux-5.13-rc2/include/linux/mtd/ |
H A D | spi-nor.h | 26 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/multimedia/v4l_compat/linux-5.13-rc2/include/linux/mtd/ |
H A D | spi-nor.h | 26 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/multimedia/v4l-utils/linux-5.13-rc2/include/linux/mtd/ |
H A D | spi-nor.h | 26 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-sopine/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-rpi/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-chip/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/include/linux/mtd/ |
H A D | spi-nor.h | 42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ macro
|