1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef PPC_CPU_H
21 #define PPC_CPU_H
22
23 #include "qemu/int128.h"
24 #include "qemu/cpu-float.h"
25 #include "exec/cpu-defs.h"
26 #include "cpu-qom.h"
27 #include "qom/object.h"
28 #include "hw/registerfields.h"
29
30 #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
31
32 #define TARGET_PAGE_BITS_64K 16
33 #define TARGET_PAGE_BITS_16M 24
34
35 #if defined(TARGET_PPC64)
36 #define PPC_ELF_MACHINE EM_PPC64
37 #else
38 #define PPC_ELF_MACHINE EM_PPC
39 #endif
40
41 #define PPC_BIT_NR(bit) (63 - (bit))
42 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
43 #define PPC_BIT32(bit) (0x80000000 >> (bit))
44 #define PPC_BIT8(bit) (0x80 >> (bit))
45 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
46 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
47 PPC_BIT32(bs))
48 #define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
49
50 /*
51 * QEMU version of the GETFIELD/SETFIELD macros from skiboot
52 *
53 * It might be better to use the existing extract64() and
54 * deposit64() but this means that all the register definitions will
55 * change and become incompatible with the ones found in skiboot.
56 */
57 #define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1)
58 #define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
59 #define SETFIELD(m, v, val) \
60 (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
61
62 /*****************************************************************************/
63 /* Exception vectors definitions */
64 enum {
65 POWERPC_EXCP_NONE = -1,
66 /* The 64 first entries are used by the PowerPC embedded specification */
67 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
68 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
69 POWERPC_EXCP_DSI = 2, /* Data storage exception */
70 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
71 POWERPC_EXCP_EXTERNAL = 4, /* External input */
72 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
73 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
74 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
75 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
76 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
77 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
78 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
79 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
80 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
81 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
82 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
83 /* Vectors 16 to 31 are reserved */
84 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
85 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
86 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
87 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
88 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
89 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
90 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
91 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
92 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
93 /* Vectors 42 to 63 are reserved */
94 /* Exceptions defined in the PowerPC server specification */
95 POWERPC_EXCP_RESET = 64, /* System reset exception */
96 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
97 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
98 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
99 POWERPC_EXCP_TRACE = 68, /* Trace exception */
100 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
101 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
102 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
103 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
104 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
105 /* 40x specific exceptions */
106 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
107 /* Vectors 75-76 are 601 specific exceptions */
108 /* 602 specific exceptions */
109 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
110 /* 602/603 specific exceptions */
111 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
112 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
113 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
114 /* Exceptions available on most PowerPC */
115 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
116 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
117 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
118 POWERPC_EXCP_SMI = 84, /* System management interrupt */
119 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
120 /* 7xx/74xx specific exceptions */
121 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
122 /* 74xx specific exceptions */
123 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
124 /* 970FX specific exceptions */
125 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
126 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
127 /* Freescale embedded cores specific exceptions */
128 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
129 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
130 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
131 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
132 /* VSX Unavailable (Power ISA 2.06 and later) */
133 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
134 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
135 /* Additional ISA 2.06 and later server exceptions */
136 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */
137 POWERPC_EXCP_HV_MAINT = 97, /* HMI */
138 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */
139 /* Server doorbell variants */
140 POWERPC_EXCP_SDOOR = 99,
141 POWERPC_EXCP_SDOOR_HV = 100,
142 /* ISA 3.00 additions */
143 POWERPC_EXCP_HVIRT = 101,
144 POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */
145 POWERPC_EXCP_PERFM_EBB = 103, /* Performance Monitor EBB Exception */
146 POWERPC_EXCP_EXTERNAL_EBB = 104, /* External EBB Exception */
147 /* EOL */
148 POWERPC_EXCP_NB = 105,
149 /* QEMU exceptions: special cases we want to stop translation */
150 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
151 };
152
153 /* Exceptions error codes */
154 enum {
155 /* Exception subtypes for POWERPC_EXCP_ALIGN */
156 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
157 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
158 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
159 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
160 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
161 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
162 POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */
163 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
164 /* FP exceptions */
165 POWERPC_EXCP_FP = 0x10,
166 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
167 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
168 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
169 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
170 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
171 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
172 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
173 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
174 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
175 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
176 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
177 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
178 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
179 /* Invalid instruction */
180 POWERPC_EXCP_INVAL = 0x20,
181 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
182 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
183 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
184 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
185 /* Privileged instruction */
186 POWERPC_EXCP_PRIV = 0x30,
187 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
188 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
189 /* Trap */
190 POWERPC_EXCP_TRAP = 0x40,
191 };
192
193 /* Exception model */
194 typedef enum powerpc_excp_t {
195 POWERPC_EXCP_UNKNOWN = 0,
196 /* Standard PowerPC exception model */
197 POWERPC_EXCP_STD,
198 /* PowerPC 40x exception model */
199 POWERPC_EXCP_40x,
200 /* PowerPC 603/604/G2 exception model */
201 POWERPC_EXCP_6xx,
202 /* PowerPC 7xx exception model */
203 POWERPC_EXCP_7xx,
204 /* PowerPC 74xx exception model */
205 POWERPC_EXCP_74xx,
206 /* BookE exception model */
207 POWERPC_EXCP_BOOKE,
208 /* PowerPC 970 exception model */
209 POWERPC_EXCP_970,
210 /* POWER7 exception model */
211 POWERPC_EXCP_POWER7,
212 /* POWER8 exception model */
213 POWERPC_EXCP_POWER8,
214 /* POWER9 exception model */
215 POWERPC_EXCP_POWER9,
216 /* POWER10 exception model */
217 POWERPC_EXCP_POWER10,
218 } powerpc_excp_t;
219
220 /*****************************************************************************/
221 /* MMU model */
222 typedef enum powerpc_mmu_t {
223 POWERPC_MMU_UNKNOWN = 0x00000000,
224 /* Standard 32 bits PowerPC MMU */
225 POWERPC_MMU_32B = 0x00000001,
226 /* PowerPC 6xx MMU with software TLB */
227 POWERPC_MMU_SOFT_6xx = 0x00000002,
228 /*
229 * PowerPC 74xx MMU with software TLB (this has been
230 * disabled, see git history for more information.
231 * keywords: tlbld tlbli TLBMISS PTEHI PTELO)
232 */
233 POWERPC_MMU_SOFT_74xx = 0x00000003,
234 /* PowerPC 4xx MMU with software TLB */
235 POWERPC_MMU_SOFT_4xx = 0x00000004,
236 /* PowerPC MMU in real mode only */
237 POWERPC_MMU_REAL = 0x00000006,
238 /* Freescale MPC8xx MMU model */
239 POWERPC_MMU_MPC8xx = 0x00000007,
240 /* BookE MMU model */
241 POWERPC_MMU_BOOKE = 0x00000008,
242 /* BookE 2.06 MMU model */
243 POWERPC_MMU_BOOKE206 = 0x00000009,
244 #define POWERPC_MMU_64 0x00010000
245 /* 64 bits PowerPC MMU */
246 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
247 /* Architecture 2.03 and later (has LPCR) */
248 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
249 /* Architecture 2.06 variant */
250 POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
251 /* Architecture 2.07 variant */
252 POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
253 /* Architecture 3.00 variant */
254 POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
255 } powerpc_mmu_t;
256
mmu_is_64bit(powerpc_mmu_t mmu_model)257 static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
258 {
259 return mmu_model & POWERPC_MMU_64;
260 }
261
262 /*****************************************************************************/
263 /* Input pins model */
264 typedef enum powerpc_input_t {
265 PPC_FLAGS_INPUT_UNKNOWN = 0,
266 /* PowerPC 6xx bus */
267 PPC_FLAGS_INPUT_6xx,
268 /* BookE bus */
269 PPC_FLAGS_INPUT_BookE,
270 /* PowerPC 405 bus */
271 PPC_FLAGS_INPUT_405,
272 /* PowerPC 970 bus */
273 PPC_FLAGS_INPUT_970,
274 /* PowerPC POWER7 bus */
275 PPC_FLAGS_INPUT_POWER7,
276 /* PowerPC POWER9 bus */
277 PPC_FLAGS_INPUT_POWER9,
278 /* Freescale RCPU bus */
279 PPC_FLAGS_INPUT_RCPU,
280 } powerpc_input_t;
281
282 #define PPC_INPUT(env) ((env)->bus_model)
283
284 /*****************************************************************************/
285 typedef struct opc_handler_t opc_handler_t;
286
287 /*****************************************************************************/
288 /* Types used to describe some PowerPC registers etc. */
289 typedef struct DisasContext DisasContext;
290 typedef struct ppc_dcr_t ppc_dcr_t;
291 typedef struct ppc_spr_t ppc_spr_t;
292 typedef struct ppc_tb_t ppc_tb_t;
293 typedef union ppc_tlb_t ppc_tlb_t;
294 typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
295 typedef struct PPCHash64Options PPCHash64Options;
296
297 typedef struct CPUArchState CPUPPCState;
298
299 /* SPR access micro-ops generations callbacks */
300 struct ppc_spr_t {
301 const char *name;
302 target_ulong default_value;
303 #ifndef CONFIG_USER_ONLY
304 unsigned int gdb_id;
305 #endif
306 #ifdef CONFIG_TCG
307 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
308 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
309 # ifndef CONFIG_USER_ONLY
310 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
311 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
312 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
313 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
314 # endif
315 #endif
316 #ifdef CONFIG_KVM
317 /*
318 * We (ab)use the fact that all the SPRs will have ids for the
319 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
320 * don't sync this
321 */
322 uint64_t one_reg_id;
323 #endif
324 };
325
326 /* VSX/Altivec registers (128 bits) */
327 typedef union _ppc_vsr_t {
328 uint8_t u8[16];
329 uint16_t u16[8];
330 uint32_t u32[4];
331 uint64_t u64[2];
332 int8_t s8[16];
333 int16_t s16[8];
334 int32_t s32[4];
335 int64_t s64[2];
336 float16 f16[8];
337 float32 f32[4];
338 float64 f64[2];
339 float128 f128;
340 #ifdef CONFIG_INT128
341 __uint128_t u128;
342 #endif
343 Int128 s128;
344 } ppc_vsr_t;
345
346 typedef ppc_vsr_t ppc_avr_t;
347 typedef ppc_vsr_t ppc_fprp_t;
348 typedef ppc_vsr_t ppc_acc_t;
349
350 #if !defined(CONFIG_USER_ONLY)
351 /* Software TLB cache */
352 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
353 struct ppc6xx_tlb_t {
354 target_ulong pte0;
355 target_ulong pte1;
356 target_ulong EPN;
357 };
358
359 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
360 struct ppcemb_tlb_t {
361 uint64_t RPN;
362 target_ulong EPN;
363 target_ulong PID;
364 target_ulong size;
365 uint32_t prot;
366 uint32_t attr; /* Storage attributes */
367 };
368
369 typedef struct ppcmas_tlb_t {
370 uint32_t mas8;
371 uint32_t mas1;
372 uint64_t mas2;
373 uint64_t mas7_3;
374 } ppcmas_tlb_t;
375
376 union ppc_tlb_t {
377 ppc6xx_tlb_t *tlb6;
378 ppcemb_tlb_t *tlbe;
379 ppcmas_tlb_t *tlbm;
380 };
381
382 /* possible TLB variants */
383 #define TLB_NONE 0
384 #define TLB_6XX 1
385 #define TLB_EMB 2
386 #define TLB_MAS 3
387 #endif
388
389 typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
390
391 typedef struct ppc_slb_t ppc_slb_t;
392 struct ppc_slb_t {
393 uint64_t esid;
394 uint64_t vsid;
395 const PPCHash64SegmentPageSizes *sps;
396 };
397
398 #define MAX_SLB_ENTRIES 64
399 #define SEGMENT_SHIFT_256M 28
400 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
401
402 #define SEGMENT_SHIFT_1T 40
403 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
404
405 typedef struct ppc_v3_pate_t {
406 uint64_t dw0;
407 uint64_t dw1;
408 } ppc_v3_pate_t;
409
410 /* PMU related structs and defines */
411 #define PMU_COUNTERS_NUM 6
412 typedef enum {
413 PMU_EVENT_INVALID = 0,
414 PMU_EVENT_INACTIVE,
415 PMU_EVENT_CYCLES,
416 PMU_EVENT_INSTRUCTIONS,
417 PMU_EVENT_INSN_RUN_LATCH,
418 } PMUEventType;
419
420 /*****************************************************************************/
421 /* Machine state register bits definition */
422 #define MSR_SF PPC_BIT_NR(0) /* Sixty-four-bit mode hflags */
423 #define MSR_TAG PPC_BIT_NR(1) /* Tag-active mode (POWERx ?) */
424 #define MSR_ISF PPC_BIT_NR(2) /* Sixty-four-bit interrupt mode on 630 */
425 #define MSR_HV PPC_BIT_NR(3) /* hypervisor state hflags */
426 #define MSR_TS0 PPC_BIT_NR(29) /* Transactional state, 2 bits (Book3s) */
427 #define MSR_TS1 PPC_BIT_NR(30)
428 #define MSR_TM PPC_BIT_NR(31) /* Transactional Memory Available (Book3s) */
429 #define MSR_CM PPC_BIT_NR(32) /* Computation mode for BookE hflags */
430 #define MSR_ICM PPC_BIT_NR(33) /* Interrupt computation mode for BookE */
431 #define MSR_GS PPC_BIT_NR(35) /* guest state for BookE */
432 #define MSR_UCLE PPC_BIT_NR(37) /* User-mode cache lock enable for BookE */
433 #define MSR_VR PPC_BIT_NR(38) /* altivec available x hflags */
434 #define MSR_SPE PPC_BIT_NR(38) /* SPE enable for BookE x hflags */
435 #define MSR_VSX PPC_BIT_NR(40) /* Vector Scalar Extension (>= 2.06)x hflags */
436 #define MSR_S PPC_BIT_NR(41) /* Secure state */
437 #define MSR_KEY PPC_BIT_NR(44) /* key bit on 603e */
438 #define MSR_POW PPC_BIT_NR(45) /* Power management */
439 #define MSR_WE PPC_BIT_NR(45) /* Wait State Enable on 405 */
440 #define MSR_TGPR PPC_BIT_NR(46) /* TGPR usage on 602/603 x */
441 #define MSR_CE PPC_BIT_NR(46) /* Critical int. enable on embedded PPC x */
442 #define MSR_ILE PPC_BIT_NR(47) /* Interrupt little-endian mode */
443 #define MSR_EE PPC_BIT_NR(48) /* External interrupt enable */
444 #define MSR_PR PPC_BIT_NR(49) /* Problem state hflags */
445 #define MSR_FP PPC_BIT_NR(50) /* Floating point available hflags */
446 #define MSR_ME PPC_BIT_NR(51) /* Machine check interrupt enable */
447 #define MSR_FE0 PPC_BIT_NR(52) /* Floating point exception mode 0 */
448 #define MSR_SE PPC_BIT_NR(53) /* Single-step trace enable x hflags */
449 #define MSR_DWE PPC_BIT_NR(53) /* Debug wait enable on 405 x */
450 #define MSR_UBLE PPC_BIT_NR(53) /* User BTB lock enable on e500 x */
451 #define MSR_BE PPC_BIT_NR(54) /* Branch trace enable x hflags */
452 #define MSR_DE PPC_BIT_NR(54) /* Debug int. enable on embedded PPC x */
453 #define MSR_FE1 PPC_BIT_NR(55) /* Floating point exception mode 1 */
454 #define MSR_AL PPC_BIT_NR(56) /* AL bit on POWER */
455 #define MSR_EP PPC_BIT_NR(57) /* Exception prefix on 601 */
456 #define MSR_IR PPC_BIT_NR(58) /* Instruction relocate */
457 #define MSR_IS PPC_BIT_NR(58) /* Instruction address space (BookE) */
458 #define MSR_DR PPC_BIT_NR(59) /* Data relocate */
459 #define MSR_DS PPC_BIT_NR(59) /* Data address space (BookE) */
460 #define MSR_PE PPC_BIT_NR(60) /* Protection enable on 403 */
461 #define MSR_PX PPC_BIT_NR(61) /* Protection exclusive on 403 x */
462 #define MSR_PMM PPC_BIT_NR(61) /* Performance monitor mark on POWER x */
463 #define MSR_RI PPC_BIT_NR(62) /* Recoverable interrupt 1 */
464 #define MSR_LE PPC_BIT_NR(63) /* Little-endian mode 1 hflags */
465
466 FIELD(MSR, SF, MSR_SF, 1)
467 FIELD(MSR, TAG, MSR_TAG, 1)
468 FIELD(MSR, ISF, MSR_ISF, 1)
469 #if defined(TARGET_PPC64)
470 FIELD(MSR, HV, MSR_HV, 1)
471 #define FIELD_EX64_HV(storage) FIELD_EX64(storage, MSR, HV)
472 #else
473 #define FIELD_EX64_HV(storage) 0
474 #endif
475 FIELD(MSR, TS0, MSR_TS0, 1)
476 FIELD(MSR, TS1, MSR_TS1, 1)
477 FIELD(MSR, TS, MSR_TS0, 2)
478 FIELD(MSR, TM, MSR_TM, 1)
479 FIELD(MSR, CM, MSR_CM, 1)
480 FIELD(MSR, ICM, MSR_ICM, 1)
481 FIELD(MSR, GS, MSR_GS, 1)
482 FIELD(MSR, UCLE, MSR_UCLE, 1)
483 FIELD(MSR, VR, MSR_VR, 1)
484 FIELD(MSR, SPE, MSR_SPE, 1)
485 FIELD(MSR, VSX, MSR_VSX, 1)
486 FIELD(MSR, S, MSR_S, 1)
487 FIELD(MSR, KEY, MSR_KEY, 1)
488 FIELD(MSR, POW, MSR_POW, 1)
489 FIELD(MSR, WE, MSR_WE, 1)
490 FIELD(MSR, TGPR, MSR_TGPR, 1)
491 FIELD(MSR, CE, MSR_CE, 1)
492 FIELD(MSR, ILE, MSR_ILE, 1)
493 FIELD(MSR, EE, MSR_EE, 1)
494 FIELD(MSR, PR, MSR_PR, 1)
495 FIELD(MSR, FP, MSR_FP, 1)
496 FIELD(MSR, ME, MSR_ME, 1)
497 FIELD(MSR, FE0, MSR_FE0, 1)
498 FIELD(MSR, SE, MSR_SE, 1)
499 FIELD(MSR, DWE, MSR_DWE, 1)
500 FIELD(MSR, UBLE, MSR_UBLE, 1)
501 FIELD(MSR, BE, MSR_BE, 1)
502 FIELD(MSR, DE, MSR_DE, 1)
503 FIELD(MSR, FE1, MSR_FE1, 1)
504 FIELD(MSR, AL, MSR_AL, 1)
505 FIELD(MSR, EP, MSR_EP, 1)
506 FIELD(MSR, IR, MSR_IR, 1)
507 FIELD(MSR, DR, MSR_DR, 1)
508 FIELD(MSR, IS, MSR_IS, 1)
509 FIELD(MSR, DS, MSR_DS, 1)
510 FIELD(MSR, PE, MSR_PE, 1)
511 FIELD(MSR, PX, MSR_PX, 1)
512 FIELD(MSR, PMM, MSR_PMM, 1)
513 FIELD(MSR, RI, MSR_RI, 1)
514 FIELD(MSR, LE, MSR_LE, 1)
515
516 /*
517 * FE0 and FE1 bits are not side-by-side
518 * so we can't combine them using FIELD()
519 */
520 #define FIELD_EX64_FE(msr) \
521 ((FIELD_EX64(msr, MSR, FE0) << 1) | FIELD_EX64(msr, MSR, FE1))
522
523 /* PMU bits */
524 #define MMCR0_FC PPC_BIT(32) /* Freeze Counters */
525 #define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Occurred */
526 #define MMCR0_PMAE PPC_BIT(37) /* Perf Monitor Alert Enable */
527 #define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */
528 #define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */
529 #define MMCR0_PMCC0 PPC_BIT(44) /* PMC Control bit 0 */
530 #define MMCR0_PMCC1 PPC_BIT(45) /* PMC Control bit 1 */
531 #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */
532 #define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */
533 #define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */
534 #define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */
535 #define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */
536 /* MMCR0 userspace r/w mask */
537 #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
538 /* MMCR2 userspace r/w mask */
539 #define MMCR2_FC1P0 PPC_BIT(1) /* MMCR2 FCnP0 for PMC1 */
540 #define MMCR2_FC2P0 PPC_BIT(10) /* MMCR2 FCnP0 for PMC2 */
541 #define MMCR2_FC3P0 PPC_BIT(19) /* MMCR2 FCnP0 for PMC3 */
542 #define MMCR2_FC4P0 PPC_BIT(28) /* MMCR2 FCnP0 for PMC4 */
543 #define MMCR2_FC5P0 PPC_BIT(37) /* MMCR2 FCnP0 for PMC5 */
544 #define MMCR2_FC6P0 PPC_BIT(46) /* MMCR2 FCnP0 for PMC6 */
545 #define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \
546 MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0)
547
548 #define MMCR1_EVT_SIZE 8
549 /* extract64() does a right shift before extracting */
550 #define MMCR1_PMC1SEL_START 32
551 #define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE)
552 #define MMCR1_PMC2SEL_START 40
553 #define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE)
554 #define MMCR1_PMC3SEL_START 48
555 #define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE)
556 #define MMCR1_PMC4SEL_START 56
557 #define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE)
558
559 /* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
560 #define CTRL_RUN PPC_BIT(63)
561
562 /* EBB/BESCR bits */
563 /* Global Enable */
564 #define BESCR_GE PPC_BIT(0)
565 /* External Event-based Exception Enable */
566 #define BESCR_EE PPC_BIT(30)
567 /* Performance Monitor Event-based Exception Enable */
568 #define BESCR_PME PPC_BIT(31)
569 /* External Event-based Exception Occurred */
570 #define BESCR_EEO PPC_BIT(62)
571 /* Performance Monitor Event-based Exception Occurred */
572 #define BESCR_PMEO PPC_BIT(63)
573 #define BESCR_INVALID PPC_BITMASK(32, 33)
574
575 /* LPCR bits */
576 #define LPCR_VPM0 PPC_BIT(0)
577 #define LPCR_VPM1 PPC_BIT(1)
578 #define LPCR_ISL PPC_BIT(2)
579 #define LPCR_KBV PPC_BIT(3)
580 #define LPCR_DPFD_SHIFT (63 - 11)
581 #define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
582 #define LPCR_VRMASD_SHIFT (63 - 16)
583 #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
584 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
585 #define LPCR_PECE_U_SHIFT (63 - 19)
586 #define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
587 #define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */
588 #define LPCR_RMLS_SHIFT (63 - 37) /* RMLS (removed in ISA v3.0) */
589 #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
590 #define LPCR_HAIL PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */
591 #define LPCR_ILE PPC_BIT(38)
592 #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
593 #define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
594 #define LPCR_UPRT PPC_BIT(41) /* Use Process Table */
595 #define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */
596 #define LPCR_HR PPC_BIT(43) /* Host Radix */
597 #define LPCR_ONL PPC_BIT(45)
598 #define LPCR_LD PPC_BIT(46) /* Large Decrementer */
599 #define LPCR_P7_PECE0 PPC_BIT(49)
600 #define LPCR_P7_PECE1 PPC_BIT(50)
601 #define LPCR_P7_PECE2 PPC_BIT(51)
602 #define LPCR_P8_PECE0 PPC_BIT(47)
603 #define LPCR_P8_PECE1 PPC_BIT(48)
604 #define LPCR_P8_PECE2 PPC_BIT(49)
605 #define LPCR_P8_PECE3 PPC_BIT(50)
606 #define LPCR_P8_PECE4 PPC_BIT(51)
607 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
608 #define LPCR_PECE_L_SHIFT (63 - 51)
609 #define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
610 #define LPCR_PDEE PPC_BIT(47) /* Privileged Doorbell Exit EN */
611 #define LPCR_HDEE PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
612 #define LPCR_EEE PPC_BIT(49) /* External Exit Enable */
613 #define LPCR_DEE PPC_BIT(50) /* Decrementer Exit Enable */
614 #define LPCR_OEE PPC_BIT(51) /* Other Exit Enable */
615 #define LPCR_MER PPC_BIT(52)
616 #define LPCR_GTSE PPC_BIT(53) /* Guest Translation Shootdown */
617 #define LPCR_TC PPC_BIT(54)
618 #define LPCR_HEIC PPC_BIT(59) /* HV Extern Interrupt Control */
619 #define LPCR_LPES0 PPC_BIT(60)
620 #define LPCR_LPES1 PPC_BIT(61)
621 #define LPCR_RMI PPC_BIT(62)
622 #define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */
623 #define LPCR_HDICE PPC_BIT(63)
624
625 /* PSSCR bits */
626 #define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */
627 #define PSSCR_EC PPC_BIT(43) /* Exit Criterion */
628
629 /* HFSCR bits */
630 #define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */
631 #define HFSCR_IC_MSGP 0xA
632
633 #define DBCR0_ICMP (1 << 27)
634 #define DBCR0_BRT (1 << 26)
635 #define DBSR_ICMP (1 << 27)
636 #define DBSR_BRT (1 << 26)
637
638 /* Hypervisor bit is more specific */
639 #if defined(TARGET_PPC64)
640 #define MSR_HVB (1ULL << MSR_HV)
641 #else
642 #define MSR_HVB (0ULL)
643 #endif
644
645 /* DSISR */
646 #define DSISR_NOPTE 0x40000000
647 /* Not permitted by access authority of encoded access authority */
648 #define DSISR_PROTFAULT 0x08000000
649 #define DSISR_ISSTORE 0x02000000
650 /* Not permitted by virtual page class key protection */
651 #define DSISR_AMR 0x00200000
652 /* Unsupported Radix Tree Configuration */
653 #define DSISR_R_BADCONFIG 0x00080000
654 #define DSISR_ATOMIC_RC 0x00040000
655 /* Unable to translate address of (guest) pde or process/page table entry */
656 #define DSISR_PRTABLE_FAULT 0x00020000
657
658 /* SRR1 error code fields */
659
660 #define SRR1_NOPTE DSISR_NOPTE
661 /* Not permitted due to no-execute or guard bit set */
662 #define SRR1_NOEXEC_GUARD 0x10000000
663 #define SRR1_PROTFAULT DSISR_PROTFAULT
664 #define SRR1_IAMR DSISR_AMR
665
666 /* SRR1[42:45] wakeup fields for System Reset Interrupt */
667
668 #define SRR1_WAKEMASK 0x003c0000 /* reason for wakeup */
669
670 #define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */
671 #define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virt. Interrupt (P9) */
672 #define SRR1_WAKEEE 0x00200000 /* External interrupt */
673 #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
674 #define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell */
675 #define SRR1_WAKERESET 0x00100000 /* System reset */
676 #define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell */
677 #define SRR1_WAKESCOM 0x00080000 /* SCOM not in power-saving mode */
678
679 /* SRR1[46:47] power-saving exit mode */
680
681 #define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask */
682
683 #define SRR1_WS_HVLOSS 0x00030000 /* HV resources not maintained */
684 #define SRR1_WS_GPRLOSS 0x00020000 /* GPRs not maintained */
685 #define SRR1_WS_NOLOSS 0x00010000 /* All resources maintained */
686
687 /* Facility Status and Control (FSCR) bits */
688 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
689 #define FSCR_TAR (63 - 55) /* Target Address Register */
690 #define FSCR_SCV (63 - 51) /* System call vectored */
691 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
692 #define FSCR_IC_MASK (0xFFULL)
693 #define FSCR_IC_POS (63 - 7)
694 #define FSCR_IC_DSCR_SPR3 2
695 #define FSCR_IC_PMU 3
696 #define FSCR_IC_BHRB 4
697 #define FSCR_IC_TM 5
698 #define FSCR_IC_EBB 7
699 #define FSCR_IC_TAR 8
700 #define FSCR_IC_SCV 12
701
702 /* Exception state register bits definition */
703 #define ESR_PIL PPC_BIT(36) /* Illegal Instruction */
704 #define ESR_PPR PPC_BIT(37) /* Privileged Instruction */
705 #define ESR_PTR PPC_BIT(38) /* Trap */
706 #define ESR_FP PPC_BIT(39) /* Floating-Point Operation */
707 #define ESR_ST PPC_BIT(40) /* Store Operation */
708 #define ESR_AP PPC_BIT(44) /* Auxiliary Processor Operation */
709 #define ESR_PUO PPC_BIT(45) /* Unimplemented Operation */
710 #define ESR_BO PPC_BIT(46) /* Byte Ordering */
711 #define ESR_PIE PPC_BIT(47) /* Imprecise exception */
712 #define ESR_DATA PPC_BIT(53) /* Data Access (Embedded page table) */
713 #define ESR_TLBI PPC_BIT(54) /* TLB Ineligible (Embedded page table) */
714 #define ESR_PT PPC_BIT(55) /* Page Table (Embedded page table) */
715 #define ESR_SPV PPC_BIT(56) /* SPE/VMX operation */
716 #define ESR_EPID PPC_BIT(57) /* External Process ID operation */
717 #define ESR_VLEMI PPC_BIT(58) /* VLE operation */
718 #define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */
719
720 /* Transaction EXception And Summary Register bits */
721 #define TEXASR_FAILURE_PERSISTENT (63 - 7)
722 #define TEXASR_DISALLOWED (63 - 8)
723 #define TEXASR_NESTING_OVERFLOW (63 - 9)
724 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
725 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
726 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
727 #define TEXASR_TRANSACTION_CONFLICT (63 - 13)
728 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
729 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
730 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
731 #define TEXASR_ABORT (63 - 31)
732 #define TEXASR_SUSPENDED (63 - 32)
733 #define TEXASR_PRIVILEGE_HV (63 - 34)
734 #define TEXASR_PRIVILEGE_PR (63 - 35)
735 #define TEXASR_FAILURE_SUMMARY (63 - 36)
736 #define TEXASR_TFIAR_EXACT (63 - 37)
737 #define TEXASR_ROT (63 - 38)
738 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
739
740 enum {
741 POWERPC_FLAG_NONE = 0x00000000,
742 /* Flag for MSR bit 25 signification (VRE/SPE) */
743 POWERPC_FLAG_SPE = 0x00000001,
744 POWERPC_FLAG_VRE = 0x00000002,
745 /* Flag for MSR bit 17 signification (TGPR/CE) */
746 POWERPC_FLAG_TGPR = 0x00000004,
747 POWERPC_FLAG_CE = 0x00000008,
748 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
749 POWERPC_FLAG_SE = 0x00000010,
750 POWERPC_FLAG_DWE = 0x00000020,
751 POWERPC_FLAG_UBLE = 0x00000040,
752 /* Flag for MSR bit 9 signification (BE/DE) */
753 POWERPC_FLAG_BE = 0x00000080,
754 POWERPC_FLAG_DE = 0x00000100,
755 /* Flag for MSR bit 2 signification (PX/PMM) */
756 POWERPC_FLAG_PX = 0x00000200,
757 POWERPC_FLAG_PMM = 0x00000400,
758 /* Flag for special features */
759 /* Decrementer clock */
760 POWERPC_FLAG_BUS_CLK = 0x00020000,
761 /* Has CFAR */
762 POWERPC_FLAG_CFAR = 0x00040000,
763 /* Has VSX */
764 POWERPC_FLAG_VSX = 0x00080000,
765 /* Has Transaction Memory (ISA 2.07) */
766 POWERPC_FLAG_TM = 0x00100000,
767 /* Has SCV (ISA 3.00) */
768 POWERPC_FLAG_SCV = 0x00200000,
769 /* Has >1 thread per core */
770 POWERPC_FLAG_SMT = 0x00400000,
771 /* Using "LPAR per core" mode (as opposed to per-thread) */
772 POWERPC_FLAG_SMT_1LPAR = 0x00800000,
773 };
774
775 /*
776 * Bits for env->hflags.
777 *
778 * Most of these bits overlap with corresponding bits in MSR,
779 * but some come from other sources. Those that do come from
780 * the MSR are validated in hreg_compute_hflags.
781 */
782 enum {
783 HFLAGS_LE = 0, /* MSR_LE */
784 HFLAGS_HV = 1, /* computed from MSR_HV and other state */
785 HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */
786 HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */
787 HFLAGS_DR = 4, /* MSR_DR */
788 HFLAGS_HR = 5, /* computed from SPR_LPCR[HR] */
789 HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
790 HFLAGS_TM = 8, /* computed from MSR_TM */
791 HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */
792 HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */
793 HFLAGS_FP = 13, /* MSR_FP */
794 HFLAGS_PR = 14, /* MSR_PR */
795 HFLAGS_PMCC0 = 15, /* MMCR0 PMCC bit 0 */
796 HFLAGS_PMCC1 = 16, /* MMCR0 PMCC bit 1 */
797 HFLAGS_PMCJCE = 17, /* MMCR0 PMCjCE bit */
798 HFLAGS_PMC_OTHER = 18, /* PMC other than PMC5-6 is enabled */
799 HFLAGS_INSN_CNT = 19, /* PMU instruction count enabled */
800 HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
801 HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */
802
803 HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */
804 HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */
805 };
806
807 /*****************************************************************************/
808 /* Floating point status and control register */
809 #define FPSCR_DRN2 PPC_BIT_NR(29) /* Decimal Floating-Point rounding ctrl. */
810 #define FPSCR_DRN1 PPC_BIT_NR(30) /* Decimal Floating-Point rounding ctrl. */
811 #define FPSCR_DRN0 PPC_BIT_NR(31) /* Decimal Floating-Point rounding ctrl. */
812 #define FPSCR_FX PPC_BIT_NR(32) /* Floating-point exception summary */
813 #define FPSCR_FEX PPC_BIT_NR(33) /* Floating-point enabled exception summ.*/
814 #define FPSCR_VX PPC_BIT_NR(34) /* Floating-point invalid op. excp. summ.*/
815 #define FPSCR_OX PPC_BIT_NR(35) /* Floating-point overflow exception */
816 #define FPSCR_UX PPC_BIT_NR(36) /* Floating-point underflow exception */
817 #define FPSCR_ZX PPC_BIT_NR(37) /* Floating-point zero divide exception */
818 #define FPSCR_XX PPC_BIT_NR(38) /* Floating-point inexact exception */
819 #define FPSCR_VXSNAN PPC_BIT_NR(39) /* Floating-point invalid op. excp (sNan)*/
820 #define FPSCR_VXISI PPC_BIT_NR(40) /* Floating-point invalid op. excp (inf) */
821 #define FPSCR_VXIDI PPC_BIT_NR(41) /* Floating-point invalid op. excp (inf) */
822 #define FPSCR_VXZDZ PPC_BIT_NR(42) /* Floating-point invalid op. excp (zero)*/
823 #define FPSCR_VXIMZ PPC_BIT_NR(43) /* Floating-point invalid op. excp (inf) */
824 #define FPSCR_VXVC PPC_BIT_NR(44) /* Floating-point invalid op. excp (comp)*/
825 #define FPSCR_FR PPC_BIT_NR(45) /* Floating-point fraction rounded */
826 #define FPSCR_FI PPC_BIT_NR(46) /* Floating-point fraction inexact */
827 #define FPSCR_C PPC_BIT_NR(47) /* Floating-point result class descriptor*/
828 #define FPSCR_FL PPC_BIT_NR(48) /* Floating-point less than or negative */
829 #define FPSCR_FG PPC_BIT_NR(49) /* Floating-point greater than or neg. */
830 #define FPSCR_FE PPC_BIT_NR(50) /* Floating-point equal or zero */
831 #define FPSCR_FU PPC_BIT_NR(51) /* Floating-point unordered or NaN */
832 #define FPSCR_FPCC PPC_BIT_NR(51) /* Floating-point condition code */
833 #define FPSCR_FPRF PPC_BIT_NR(51) /* Floating-point result flags */
834 #define FPSCR_VXSOFT PPC_BIT_NR(53) /* Floating-point invalid op. excp (soft)*/
835 #define FPSCR_VXSQRT PPC_BIT_NR(54) /* Floating-point invalid op. excp (sqrt)*/
836 #define FPSCR_VXCVI PPC_BIT_NR(55) /* Floating-point invalid op. excp (int) */
837 #define FPSCR_VE PPC_BIT_NR(56) /* Floating-point invalid op. excp enable*/
838 #define FPSCR_OE PPC_BIT_NR(57) /* Floating-point overflow excp. enable */
839 #define FPSCR_UE PPC_BIT_NR(58) /* Floating-point underflow excp. enable */
840 #define FPSCR_ZE PPC_BIT_NR(59) /* Floating-point zero divide excp enable*/
841 #define FPSCR_XE PPC_BIT_NR(60) /* Floating-point inexact excp. enable */
842 #define FPSCR_NI PPC_BIT_NR(61) /* Floating-point non-IEEE mode */
843 #define FPSCR_RN1 PPC_BIT_NR(62)
844 #define FPSCR_RN0 PPC_BIT_NR(63) /* Floating-point rounding control */
845 /* Invalid operation exception summary */
846 #define FPSCR_IX ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
847 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
848 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
849 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
850 (1 << FPSCR_VXCVI))
851
852 FIELD(FPSCR, FI, FPSCR_FI, 1)
853
854 #define FP_DRN2 (1ull << FPSCR_DRN2)
855 #define FP_DRN1 (1ull << FPSCR_DRN1)
856 #define FP_DRN0 (1ull << FPSCR_DRN0)
857 #define FP_DRN (FP_DRN2 | FP_DRN1 | FP_DRN0)
858 #define FP_FX (1ull << FPSCR_FX)
859 #define FP_FEX (1ull << FPSCR_FEX)
860 #define FP_VX (1ull << FPSCR_VX)
861 #define FP_OX (1ull << FPSCR_OX)
862 #define FP_UX (1ull << FPSCR_UX)
863 #define FP_ZX (1ull << FPSCR_ZX)
864 #define FP_XX (1ull << FPSCR_XX)
865 #define FP_VXSNAN (1ull << FPSCR_VXSNAN)
866 #define FP_VXISI (1ull << FPSCR_VXISI)
867 #define FP_VXIDI (1ull << FPSCR_VXIDI)
868 #define FP_VXZDZ (1ull << FPSCR_VXZDZ)
869 #define FP_VXIMZ (1ull << FPSCR_VXIMZ)
870 #define FP_VXVC (1ull << FPSCR_VXVC)
871 #define FP_FR (1ull << FPSCR_FR)
872 #define FP_FI (1ull << FPSCR_FI)
873 #define FP_C (1ull << FPSCR_C)
874 #define FP_FL (1ull << FPSCR_FL)
875 #define FP_FG (1ull << FPSCR_FG)
876 #define FP_FE (1ull << FPSCR_FE)
877 #define FP_FU (1ull << FPSCR_FU)
878 #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
879 #define FP_FPRF (FP_C | FP_FPCC)
880 #define FP_VXSOFT (1ull << FPSCR_VXSOFT)
881 #define FP_VXSQRT (1ull << FPSCR_VXSQRT)
882 #define FP_VXCVI (1ull << FPSCR_VXCVI)
883 #define FP_VE (1ull << FPSCR_VE)
884 #define FP_OE (1ull << FPSCR_OE)
885 #define FP_UE (1ull << FPSCR_UE)
886 #define FP_ZE (1ull << FPSCR_ZE)
887 #define FP_XE (1ull << FPSCR_XE)
888 #define FP_NI (1ull << FPSCR_NI)
889 #define FP_RN1 (1ull << FPSCR_RN1)
890 #define FP_RN0 (1ull << FPSCR_RN0)
891 #define FP_RN (FP_RN1 | FP_RN0)
892
893 #define FP_ENABLES (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
894 #define FP_STATUS (FP_FR | FP_FI | FP_FPRF)
895
896 /* the exception bits which can be cleared by mcrfs - includes FX */
897 #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
898 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
899 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
900 FP_VXSQRT | FP_VXCVI)
901
902 /* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */
903 #define FPSCR_MTFS_MASK (~(MAKE_64BIT_MASK(36, 28) | PPC_BIT(28) | \
904 FP_FEX | FP_VX | PPC_BIT(52)))
905
906 /*****************************************************************************/
907 /* Vector status and control register */
908 #define VSCR_NJ 16 /* Vector non-java */
909 #define VSCR_SAT 0 /* Vector saturation */
910
911 /*****************************************************************************/
912 /* BookE e500 MMU registers */
913
914 #define MAS0_NV_SHIFT 0
915 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
916
917 #define MAS0_WQ_SHIFT 12
918 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
919 /* Write TLB entry regardless of reservation */
920 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
921 /* Write TLB entry only already in use */
922 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
923 /* Clear TLB entry */
924 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
925
926 #define MAS0_HES_SHIFT 14
927 #define MAS0_HES (1 << MAS0_HES_SHIFT)
928
929 #define MAS0_ESEL_SHIFT 16
930 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
931
932 #define MAS0_TLBSEL_SHIFT 28
933 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
934 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
935 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
936 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
937 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
938
939 #define MAS0_ATSEL_SHIFT 31
940 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
941 #define MAS0_ATSEL_TLB 0
942 #define MAS0_ATSEL_LRAT MAS0_ATSEL
943
944 #define MAS1_TSIZE_SHIFT 7
945 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
946
947 #define MAS1_TS_SHIFT 12
948 #define MAS1_TS (1 << MAS1_TS_SHIFT)
949
950 #define MAS1_IND_SHIFT 13
951 #define MAS1_IND (1 << MAS1_IND_SHIFT)
952
953 #define MAS1_TID_SHIFT 16
954 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
955
956 #define MAS1_IPROT_SHIFT 30
957 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
958
959 #define MAS1_VALID_SHIFT 31
960 #define MAS1_VALID 0x80000000
961
962 #define MAS2_EPN_SHIFT 12
963 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
964
965 #define MAS2_ACM_SHIFT 6
966 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
967
968 #define MAS2_VLE_SHIFT 5
969 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
970
971 #define MAS2_W_SHIFT 4
972 #define MAS2_W (1 << MAS2_W_SHIFT)
973
974 #define MAS2_I_SHIFT 3
975 #define MAS2_I (1 << MAS2_I_SHIFT)
976
977 #define MAS2_M_SHIFT 2
978 #define MAS2_M (1 << MAS2_M_SHIFT)
979
980 #define MAS2_G_SHIFT 1
981 #define MAS2_G (1 << MAS2_G_SHIFT)
982
983 #define MAS2_E_SHIFT 0
984 #define MAS2_E (1 << MAS2_E_SHIFT)
985
986 #define MAS3_RPN_SHIFT 12
987 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
988
989 #define MAS3_U0 0x00000200
990 #define MAS3_U1 0x00000100
991 #define MAS3_U2 0x00000080
992 #define MAS3_U3 0x00000040
993 #define MAS3_UX 0x00000020
994 #define MAS3_SX 0x00000010
995 #define MAS3_UW 0x00000008
996 #define MAS3_SW 0x00000004
997 #define MAS3_UR 0x00000002
998 #define MAS3_SR 0x00000001
999 #define MAS3_SPSIZE_SHIFT 1
1000 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
1001
1002 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
1003 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
1004 #define MAS4_TIDSELD_MASK 0x00030000
1005 #define MAS4_TIDSELD_PID0 0x00000000
1006 #define MAS4_TIDSELD_PID1 0x00010000
1007 #define MAS4_TIDSELD_PID2 0x00020000
1008 #define MAS4_TIDSELD_PIDZ 0x00030000
1009 #define MAS4_INDD 0x00008000 /* Default IND */
1010 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
1011 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
1012 #define MAS4_ACMD 0x00000040
1013 #define MAS4_VLED 0x00000020
1014 #define MAS4_WD 0x00000010
1015 #define MAS4_ID 0x00000008
1016 #define MAS4_MD 0x00000004
1017 #define MAS4_GD 0x00000002
1018 #define MAS4_ED 0x00000001
1019 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
1020 #define MAS4_WIMGED_SHIFT 0
1021
1022 #define MAS5_SGS 0x80000000
1023 #define MAS5_SLPID_MASK 0x00000fff
1024
1025 #define MAS6_SPID0 0x3fff0000
1026 #define MAS6_SPID1 0x00007ffe
1027 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
1028 #define MAS6_SAS 0x00000001
1029 #define MAS6_SPID MAS6_SPID0
1030 #define MAS6_SIND 0x00000002 /* Indirect page */
1031 #define MAS6_SIND_SHIFT 1
1032 #define MAS6_SPID_MASK 0x3fff0000
1033 #define MAS6_SPID_SHIFT 16
1034 #define MAS6_ISIZE_MASK 0x00000f80
1035 #define MAS6_ISIZE_SHIFT 7
1036
1037 #define MAS7_RPN 0xffffffff
1038
1039 #define MAS8_TGS 0x80000000
1040 #define MAS8_VF 0x40000000
1041 #define MAS8_TLBPID 0x00000fff
1042
1043 /* Bit definitions for MMUCFG */
1044 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
1045 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
1046 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
1047 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
1048 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
1049 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
1050 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
1051 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
1052 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
1053
1054 /* Bit definitions for MMUCSR0 */
1055 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
1056 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
1057 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
1058 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
1059 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
1060 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
1061 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
1062 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
1063 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
1064 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
1065
1066 /* TLBnCFG encoding */
1067 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
1068 #define TLBnCFG_HES 0x00002000 /* HW select supported */
1069 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
1070 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
1071 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
1072 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
1073 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
1074 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
1075 #define TLBnCFG_MINSIZE_SHIFT 20
1076 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
1077 #define TLBnCFG_MAXSIZE_SHIFT 16
1078 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
1079 #define TLBnCFG_ASSOC_SHIFT 24
1080
1081 /* TLBnPS encoding */
1082 #define TLBnPS_4K 0x00000004
1083 #define TLBnPS_8K 0x00000008
1084 #define TLBnPS_16K 0x00000010
1085 #define TLBnPS_32K 0x00000020
1086 #define TLBnPS_64K 0x00000040
1087 #define TLBnPS_128K 0x00000080
1088 #define TLBnPS_256K 0x00000100
1089 #define TLBnPS_512K 0x00000200
1090 #define TLBnPS_1M 0x00000400
1091 #define TLBnPS_2M 0x00000800
1092 #define TLBnPS_4M 0x00001000
1093 #define TLBnPS_8M 0x00002000
1094 #define TLBnPS_16M 0x00004000
1095 #define TLBnPS_32M 0x00008000
1096 #define TLBnPS_64M 0x00010000
1097 #define TLBnPS_128M 0x00020000
1098 #define TLBnPS_256M 0x00040000
1099 #define TLBnPS_512M 0x00080000
1100 #define TLBnPS_1G 0x00100000
1101 #define TLBnPS_2G 0x00200000
1102 #define TLBnPS_4G 0x00400000
1103 #define TLBnPS_8G 0x00800000
1104 #define TLBnPS_16G 0x01000000
1105 #define TLBnPS_32G 0x02000000
1106 #define TLBnPS_64G 0x04000000
1107 #define TLBnPS_128G 0x08000000
1108 #define TLBnPS_256G 0x10000000
1109
1110 /* tlbilx action encoding */
1111 #define TLBILX_T_ALL 0
1112 #define TLBILX_T_TID 1
1113 #define TLBILX_T_FULLMATCH 3
1114 #define TLBILX_T_CLASS0 4
1115 #define TLBILX_T_CLASS1 5
1116 #define TLBILX_T_CLASS2 6
1117 #define TLBILX_T_CLASS3 7
1118
1119 /* BookE 2.06 helper defines */
1120
1121 #define BOOKE206_FLUSH_TLB0 (1 << 0)
1122 #define BOOKE206_FLUSH_TLB1 (1 << 1)
1123 #define BOOKE206_FLUSH_TLB2 (1 << 2)
1124 #define BOOKE206_FLUSH_TLB3 (1 << 3)
1125
1126 /* number of possible TLBs */
1127 #define BOOKE206_MAX_TLBN 4
1128
1129 #define EPID_EPID_SHIFT 0x0
1130 #define EPID_EPID 0xFF
1131 #define EPID_ELPID_SHIFT 0x10
1132 #define EPID_ELPID 0x3F0000
1133 #define EPID_EGS 0x20000000
1134 #define EPID_EGS_SHIFT 29
1135 #define EPID_EAS 0x40000000
1136 #define EPID_EAS_SHIFT 30
1137 #define EPID_EPR 0x80000000
1138 #define EPID_EPR_SHIFT 31
1139 /* We don't support EGS and ELPID */
1140 #define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
1141
1142 /*****************************************************************************/
1143 /* Server and Embedded Processor Control */
1144
1145 #define DBELL_TYPE_SHIFT 27
1146 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
1147 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
1148 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
1149 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
1150 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
1151 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
1152
1153 #define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT)
1154
1155 #define DBELL_BRDCAST PPC_BIT(37)
1156 #define DBELL_LPIDTAG_SHIFT 14
1157 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
1158 #define DBELL_PIRTAG_MASK 0x3fff
1159
1160 #define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
1161
1162 #define PPC_PAGE_SIZES_MAX_SZ 8
1163
1164 struct ppc_radix_page_info {
1165 uint32_t count;
1166 uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
1167 };
1168
1169 /*****************************************************************************/
1170 /* Dynamic Execution Control Register */
1171
1172 #define DEXCR_ASPECT(name, num) \
1173 FIELD(DEXCR, PNH_##name, PPC_BIT_NR(num), 1) \
1174 FIELD(DEXCR, PRO_##name, PPC_BIT_NR(num + 32), 1) \
1175 FIELD(HDEXCR, HNU_##name, PPC_BIT_NR(num), 1) \
1176 FIELD(HDEXCR, ENF_##name, PPC_BIT_NR(num + 32), 1) \
1177
1178 DEXCR_ASPECT(SBHE, 0)
1179 DEXCR_ASPECT(IBRTPD, 1)
1180 DEXCR_ASPECT(SRAPD, 4)
1181 DEXCR_ASPECT(NPHIE, 5)
1182 DEXCR_ASPECT(PHIE, 6)
1183
1184 /*****************************************************************************/
1185 /* PowerNV ChipTOD and TimeBase State Machine */
1186 struct pnv_tod_tbst {
1187 int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */
1188 int tod_sent_to_tb; /* chiptod sent TOD to the core TB */
1189
1190 /*
1191 * "Timers" for async TBST events are simulated by mfTFAC because TFAC
1192 * is polled for such events. These are just used to ensure firmware
1193 * performs the polling at least a few times.
1194 */
1195 int tb_state_timer;
1196 int tb_sync_pulse_timer;
1197 };
1198
1199 /*****************************************************************************/
1200 /* The whole PowerPC CPU context */
1201
1202 /*
1203 * PowerPC needs eight modes for different hypervisor/supervisor/guest
1204 * + real/paged mode combinations. The other two modes are for
1205 * external PID load/store.
1206 */
1207 #define PPC_TLB_EPID_LOAD 8
1208 #define PPC_TLB_EPID_STORE 9
1209
1210 #define PPC_CPU_OPCODES_LEN 0x40
1211 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
1212
1213 struct CPUArchState {
1214 /* Most commonly used resources during translated code execution first */
1215 target_ulong gpr[32]; /* general purpose registers */
1216 target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
1217 target_ulong lr;
1218 target_ulong ctr;
1219 uint32_t crf[8]; /* condition register */
1220 #if defined(TARGET_PPC64)
1221 target_ulong cfar;
1222 #endif
1223 target_ulong xer; /* XER (with SO, OV, CA split out) */
1224 target_ulong so;
1225 target_ulong ov;
1226 target_ulong ca;
1227 target_ulong ov32;
1228 target_ulong ca32;
1229
1230 target_ulong reserve_addr; /* Reservation address */
1231 target_ulong reserve_length; /* Reservation larx op size (bytes) */
1232 target_ulong reserve_val; /* Reservation value */
1233 #if defined(TARGET_PPC64)
1234 target_ulong reserve_val2;
1235 #endif
1236
1237 /* These are used in supervisor mode only */
1238 target_ulong msr; /* machine state register */
1239 target_ulong tgpr[4]; /* temporary general purpose registers, */
1240 /* used to speed-up TLB assist handlers */
1241
1242 target_ulong nip; /* next instruction pointer */
1243
1244 /* when a memory exception occurs, the access type is stored here */
1245 int access_type;
1246
1247 #if !defined(CONFIG_USER_ONLY)
1248 /* MMU context, only relevant for full system emulation */
1249 #if defined(TARGET_PPC64)
1250 ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
1251 struct CPUBreakpoint *ciabr_breakpoint;
1252 struct CPUWatchpoint *dawr0_watchpoint;
1253 #endif
1254 target_ulong sr[32]; /* segment registers */
1255 uint32_t nb_BATs; /* number of BATs */
1256 target_ulong DBAT[2][8];
1257 target_ulong IBAT[2][8];
1258 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1259 int32_t nb_tlb; /* Total number of TLB */
1260 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1261 int nb_ways; /* Number of ways in the TLB set */
1262 int last_way; /* Last used way used to allocate TLB in a LRU way */
1263 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1264 int nb_pids; /* Number of available PID registers */
1265 int tlb_type; /* Type of TLB we're dealing with */
1266 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
1267 #ifdef CONFIG_KVM
1268 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1269 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1270 #endif /* CONFIG_KVM */
1271 uint32_t tlb_need_flush; /* Delayed flush needed */
1272 #define TLB_NEED_LOCAL_FLUSH 0x1
1273 #define TLB_NEED_GLOBAL_FLUSH 0x2
1274
1275 #if defined(TARGET_PPC64)
1276 /* PowerNV chiptod / timebase facility state. */
1277 /* Would be nice to put these into PnvCore */
1278 struct pnv_tod_tbst pnv_tod_tbst;
1279 #endif
1280 #endif
1281
1282 /* Other registers */
1283 target_ulong spr[1024]; /* special purpose registers */
1284 ppc_spr_t spr_cb[1024];
1285 /* Composite status for PMC[1-6] enabled and counting insns or cycles. */
1286 uint8_t pmc_ins_cnt;
1287 uint8_t pmc_cyc_cnt;
1288 /* Vector status and control register, minus VSCR_SAT */
1289 uint32_t vscr;
1290 /* VSX registers (including FP and AVR) */
1291 ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1292 /* Non-zero if and only if VSCR_SAT should be set */
1293 ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
1294 /* SPE registers */
1295 uint64_t spe_acc;
1296 uint32_t spe_fscr;
1297 /* SPE and Altivec share status as they'll never be used simultaneously */
1298 float_status vec_status;
1299 float_status fp_status; /* Floating point execution context */
1300 target_ulong fpscr; /* Floating point status and control register */
1301
1302 /* Internal devices resources */
1303 ppc_tb_t *tb_env; /* Time base and decrementer */
1304 ppc_dcr_t *dcr_env; /* Device control registers */
1305
1306 int dcache_line_size;
1307 int icache_line_size;
1308
1309 /* These resources are used during exception processing */
1310 /* CPU model definition */
1311 target_ulong msr_mask;
1312 powerpc_mmu_t mmu_model;
1313 powerpc_excp_t excp_model;
1314 powerpc_input_t bus_model;
1315 int bfd_mach;
1316 uint32_t flags;
1317 uint64_t insns_flags;
1318 uint64_t insns_flags2;
1319
1320 int error_code;
1321 uint32_t pending_interrupts;
1322 #if !defined(CONFIG_USER_ONLY)
1323 uint64_t excp_stats[POWERPC_EXCP_NB];
1324 /*
1325 * This is the IRQ controller, which is implementation dependent and only
1326 * relevant when emulating a complete machine. Note that this isn't used
1327 * by recent Book3s compatible CPUs (POWER7 and newer).
1328 */
1329 uint32_t irq_input_state;
1330
1331 target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
1332 target_ulong excp_prefix;
1333 target_ulong ivor_mask;
1334 target_ulong ivpr_mask;
1335 target_ulong hreset_vector;
1336 hwaddr mpic_iack;
1337 bool mpic_proxy; /* true if the external proxy facility mode is enabled */
1338 bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */
1339 /* instructions and SPRs are diallowed if MSR:HV is 0 */
1340 /*
1341 * On P7/P8/P9, set when in PM state so we need to handle resume in a
1342 * special way (such as routing some resume causes to 0x100, i.e. sreset).
1343 */
1344 bool resume_as_sreset;
1345 #endif
1346
1347 /* These resources are used only in TCG */
1348 uint32_t hflags;
1349 target_ulong hflags_compat_nmsr; /* for migration compatibility */
1350
1351 /* Power management */
1352 int (*check_pow)(CPUPPCState *env);
1353
1354 #if !defined(CONFIG_USER_ONLY)
1355 void *load_info; /* holds boot loading state */
1356 #endif
1357
1358 /* booke timers */
1359
1360 /*
1361 * Specifies bit locations of the Time Base used to signal a fixed timer
1362 * exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
1363 *
1364 * 0 selects the least significant bit, 63 selects the most significant bit
1365 */
1366 uint8_t fit_period[4];
1367 uint8_t wdt_period[4];
1368
1369 /* Transactional memory state */
1370 target_ulong tm_gpr[32];
1371 ppc_avr_t tm_vsr[64];
1372 uint64_t tm_cr;
1373 uint64_t tm_lr;
1374 uint64_t tm_ctr;
1375 uint64_t tm_fpscr;
1376 uint64_t tm_amr;
1377 uint64_t tm_ppr;
1378 uint64_t tm_vrsave;
1379 uint32_t tm_vscr;
1380 uint64_t tm_dscr;
1381 uint64_t tm_tar;
1382
1383 /*
1384 * Timers used to fire performance monitor alerts
1385 * when counting cycles.
1386 */
1387 QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM];
1388
1389 /*
1390 * PMU base time value used by the PMU to calculate
1391 * running cycles.
1392 */
1393 uint64_t pmu_base_time;
1394 };
1395
1396 #define _CORE_ID(cs) \
1397 (POWERPC_CPU(cs)->env.spr_cb[SPR_PIR].default_value & ~(cs->nr_threads - 1))
1398
1399 #define THREAD_SIBLING_FOREACH(cs, cs_sibling) \
1400 CPU_FOREACH(cs_sibling) \
1401 if (_CORE_ID(cs) == _CORE_ID(cs_sibling))
1402
1403 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1404 do { \
1405 env->fit_period[0] = (a_); \
1406 env->fit_period[1] = (b_); \
1407 env->fit_period[2] = (c_); \
1408 env->fit_period[3] = (d_); \
1409 } while (0)
1410
1411 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1412 do { \
1413 env->wdt_period[0] = (a_); \
1414 env->wdt_period[1] = (b_); \
1415 env->wdt_period[2] = (c_); \
1416 env->wdt_period[3] = (d_); \
1417 } while (0)
1418
1419 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1420 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1421
1422 /**
1423 * PowerPCCPU:
1424 * @env: #CPUPPCState
1425 * @vcpu_id: vCPU identifier given to KVM
1426 * @compat_pvr: Current logical PVR, zero if in "raw" mode
1427 *
1428 * A PowerPC CPU.
1429 */
1430 struct ArchCPU {
1431 CPUState parent_obj;
1432
1433 CPUPPCState env;
1434
1435 int vcpu_id;
1436 uint32_t compat_pvr;
1437 PPCVirtualHypervisor *vhyp;
1438 void *machine_data;
1439 int32_t node_id; /* NUMA node this CPU belongs to */
1440 PPCHash64Options *hash64_opts;
1441
1442 /* Those resources are used only during code translation */
1443 /* opcode handlers */
1444 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1445
1446 /* Fields related to migration compatibility hacks */
1447 bool pre_2_8_migration;
1448 target_ulong mig_msr_mask;
1449 uint64_t mig_insns_flags;
1450 uint64_t mig_insns_flags2;
1451 uint32_t mig_nb_BATs;
1452 bool pre_2_10_migration;
1453 bool pre_3_0_migration;
1454 int32_t mig_slb_nr;
1455 };
1456
1457 /**
1458 * PowerPCCPUClass:
1459 * @parent_realize: The parent class' realize handler.
1460 * @parent_phases: The parent class' reset phase handlers.
1461 *
1462 * A PowerPC CPU model.
1463 */
1464 struct PowerPCCPUClass {
1465 CPUClass parent_class;
1466
1467 DeviceRealize parent_realize;
1468 DeviceUnrealize parent_unrealize;
1469 ResettablePhases parent_phases;
1470 void (*parent_parse_features)(const char *type, char *str, Error **errp);
1471
1472 uint32_t pvr;
1473 /*
1474 * If @best is false, match if pcc is in the family of pvr
1475 * Else match only if pcc is the best match for pvr in this family.
1476 */
1477 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best);
1478 uint64_t pcr_mask; /* Available bits in PCR register */
1479 uint64_t pcr_supported; /* Bits for supported PowerISA versions */
1480 uint32_t svr;
1481 uint64_t insns_flags;
1482 uint64_t insns_flags2;
1483 uint64_t msr_mask;
1484 uint64_t lpcr_mask; /* Available bits in the LPCR */
1485 uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
1486 powerpc_mmu_t mmu_model;
1487 powerpc_excp_t excp_model;
1488 powerpc_input_t bus_model;
1489 uint32_t flags;
1490 int bfd_mach;
1491 uint32_t l1_dcache_size, l1_icache_size;
1492 #ifndef CONFIG_USER_ONLY
1493 GDBFeature gdb_spr;
1494 #endif
1495 const PPCHash64Options *hash64_opts;
1496 struct ppc_radix_page_info *radix_page_info;
1497 uint32_t lrg_decr_bits;
1498 int n_host_threads;
1499 void (*init_proc)(CPUPPCState *env);
1500 int (*check_pow)(CPUPPCState *env);
1501 };
1502
1503 ObjectClass *ppc_cpu_class_by_name(const char *name);
1504 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1505 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1506 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1507
1508 #ifndef CONFIG_USER_ONLY
1509 struct PPCVirtualHypervisorClass {
1510 InterfaceClass parent;
1511 bool (*cpu_in_nested)(PowerPCCPU *cpu);
1512 void (*deliver_hv_excp)(PowerPCCPU *cpu, int excp);
1513 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1514 hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1515 const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1516 hwaddr ptex, int n);
1517 void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1518 const ppc_hash_pte64_t *hptes,
1519 hwaddr ptex, int n);
1520 void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1521 void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1522 bool (*get_pate)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
1523 target_ulong lpid, ppc_v3_pate_t *entry);
1524 target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1525 void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1526 void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1527 };
1528
1529 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor,PPCVirtualHypervisorClass,PPC_VIRTUAL_HYPERVISOR,TYPE_PPC_VIRTUAL_HYPERVISOR)1530 DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass,
1531 PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR)
1532
1533 static inline bool vhyp_cpu_in_nested(PowerPCCPU *cpu)
1534 {
1535 return PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp)->cpu_in_nested(cpu);
1536 }
1537 #endif /* CONFIG_USER_ONLY */
1538
1539 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
1540 int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1541 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
1542 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1543 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1544 #ifndef CONFIG_USER_ONLY
1545 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1546 #endif
1547 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1548 int cpuid, DumpState *s);
1549 int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1550 int cpuid, DumpState *s);
1551 #ifndef CONFIG_USER_ONLY
1552 void ppc_maybe_interrupt(CPUPPCState *env);
1553 void ppc_cpu_do_interrupt(CPUState *cpu);
1554 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1555 void ppc_cpu_do_system_reset(CPUState *cs);
1556 void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
1557 extern const VMStateDescription vmstate_ppc_cpu;
1558 #endif
1559
1560 /*****************************************************************************/
1561 void ppc_translate_init(void);
1562
1563 #if !defined(CONFIG_USER_ONLY)
1564 void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
1565 void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
1566 void ppc_update_ciabr(CPUPPCState *env);
1567 void ppc_store_ciabr(CPUPPCState *env, target_ulong value);
1568 void ppc_update_daw0(CPUPPCState *env);
1569 void ppc_store_dawr0(CPUPPCState *env, target_ulong value);
1570 void ppc_store_dawrx0(CPUPPCState *env, uint32_t value);
1571 #endif /* !defined(CONFIG_USER_ONLY) */
1572 void ppc_store_msr(CPUPPCState *env, target_ulong value);
1573
1574 void ppc_cpu_list(void);
1575
1576 /* Time-base and decrementer management */
1577 uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
1578 uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
1579 void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
1580 void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
1581 uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
1582 uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
1583 void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
1584 void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
1585 void cpu_ppc_increase_tb_by_offset(CPUPPCState *env, int64_t offset);
1586 void cpu_ppc_decrease_tb_by_offset(CPUPPCState *env, int64_t offset);
1587 uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
1588 void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
1589 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1590 target_ulong cpu_ppc_load_decr(CPUPPCState *env);
1591 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
1592 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
1593 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
1594 void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
1595 uint64_t cpu_ppc_load_purr(CPUPPCState *env);
1596 void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
1597 #if !defined(CONFIG_USER_ONLY)
1598 target_ulong load_40x_pit(CPUPPCState *env);
1599 void store_40x_pit(CPUPPCState *env, target_ulong val);
1600 void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
1601 void store_40x_sler(CPUPPCState *env, uint32_t val);
1602 void store_40x_tcr(CPUPPCState *env, target_ulong val);
1603 void store_40x_tsr(CPUPPCState *env, target_ulong val);
1604 void store_booke_tcr(CPUPPCState *env, target_ulong val);
1605 void store_booke_tsr(CPUPPCState *env, target_ulong val);
1606 void ppc_tlb_invalidate_all(CPUPPCState *env);
1607 void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
1608 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1609 void cpu_ppc_set_1lpar(PowerPCCPU *cpu);
1610 int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, hwaddr *raddrp,
1611 target_ulong address, uint32_t pid);
1612 int ppcemb_tlb_search(CPUPPCState *env, target_ulong address, uint32_t pid);
1613 hwaddr booke206_tlb_to_page_size(CPUPPCState *env, ppcmas_tlb_t *tlb);
1614 #endif
1615
1616 void ppc_store_fpscr(CPUPPCState *env, target_ulong val);
1617 void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
1618 const char *caller, uint32_t cause);
1619
ppc_dump_gpr(CPUPPCState * env,int gprn)1620 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1621 {
1622 uint64_t gprv;
1623
1624 gprv = env->gpr[gprn];
1625 if (env->flags & POWERPC_FLAG_SPE) {
1626 /*
1627 * If the CPU implements the SPE extension, we have to get the
1628 * high bits of the GPR from the gprh storage area
1629 */
1630 gprv &= 0xFFFFFFFFULL;
1631 gprv |= (uint64_t)env->gprh[gprn] << 32;
1632 }
1633
1634 return gprv;
1635 }
1636
1637 /* Device control registers */
1638 int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1639 int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1640
1641 #define cpu_list ppc_cpu_list
1642
1643 /* MMU modes definitions */
1644 #define MMU_USER_IDX 0
ppc_env_mmu_index(CPUPPCState * env,bool ifetch)1645 static inline int ppc_env_mmu_index(CPUPPCState *env, bool ifetch)
1646 {
1647 #ifdef CONFIG_USER_ONLY
1648 return MMU_USER_IDX;
1649 #else
1650 return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
1651 #endif
1652 }
1653
1654 /* Compatibility modes */
1655 #if defined(TARGET_PPC64)
1656 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1657 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1658 bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1659 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1660
1661 int ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1662
1663 #if !defined(CONFIG_USER_ONLY)
1664 int ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1665 int ppc_init_compat_all(uint32_t compat_pvr, Error **errp);
1666 #endif
1667 int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1668 void ppc_compat_add_property(Object *obj, const char *name,
1669 uint32_t *compat_pvr, const char *basedesc);
1670 #endif /* defined(TARGET_PPC64) */
1671
1672 #include "exec/cpu-all.h"
1673
1674 /*****************************************************************************/
1675 /* CRF definitions */
1676 #define CRF_LT_BIT 3
1677 #define CRF_GT_BIT 2
1678 #define CRF_EQ_BIT 1
1679 #define CRF_SO_BIT 0
1680 #define CRF_LT (1 << CRF_LT_BIT)
1681 #define CRF_GT (1 << CRF_GT_BIT)
1682 #define CRF_EQ (1 << CRF_EQ_BIT)
1683 #define CRF_SO (1 << CRF_SO_BIT)
1684 /* For SPE extensions */
1685 #define CRF_CH (1 << CRF_LT_BIT)
1686 #define CRF_CL (1 << CRF_GT_BIT)
1687 #define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
1688 #define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1689
1690 /* XER definitions */
1691 #define XER_SO 31
1692 #define XER_OV 30
1693 #define XER_CA 29
1694 #define XER_OV32 19
1695 #define XER_CA32 18
1696 #define XER_CMP 8
1697 #define XER_BC 0
1698 #define xer_so (env->so)
1699 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1700 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1701
1702 /* SPR definitions */
1703 #define SPR_MQ (0x000)
1704 #define SPR_XER (0x001)
1705 #define SPR_LR (0x008)
1706 #define SPR_CTR (0x009)
1707 #define SPR_UAMR (0x00D)
1708 #define SPR_DSCR (0x011)
1709 #define SPR_DSISR (0x012)
1710 #define SPR_DAR (0x013)
1711 #define SPR_DECR (0x016)
1712 #define SPR_SDR1 (0x019)
1713 #define SPR_SRR0 (0x01A)
1714 #define SPR_SRR1 (0x01B)
1715 #define SPR_CFAR (0x01C)
1716 #define SPR_AMR (0x01D)
1717 #define SPR_ACOP (0x01F)
1718 #define SPR_BOOKE_PID (0x030)
1719 #define SPR_BOOKS_PID (0x030)
1720 #define SPR_BOOKE_DECAR (0x036)
1721 #define SPR_BOOKE_CSRR0 (0x03A)
1722 #define SPR_BOOKE_CSRR1 (0x03B)
1723 #define SPR_BOOKE_DEAR (0x03D)
1724 #define SPR_IAMR (0x03D)
1725 #define SPR_BOOKE_ESR (0x03E)
1726 #define SPR_BOOKE_IVPR (0x03F)
1727 #define SPR_MPC_EIE (0x050)
1728 #define SPR_MPC_EID (0x051)
1729 #define SPR_MPC_NRI (0x052)
1730 #define SPR_TFHAR (0x080)
1731 #define SPR_TFIAR (0x081)
1732 #define SPR_TEXASR (0x082)
1733 #define SPR_TEXASRU (0x083)
1734 #define SPR_UCTRL (0x088)
1735 #define SPR_TIDR (0x090)
1736 #define SPR_MPC_CMPA (0x090)
1737 #define SPR_MPC_CMPB (0x091)
1738 #define SPR_MPC_CMPC (0x092)
1739 #define SPR_MPC_CMPD (0x093)
1740 #define SPR_MPC_ECR (0x094)
1741 #define SPR_MPC_DER (0x095)
1742 #define SPR_MPC_COUNTA (0x096)
1743 #define SPR_MPC_COUNTB (0x097)
1744 #define SPR_CTRL (0x098)
1745 #define SPR_MPC_CMPE (0x098)
1746 #define SPR_MPC_CMPF (0x099)
1747 #define SPR_FSCR (0x099)
1748 #define SPR_MPC_CMPG (0x09A)
1749 #define SPR_MPC_CMPH (0x09B)
1750 #define SPR_MPC_LCTRL1 (0x09C)
1751 #define SPR_MPC_LCTRL2 (0x09D)
1752 #define SPR_UAMOR (0x09D)
1753 #define SPR_MPC_ICTRL (0x09E)
1754 #define SPR_MPC_BAR (0x09F)
1755 #define SPR_PSPB (0x09F)
1756 #define SPR_DPDES (0x0B0)
1757 #define SPR_DAWR0 (0x0B4)
1758 #define SPR_DAWR1 (0x0B5)
1759 #define SPR_RPR (0x0BA)
1760 #define SPR_CIABR (0x0BB)
1761 #define SPR_DAWRX0 (0x0BC)
1762 #define SPR_DAWRX1 (0x0BD)
1763 #define SPR_HFSCR (0x0BE)
1764 #define SPR_VRSAVE (0x100)
1765 #define SPR_USPRG0 (0x100)
1766 #define SPR_USPRG1 (0x101)
1767 #define SPR_USPRG2 (0x102)
1768 #define SPR_USPRG3 (0x103)
1769 #define SPR_USPRG4 (0x104)
1770 #define SPR_USPRG5 (0x105)
1771 #define SPR_USPRG6 (0x106)
1772 #define SPR_USPRG7 (0x107)
1773 #define SPR_TBL (0x10C)
1774 #define SPR_TBU (0x10D)
1775 #define SPR_SPRG0 (0x110)
1776 #define SPR_SPRG1 (0x111)
1777 #define SPR_SPRG2 (0x112)
1778 #define SPR_SPRG3 (0x113)
1779 #define SPR_SPRG4 (0x114)
1780 #define SPR_SCOMC (0x114)
1781 #define SPR_SPRG5 (0x115)
1782 #define SPR_SCOMD (0x115)
1783 #define SPR_SPRG6 (0x116)
1784 #define SPR_SPRG7 (0x117)
1785 #define SPR_ASR (0x118)
1786 #define SPR_EAR (0x11A)
1787 #define SPR_WR_TBL (0x11C)
1788 #define SPR_WR_TBU (0x11D)
1789 #define SPR_TBU40 (0x11E)
1790 #define SPR_SVR (0x11E)
1791 #define SPR_BOOKE_PIR (0x11E)
1792 #define SPR_PVR (0x11F)
1793 #define SPR_HSPRG0 (0x130)
1794 #define SPR_BOOKE_DBSR (0x130)
1795 #define SPR_HSPRG1 (0x131)
1796 #define SPR_HDSISR (0x132)
1797 #define SPR_HDAR (0x133)
1798 #define SPR_BOOKE_EPCR (0x133)
1799 #define SPR_SPURR (0x134)
1800 #define SPR_BOOKE_DBCR0 (0x134)
1801 #define SPR_IBCR (0x135)
1802 #define SPR_PURR (0x135)
1803 #define SPR_BOOKE_DBCR1 (0x135)
1804 #define SPR_DBCR (0x136)
1805 #define SPR_HDEC (0x136)
1806 #define SPR_BOOKE_DBCR2 (0x136)
1807 #define SPR_HIOR (0x137)
1808 #define SPR_MBAR (0x137)
1809 #define SPR_RMOR (0x138)
1810 #define SPR_BOOKE_IAC1 (0x138)
1811 #define SPR_HRMOR (0x139)
1812 #define SPR_BOOKE_IAC2 (0x139)
1813 #define SPR_HSRR0 (0x13A)
1814 #define SPR_BOOKE_IAC3 (0x13A)
1815 #define SPR_HSRR1 (0x13B)
1816 #define SPR_BOOKE_IAC4 (0x13B)
1817 #define SPR_BOOKE_DAC1 (0x13C)
1818 #define SPR_MMCRH (0x13C)
1819 #define SPR_DABR2 (0x13D)
1820 #define SPR_BOOKE_DAC2 (0x13D)
1821 #define SPR_TFMR (0x13D)
1822 #define SPR_BOOKE_DVC1 (0x13E)
1823 #define SPR_LPCR (0x13E)
1824 #define SPR_BOOKE_DVC2 (0x13F)
1825 #define SPR_LPIDR (0x13F)
1826 #define SPR_BOOKE_TSR (0x150)
1827 #define SPR_HMER (0x150)
1828 #define SPR_HMEER (0x151)
1829 #define SPR_PCR (0x152)
1830 #define SPR_HEIR (0x153)
1831 #define SPR_BOOKE_LPIDR (0x152)
1832 #define SPR_BOOKE_TCR (0x154)
1833 #define SPR_BOOKE_TLB0PS (0x158)
1834 #define SPR_BOOKE_TLB1PS (0x159)
1835 #define SPR_BOOKE_TLB2PS (0x15A)
1836 #define SPR_BOOKE_TLB3PS (0x15B)
1837 #define SPR_AMOR (0x15D)
1838 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1839 #define SPR_BOOKE_IVOR0 (0x190)
1840 #define SPR_BOOKE_IVOR1 (0x191)
1841 #define SPR_BOOKE_IVOR2 (0x192)
1842 #define SPR_BOOKE_IVOR3 (0x193)
1843 #define SPR_BOOKE_IVOR4 (0x194)
1844 #define SPR_BOOKE_IVOR5 (0x195)
1845 #define SPR_BOOKE_IVOR6 (0x196)
1846 #define SPR_BOOKE_IVOR7 (0x197)
1847 #define SPR_BOOKE_IVOR8 (0x198)
1848 #define SPR_BOOKE_IVOR9 (0x199)
1849 #define SPR_BOOKE_IVOR10 (0x19A)
1850 #define SPR_BOOKE_IVOR11 (0x19B)
1851 #define SPR_BOOKE_IVOR12 (0x19C)
1852 #define SPR_BOOKE_IVOR13 (0x19D)
1853 #define SPR_BOOKE_IVOR14 (0x19E)
1854 #define SPR_BOOKE_IVOR15 (0x19F)
1855 #define SPR_BOOKE_IVOR38 (0x1B0)
1856 #define SPR_BOOKE_IVOR39 (0x1B1)
1857 #define SPR_BOOKE_IVOR40 (0x1B2)
1858 #define SPR_BOOKE_IVOR41 (0x1B3)
1859 #define SPR_BOOKE_IVOR42 (0x1B4)
1860 #define SPR_BOOKE_GIVOR2 (0x1B8)
1861 #define SPR_BOOKE_GIVOR3 (0x1B9)
1862 #define SPR_BOOKE_GIVOR4 (0x1BA)
1863 #define SPR_BOOKE_GIVOR8 (0x1BB)
1864 #define SPR_BOOKE_GIVOR13 (0x1BC)
1865 #define SPR_BOOKE_GIVOR14 (0x1BD)
1866 #define SPR_TIR (0x1BE)
1867 #define SPR_UHDEXCR (0x1C7)
1868 #define SPR_PTCR (0x1D0)
1869 #define SPR_HASHKEYR (0x1D4)
1870 #define SPR_HASHPKEYR (0x1D5)
1871 #define SPR_HDEXCR (0x1D7)
1872 #define SPR_BOOKE_SPEFSCR (0x200)
1873 #define SPR_Exxx_BBEAR (0x201)
1874 #define SPR_Exxx_BBTAR (0x202)
1875 #define SPR_Exxx_L1CFG0 (0x203)
1876 #define SPR_Exxx_L1CFG1 (0x204)
1877 #define SPR_Exxx_NPIDR (0x205)
1878 #define SPR_ATBL (0x20E)
1879 #define SPR_ATBU (0x20F)
1880 #define SPR_IBAT0U (0x210)
1881 #define SPR_BOOKE_IVOR32 (0x210)
1882 #define SPR_RCPU_MI_GRA (0x210)
1883 #define SPR_IBAT0L (0x211)
1884 #define SPR_BOOKE_IVOR33 (0x211)
1885 #define SPR_IBAT1U (0x212)
1886 #define SPR_BOOKE_IVOR34 (0x212)
1887 #define SPR_IBAT1L (0x213)
1888 #define SPR_BOOKE_IVOR35 (0x213)
1889 #define SPR_IBAT2U (0x214)
1890 #define SPR_BOOKE_IVOR36 (0x214)
1891 #define SPR_IBAT2L (0x215)
1892 #define SPR_BOOKE_IVOR37 (0x215)
1893 #define SPR_IBAT3U (0x216)
1894 #define SPR_IBAT3L (0x217)
1895 #define SPR_DBAT0U (0x218)
1896 #define SPR_RCPU_L2U_GRA (0x218)
1897 #define SPR_DBAT0L (0x219)
1898 #define SPR_DBAT1U (0x21A)
1899 #define SPR_DBAT1L (0x21B)
1900 #define SPR_DBAT2U (0x21C)
1901 #define SPR_DBAT2L (0x21D)
1902 #define SPR_DBAT3U (0x21E)
1903 #define SPR_DBAT3L (0x21F)
1904 #define SPR_IBAT4U (0x230)
1905 #define SPR_RPCU_BBCMCR (0x230)
1906 #define SPR_MPC_IC_CST (0x230)
1907 #define SPR_Exxx_CTXCR (0x230)
1908 #define SPR_IBAT4L (0x231)
1909 #define SPR_MPC_IC_ADR (0x231)
1910 #define SPR_Exxx_DBCR3 (0x231)
1911 #define SPR_IBAT5U (0x232)
1912 #define SPR_MPC_IC_DAT (0x232)
1913 #define SPR_Exxx_DBCNT (0x232)
1914 #define SPR_IBAT5L (0x233)
1915 #define SPR_IBAT6U (0x234)
1916 #define SPR_IBAT6L (0x235)
1917 #define SPR_IBAT7U (0x236)
1918 #define SPR_IBAT7L (0x237)
1919 #define SPR_DBAT4U (0x238)
1920 #define SPR_RCPU_L2U_MCR (0x238)
1921 #define SPR_MPC_DC_CST (0x238)
1922 #define SPR_Exxx_ALTCTXCR (0x238)
1923 #define SPR_DBAT4L (0x239)
1924 #define SPR_MPC_DC_ADR (0x239)
1925 #define SPR_DBAT5U (0x23A)
1926 #define SPR_BOOKE_MCSRR0 (0x23A)
1927 #define SPR_MPC_DC_DAT (0x23A)
1928 #define SPR_DBAT5L (0x23B)
1929 #define SPR_BOOKE_MCSRR1 (0x23B)
1930 #define SPR_DBAT6U (0x23C)
1931 #define SPR_BOOKE_MCSR (0x23C)
1932 #define SPR_DBAT6L (0x23D)
1933 #define SPR_Exxx_MCAR (0x23D)
1934 #define SPR_DBAT7U (0x23E)
1935 #define SPR_BOOKE_DSRR0 (0x23E)
1936 #define SPR_DBAT7L (0x23F)
1937 #define SPR_BOOKE_DSRR1 (0x23F)
1938 #define SPR_BOOKE_SPRG8 (0x25C)
1939 #define SPR_BOOKE_SPRG9 (0x25D)
1940 #define SPR_BOOKE_MAS0 (0x270)
1941 #define SPR_BOOKE_MAS1 (0x271)
1942 #define SPR_BOOKE_MAS2 (0x272)
1943 #define SPR_BOOKE_MAS3 (0x273)
1944 #define SPR_BOOKE_MAS4 (0x274)
1945 #define SPR_BOOKE_MAS5 (0x275)
1946 #define SPR_BOOKE_MAS6 (0x276)
1947 #define SPR_BOOKE_PID1 (0x279)
1948 #define SPR_BOOKE_PID2 (0x27A)
1949 #define SPR_MPC_DPDR (0x280)
1950 #define SPR_MPC_IMMR (0x288)
1951 #define SPR_BOOKE_TLB0CFG (0x2B0)
1952 #define SPR_BOOKE_TLB1CFG (0x2B1)
1953 #define SPR_BOOKE_TLB2CFG (0x2B2)
1954 #define SPR_BOOKE_TLB3CFG (0x2B3)
1955 #define SPR_BOOKE_EPR (0x2BE)
1956 #define SPR_POWER_USIER2 (0x2E0)
1957 #define SPR_POWER_USIER3 (0x2E1)
1958 #define SPR_POWER_UMMCR3 (0x2E2)
1959 #define SPR_POWER_SIER2 (0x2F0)
1960 #define SPR_POWER_SIER3 (0x2F1)
1961 #define SPR_POWER_MMCR3 (0x2F2)
1962 #define SPR_PERF0 (0x300)
1963 #define SPR_RCPU_MI_RBA0 (0x300)
1964 #define SPR_MPC_MI_CTR (0x300)
1965 #define SPR_POWER_USIER (0x300)
1966 #define SPR_PERF1 (0x301)
1967 #define SPR_RCPU_MI_RBA1 (0x301)
1968 #define SPR_POWER_UMMCR2 (0x301)
1969 #define SPR_PERF2 (0x302)
1970 #define SPR_RCPU_MI_RBA2 (0x302)
1971 #define SPR_MPC_MI_AP (0x302)
1972 #define SPR_POWER_UMMCRA (0x302)
1973 #define SPR_PERF3 (0x303)
1974 #define SPR_RCPU_MI_RBA3 (0x303)
1975 #define SPR_MPC_MI_EPN (0x303)
1976 #define SPR_POWER_UPMC1 (0x303)
1977 #define SPR_PERF4 (0x304)
1978 #define SPR_POWER_UPMC2 (0x304)
1979 #define SPR_PERF5 (0x305)
1980 #define SPR_MPC_MI_TWC (0x305)
1981 #define SPR_POWER_UPMC3 (0x305)
1982 #define SPR_PERF6 (0x306)
1983 #define SPR_MPC_MI_RPN (0x306)
1984 #define SPR_POWER_UPMC4 (0x306)
1985 #define SPR_PERF7 (0x307)
1986 #define SPR_POWER_UPMC5 (0x307)
1987 #define SPR_PERF8 (0x308)
1988 #define SPR_RCPU_L2U_RBA0 (0x308)
1989 #define SPR_MPC_MD_CTR (0x308)
1990 #define SPR_POWER_UPMC6 (0x308)
1991 #define SPR_PERF9 (0x309)
1992 #define SPR_RCPU_L2U_RBA1 (0x309)
1993 #define SPR_MPC_MD_CASID (0x309)
1994 #define SPR_970_UPMC7 (0X309)
1995 #define SPR_PERFA (0x30A)
1996 #define SPR_RCPU_L2U_RBA2 (0x30A)
1997 #define SPR_MPC_MD_AP (0x30A)
1998 #define SPR_970_UPMC8 (0X30A)
1999 #define SPR_PERFB (0x30B)
2000 #define SPR_RCPU_L2U_RBA3 (0x30B)
2001 #define SPR_MPC_MD_EPN (0x30B)
2002 #define SPR_POWER_UMMCR0 (0X30B)
2003 #define SPR_PERFC (0x30C)
2004 #define SPR_MPC_MD_TWB (0x30C)
2005 #define SPR_POWER_USIAR (0X30C)
2006 #define SPR_PERFD (0x30D)
2007 #define SPR_MPC_MD_TWC (0x30D)
2008 #define SPR_POWER_USDAR (0X30D)
2009 #define SPR_PERFE (0x30E)
2010 #define SPR_MPC_MD_RPN (0x30E)
2011 #define SPR_POWER_UMMCR1 (0X30E)
2012 #define SPR_PERFF (0x30F)
2013 #define SPR_MPC_MD_TW (0x30F)
2014 #define SPR_UPERF0 (0x310)
2015 #define SPR_POWER_SIER (0x310)
2016 #define SPR_UPERF1 (0x311)
2017 #define SPR_POWER_MMCR2 (0x311)
2018 #define SPR_UPERF2 (0x312)
2019 #define SPR_POWER_MMCRA (0X312)
2020 #define SPR_UPERF3 (0x313)
2021 #define SPR_POWER_PMC1 (0X313)
2022 #define SPR_UPERF4 (0x314)
2023 #define SPR_POWER_PMC2 (0X314)
2024 #define SPR_UPERF5 (0x315)
2025 #define SPR_POWER_PMC3 (0X315)
2026 #define SPR_UPERF6 (0x316)
2027 #define SPR_POWER_PMC4 (0X316)
2028 #define SPR_UPERF7 (0x317)
2029 #define SPR_POWER_PMC5 (0X317)
2030 #define SPR_UPERF8 (0x318)
2031 #define SPR_POWER_PMC6 (0X318)
2032 #define SPR_UPERF9 (0x319)
2033 #define SPR_970_PMC7 (0X319)
2034 #define SPR_UPERFA (0x31A)
2035 #define SPR_970_PMC8 (0X31A)
2036 #define SPR_UPERFB (0x31B)
2037 #define SPR_POWER_MMCR0 (0X31B)
2038 #define SPR_UPERFC (0x31C)
2039 #define SPR_POWER_SIAR (0X31C)
2040 #define SPR_UPERFD (0x31D)
2041 #define SPR_POWER_SDAR (0X31D)
2042 #define SPR_UPERFE (0x31E)
2043 #define SPR_POWER_MMCR1 (0X31E)
2044 #define SPR_UPERFF (0x31F)
2045 #define SPR_RCPU_MI_RA0 (0x320)
2046 #define SPR_MPC_MI_DBCAM (0x320)
2047 #define SPR_BESCRS (0x320)
2048 #define SPR_RCPU_MI_RA1 (0x321)
2049 #define SPR_MPC_MI_DBRAM0 (0x321)
2050 #define SPR_BESCRSU (0x321)
2051 #define SPR_RCPU_MI_RA2 (0x322)
2052 #define SPR_MPC_MI_DBRAM1 (0x322)
2053 #define SPR_BESCRR (0x322)
2054 #define SPR_RCPU_MI_RA3 (0x323)
2055 #define SPR_BESCRRU (0x323)
2056 #define SPR_EBBHR (0x324)
2057 #define SPR_EBBRR (0x325)
2058 #define SPR_BESCR (0x326)
2059 #define SPR_RCPU_L2U_RA0 (0x328)
2060 #define SPR_MPC_MD_DBCAM (0x328)
2061 #define SPR_RCPU_L2U_RA1 (0x329)
2062 #define SPR_MPC_MD_DBRAM0 (0x329)
2063 #define SPR_RCPU_L2U_RA2 (0x32A)
2064 #define SPR_MPC_MD_DBRAM1 (0x32A)
2065 #define SPR_RCPU_L2U_RA3 (0x32B)
2066 #define SPR_UDEXCR (0x32C)
2067 #define SPR_TAR (0x32F)
2068 #define SPR_ASDR (0x330)
2069 #define SPR_DEXCR (0x33C)
2070 #define SPR_IC (0x350)
2071 #define SPR_VTB (0x351)
2072 #define SPR_MMCRC (0x353)
2073 #define SPR_PSSCR (0x357)
2074 #define SPR_440_INV0 (0x370)
2075 #define SPR_440_INV1 (0x371)
2076 #define SPR_TRIG1 (0x371)
2077 #define SPR_440_INV2 (0x372)
2078 #define SPR_TRIG2 (0x372)
2079 #define SPR_440_INV3 (0x373)
2080 #define SPR_440_ITV0 (0x374)
2081 #define SPR_440_ITV1 (0x375)
2082 #define SPR_440_ITV2 (0x376)
2083 #define SPR_440_ITV3 (0x377)
2084 #define SPR_440_CCR1 (0x378)
2085 #define SPR_TACR (0x378)
2086 #define SPR_TCSCR (0x379)
2087 #define SPR_CSIGR (0x37a)
2088 #define SPR_DCRIPR (0x37B)
2089 #define SPR_POWER_SPMC1 (0x37C)
2090 #define SPR_POWER_SPMC2 (0x37D)
2091 #define SPR_POWER_MMCRS (0x37E)
2092 #define SPR_WORT (0x37F)
2093 #define SPR_PPR (0x380)
2094 #define SPR_750_GQR0 (0x390)
2095 #define SPR_440_DNV0 (0x390)
2096 #define SPR_750_GQR1 (0x391)
2097 #define SPR_440_DNV1 (0x391)
2098 #define SPR_750_GQR2 (0x392)
2099 #define SPR_440_DNV2 (0x392)
2100 #define SPR_750_GQR3 (0x393)
2101 #define SPR_440_DNV3 (0x393)
2102 #define SPR_750_GQR4 (0x394)
2103 #define SPR_440_DTV0 (0x394)
2104 #define SPR_750_GQR5 (0x395)
2105 #define SPR_440_DTV1 (0x395)
2106 #define SPR_750_GQR6 (0x396)
2107 #define SPR_440_DTV2 (0x396)
2108 #define SPR_750_GQR7 (0x397)
2109 #define SPR_440_DTV3 (0x397)
2110 #define SPR_750_THRM4 (0x398)
2111 #define SPR_750CL_HID2 (0x398)
2112 #define SPR_440_DVLIM (0x398)
2113 #define SPR_750_WPAR (0x399)
2114 #define SPR_440_IVLIM (0x399)
2115 #define SPR_TSCR (0x399)
2116 #define SPR_750_DMAU (0x39A)
2117 #define SPR_750_DMAL (0x39B)
2118 #define SPR_440_RSTCFG (0x39B)
2119 #define SPR_BOOKE_DCDBTRL (0x39C)
2120 #define SPR_BOOKE_DCDBTRH (0x39D)
2121 #define SPR_BOOKE_ICDBTRL (0x39E)
2122 #define SPR_BOOKE_ICDBTRH (0x39F)
2123 #define SPR_74XX_UMMCR2 (0x3A0)
2124 #define SPR_7XX_UPMC5 (0x3A1)
2125 #define SPR_7XX_UPMC6 (0x3A2)
2126 #define SPR_UBAMR (0x3A7)
2127 #define SPR_7XX_UMMCR0 (0x3A8)
2128 #define SPR_7XX_UPMC1 (0x3A9)
2129 #define SPR_7XX_UPMC2 (0x3AA)
2130 #define SPR_7XX_USIAR (0x3AB)
2131 #define SPR_7XX_UMMCR1 (0x3AC)
2132 #define SPR_7XX_UPMC3 (0x3AD)
2133 #define SPR_7XX_UPMC4 (0x3AE)
2134 #define SPR_USDA (0x3AF)
2135 #define SPR_40x_ZPR (0x3B0)
2136 #define SPR_BOOKE_MAS7 (0x3B0)
2137 #define SPR_74XX_MMCR2 (0x3B0)
2138 #define SPR_7XX_PMC5 (0x3B1)
2139 #define SPR_40x_PID (0x3B1)
2140 #define SPR_7XX_PMC6 (0x3B2)
2141 #define SPR_440_MMUCR (0x3B2)
2142 #define SPR_4xx_CCR0 (0x3B3)
2143 #define SPR_BOOKE_EPLC (0x3B3)
2144 #define SPR_405_IAC3 (0x3B4)
2145 #define SPR_BOOKE_EPSC (0x3B4)
2146 #define SPR_405_IAC4 (0x3B5)
2147 #define SPR_405_DVC1 (0x3B6)
2148 #define SPR_405_DVC2 (0x3B7)
2149 #define SPR_BAMR (0x3B7)
2150 #define SPR_7XX_MMCR0 (0x3B8)
2151 #define SPR_7XX_PMC1 (0x3B9)
2152 #define SPR_40x_SGR (0x3B9)
2153 #define SPR_7XX_PMC2 (0x3BA)
2154 #define SPR_40x_DCWR (0x3BA)
2155 #define SPR_7XX_SIAR (0x3BB)
2156 #define SPR_405_SLER (0x3BB)
2157 #define SPR_7XX_MMCR1 (0x3BC)
2158 #define SPR_405_SU0R (0x3BC)
2159 #define SPR_401_SKR (0x3BC)
2160 #define SPR_7XX_PMC3 (0x3BD)
2161 #define SPR_405_DBCR1 (0x3BD)
2162 #define SPR_7XX_PMC4 (0x3BE)
2163 #define SPR_SDA (0x3BF)
2164 #define SPR_403_VTBL (0x3CC)
2165 #define SPR_403_VTBU (0x3CD)
2166 #define SPR_DMISS (0x3D0)
2167 #define SPR_DCMP (0x3D1)
2168 #define SPR_HASH1 (0x3D2)
2169 #define SPR_HASH2 (0x3D3)
2170 #define SPR_BOOKE_ICDBDR (0x3D3)
2171 #define SPR_TLBMISS (0x3D4)
2172 #define SPR_IMISS (0x3D4)
2173 #define SPR_40x_ESR (0x3D4)
2174 #define SPR_PTEHI (0x3D5)
2175 #define SPR_ICMP (0x3D5)
2176 #define SPR_40x_DEAR (0x3D5)
2177 #define SPR_PTELO (0x3D6)
2178 #define SPR_RPA (0x3D6)
2179 #define SPR_40x_EVPR (0x3D6)
2180 #define SPR_L3PM (0x3D7)
2181 #define SPR_403_CDBCR (0x3D7)
2182 #define SPR_L3ITCR0 (0x3D8)
2183 #define SPR_TCR (0x3D8)
2184 #define SPR_40x_TSR (0x3D8)
2185 #define SPR_IBR (0x3DA)
2186 #define SPR_40x_TCR (0x3DA)
2187 #define SPR_ESASRR (0x3DB)
2188 #define SPR_40x_PIT (0x3DB)
2189 #define SPR_403_TBL (0x3DC)
2190 #define SPR_403_TBU (0x3DD)
2191 #define SPR_SEBR (0x3DE)
2192 #define SPR_40x_SRR2 (0x3DE)
2193 #define SPR_SER (0x3DF)
2194 #define SPR_40x_SRR3 (0x3DF)
2195 #define SPR_L3OHCR (0x3E8)
2196 #define SPR_L3ITCR1 (0x3E9)
2197 #define SPR_L3ITCR2 (0x3EA)
2198 #define SPR_L3ITCR3 (0x3EB)
2199 #define SPR_HID0 (0x3F0)
2200 #define SPR_40x_DBSR (0x3F0)
2201 #define SPR_HID1 (0x3F1)
2202 #define SPR_IABR (0x3F2)
2203 #define SPR_40x_DBCR0 (0x3F2)
2204 #define SPR_Exxx_L1CSR0 (0x3F2)
2205 #define SPR_ICTRL (0x3F3)
2206 #define SPR_HID2 (0x3F3)
2207 #define SPR_750CL_HID4 (0x3F3)
2208 #define SPR_Exxx_L1CSR1 (0x3F3)
2209 #define SPR_440_DBDR (0x3F3)
2210 #define SPR_LDSTDB (0x3F4)
2211 #define SPR_750_TDCL (0x3F4)
2212 #define SPR_40x_IAC1 (0x3F4)
2213 #define SPR_MMUCSR0 (0x3F4)
2214 #define SPR_970_HID4 (0x3F4)
2215 #define SPR_DABR (0x3F5)
2216 #define DABR_MASK (~(target_ulong)0x7)
2217 #define SPR_Exxx_BUCSR (0x3F5)
2218 #define SPR_40x_IAC2 (0x3F5)
2219 #define SPR_40x_DAC1 (0x3F6)
2220 #define SPR_MSSCR0 (0x3F6)
2221 #define SPR_970_HID5 (0x3F6)
2222 #define SPR_MSSSR0 (0x3F7)
2223 #define SPR_MSSCR1 (0x3F7)
2224 #define SPR_DABRX (0x3F7)
2225 #define SPR_40x_DAC2 (0x3F7)
2226 #define SPR_MMUCFG (0x3F7)
2227 #define SPR_LDSTCR (0x3F8)
2228 #define SPR_L2PMCR (0x3F8)
2229 #define SPR_750FX_HID2 (0x3F8)
2230 #define SPR_Exxx_L1FINV0 (0x3F8)
2231 #define SPR_L2CR (0x3F9)
2232 #define SPR_Exxx_L2CSR0 (0x3F9)
2233 #define SPR_L3CR (0x3FA)
2234 #define SPR_750_TDCH (0x3FA)
2235 #define SPR_IABR2 (0x3FA)
2236 #define SPR_40x_DCCR (0x3FA)
2237 #define SPR_ICTC (0x3FB)
2238 #define SPR_40x_ICCR (0x3FB)
2239 #define SPR_THRM1 (0x3FC)
2240 #define SPR_403_PBL1 (0x3FC)
2241 #define SPR_SP (0x3FD)
2242 #define SPR_THRM2 (0x3FD)
2243 #define SPR_403_PBU1 (0x3FD)
2244 #define SPR_604_HID13 (0x3FD)
2245 #define SPR_LT (0x3FE)
2246 #define SPR_THRM3 (0x3FE)
2247 #define SPR_RCPU_FPECR (0x3FE)
2248 #define SPR_403_PBL2 (0x3FE)
2249 #define SPR_PIR (0x3FF)
2250 #define SPR_403_PBU2 (0x3FF)
2251 #define SPR_604_HID15 (0x3FF)
2252 #define SPR_E500_SVR (0x3FF)
2253
2254 /* Disable MAS Interrupt Updates for Hypervisor */
2255 #define EPCR_DMIUH (1 << 22)
2256 /* Disable Guest TLB Management Instructions */
2257 #define EPCR_DGTMI (1 << 23)
2258 /* Guest Interrupt Computation Mode */
2259 #define EPCR_GICM (1 << 24)
2260 /* Interrupt Computation Mode */
2261 #define EPCR_ICM (1 << 25)
2262 /* Disable Embedded Hypervisor Debug */
2263 #define EPCR_DUVD (1 << 26)
2264 /* Instruction Storage Interrupt Directed to Guest State */
2265 #define EPCR_ISIGS (1 << 27)
2266 /* Data Storage Interrupt Directed to Guest State */
2267 #define EPCR_DSIGS (1 << 28)
2268 /* Instruction TLB Error Interrupt Directed to Guest State */
2269 #define EPCR_ITLBGS (1 << 29)
2270 /* Data TLB Error Interrupt Directed to Guest State */
2271 #define EPCR_DTLBGS (1 << 30)
2272 /* External Input Interrupt Directed to Guest State */
2273 #define EPCR_EXTGS (1 << 31)
2274
2275 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
2276 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
2277 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
2278 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
2279 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
2280
2281 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
2282 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
2283 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
2284 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
2285 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
2286
2287 /* E500 L2CSR0 */
2288 #define E500_L2CSR0_L2FI (1 << 21) /* L2 cache flash invalidate */
2289 #define E500_L2CSR0_L2FL (1 << 11) /* L2 cache flush */
2290 #define E500_L2CSR0_L2LFC (1 << 10) /* L2 cache lock flash clear */
2291
2292 /* HID0 bits */
2293 #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
2294 #define HID0_DOZE (1 << 23) /* pre-2.06 */
2295 #define HID0_NAP (1 << 22) /* pre-2.06 */
2296 #define HID0_HILE PPC_BIT(19) /* POWER8 */
2297 #define HID0_POWER9_HILE PPC_BIT(4)
2298
2299 /*****************************************************************************/
2300 /* PowerPC Instructions types definitions */
2301 enum {
2302 PPC_NONE = 0x0000000000000000ULL,
2303 /* PowerPC base instructions set */
2304 PPC_INSNS_BASE = 0x0000000000000001ULL,
2305 /* integer operations instructions */
2306 #define PPC_INTEGER PPC_INSNS_BASE
2307 /* flow control instructions */
2308 #define PPC_FLOW PPC_INSNS_BASE
2309 /* virtual memory instructions */
2310 #define PPC_MEM PPC_INSNS_BASE
2311 /* ld/st with reservation instructions */
2312 #define PPC_RES PPC_INSNS_BASE
2313 /* spr/msr access instructions */
2314 #define PPC_MISC PPC_INSNS_BASE
2315 /* 64 bits PowerPC instruction set */
2316 PPC_64B = 0x0000000000000020ULL,
2317 /* New 64 bits extensions (PowerPC 2.0x) */
2318 PPC_64BX = 0x0000000000000040ULL,
2319 /* 64 bits hypervisor extensions */
2320 PPC_64H = 0x0000000000000080ULL,
2321 /* New wait instruction (PowerPC 2.0x) */
2322 PPC_WAIT = 0x0000000000000100ULL,
2323 /* Time base mftb instruction */
2324 PPC_MFTB = 0x0000000000000200ULL,
2325
2326 /* Fixed-point unit extensions */
2327 /* isel instruction */
2328 PPC_ISEL = 0x0000000000000800ULL,
2329 /* popcntb instruction */
2330 PPC_POPCNTB = 0x0000000000001000ULL,
2331 /* string load / store */
2332 PPC_STRING = 0x0000000000002000ULL,
2333 /* real mode cache inhibited load / store */
2334 PPC_CILDST = 0x0000000000004000ULL,
2335
2336 /* Floating-point unit extensions */
2337 /* Optional floating point instructions */
2338 PPC_FLOAT = 0x0000000000010000ULL,
2339 /* New floating-point extensions (PowerPC 2.0x) */
2340 PPC_FLOAT_EXT = 0x0000000000020000ULL,
2341 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
2342 PPC_FLOAT_FRES = 0x0000000000080000ULL,
2343 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
2344 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2345 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
2346 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
2347
2348 /* Vector/SIMD extensions */
2349 /* Altivec support */
2350 PPC_ALTIVEC = 0x0000000001000000ULL,
2351 /* PowerPC 2.03 SPE extension */
2352 PPC_SPE = 0x0000000002000000ULL,
2353 /* PowerPC 2.03 SPE single-precision floating-point extension */
2354 PPC_SPE_SINGLE = 0x0000000004000000ULL,
2355 /* PowerPC 2.03 SPE double-precision floating-point extension */
2356 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
2357
2358 /* Optional memory control instructions */
2359 PPC_MEM_TLBIA = 0x0000000010000000ULL,
2360 PPC_MEM_TLBIE = 0x0000000020000000ULL,
2361 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
2362 /* sync instruction */
2363 PPC_MEM_SYNC = 0x0000000080000000ULL,
2364 /* eieio instruction */
2365 PPC_MEM_EIEIO = 0x0000000100000000ULL,
2366
2367 /* Cache control instructions */
2368 PPC_CACHE = 0x0000000200000000ULL,
2369 /* icbi instruction */
2370 PPC_CACHE_ICBI = 0x0000000400000000ULL,
2371 /* dcbz instruction */
2372 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
2373 /* dcba instruction */
2374 PPC_CACHE_DCBA = 0x0000002000000000ULL,
2375 /* Freescale cache locking instructions */
2376 PPC_CACHE_LOCK = 0x0000004000000000ULL,
2377
2378 /* MMU related extensions */
2379 /* external control instructions */
2380 PPC_EXTERN = 0x0000010000000000ULL,
2381 /* segment register access instructions */
2382 PPC_SEGMENT = 0x0000020000000000ULL,
2383 /* PowerPC 6xx TLB management instructions */
2384 PPC_6xx_TLB = 0x0000040000000000ULL,
2385 /* PowerPC 40x TLB management instructions */
2386 PPC_40x_TLB = 0x0000100000000000ULL,
2387 /* segment register access instructions for PowerPC 64 "bridge" */
2388 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2389 /* SLB management */
2390 PPC_SLBI = 0x0000400000000000ULL,
2391
2392 /* Embedded PowerPC dedicated instructions */
2393 PPC_WRTEE = 0x0001000000000000ULL,
2394 /* PowerPC 40x exception model */
2395 PPC_40x_EXCP = 0x0002000000000000ULL,
2396 /* PowerPC 405 Mac instructions */
2397 PPC_405_MAC = 0x0004000000000000ULL,
2398 /* PowerPC 440 specific instructions */
2399 PPC_440_SPEC = 0x0008000000000000ULL,
2400 /* BookE (embedded) PowerPC specification */
2401 PPC_BOOKE = 0x0010000000000000ULL,
2402 /* mfapidi instruction */
2403 PPC_MFAPIDI = 0x0020000000000000ULL,
2404 /* tlbiva instruction */
2405 PPC_TLBIVA = 0x0040000000000000ULL,
2406 /* tlbivax instruction */
2407 PPC_TLBIVAX = 0x0080000000000000ULL,
2408 /* PowerPC 4xx dedicated instructions */
2409 PPC_4xx_COMMON = 0x0100000000000000ULL,
2410 /* PowerPC 40x ibct instructions */
2411 PPC_40x_ICBT = 0x0200000000000000ULL,
2412 /* rfmci is not implemented in all BookE PowerPC */
2413 PPC_RFMCI = 0x0400000000000000ULL,
2414 /* rfdi instruction */
2415 PPC_RFDI = 0x0800000000000000ULL,
2416 /* DCR accesses */
2417 PPC_DCR = 0x1000000000000000ULL,
2418 /* DCR extended accesse */
2419 PPC_DCRX = 0x2000000000000000ULL,
2420 /* popcntw and popcntd instructions */
2421 PPC_POPCNTWD = 0x8000000000000000ULL,
2422
2423 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_64B \
2424 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2425 | PPC_ISEL | PPC_POPCNTB \
2426 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2427 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2428 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2429 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2430 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2431 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2432 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2433 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2434 | PPC_CACHE | PPC_CACHE_ICBI \
2435 | PPC_CACHE_DCBZ \
2436 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2437 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2438 | PPC_40x_TLB | PPC_SEGMENT_64B \
2439 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2440 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2441 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2442 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2443 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_POPCNTWD \
2444 | PPC_CILDST)
2445
2446 /* extended type values */
2447
2448 /* BookE 2.06 PowerPC specification */
2449 PPC2_BOOKE206 = 0x0000000000000001ULL,
2450 /* VSX (extensions to Altivec / VMX) */
2451 PPC2_VSX = 0x0000000000000002ULL,
2452 /* Decimal Floating Point (DFP) */
2453 PPC2_DFP = 0x0000000000000004ULL,
2454 /* Embedded.Processor Control */
2455 PPC2_PRCNTL = 0x0000000000000008ULL,
2456 /* Byte-reversed, indexed, double-word load and store */
2457 PPC2_DBRX = 0x0000000000000010ULL,
2458 /* Book I 2.05 PowerPC specification */
2459 PPC2_ISA205 = 0x0000000000000020ULL,
2460 /* VSX additions in ISA 2.07 */
2461 PPC2_VSX207 = 0x0000000000000040ULL,
2462 /* ISA 2.06B bpermd */
2463 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2464 /* ISA 2.06B divide extended variants */
2465 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2466 /* ISA 2.06B larx/stcx. instructions */
2467 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2468 /* ISA 2.06B floating point integer conversion */
2469 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2470 /* ISA 2.06B floating point test instructions */
2471 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2472 /* ISA 2.07 bctar instruction */
2473 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2474 /* ISA 2.07 load/store quadword */
2475 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2476 /* ISA 2.07 Altivec */
2477 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2478 /* PowerISA 2.07 Book3s specification */
2479 PPC2_ISA207S = 0x0000000000008000ULL,
2480 /* Double precision floating point conversion for signed integer 64 */
2481 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2482 /* Transactional Memory (ISA 2.07, Book II) */
2483 PPC2_TM = 0x0000000000020000ULL,
2484 /* Server PM instructgions (ISA 2.06, Book III) */
2485 PPC2_PM_ISA206 = 0x0000000000040000ULL,
2486 /* POWER ISA 3.0 */
2487 PPC2_ISA300 = 0x0000000000080000ULL,
2488 /* POWER ISA 3.1 */
2489 PPC2_ISA310 = 0x0000000000100000ULL,
2490 /* lwsync instruction */
2491 PPC2_MEM_LWSYNC = 0x0000000000200000ULL,
2492 /* ISA 2.06 BCD assist instructions */
2493 PPC2_BCDA_ISA206 = 0x0000000000400000ULL,
2494
2495 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2496 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2497 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2498 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2499 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2500 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2501 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2502 PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \
2503 PPC2_BCDA_ISA206)
2504 };
2505
2506 /*****************************************************************************/
2507 /*
2508 * Memory access type :
2509 * may be needed for precise access rights control and precise exceptions.
2510 */
2511 enum {
2512 /* Type of instruction that generated the access */
2513 ACCESS_CODE = 0x10, /* Code fetch access */
2514 ACCESS_INT = 0x20, /* Integer load/store access */
2515 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2516 ACCESS_RES = 0x40, /* load/store with reservation */
2517 ACCESS_EXT = 0x50, /* external access */
2518 ACCESS_CACHE = 0x60, /* Cache manipulation */
2519 };
2520
2521 /*
2522 * Hardware interrupt sources:
2523 * all those exception can be raised simulteaneously
2524 */
2525 /* Input pins definitions */
2526 enum {
2527 /* 6xx bus input pins */
2528 PPC6xx_INPUT_HRESET = 0,
2529 PPC6xx_INPUT_SRESET = 1,
2530 PPC6xx_INPUT_CKSTP_IN = 2,
2531 PPC6xx_INPUT_MCP = 3,
2532 PPC6xx_INPUT_SMI = 4,
2533 PPC6xx_INPUT_INT = 5,
2534 PPC6xx_INPUT_TBEN = 6,
2535 PPC6xx_INPUT_WAKEUP = 7,
2536 PPC6xx_INPUT_NB,
2537 };
2538
2539 enum {
2540 /* Embedded PowerPC input pins */
2541 PPCBookE_INPUT_HRESET = 0,
2542 PPCBookE_INPUT_SRESET = 1,
2543 PPCBookE_INPUT_CKSTP_IN = 2,
2544 PPCBookE_INPUT_MCP = 3,
2545 PPCBookE_INPUT_SMI = 4,
2546 PPCBookE_INPUT_INT = 5,
2547 PPCBookE_INPUT_CINT = 6,
2548 PPCBookE_INPUT_NB,
2549 };
2550
2551 enum {
2552 /* PowerPC E500 input pins */
2553 PPCE500_INPUT_RESET_CORE = 0,
2554 PPCE500_INPUT_MCK = 1,
2555 PPCE500_INPUT_CINT = 3,
2556 PPCE500_INPUT_INT = 4,
2557 PPCE500_INPUT_DEBUG = 6,
2558 PPCE500_INPUT_NB,
2559 };
2560
2561 enum {
2562 /* PowerPC 40x input pins */
2563 PPC40x_INPUT_RESET_CORE = 0,
2564 PPC40x_INPUT_RESET_CHIP = 1,
2565 PPC40x_INPUT_RESET_SYS = 2,
2566 PPC40x_INPUT_CINT = 3,
2567 PPC40x_INPUT_INT = 4,
2568 PPC40x_INPUT_HALT = 5,
2569 PPC40x_INPUT_DEBUG = 6,
2570 PPC40x_INPUT_NB,
2571 };
2572
2573 enum {
2574 /* RCPU input pins */
2575 PPCRCPU_INPUT_PORESET = 0,
2576 PPCRCPU_INPUT_HRESET = 1,
2577 PPCRCPU_INPUT_SRESET = 2,
2578 PPCRCPU_INPUT_IRQ0 = 3,
2579 PPCRCPU_INPUT_IRQ1 = 4,
2580 PPCRCPU_INPUT_IRQ2 = 5,
2581 PPCRCPU_INPUT_IRQ3 = 6,
2582 PPCRCPU_INPUT_IRQ4 = 7,
2583 PPCRCPU_INPUT_IRQ5 = 8,
2584 PPCRCPU_INPUT_IRQ6 = 9,
2585 PPCRCPU_INPUT_IRQ7 = 10,
2586 PPCRCPU_INPUT_NB,
2587 };
2588
2589 #if defined(TARGET_PPC64)
2590 enum {
2591 /* PowerPC 970 input pins */
2592 PPC970_INPUT_HRESET = 0,
2593 PPC970_INPUT_SRESET = 1,
2594 PPC970_INPUT_CKSTP = 2,
2595 PPC970_INPUT_TBEN = 3,
2596 PPC970_INPUT_MCP = 4,
2597 PPC970_INPUT_INT = 5,
2598 PPC970_INPUT_THINT = 6,
2599 PPC970_INPUT_NB,
2600 };
2601
2602 enum {
2603 /* POWER7 input pins */
2604 POWER7_INPUT_INT = 0,
2605 /*
2606 * POWER7 probably has other inputs, but we don't care about them
2607 * for any existing machine. We can wire these up when we need
2608 * them
2609 */
2610 POWER7_INPUT_NB,
2611 };
2612
2613 enum {
2614 /* POWER9 input pins */
2615 POWER9_INPUT_INT = 0,
2616 POWER9_INPUT_HINT = 1,
2617 POWER9_INPUT_NB,
2618 };
2619 #endif
2620
2621 /* Hardware exceptions definitions */
2622 enum {
2623 /* External hardware exception sources */
2624 PPC_INTERRUPT_RESET = 0x00001, /* Reset exception */
2625 PPC_INTERRUPT_WAKEUP = 0x00002, /* Wakeup exception */
2626 PPC_INTERRUPT_MCK = 0x00004, /* Machine check exception */
2627 PPC_INTERRUPT_EXT = 0x00008, /* External interrupt */
2628 PPC_INTERRUPT_SMI = 0x00010, /* System management interrupt */
2629 PPC_INTERRUPT_CEXT = 0x00020, /* Critical external interrupt */
2630 PPC_INTERRUPT_DEBUG = 0x00040, /* External debug exception */
2631 PPC_INTERRUPT_THERM = 0x00080, /* Thermal exception */
2632 /* Internal hardware exception sources */
2633 PPC_INTERRUPT_DECR = 0x00100, /* Decrementer exception */
2634 PPC_INTERRUPT_HDECR = 0x00200, /* Hypervisor decrementer exception */
2635 PPC_INTERRUPT_PIT = 0x00400, /* Programmable interval timer int. */
2636 PPC_INTERRUPT_FIT = 0x00800, /* Fixed interval timer interrupt */
2637 PPC_INTERRUPT_WDT = 0x01000, /* Watchdog timer interrupt */
2638 PPC_INTERRUPT_CDOORBELL = 0x02000, /* Critical doorbell interrupt */
2639 PPC_INTERRUPT_DOORBELL = 0x04000, /* Doorbell interrupt */
2640 PPC_INTERRUPT_PERFM = 0x08000, /* Performance monitor interrupt */
2641 PPC_INTERRUPT_HMI = 0x10000, /* Hypervisor Maintenance interrupt */
2642 PPC_INTERRUPT_HDOORBELL = 0x20000, /* Hypervisor Doorbell interrupt */
2643 PPC_INTERRUPT_HVIRT = 0x40000, /* Hypervisor virtualization interrupt */
2644 PPC_INTERRUPT_EBB = 0x80000, /* Event-based Branch exception */
2645 };
2646
2647 /* Processor Compatibility mask (PCR) */
2648 enum {
2649 PCR_COMPAT_2_05 = PPC_BIT(62),
2650 PCR_COMPAT_2_06 = PPC_BIT(61),
2651 PCR_COMPAT_2_07 = PPC_BIT(60),
2652 PCR_COMPAT_3_00 = PPC_BIT(59),
2653 PCR_COMPAT_3_10 = PPC_BIT(58),
2654 PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2655 PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2656 PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2657 };
2658
2659 /* HMER/HMEER */
2660 enum {
2661 HMER_MALFUNCTION_ALERT = PPC_BIT(0),
2662 HMER_PROC_RECV_DONE = PPC_BIT(2),
2663 HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2664 HMER_TFAC_ERROR = PPC_BIT(4),
2665 HMER_TFMR_PARITY_ERROR = PPC_BIT(5),
2666 HMER_XSCOM_FAIL = PPC_BIT(8),
2667 HMER_XSCOM_DONE = PPC_BIT(9),
2668 HMER_PROC_RECV_AGAIN = PPC_BIT(11),
2669 HMER_WARN_RISE = PPC_BIT(14),
2670 HMER_WARN_FALL = PPC_BIT(15),
2671 HMER_SCOM_FIR_HMI = PPC_BIT(16),
2672 HMER_TRIG_FIR_HMI = PPC_BIT(17),
2673 HMER_HYP_RESOURCE_ERR = PPC_BIT(20),
2674 HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23),
2675 };
2676
2677 /* TFMR */
2678 enum {
2679 TFMR_CONTROL_MASK = PPC_BITMASK(0, 24),
2680 TFMR_MASK_HMI = PPC_BIT(10),
2681 TFMR_TB_ECLIPZ = PPC_BIT(14),
2682 TFMR_LOAD_TOD_MOD = PPC_BIT(16),
2683 TFMR_MOVE_CHIP_TOD_TO_TB = PPC_BIT(18),
2684 TFMR_CLEAR_TB_ERRORS = PPC_BIT(24),
2685 TFMR_STATUS_MASK = PPC_BITMASK(25, 63),
2686 TFMR_TBST_ENCODED = PPC_BITMASK(28, 31), /* TBST = TB State */
2687 TFMR_TBST_LAST = PPC_BITMASK(32, 35), /* Previous TBST */
2688 TFMR_TB_ENABLED = PPC_BIT(40),
2689 TFMR_TB_VALID = PPC_BIT(41),
2690 TFMR_TB_SYNC_OCCURED = PPC_BIT(42),
2691 TFMR_FIRMWARE_CONTROL_ERROR = PPC_BIT(46),
2692 };
2693
2694 /* TFMR TBST (Time Base State Machine). */
2695 enum {
2696 TBST_RESET = 0x0,
2697 TBST_SEND_TOD_MOD = 0x1,
2698 TBST_NOT_SET = 0x2,
2699 TBST_SYNC_WAIT = 0x6,
2700 TBST_GET_TOD = 0x7,
2701 TBST_TB_RUNNING = 0x8,
2702 TBST_TB_ERROR = 0x9,
2703 };
2704
2705 /*****************************************************************************/
2706
2707 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2708 target_ulong cpu_read_xer(const CPUPPCState *env);
2709 void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2710
2711 /*
2712 * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2713 * have PPC_SEGMENT_64B.
2714 */
2715 #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2716
2717 #ifdef CONFIG_DEBUG_TCG
2718 void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
2719 uint64_t *cs_base, uint32_t *flags);
2720 #else
cpu_get_tb_cpu_state(CPUPPCState * env,vaddr * pc,uint64_t * cs_base,uint32_t * flags)2721 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
2722 uint64_t *cs_base, uint32_t *flags)
2723 {
2724 *pc = env->nip;
2725 *cs_base = 0;
2726 *flags = env->hflags;
2727 }
2728 #endif
2729
2730 G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception);
2731 G_NORETURN void raise_exception_ra(CPUPPCState *env, uint32_t exception,
2732 uintptr_t raddr);
2733 G_NORETURN void raise_exception_err(CPUPPCState *env, uint32_t exception,
2734 uint32_t error_code);
2735 G_NORETURN void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2736 uint32_t error_code, uintptr_t raddr);
2737
2738 /* PERFM EBB helper*/
2739 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2740 void raise_ebb_perfm_exception(CPUPPCState *env);
2741 #endif
2742
2743 #if !defined(CONFIG_USER_ONLY)
booke206_tlbm_id(CPUPPCState * env,ppcmas_tlb_t * tlbm)2744 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2745 {
2746 uintptr_t tlbml = (uintptr_t)tlbm;
2747 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2748
2749 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2750 }
2751
booke206_tlb_size(CPUPPCState * env,int tlbn)2752 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2753 {
2754 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2755 int r = tlbncfg & TLBnCFG_N_ENTRY;
2756 return r;
2757 }
2758
booke206_tlb_ways(CPUPPCState * env,int tlbn)2759 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2760 {
2761 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2762 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2763 return r;
2764 }
2765
booke206_tlbm_to_tlbn(CPUPPCState * env,ppcmas_tlb_t * tlbm)2766 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2767 {
2768 int id = booke206_tlbm_id(env, tlbm);
2769 int end = 0;
2770 int i;
2771
2772 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2773 end += booke206_tlb_size(env, i);
2774 if (id < end) {
2775 return i;
2776 }
2777 }
2778
2779 cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
2780 return 0;
2781 }
2782
booke206_tlbm_to_way(CPUPPCState * env,ppcmas_tlb_t * tlb)2783 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2784 {
2785 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2786 int tlbid = booke206_tlbm_id(env, tlb);
2787 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2788 }
2789
booke206_get_tlbm(CPUPPCState * env,const int tlbn,target_ulong ea,int way)2790 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2791 target_ulong ea, int way)
2792 {
2793 int r;
2794 uint32_t ways = booke206_tlb_ways(env, tlbn);
2795 int ways_bits = ctz32(ways);
2796 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2797 int i;
2798
2799 way &= ways - 1;
2800 ea >>= MAS2_EPN_SHIFT;
2801 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2802 r = (ea << ways_bits) | way;
2803
2804 if (r >= booke206_tlb_size(env, tlbn)) {
2805 return NULL;
2806 }
2807
2808 /* bump up to tlbn index */
2809 for (i = 0; i < tlbn; i++) {
2810 r += booke206_tlb_size(env, i);
2811 }
2812
2813 return &env->tlb.tlbm[r];
2814 }
2815
2816 /* returns bitmap of supported page sizes for a given TLB */
booke206_tlbnps(CPUPPCState * env,const int tlbn)2817 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2818 {
2819 uint32_t ret = 0;
2820
2821 if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2822 /* MAV2 */
2823 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2824 } else {
2825 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2826 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2827 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2828 int i;
2829 for (i = min; i <= max; i++) {
2830 ret |= (1 << (i << 1));
2831 }
2832 }
2833
2834 return ret;
2835 }
2836
booke206_fixed_size_tlbn(CPUPPCState * env,const int tlbn,ppcmas_tlb_t * tlb)2837 static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2838 ppcmas_tlb_t *tlb)
2839 {
2840 uint8_t i;
2841 int32_t tsize = -1;
2842
2843 for (i = 0; i < 32; i++) {
2844 if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2845 if (tsize == -1) {
2846 tsize = i;
2847 } else {
2848 return;
2849 }
2850 }
2851 }
2852
2853 /* TLBnPS unimplemented? Odd.. */
2854 assert(tsize != -1);
2855 tlb->mas1 &= ~MAS1_TSIZE_MASK;
2856 tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2857 }
2858
2859 #endif
2860
msr_is_64bit(CPUPPCState * env,target_ulong msr)2861 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2862 {
2863 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2864 return msr & (1ULL << MSR_CM);
2865 }
2866
2867 return msr & (1ULL << MSR_SF);
2868 }
2869
2870 /**
2871 * Check whether register rx is in the range between start and
2872 * start + nregs (as needed by the LSWX and LSWI instructions)
2873 */
lsw_reg_in_range(int start,int nregs,int rx)2874 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2875 {
2876 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2877 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2878 }
2879
2880 /* Accessors for FP, VMX and VSX registers */
2881 #if HOST_BIG_ENDIAN
2882 #define VsrB(i) u8[i]
2883 #define VsrSB(i) s8[i]
2884 #define VsrH(i) u16[i]
2885 #define VsrSH(i) s16[i]
2886 #define VsrW(i) u32[i]
2887 #define VsrSW(i) s32[i]
2888 #define VsrD(i) u64[i]
2889 #define VsrSD(i) s64[i]
2890 #define VsrHF(i) f16[i]
2891 #define VsrSF(i) f32[i]
2892 #define VsrDF(i) f64[i]
2893 #else
2894 #define VsrB(i) u8[15 - (i)]
2895 #define VsrSB(i) s8[15 - (i)]
2896 #define VsrH(i) u16[7 - (i)]
2897 #define VsrSH(i) s16[7 - (i)]
2898 #define VsrW(i) u32[3 - (i)]
2899 #define VsrSW(i) s32[3 - (i)]
2900 #define VsrD(i) u64[1 - (i)]
2901 #define VsrSD(i) s64[1 - (i)]
2902 #define VsrHF(i) f16[7 - (i)]
2903 #define VsrSF(i) f32[3 - (i)]
2904 #define VsrDF(i) f64[1 - (i)]
2905 #endif
2906
vsr64_offset(int i,bool high)2907 static inline int vsr64_offset(int i, bool high)
2908 {
2909 return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
2910 }
2911
vsr_full_offset(int i)2912 static inline int vsr_full_offset(int i)
2913 {
2914 return offsetof(CPUPPCState, vsr[i].u64[0]);
2915 }
2916
acc_full_offset(int i)2917 static inline int acc_full_offset(int i)
2918 {
2919 return vsr_full_offset(i * 4);
2920 }
2921
fpr_offset(int i)2922 static inline int fpr_offset(int i)
2923 {
2924 return vsr64_offset(i, true);
2925 }
2926
cpu_fpr_ptr(CPUPPCState * env,int i)2927 static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
2928 {
2929 return (uint64_t *)((uintptr_t)env + fpr_offset(i));
2930 }
2931
cpu_vsrl_ptr(CPUPPCState * env,int i)2932 static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2933 {
2934 return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
2935 }
2936
avr64_offset(int i,bool high)2937 static inline long avr64_offset(int i, bool high)
2938 {
2939 return vsr64_offset(i + 32, high);
2940 }
2941
avr_full_offset(int i)2942 static inline int avr_full_offset(int i)
2943 {
2944 return vsr_full_offset(i + 32);
2945 }
2946
cpu_avr_ptr(CPUPPCState * env,int i)2947 static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2948 {
2949 return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
2950 }
2951
ppc_has_spr(PowerPCCPU * cpu,int spr)2952 static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr)
2953 {
2954 /* We can test whether the SPR is defined by checking for a valid name */
2955 return cpu->env.spr_cb[spr].name != NULL;
2956 }
2957
2958 #if !defined(CONFIG_USER_ONLY)
2959 /* Sort out endianness of interrupt. Depends on the CPU, HV mode, etc. */
ppc_interrupts_little_endian(PowerPCCPU * cpu,bool hv)2960 static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
2961 {
2962 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
2963 CPUPPCState *env = &cpu->env;
2964 bool ile;
2965
2966 if (hv && env->has_hv_mode) {
2967 if (is_isa300(pcc)) {
2968 ile = !!(env->spr[SPR_HID0] & HID0_POWER9_HILE);
2969 } else {
2970 ile = !!(env->spr[SPR_HID0] & HID0_HILE);
2971 }
2972
2973 } else if (pcc->lpcr_mask & LPCR_ILE) {
2974 ile = !!(env->spr[SPR_LPCR] & LPCR_ILE);
2975 } else {
2976 ile = FIELD_EX64(env->msr, MSR, ILE);
2977 }
2978
2979 return ile;
2980 }
2981 #endif
2982
2983 void dump_mmu(CPUPPCState *env);
2984
2985 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2986 void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
2987 uint32_t ppc_get_vscr(CPUPPCState *env);
2988 void ppc_set_cr(CPUPPCState *env, uint64_t cr);
2989 uint64_t ppc_get_cr(const CPUPPCState *env);
2990
2991 /*****************************************************************************/
2992 /* Power management enable checks */
check_pow_none(CPUPPCState * env)2993 static inline int check_pow_none(CPUPPCState *env)
2994 {
2995 return 0;
2996 }
2997
check_pow_nocheck(CPUPPCState * env)2998 static inline int check_pow_nocheck(CPUPPCState *env)
2999 {
3000 return 1;
3001 }
3002
3003 /*****************************************************************************/
3004 /* PowerPC implementations definitions */
3005
3006 #define POWERPC_FAMILY(_name) \
3007 static void \
3008 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3009 \
3010 static const TypeInfo \
3011 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3012 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3013 .parent = TYPE_POWERPC_CPU, \
3014 .abstract = true, \
3015 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3016 }; \
3017 \
3018 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3019 { \
3020 type_register_static( \
3021 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3022 } \
3023 \
3024 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3025 \
3026 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3027
3028
3029 #endif /* PPC_CPU_H */
3030