Home
last modified time | relevance | path

Searched defs:SSCG_PLL_BYPASS1_MASK (Results 1 – 25 of 65) sorted by relevance

123

/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clk/imx/
H A Dclk-sscg-pll.c65 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clk/imx/
H A Dclk-sscg-pll.c65 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/imx/
H A Dclk-sscg-pll.c65 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h356 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro

123