1 /* 2 * QEMU PIIX PCI ISA Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/range.h" 27 #include "hw/southbridge/piix.h" 28 #include "hw/irq.h" 29 #include "hw/isa/isa.h" 30 #include "hw/xen/xen.h" 31 #include "sysemu/xen.h" 32 #include "sysemu/reset.h" 33 #include "sysemu/runstate.h" 34 #include "migration/vmstate.h" 35 36 #define XEN_PIIX_NUM_PIRQS 128ULL 37 38 #define TYPE_PIIX3_DEVICE "PIIX3" 39 #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen" 40 41 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) 42 { 43 qemu_set_irq(piix3->pic[pic_irq], 44 !!(piix3->pic_levels & 45 (((1ULL << PIIX_NUM_PIRQS) - 1) << 46 (pic_irq * PIIX_NUM_PIRQS)))); 47 } 48 49 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) 50 { 51 int pic_irq; 52 uint64_t mask; 53 54 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; 55 if (pic_irq >= PIIX_NUM_PIC_IRQS) { 56 return; 57 } 58 59 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); 60 piix3->pic_levels &= ~mask; 61 piix3->pic_levels |= mask * !!level; 62 } 63 64 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) 65 { 66 int pic_irq; 67 68 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; 69 if (pic_irq >= PIIX_NUM_PIC_IRQS) { 70 return; 71 } 72 73 piix3_set_irq_level_internal(piix3, pirq, level); 74 75 piix3_set_irq_pic(piix3, pic_irq); 76 } 77 78 static void piix3_set_irq(void *opaque, int pirq, int level) 79 { 80 PIIX3State *piix3 = opaque; 81 piix3_set_irq_level(piix3, pirq, level); 82 } 83 84 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) 85 { 86 PIIX3State *piix3 = opaque; 87 int irq = piix3->dev.config[PIIX_PIRQCA + pin]; 88 PCIINTxRoute route; 89 90 if (irq < PIIX_NUM_PIC_IRQS) { 91 route.mode = PCI_INTX_ENABLED; 92 route.irq = irq; 93 } else { 94 route.mode = PCI_INTX_DISABLED; 95 route.irq = -1; 96 } 97 return route; 98 } 99 100 /* irq routing is changed. so rebuild bitmap */ 101 static void piix3_update_irq_levels(PIIX3State *piix3) 102 { 103 PCIBus *bus = pci_get_bus(&piix3->dev); 104 int pirq; 105 106 piix3->pic_levels = 0; 107 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { 108 piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq)); 109 } 110 } 111 112 static void piix3_write_config(PCIDevice *dev, 113 uint32_t address, uint32_t val, int len) 114 { 115 pci_default_write_config(dev, address, val, len); 116 if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { 117 PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); 118 int pic_irq; 119 120 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); 121 piix3_update_irq_levels(piix3); 122 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { 123 piix3_set_irq_pic(piix3, pic_irq); 124 } 125 } 126 } 127 128 static void piix3_write_config_xen(PCIDevice *dev, 129 uint32_t address, uint32_t val, int len) 130 { 131 xen_piix_pci_write_config_client(address, val, len); 132 piix3_write_config(dev, address, val, len); 133 } 134 135 static void piix3_reset(void *opaque) 136 { 137 PIIX3State *d = opaque; 138 uint8_t *pci_conf = d->dev.config; 139 140 pci_conf[0x04] = 0x07; /* master, memory and I/O */ 141 pci_conf[0x05] = 0x00; 142 pci_conf[0x06] = 0x00; 143 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */ 144 pci_conf[0x4c] = 0x4d; 145 pci_conf[0x4e] = 0x03; 146 pci_conf[0x4f] = 0x00; 147 pci_conf[0x60] = 0x80; 148 pci_conf[0x61] = 0x80; 149 pci_conf[0x62] = 0x80; 150 pci_conf[0x63] = 0x80; 151 pci_conf[0x69] = 0x02; 152 pci_conf[0x70] = 0x80; 153 pci_conf[0x76] = 0x0c; 154 pci_conf[0x77] = 0x0c; 155 pci_conf[0x78] = 0x02; 156 pci_conf[0x79] = 0x00; 157 pci_conf[0x80] = 0x00; 158 pci_conf[0x82] = 0x00; 159 pci_conf[0xa0] = 0x08; 160 pci_conf[0xa2] = 0x00; 161 pci_conf[0xa3] = 0x00; 162 pci_conf[0xa4] = 0x00; 163 pci_conf[0xa5] = 0x00; 164 pci_conf[0xa6] = 0x00; 165 pci_conf[0xa7] = 0x00; 166 pci_conf[0xa8] = 0x0f; 167 pci_conf[0xaa] = 0x00; 168 pci_conf[0xab] = 0x00; 169 pci_conf[0xac] = 0x00; 170 pci_conf[0xae] = 0x00; 171 172 d->pic_levels = 0; 173 d->rcr = 0; 174 } 175 176 static int piix3_post_load(void *opaque, int version_id) 177 { 178 PIIX3State *piix3 = opaque; 179 int pirq; 180 181 /* 182 * Because the i8259 has not been deserialized yet, qemu_irq_raise 183 * might bring the system to a different state than the saved one; 184 * for example, the interrupt could be masked but the i8259 would 185 * not know that yet and would trigger an interrupt in the CPU. 186 * 187 * Here, we update irq levels without raising the interrupt. 188 * Interrupt state will be deserialized separately through the i8259. 189 */ 190 piix3->pic_levels = 0; 191 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { 192 piix3_set_irq_level_internal(piix3, pirq, 193 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq)); 194 } 195 return 0; 196 } 197 198 static int piix3_pre_save(void *opaque) 199 { 200 int i; 201 PIIX3State *piix3 = opaque; 202 203 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { 204 piix3->pci_irq_levels_vmstate[i] = 205 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i); 206 } 207 208 return 0; 209 } 210 211 static bool piix3_rcr_needed(void *opaque) 212 { 213 PIIX3State *piix3 = opaque; 214 215 return (piix3->rcr != 0); 216 } 217 218 static const VMStateDescription vmstate_piix3_rcr = { 219 .name = "PIIX3/rcr", 220 .version_id = 1, 221 .minimum_version_id = 1, 222 .needed = piix3_rcr_needed, 223 .fields = (VMStateField[]) { 224 VMSTATE_UINT8(rcr, PIIX3State), 225 VMSTATE_END_OF_LIST() 226 } 227 }; 228 229 static const VMStateDescription vmstate_piix3 = { 230 .name = "PIIX3", 231 .version_id = 3, 232 .minimum_version_id = 2, 233 .post_load = piix3_post_load, 234 .pre_save = piix3_pre_save, 235 .fields = (VMStateField[]) { 236 VMSTATE_PCI_DEVICE(dev, PIIX3State), 237 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, 238 PIIX_NUM_PIRQS, 3), 239 VMSTATE_END_OF_LIST() 240 }, 241 .subsections = (const VMStateDescription*[]) { 242 &vmstate_piix3_rcr, 243 NULL 244 } 245 }; 246 247 248 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) 249 { 250 PIIX3State *d = opaque; 251 252 if (val & 4) { 253 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 254 return; 255 } 256 d->rcr = val & 2; /* keep System Reset type only */ 257 } 258 259 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) 260 { 261 PIIX3State *d = opaque; 262 263 return d->rcr; 264 } 265 266 static const MemoryRegionOps rcr_ops = { 267 .read = rcr_read, 268 .write = rcr_write, 269 .endianness = DEVICE_LITTLE_ENDIAN 270 }; 271 272 static void piix3_realize(PCIDevice *dev, Error **errp) 273 { 274 PIIX3State *d = PIIX3_PCI_DEVICE(dev); 275 276 if (!isa_bus_new(DEVICE(d), get_system_memory(), 277 pci_address_space_io(dev), errp)) { 278 return; 279 } 280 281 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, 282 "piix3-reset-control", 1); 283 memory_region_add_subregion_overlap(pci_address_space_io(dev), 284 PIIX_RCR_IOPORT, &d->rcr_mem, 1); 285 286 qemu_register_reset(piix3_reset, d); 287 } 288 289 static void pci_piix3_class_init(ObjectClass *klass, void *data) 290 { 291 DeviceClass *dc = DEVICE_CLASS(klass); 292 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 293 294 dc->desc = "ISA bridge"; 295 dc->vmsd = &vmstate_piix3; 296 dc->hotpluggable = false; 297 k->realize = piix3_realize; 298 k->vendor_id = PCI_VENDOR_ID_INTEL; 299 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ 300 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; 301 k->class_id = PCI_CLASS_BRIDGE_ISA; 302 /* 303 * Reason: part of PIIX3 southbridge, needs to be wired up by 304 * pc_piix.c's pc_init1() 305 */ 306 dc->user_creatable = false; 307 } 308 309 static const TypeInfo piix3_pci_type_info = { 310 .name = TYPE_PIIX3_PCI_DEVICE, 311 .parent = TYPE_PCI_DEVICE, 312 .instance_size = sizeof(PIIX3State), 313 .abstract = true, 314 .class_init = pci_piix3_class_init, 315 .interfaces = (InterfaceInfo[]) { 316 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 317 { }, 318 }, 319 }; 320 321 static void piix3_class_init(ObjectClass *klass, void *data) 322 { 323 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 324 325 k->config_write = piix3_write_config; 326 } 327 328 static const TypeInfo piix3_info = { 329 .name = TYPE_PIIX3_DEVICE, 330 .parent = TYPE_PIIX3_PCI_DEVICE, 331 .class_init = piix3_class_init, 332 }; 333 334 static void piix3_xen_class_init(ObjectClass *klass, void *data) 335 { 336 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 337 338 k->config_write = piix3_write_config_xen; 339 }; 340 341 static const TypeInfo piix3_xen_info = { 342 .name = TYPE_PIIX3_XEN_DEVICE, 343 .parent = TYPE_PIIX3_PCI_DEVICE, 344 .class_init = piix3_xen_class_init, 345 }; 346 347 static void piix3_register_types(void) 348 { 349 type_register_static(&piix3_pci_type_info); 350 type_register_static(&piix3_info); 351 type_register_static(&piix3_xen_info); 352 } 353 354 type_init(piix3_register_types) 355 356 /* 357 * Return the global irq number corresponding to a given device irq 358 * pin. We could also use the bus number to have a more precise mapping. 359 */ 360 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) 361 { 362 int slot_addend; 363 slot_addend = PCI_SLOT(pci_dev->devfn) - 1; 364 return (pci_intx + slot_addend) & 3; 365 } 366 367 PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus) 368 { 369 PIIX3State *piix3; 370 PCIDevice *pci_dev; 371 372 /* 373 * Xen supports additional interrupt routes from the PCI devices to 374 * the IOAPIC: the four pins of each PCI device on the bus are also 375 * connected to the IOAPIC directly. 376 * These additional routes can be discovered through ACPI. 377 */ 378 if (xen_enabled()) { 379 pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, 380 TYPE_PIIX3_XEN_DEVICE); 381 piix3 = PIIX3_PCI_DEVICE(pci_dev); 382 pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, 383 piix3, XEN_PIIX_NUM_PIRQS); 384 } else { 385 pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, 386 TYPE_PIIX3_DEVICE); 387 piix3 = PIIX3_PCI_DEVICE(pci_dev); 388 pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, 389 piix3, PIIX_NUM_PIRQS); 390 pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); 391 } 392 *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); 393 394 return piix3; 395 } 396