1 /*
2 * QEMU CPU model
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20 #ifndef QEMU_CPU_H
21 #define QEMU_CPU_H
22
23 #include "hw/qdev-core.h"
24 #include "disas/dis-asm.h"
25 #include "exec/breakpoint.h"
26 #include "exec/hwaddr.h"
27 #include "exec/vaddr.h"
28 #include "exec/memattrs.h"
29 #include "exec/mmu-access-type.h"
30 #include "exec/tlb-common.h"
31 #include "qapi/qapi-types-machine.h"
32 #include "qapi/qapi-types-run-state.h"
33 #include "qemu/bitmap.h"
34 #include "qemu/rcu_queue.h"
35 #include "qemu/queue.h"
36 #include "qemu/thread.h"
37 #include "qom/object.h"
38
39 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
40 void *opaque);
41
42 /**
43 * SECTION:cpu
44 * @section_id: QEMU-cpu
45 * @title: CPU Class
46 * @short_description: Base class for all CPUs
47 */
48
49 #define TYPE_CPU "cpu"
50
51 /* Since this macro is used a lot in hot code paths and in conjunction with
52 * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
53 * an unchecked cast.
54 */
55 #define CPU(obj) ((CPUState *)(obj))
56
57 /*
58 * The class checkers bring in CPU_GET_CLASS() which is potentially
59 * expensive given the eventual call to
60 * object_class_dynamic_cast_assert(). Because of this the CPUState
61 * has a cached value for the class in cs->cc which is set up in
62 * cpu_exec_realizefn() for use in hot code paths.
63 */
64 typedef struct CPUClass CPUClass;
65 DECLARE_CLASS_CHECKERS(CPUClass, CPU,
66 TYPE_CPU)
67
68 /**
69 * OBJECT_DECLARE_CPU_TYPE:
70 * @CpuInstanceType: instance struct name
71 * @CpuClassType: class struct name
72 * @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separators
73 *
74 * This macro is typically used in "cpu-qom.h" header file, and will:
75 *
76 * - create the typedefs for the CPU object and class structs
77 * - register the type for use with g_autoptr
78 * - provide three standard type cast functions
79 *
80 * The object struct and class struct need to be declared manually.
81 */
82 #define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \
83 typedef struct ArchCPU CpuInstanceType; \
84 OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME);
85
86 typedef struct CPUWatchpoint CPUWatchpoint;
87
88 /* see physmem.c */
89 struct CPUAddressSpace;
90
91 /* see accel/tcg/tb-jmp-cache.h */
92 struct CPUJumpCache;
93
94 /* see accel-cpu.h */
95 struct AccelCPUClass;
96
97 /* see sysemu-cpu-ops.h */
98 struct SysemuCPUOps;
99
100 /**
101 * CPUClass:
102 * @class_by_name: Callback to map -cpu command line model name to an
103 * instantiatable CPU type.
104 * @parse_features: Callback to parse command line arguments.
105 * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
106 * @has_work: Callback for checking if there is work to do.
107 * @mmu_index: Callback for choosing softmmu mmu index;
108 * may be used internally by memory_rw_debug without TCG.
109 * @memory_rw_debug: Callback for GDB memory access.
110 * @dump_state: Callback for dumping state.
111 * @query_cpu_fast:
112 * Fill in target specific information for the "query-cpus-fast"
113 * QAPI call.
114 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
115 * @set_pc: Callback for setting the Program Counter register. This
116 * should have the semantics used by the target architecture when
117 * setting the PC from a source such as an ELF file entry point;
118 * for example on Arm it will also set the Thumb mode bit based
119 * on the least significant bit of the new PC value.
120 * If the target behaviour here is anything other than "set
121 * the PC register to the value passed in" then the target must
122 * also implement the synchronize_from_tb hook.
123 * @get_pc: Callback for getting the Program Counter register.
124 * As above, with the semantics of the target architecture.
125 * @gdb_read_register: Callback for letting GDB read a register.
126 * @gdb_write_register: Callback for letting GDB write a register.
127 * @gdb_adjust_breakpoint: Callback for adjusting the address of a
128 * breakpoint. Used by AVR to handle a gdb mis-feature with
129 * its Harvard architecture split code and data.
130 * @gdb_num_core_regs: Number of core registers accessible to GDB or 0 to infer
131 * from @gdb_core_xml_file.
132 * @gdb_core_xml_file: File name for core registers GDB XML description.
133 * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
134 * before the insn which triggers a watchpoint rather than after it.
135 * @gdb_arch_name: Optional callback that returns the architecture name known
136 * to GDB. The caller must free the returned string with g_free.
137 * @disas_set_info: Setup architecture specific components of disassembly info
138 * @adjust_watchpoint_address: Perform a target-specific adjustment to an
139 * address before attempting to match it against watchpoints.
140 * @deprecation_note: If this CPUClass is deprecated, this field provides
141 * related information.
142 *
143 * Represents a CPU family or model.
144 */
145 struct CPUClass {
146 /*< private >*/
147 DeviceClass parent_class;
148 /*< public >*/
149
150 ObjectClass *(*class_by_name)(const char *cpu_model);
151 void (*parse_features)(const char *typename, char *str, Error **errp);
152
153 bool (*has_work)(CPUState *cpu);
154 int (*mmu_index)(CPUState *cpu, bool ifetch);
155 int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
156 uint8_t *buf, int len, bool is_write);
157 void (*dump_state)(CPUState *cpu, FILE *, int flags);
158 void (*query_cpu_fast)(CPUState *cpu, CpuInfoFast *value);
159 int64_t (*get_arch_id)(CPUState *cpu);
160 void (*set_pc)(CPUState *cpu, vaddr value);
161 vaddr (*get_pc)(CPUState *cpu);
162 int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
163 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
164 vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr);
165
166 const char *gdb_core_xml_file;
167 const gchar * (*gdb_arch_name)(CPUState *cpu);
168
169 void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
170
171 const char *deprecation_note;
172 struct AccelCPUClass *accel_cpu;
173
174 /* when system emulation is not available, this pointer is NULL */
175 const struct SysemuCPUOps *sysemu_ops;
176
177 /* when TCG is not available, this pointer is NULL */
178 const TCGCPUOps *tcg_ops;
179
180 /*
181 * if not NULL, this is called in order for the CPUClass to initialize
182 * class data that depends on the accelerator, see accel/accel-common.c.
183 */
184 void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc);
185
186 /*
187 * Keep non-pointer data at the end to minimize holes.
188 */
189 int reset_dump_flags;
190 int gdb_num_core_regs;
191 bool gdb_stop_before_watchpoint;
192 };
193
194 /*
195 * Fix the number of mmu modes to 16, which is also the maximum
196 * supported by the softmmu tlb api.
197 */
198 #define NB_MMU_MODES 16
199
200 /* Use a fully associative victim tlb of 8 entries. */
201 #define CPU_VTLB_SIZE 8
202
203 /*
204 * The full TLB entry, which is not accessed by generated TCG code,
205 * so the layout is not as critical as that of CPUTLBEntry. This is
206 * also why we don't want to combine the two structs.
207 */
208 typedef struct CPUTLBEntryFull {
209 /*
210 * @xlat_section contains:
211 * - in the lower TARGET_PAGE_BITS, a physical section number
212 * - with the lower TARGET_PAGE_BITS masked off, an offset which
213 * must be added to the virtual address to obtain:
214 * + the ram_addr_t of the target RAM (if the physical section
215 * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM)
216 * + the offset within the target MemoryRegion (otherwise)
217 */
218 hwaddr xlat_section;
219
220 /*
221 * @phys_addr contains the physical address in the address space
222 * given by cpu_asidx_from_attrs(cpu, @attrs).
223 */
224 hwaddr phys_addr;
225
226 /* @attrs contains the memory transaction attributes for the page. */
227 MemTxAttrs attrs;
228
229 /* @prot contains the complete protections for the page. */
230 uint8_t prot;
231
232 /* @lg_page_size contains the log2 of the page size. */
233 uint8_t lg_page_size;
234
235 /* Additional tlb flags requested by tlb_fill. */
236 uint8_t tlb_fill_flags;
237
238 /*
239 * Additional tlb flags for use by the slow path. If non-zero,
240 * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW.
241 */
242 uint8_t slow_flags[MMU_ACCESS_COUNT];
243
244 /*
245 * Allow target-specific additions to this structure.
246 * This may be used to cache items from the guest cpu
247 * page tables for later use by the implementation.
248 */
249 union {
250 /*
251 * Cache the attrs and shareability fields from the page table entry.
252 *
253 * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2].
254 * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format.
255 * For shareability and guarded, as in the SH and GP fields respectively
256 * of the VMSAv8-64 PTEs.
257 */
258 struct {
259 uint8_t pte_attrs;
260 uint8_t shareability;
261 bool guarded;
262 } arm;
263 } extra;
264 } CPUTLBEntryFull;
265
266 /*
267 * Data elements that are per MMU mode, minus the bits accessed by
268 * the TCG fast path.
269 */
270 typedef struct CPUTLBDesc {
271 /*
272 * Describe a region covering all of the large pages allocated
273 * into the tlb. When any page within this region is flushed,
274 * we must flush the entire tlb. The region is matched if
275 * (addr & large_page_mask) == large_page_addr.
276 */
277 vaddr large_page_addr;
278 vaddr large_page_mask;
279 /* host time (in ns) at the beginning of the time window */
280 int64_t window_begin_ns;
281 /* maximum number of entries observed in the window */
282 size_t window_max_entries;
283 size_t n_used_entries;
284 /* The next index to use in the tlb victim table. */
285 size_t vindex;
286 /* The tlb victim table, in two parts. */
287 CPUTLBEntry vtable[CPU_VTLB_SIZE];
288 CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE];
289 CPUTLBEntryFull *fulltlb;
290 } CPUTLBDesc;
291
292 /*
293 * Data elements that are shared between all MMU modes.
294 */
295 typedef struct CPUTLBCommon {
296 /* Serialize updates to f.table and d.vtable, and others as noted. */
297 QemuSpin lock;
298 /*
299 * Within dirty, for each bit N, modifications have been made to
300 * mmu_idx N since the last time that mmu_idx was flushed.
301 * Protected by tlb_c.lock.
302 */
303 uint16_t dirty;
304 /*
305 * Statistics. These are not lock protected, but are read and
306 * written atomically. This allows the monitor to print a snapshot
307 * of the stats without interfering with the cpu.
308 */
309 size_t full_flush_count;
310 size_t part_flush_count;
311 size_t elide_flush_count;
312 } CPUTLBCommon;
313
314 /*
315 * The entire softmmu tlb, for all MMU modes.
316 * The meaning of each of the MMU modes is defined in the target code.
317 * Since this is placed within CPUNegativeOffsetState, the smallest
318 * negative offsets are at the end of the struct.
319 */
320 typedef struct CPUTLB {
321 #ifdef CONFIG_TCG
322 CPUTLBCommon c;
323 CPUTLBDesc d[NB_MMU_MODES];
324 CPUTLBDescFast f[NB_MMU_MODES];
325 #endif
326 } CPUTLB;
327
328 /*
329 * Low 16 bits: number of cycles left, used only in icount mode.
330 * High 16 bits: Set to -1 to force TCG to stop executing linked TBs
331 * for this CPU and return to its top level loop (even in non-icount mode).
332 * This allows a single read-compare-cbranch-write sequence to test
333 * for both decrementer underflow and exceptions.
334 */
335 typedef union IcountDecr {
336 uint32_t u32;
337 struct {
338 #if HOST_BIG_ENDIAN
339 uint16_t high;
340 uint16_t low;
341 #else
342 uint16_t low;
343 uint16_t high;
344 #endif
345 } u16;
346 } IcountDecr;
347
348 /**
349 * CPUNegativeOffsetState: Elements of CPUState most efficiently accessed
350 * from CPUArchState, via small negative offsets.
351 * @can_do_io: True if memory-mapped IO is allowed.
352 * @plugin_mem_cbs: active plugin memory callbacks
353 */
354 typedef struct CPUNegativeOffsetState {
355 CPUTLB tlb;
356 #ifdef CONFIG_PLUGIN
357 /*
358 * The callback pointer are accessed via TCG (see gen_empty_mem_helper).
359 */
360 GArray *plugin_mem_cbs;
361 #endif
362 IcountDecr icount_decr;
363 bool can_do_io;
364 } CPUNegativeOffsetState;
365
366 struct KVMState;
367 struct kvm_run;
368
369 /* work queue */
370
371 /* The union type allows passing of 64 bit target pointers on 32 bit
372 * hosts in a single parameter
373 */
374 typedef union {
375 int host_int;
376 unsigned long host_ulong;
377 void *host_ptr;
378 vaddr target_ptr;
379 } run_on_cpu_data;
380
381 #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)})
382 #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)})
383 #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)})
384 #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)})
385 #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL)
386
387 typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data);
388
389 struct qemu_work_item;
390
391 #define CPU_UNSET_NUMA_NODE_ID -1
392
393 /**
394 * struct CPUState - common state of one CPU core or thread.
395 *
396 * @cpu_index: CPU index (informative).
397 * @cluster_index: Identifies which cluster this CPU is in.
398 * For boards which don't define clusters or for "loose" CPUs not assigned
399 * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will
400 * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER
401 * QOM parent.
402 * Under TCG this value is propagated to @tcg_cflags.
403 * See TranslationBlock::TCG CF_CLUSTER_MASK.
404 * @tcg_cflags: Pre-computed cflags for this cpu.
405 * @nr_cores: Number of cores within this CPU package.
406 * @nr_threads: Number of threads within this CPU core.
407 * @thread: Host thread details, only live once @created is #true
408 * @sem: WIN32 only semaphore used only for qtest
409 * @thread_id: native thread id of vCPU, only live once @created is #true
410 * @running: #true if CPU is currently running (lockless).
411 * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end;
412 * valid under cpu_list_lock.
413 * @created: Indicates whether the CPU thread has been successfully created.
414 * @halt_cond: condition variable sleeping threads can wait on.
415 * @interrupt_request: Indicates a pending interrupt request.
416 * @halted: Nonzero if the CPU is in suspended state.
417 * @stop: Indicates a pending stop request.
418 * @stopped: Indicates the CPU has been artificially stopped.
419 * @unplug: Indicates a pending CPU unplug request.
420 * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
421 * @singlestep_enabled: Flags for single-stepping.
422 * @icount_extra: Instructions until next timer event.
423 * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the
424 * AddressSpaces this CPU has)
425 * @num_ases: number of CPUAddressSpaces in @cpu_ases
426 * @as: Pointer to the first AddressSpace, for the convenience of targets which
427 * only have a single AddressSpace
428 * @gdb_regs: Additional GDB registers.
429 * @gdb_num_regs: Number of total registers accessible to GDB.
430 * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
431 * @node: QTAILQ of CPUs sharing TB cache.
432 * @opaque: User data.
433 * @mem_io_pc: Host Program Counter at which the memory was accessed.
434 * @accel: Pointer to accelerator specific state.
435 * @kvm_fd: vCPU file descriptor for KVM.
436 * @work_mutex: Lock to prevent multiple access to @work_list.
437 * @work_list: List of pending asynchronous work.
438 * @plugin_state: per-CPU plugin state
439 * @ignore_memory_transaction_failures: Cached copy of the MachineState
440 * flag of the same name: allows the board to suppress calling of the
441 * CPU do_transaction_failed hook function.
442 * @kvm_dirty_gfns: Points to the KVM dirty ring for this CPU when KVM dirty
443 * ring is enabled.
444 * @kvm_fetch_index: Keeps the index that we last fetched from the per-vCPU
445 * dirty ring structure.
446 *
447 * @neg_align: The CPUState is the common part of a concrete ArchCPU
448 * which is allocated when an individual CPU instance is created. As
449 * such care is taken is ensure there is no gap between between
450 * CPUState and CPUArchState within ArchCPU.
451 *
452 * @neg: The architectural register state ("cpu_env") immediately follows
453 * CPUState in ArchCPU and is passed to TCG code. The @neg structure holds
454 * some common TCG CPU variables which are accessed with a negative offset
455 * from cpu_env.
456 */
457 struct CPUState {
458 /*< private >*/
459 DeviceState parent_obj;
460 /* cache to avoid expensive CPU_GET_CLASS */
461 CPUClass *cc;
462 /*< public >*/
463
464 int nr_cores;
465 int nr_threads;
466
467 struct QemuThread *thread;
468 #ifdef _WIN32
469 QemuSemaphore sem;
470 #endif
471 int thread_id;
472 bool running, has_waiter;
473 struct QemuCond *halt_cond;
474 bool thread_kicked;
475 bool created;
476 bool stop;
477 bool stopped;
478
479 /* Should CPU start in powered-off state? */
480 bool start_powered_off;
481
482 bool unplug;
483 bool crash_occurred;
484 bool exit_request;
485 int exclusive_context_count;
486 uint32_t cflags_next_tb;
487 /* updates protected by BQL */
488 uint32_t interrupt_request;
489 int singlestep_enabled;
490 int64_t icount_budget;
491 int64_t icount_extra;
492 uint64_t random_seed;
493 sigjmp_buf jmp_env;
494
495 QemuMutex work_mutex;
496 QSIMPLEQ_HEAD(, qemu_work_item) work_list;
497
498 struct CPUAddressSpace *cpu_ases;
499 int num_ases;
500 AddressSpace *as;
501 MemoryRegion *memory;
502
503 struct CPUJumpCache *tb_jmp_cache;
504
505 GArray *gdb_regs;
506 int gdb_num_regs;
507 int gdb_num_g_regs;
508 QTAILQ_ENTRY(CPUState) node;
509
510 /* ice debug support */
511 QTAILQ_HEAD(, CPUBreakpoint) breakpoints;
512
513 QTAILQ_HEAD(, CPUWatchpoint) watchpoints;
514 CPUWatchpoint *watchpoint_hit;
515
516 void *opaque;
517
518 /* In order to avoid passing too many arguments to the MMIO helpers,
519 * we store some rarely used information in the CPU context.
520 */
521 uintptr_t mem_io_pc;
522
523 /* Only used in KVM */
524 int kvm_fd;
525 struct KVMState *kvm_state;
526 struct kvm_run *kvm_run;
527 struct kvm_dirty_gfn *kvm_dirty_gfns;
528 uint32_t kvm_fetch_index;
529 uint64_t dirty_pages;
530 int kvm_vcpu_stats_fd;
531 bool vcpu_dirty;
532
533 /* Use by accel-block: CPU is executing an ioctl() */
534 QemuLockCnt in_ioctl_lock;
535
536 #ifdef CONFIG_PLUGIN
537 CPUPluginState *plugin_state;
538 #endif
539
540 /* TODO Move common fields from CPUArchState here. */
541 int cpu_index;
542 int cluster_index;
543 uint32_t tcg_cflags;
544 uint32_t halted;
545 int32_t exception_index;
546
547 AccelCPUState *accel;
548
549 /* Used to keep track of an outstanding cpu throttle thread for migration
550 * autoconverge
551 */
552 bool throttle_thread_scheduled;
553
554 /*
555 * Sleep throttle_us_per_full microseconds once dirty ring is full
556 * if dirty page rate limit is enabled.
557 */
558 int64_t throttle_us_per_full;
559
560 bool ignore_memory_transaction_failures;
561
562 /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */
563 bool prctl_unalign_sigbus;
564
565 /* track IOMMUs whose translations we've cached in the TCG TLB */
566 GArray *iommu_notifiers;
567
568 /*
569 * MUST BE LAST in order to minimize the displacement to CPUArchState.
570 */
571 char neg_align[-sizeof(CPUNegativeOffsetState) % 16] QEMU_ALIGNED(16);
572 CPUNegativeOffsetState neg;
573 };
574
575 /* Validate placement of CPUNegativeOffsetState. */
576 QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) !=
577 sizeof(CPUState) - sizeof(CPUNegativeOffsetState));
578
cpu_env(CPUState * cpu)579 static inline CPUArchState *cpu_env(CPUState *cpu)
580 {
581 /* We validate that CPUArchState follows CPUState in cpu-all.h. */
582 return (CPUArchState *)(cpu + 1);
583 }
584
585 typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ;
586 extern CPUTailQ cpus_queue;
587
588 #define first_cpu QTAILQ_FIRST_RCU(&cpus_queue)
589 #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node)
590 #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus_queue, node)
591 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
592 QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus_queue, node, next_cpu)
593
594 extern __thread CPUState *current_cpu;
595
596 /**
597 * qemu_tcg_mttcg_enabled:
598 * Check whether we are running MultiThread TCG or not.
599 *
600 * Returns: %true if we are in MTTCG mode %false otherwise.
601 */
602 extern bool mttcg_enabled;
603 #define qemu_tcg_mttcg_enabled() (mttcg_enabled)
604
605 /**
606 * cpu_paging_enabled:
607 * @cpu: The CPU whose state is to be inspected.
608 *
609 * Returns: %true if paging is enabled, %false otherwise.
610 */
611 bool cpu_paging_enabled(const CPUState *cpu);
612
613 /**
614 * cpu_get_memory_mapping:
615 * @cpu: The CPU whose memory mappings are to be obtained.
616 * @list: Where to write the memory mappings to.
617 * @errp: Pointer for reporting an #Error.
618 *
619 * Returns: %true on success, %false otherwise.
620 */
621 bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
622 Error **errp);
623
624 #if !defined(CONFIG_USER_ONLY)
625
626 /**
627 * cpu_write_elf64_note:
628 * @f: pointer to a function that writes memory to a file
629 * @cpu: The CPU whose memory is to be dumped
630 * @cpuid: ID number of the CPU
631 * @opaque: pointer to the CPUState struct
632 */
633 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
634 int cpuid, void *opaque);
635
636 /**
637 * cpu_write_elf64_qemunote:
638 * @f: pointer to a function that writes memory to a file
639 * @cpu: The CPU whose memory is to be dumped
640 * @cpuid: ID number of the CPU
641 * @opaque: pointer to the CPUState struct
642 */
643 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
644 void *opaque);
645
646 /**
647 * cpu_write_elf32_note:
648 * @f: pointer to a function that writes memory to a file
649 * @cpu: The CPU whose memory is to be dumped
650 * @cpuid: ID number of the CPU
651 * @opaque: pointer to the CPUState struct
652 */
653 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
654 int cpuid, void *opaque);
655
656 /**
657 * cpu_write_elf32_qemunote:
658 * @f: pointer to a function that writes memory to a file
659 * @cpu: The CPU whose memory is to be dumped
660 * @cpuid: ID number of the CPU
661 * @opaque: pointer to the CPUState struct
662 */
663 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
664 void *opaque);
665
666 /**
667 * cpu_get_crash_info:
668 * @cpu: The CPU to get crash information for
669 *
670 * Gets the previously saved crash information.
671 * Caller is responsible for freeing the data.
672 */
673 GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
674
675 #endif /* !CONFIG_USER_ONLY */
676
677 /**
678 * CPUDumpFlags:
679 * @CPU_DUMP_CODE:
680 * @CPU_DUMP_FPU: dump FPU register state, not just integer
681 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
682 * @CPU_DUMP_VPU: dump VPU registers
683 */
684 enum CPUDumpFlags {
685 CPU_DUMP_CODE = 0x00010000,
686 CPU_DUMP_FPU = 0x00020000,
687 CPU_DUMP_CCOP = 0x00040000,
688 CPU_DUMP_VPU = 0x00080000,
689 };
690
691 /**
692 * cpu_dump_state:
693 * @cpu: The CPU whose state is to be dumped.
694 * @f: If non-null, dump to this stream, else to current print sink.
695 *
696 * Dumps CPU state.
697 */
698 void cpu_dump_state(CPUState *cpu, FILE *f, int flags);
699
700 #ifndef CONFIG_USER_ONLY
701 /**
702 * cpu_get_phys_page_attrs_debug:
703 * @cpu: The CPU to obtain the physical page address for.
704 * @addr: The virtual address.
705 * @attrs: Updated on return with the memory transaction attributes to use
706 * for this access.
707 *
708 * Obtains the physical page corresponding to a virtual one, together
709 * with the corresponding memory transaction attributes to use for the access.
710 * Use it only for debugging because no protection checks are done.
711 *
712 * Returns: Corresponding physical page address or -1 if no page found.
713 */
714 hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
715 MemTxAttrs *attrs);
716
717 /**
718 * cpu_get_phys_page_debug:
719 * @cpu: The CPU to obtain the physical page address for.
720 * @addr: The virtual address.
721 *
722 * Obtains the physical page corresponding to a virtual one.
723 * Use it only for debugging because no protection checks are done.
724 *
725 * Returns: Corresponding physical page address or -1 if no page found.
726 */
727 hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
728
729 /** cpu_asidx_from_attrs:
730 * @cpu: CPU
731 * @attrs: memory transaction attributes
732 *
733 * Returns the address space index specifying the CPU AddressSpace
734 * to use for a memory access with the given transaction attributes.
735 */
736 int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
737
738 /**
739 * cpu_virtio_is_big_endian:
740 * @cpu: CPU
741
742 * Returns %true if a CPU which supports runtime configurable endianness
743 * is currently big-endian.
744 */
745 bool cpu_virtio_is_big_endian(CPUState *cpu);
746
747 #endif /* CONFIG_USER_ONLY */
748
749 /**
750 * cpu_list_add:
751 * @cpu: The CPU to be added to the list of CPUs.
752 */
753 void cpu_list_add(CPUState *cpu);
754
755 /**
756 * cpu_list_remove:
757 * @cpu: The CPU to be removed from the list of CPUs.
758 */
759 void cpu_list_remove(CPUState *cpu);
760
761 /**
762 * cpu_reset:
763 * @cpu: The CPU whose state is to be reset.
764 */
765 void cpu_reset(CPUState *cpu);
766
767 /**
768 * cpu_class_by_name:
769 * @typename: The CPU base type.
770 * @cpu_model: The model string without any parameters.
771 *
772 * Looks up a concrete CPU #ObjectClass matching name @cpu_model.
773 *
774 * Returns: A concrete #CPUClass or %NULL if no matching class is found
775 * or if the matching class is abstract.
776 */
777 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
778
779 /**
780 * cpu_model_from_type:
781 * @typename: The CPU type name
782 *
783 * Extract the CPU model name from the CPU type name. The
784 * CPU type name is either the combination of the CPU model
785 * name and suffix, or same to the CPU model name.
786 *
787 * Returns: CPU model name or NULL if the CPU class doesn't exist
788 * The user should g_free() the string once no longer needed.
789 */
790 char *cpu_model_from_type(const char *typename);
791
792 /**
793 * cpu_create:
794 * @typename: The CPU type.
795 *
796 * Instantiates a CPU and realizes the CPU.
797 *
798 * Returns: A #CPUState or %NULL if an error occurred.
799 */
800 CPUState *cpu_create(const char *typename);
801
802 /**
803 * parse_cpu_option:
804 * @cpu_option: The -cpu option including optional parameters.
805 *
806 * processes optional parameters and registers them as global properties
807 *
808 * Returns: type of CPU to create or prints error and terminates process
809 * if an error occurred.
810 */
811 const char *parse_cpu_option(const char *cpu_option);
812
813 /**
814 * cpu_has_work:
815 * @cpu: The vCPU to check.
816 *
817 * Checks whether the CPU has work to do.
818 *
819 * Returns: %true if the CPU has work, %false otherwise.
820 */
cpu_has_work(CPUState * cpu)821 static inline bool cpu_has_work(CPUState *cpu)
822 {
823 CPUClass *cc = CPU_GET_CLASS(cpu);
824
825 g_assert(cc->has_work);
826 return cc->has_work(cpu);
827 }
828
829 /**
830 * qemu_cpu_is_self:
831 * @cpu: The vCPU to check against.
832 *
833 * Checks whether the caller is executing on the vCPU thread.
834 *
835 * Returns: %true if called from @cpu's thread, %false otherwise.
836 */
837 bool qemu_cpu_is_self(CPUState *cpu);
838
839 /**
840 * qemu_cpu_kick:
841 * @cpu: The vCPU to kick.
842 *
843 * Kicks @cpu's thread.
844 */
845 void qemu_cpu_kick(CPUState *cpu);
846
847 /**
848 * cpu_is_stopped:
849 * @cpu: The CPU to check.
850 *
851 * Checks whether the CPU is stopped.
852 *
853 * Returns: %true if run state is not running or if artificially stopped;
854 * %false otherwise.
855 */
856 bool cpu_is_stopped(CPUState *cpu);
857
858 /**
859 * do_run_on_cpu:
860 * @cpu: The vCPU to run on.
861 * @func: The function to be executed.
862 * @data: Data to pass to the function.
863 * @mutex: Mutex to release while waiting for @func to run.
864 *
865 * Used internally in the implementation of run_on_cpu.
866 */
867 void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data,
868 QemuMutex *mutex);
869
870 /**
871 * run_on_cpu:
872 * @cpu: The vCPU to run on.
873 * @func: The function to be executed.
874 * @data: Data to pass to the function.
875 *
876 * Schedules the function @func for execution on the vCPU @cpu.
877 */
878 void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
879
880 /**
881 * async_run_on_cpu:
882 * @cpu: The vCPU to run on.
883 * @func: The function to be executed.
884 * @data: Data to pass to the function.
885 *
886 * Schedules the function @func for execution on the vCPU @cpu asynchronously.
887 */
888 void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
889
890 /**
891 * async_safe_run_on_cpu:
892 * @cpu: The vCPU to run on.
893 * @func: The function to be executed.
894 * @data: Data to pass to the function.
895 *
896 * Schedules the function @func for execution on the vCPU @cpu asynchronously,
897 * while all other vCPUs are sleeping.
898 *
899 * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the
900 * BQL.
901 */
902 void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
903
904 /**
905 * cpu_in_exclusive_context()
906 * @cpu: The vCPU to check
907 *
908 * Returns true if @cpu is an exclusive context, for example running
909 * something which has previously been queued via async_safe_run_on_cpu().
910 */
cpu_in_exclusive_context(const CPUState * cpu)911 static inline bool cpu_in_exclusive_context(const CPUState *cpu)
912 {
913 return cpu->exclusive_context_count;
914 }
915
916 /**
917 * qemu_get_cpu:
918 * @index: The CPUState@cpu_index value of the CPU to obtain.
919 *
920 * Gets a CPU matching @index.
921 *
922 * Returns: The CPU or %NULL if there is no matching CPU.
923 */
924 CPUState *qemu_get_cpu(int index);
925
926 /**
927 * cpu_exists:
928 * @id: Guest-exposed CPU ID to lookup.
929 *
930 * Search for CPU with specified ID.
931 *
932 * Returns: %true - CPU is found, %false - CPU isn't found.
933 */
934 bool cpu_exists(int64_t id);
935
936 /**
937 * cpu_by_arch_id:
938 * @id: Guest-exposed CPU ID of the CPU to obtain.
939 *
940 * Get a CPU with matching @id.
941 *
942 * Returns: The CPU or %NULL if there is no matching CPU.
943 */
944 CPUState *cpu_by_arch_id(int64_t id);
945
946 /**
947 * cpu_interrupt:
948 * @cpu: The CPU to set an interrupt on.
949 * @mask: The interrupts to set.
950 *
951 * Invokes the interrupt handler.
952 */
953
954 void cpu_interrupt(CPUState *cpu, int mask);
955
956 /**
957 * cpu_set_pc:
958 * @cpu: The CPU to set the program counter for.
959 * @addr: Program counter value.
960 *
961 * Sets the program counter for a CPU.
962 */
cpu_set_pc(CPUState * cpu,vaddr addr)963 static inline void cpu_set_pc(CPUState *cpu, vaddr addr)
964 {
965 CPUClass *cc = CPU_GET_CLASS(cpu);
966
967 cc->set_pc(cpu, addr);
968 }
969
970 /**
971 * cpu_reset_interrupt:
972 * @cpu: The CPU to clear the interrupt on.
973 * @mask: The interrupt mask to clear.
974 *
975 * Resets interrupts on the vCPU @cpu.
976 */
977 void cpu_reset_interrupt(CPUState *cpu, int mask);
978
979 /**
980 * cpu_exit:
981 * @cpu: The CPU to exit.
982 *
983 * Requests the CPU @cpu to exit execution.
984 */
985 void cpu_exit(CPUState *cpu);
986
987 /**
988 * cpu_resume:
989 * @cpu: The CPU to resume.
990 *
991 * Resumes CPU, i.e. puts CPU into runnable state.
992 */
993 void cpu_resume(CPUState *cpu);
994
995 /**
996 * cpu_remove_sync:
997 * @cpu: The CPU to remove.
998 *
999 * Requests the CPU to be removed and waits till it is removed.
1000 */
1001 void cpu_remove_sync(CPUState *cpu);
1002
1003 /**
1004 * process_queued_cpu_work() - process all items on CPU work queue
1005 * @cpu: The CPU which work queue to process.
1006 */
1007 void process_queued_cpu_work(CPUState *cpu);
1008
1009 /**
1010 * cpu_exec_start:
1011 * @cpu: The CPU for the current thread.
1012 *
1013 * Record that a CPU has started execution and can be interrupted with
1014 * cpu_exit.
1015 */
1016 void cpu_exec_start(CPUState *cpu);
1017
1018 /**
1019 * cpu_exec_end:
1020 * @cpu: The CPU for the current thread.
1021 *
1022 * Record that a CPU has stopped execution and exclusive sections
1023 * can be executed without interrupting it.
1024 */
1025 void cpu_exec_end(CPUState *cpu);
1026
1027 /**
1028 * start_exclusive:
1029 *
1030 * Wait for a concurrent exclusive section to end, and then start
1031 * a section of work that is run while other CPUs are not running
1032 * between cpu_exec_start and cpu_exec_end. CPUs that are running
1033 * cpu_exec are exited immediately. CPUs that call cpu_exec_start
1034 * during the exclusive section go to sleep until this CPU calls
1035 * end_exclusive.
1036 */
1037 void start_exclusive(void);
1038
1039 /**
1040 * end_exclusive:
1041 *
1042 * Concludes an exclusive execution section started by start_exclusive.
1043 */
1044 void end_exclusive(void);
1045
1046 /**
1047 * qemu_init_vcpu:
1048 * @cpu: The vCPU to initialize.
1049 *
1050 * Initializes a vCPU.
1051 */
1052 void qemu_init_vcpu(CPUState *cpu);
1053
1054 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
1055 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
1056 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
1057
1058 /**
1059 * cpu_single_step:
1060 * @cpu: CPU to the flags for.
1061 * @enabled: Flags to enable.
1062 *
1063 * Enables or disables single-stepping for @cpu.
1064 */
1065 void cpu_single_step(CPUState *cpu, int enabled);
1066
1067 /* Breakpoint/watchpoint flags */
1068 #define BP_MEM_READ 0x01
1069 #define BP_MEM_WRITE 0x02
1070 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
1071 #define BP_STOP_BEFORE_ACCESS 0x04
1072 /* 0x08 currently unused */
1073 #define BP_GDB 0x10
1074 #define BP_CPU 0x20
1075 #define BP_ANY (BP_GDB | BP_CPU)
1076 #define BP_HIT_SHIFT 6
1077 #define BP_WATCHPOINT_HIT_READ (BP_MEM_READ << BP_HIT_SHIFT)
1078 #define BP_WATCHPOINT_HIT_WRITE (BP_MEM_WRITE << BP_HIT_SHIFT)
1079 #define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT)
1080
1081 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
1082 CPUBreakpoint **breakpoint);
1083 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
1084 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
1085 void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
1086
1087 /* Return true if PC matches an installed breakpoint. */
cpu_breakpoint_test(CPUState * cpu,vaddr pc,int mask)1088 static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
1089 {
1090 CPUBreakpoint *bp;
1091
1092 if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
1093 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
1094 if (bp->pc == pc && (bp->flags & mask)) {
1095 return true;
1096 }
1097 }
1098 }
1099 return false;
1100 }
1101
1102 #if defined(CONFIG_USER_ONLY)
cpu_watchpoint_insert(CPUState * cpu,vaddr addr,vaddr len,int flags,CPUWatchpoint ** watchpoint)1103 static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1104 int flags, CPUWatchpoint **watchpoint)
1105 {
1106 return -ENOSYS;
1107 }
1108
cpu_watchpoint_remove(CPUState * cpu,vaddr addr,vaddr len,int flags)1109 static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
1110 vaddr len, int flags)
1111 {
1112 return -ENOSYS;
1113 }
1114
cpu_watchpoint_remove_by_ref(CPUState * cpu,CPUWatchpoint * wp)1115 static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu,
1116 CPUWatchpoint *wp)
1117 {
1118 }
1119
cpu_watchpoint_remove_all(CPUState * cpu,int mask)1120 static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
1121 {
1122 }
1123 #else
1124 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1125 int flags, CPUWatchpoint **watchpoint);
1126 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
1127 vaddr len, int flags);
1128 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
1129 void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
1130 #endif
1131
1132 /**
1133 * cpu_get_address_space:
1134 * @cpu: CPU to get address space from
1135 * @asidx: index identifying which address space to get
1136 *
1137 * Return the requested address space of this CPU. @asidx
1138 * specifies which address space to read.
1139 */
1140 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx);
1141
1142 G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...)
1143 G_GNUC_PRINTF(2, 3);
1144
1145 /* $(top_srcdir)/cpu.c */
1146 void cpu_class_init_props(DeviceClass *dc);
1147 void cpu_exec_initfn(CPUState *cpu);
1148 bool cpu_exec_realizefn(CPUState *cpu, Error **errp);
1149 void cpu_exec_unrealizefn(CPUState *cpu);
1150 void cpu_exec_reset_hold(CPUState *cpu);
1151
1152 const char *target_name(void);
1153
1154 #ifdef COMPILING_PER_TARGET
1155
1156 #ifndef CONFIG_USER_ONLY
1157
1158 extern const VMStateDescription vmstate_cpu_common;
1159
1160 #define VMSTATE_CPU() { \
1161 .name = "parent_obj", \
1162 .size = sizeof(CPUState), \
1163 .vmsd = &vmstate_cpu_common, \
1164 .flags = VMS_STRUCT, \
1165 .offset = 0, \
1166 }
1167 #endif /* !CONFIG_USER_ONLY */
1168
1169 #endif /* COMPILING_PER_TARGET */
1170
1171 #define UNASSIGNED_CPU_INDEX -1
1172 #define UNASSIGNED_CLUSTER_INDEX -1
1173
1174 #endif
1175