1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #ifndef __MT76_CONNAC_MCU_H
5 #define __MT76_CONNAC_MCU_H
6
7 #include "mt76_connac.h"
8
9 #define FW_FEATURE_SET_ENCRYPT BIT(0)
10 #define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1)
11 #define FW_FEATURE_ENCRY_MODE BIT(4)
12 #define FW_FEATURE_OVERRIDE_ADDR BIT(5)
13 #define FW_FEATURE_NON_DL BIT(6)
14
15 #define DL_MODE_ENCRYPT BIT(0)
16 #define DL_MODE_KEY_IDX GENMASK(2, 1)
17 #define DL_MODE_RESET_SEC_IV BIT(3)
18 #define DL_MODE_WORKING_PDA_CR4 BIT(4)
19 #define DL_MODE_VALID_RAM_ENTRY BIT(5)
20 #define DL_CONFIG_ENCRY_MODE_SEL BIT(6)
21 #define DL_MODE_NEED_RSP BIT(31)
22
23 #define FW_START_OVERRIDE BIT(0)
24 #define FW_START_WORKING_PDA_CR4 BIT(2)
25 #define FW_START_WORKING_PDA_DSP BIT(3)
26
27 #define PATCH_SEC_NOT_SUPPORT GENMASK(31, 0)
28 #define PATCH_SEC_TYPE_MASK GENMASK(15, 0)
29 #define PATCH_SEC_TYPE_INFO 0x2
30
31 #define PATCH_SEC_ENC_TYPE_MASK GENMASK(31, 24)
32 #define PATCH_SEC_ENC_TYPE_PLAIN 0x00
33 #define PATCH_SEC_ENC_TYPE_AES 0x01
34 #define PATCH_SEC_ENC_TYPE_SCRAMBLE 0x02
35 #define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK GENMASK(15, 0)
36 #define PATCH_SEC_ENC_AES_KEY_MASK GENMASK(7, 0)
37
38 enum {
39 FW_TYPE_DEFAULT = 0,
40 FW_TYPE_CLC = 2,
41 FW_TYPE_MAX_NUM = 255
42 };
43
44 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10))
45 #define MCU_PKT_ID 0xa0
46
47 struct mt76_connac2_mcu_txd {
48 __le32 txd[8];
49
50 __le16 len;
51 __le16 pq_id;
52
53 u8 cid;
54 u8 pkt_type;
55 u8 set_query; /* FW don't care */
56 u8 seq;
57
58 u8 uc_d2b0_rev;
59 u8 ext_cid;
60 u8 s2d_index;
61 u8 ext_cid_ack;
62
63 u32 rsv[5];
64 } __packed __aligned(4);
65
66 /**
67 * struct mt76_connac2_mcu_uni_txd - mcu command descriptor for connac2 and connac3
68 * @txd: hardware descriptor
69 * @len: total length not including txd
70 * @cid: command identifier
71 * @pkt_type: must be 0xa0 (cmd packet by long format)
72 * @frag_n: fragment number
73 * @seq: sequence number
74 * @checksum: 0 mean there is no checksum
75 * @s2d_index: index for command source and destination
76 * Definition | value | note
77 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM
78 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM
79 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA
80 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM
81 *
82 * @option: command option
83 * BIT[0]: UNI_CMD_OPT_BIT_ACK
84 * set to 1 to request a fw reply
85 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY
86 * is set, mcu firmware will send response event EID = 0x01
87 * (UNI_EVENT_ID_CMD_RESULT) to the host.
88 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD
89 * 0: original command
90 * 1: unified command
91 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY
92 * 0: QUERY command
93 * 1: SET command
94 */
95 struct mt76_connac2_mcu_uni_txd {
96 __le32 txd[8];
97
98 /* DW1 */
99 __le16 len;
100 __le16 cid;
101
102 /* DW2 */
103 u8 rsv;
104 u8 pkt_type;
105 u8 frag_n;
106 u8 seq;
107
108 /* DW3 */
109 __le16 checksum;
110 u8 s2d_index;
111 u8 option;
112
113 /* DW4 */
114 u8 rsv1[4];
115 } __packed __aligned(4);
116
117 struct mt76_connac2_mcu_rxd {
118 __le32 rxd[6];
119
120 __le16 len;
121 __le16 pkt_type_id;
122
123 u8 eid;
124 u8 seq;
125 u8 option;
126 u8 rsv;
127 u8 ext_eid;
128 u8 rsv1[2];
129 u8 s2d_index;
130
131 u8 tlv[];
132 };
133
134 struct mt76_connac2_patch_hdr {
135 char build_date[16];
136 char platform[4];
137 __be32 hw_sw_ver;
138 __be32 patch_ver;
139 __be16 checksum;
140 u16 rsv;
141 struct {
142 __be32 patch_ver;
143 __be32 subsys;
144 __be32 feature;
145 __be32 n_region;
146 __be32 crc;
147 u32 rsv[11];
148 } desc;
149 } __packed;
150
151 struct mt76_connac2_patch_sec {
152 __be32 type;
153 __be32 offs;
154 __be32 size;
155 union {
156 __be32 spec[13];
157 struct {
158 __be32 addr;
159 __be32 len;
160 __be32 sec_key_idx;
161 __be32 align_len;
162 u32 rsv[9];
163 } info;
164 };
165 } __packed;
166
167 struct mt76_connac2_fw_trailer {
168 u8 chip_id;
169 u8 eco_code;
170 u8 n_region;
171 u8 format_ver;
172 u8 format_flag;
173 u8 rsv[2];
174 char fw_ver[10];
175 char build_date[15];
176 __le32 crc;
177 } __packed;
178
179 struct mt76_connac2_fw_region {
180 __le32 decomp_crc;
181 __le32 decomp_len;
182 __le32 decomp_blk_sz;
183 u8 rsv[4];
184 __le32 addr;
185 __le32 len;
186 u8 feature_set;
187 u8 type;
188 u8 rsv1[14];
189 } __packed;
190
191 struct tlv {
192 __le16 tag;
193 __le16 len;
194 u8 data[];
195 } __packed;
196
197 struct bss_info_omac {
198 __le16 tag;
199 __le16 len;
200 u8 hw_bss_idx;
201 u8 omac_idx;
202 u8 band_idx;
203 u8 rsv0;
204 __le32 conn_type;
205 u32 rsv1;
206 } __packed;
207
208 struct bss_info_basic {
209 __le16 tag;
210 __le16 len;
211 __le32 network_type;
212 u8 active;
213 u8 rsv0;
214 __le16 bcn_interval;
215 u8 bssid[ETH_ALEN];
216 u8 wmm_idx;
217 u8 dtim_period;
218 u8 bmc_wcid_lo;
219 u8 cipher;
220 u8 phy_mode;
221 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */
222 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */
223 u8 bmc_wcid_hi; /* high Byte and version */
224 u8 rsv[2];
225 } __packed;
226
227 struct bss_info_rf_ch {
228 __le16 tag;
229 __le16 len;
230 u8 pri_ch;
231 u8 center_ch0;
232 u8 center_ch1;
233 u8 bw;
234 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */
235 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */
236 u8 rsv[2];
237 } __packed;
238
239 struct bss_info_ext_bss {
240 __le16 tag;
241 __le16 len;
242 __le32 mbss_tsf_offset; /* in unit of us */
243 u8 rsv[8];
244 } __packed;
245
246 enum {
247 BSS_INFO_OMAC,
248 BSS_INFO_BASIC,
249 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */
250 BSS_INFO_PM, /* sta only */
251 BSS_INFO_UAPSD, /* sta only */
252 BSS_INFO_ROAM_DETECT, /* obsoleted */
253 BSS_INFO_LQ_RM, /* obsoleted */
254 BSS_INFO_EXT_BSS,
255 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */
256 BSS_INFO_SYNC_MODE, /* obsoleted */
257 BSS_INFO_RA,
258 BSS_INFO_HW_AMSDU,
259 BSS_INFO_BSS_COLOR,
260 BSS_INFO_HE_BASIC,
261 BSS_INFO_PROTECT_INFO,
262 BSS_INFO_OFFLOAD,
263 BSS_INFO_11V_MBSSID,
264 BSS_INFO_MAX_NUM
265 };
266
267 /* sta_rec */
268
269 struct sta_ntlv_hdr {
270 u8 rsv[2];
271 __le16 tlv_num;
272 } __packed;
273
274 struct sta_req_hdr {
275 u8 bss_idx;
276 u8 wlan_idx_lo;
277 __le16 tlv_num;
278 u8 is_tlv_append;
279 u8 muar_idx;
280 u8 wlan_idx_hi;
281 u8 rsv;
282 } __packed;
283
284 struct sta_rec_basic {
285 __le16 tag;
286 __le16 len;
287 __le32 conn_type;
288 u8 conn_state;
289 u8 qos;
290 __le16 aid;
291 u8 peer_addr[ETH_ALEN];
292 #define EXTRA_INFO_VER BIT(0)
293 #define EXTRA_INFO_NEW BIT(1)
294 __le16 extra_info;
295 } __packed;
296
297 struct sta_rec_ht {
298 __le16 tag;
299 __le16 len;
300 __le16 ht_cap;
301 u16 rsv;
302 } __packed;
303
304 struct sta_rec_vht {
305 __le16 tag;
306 __le16 len;
307 __le32 vht_cap;
308 __le16 vht_rx_mcs_map;
309 __le16 vht_tx_mcs_map;
310 /* mt7915 - mt7921 */
311 u8 rts_bw_sig;
312 u8 rsv[3];
313 } __packed;
314
315 struct sta_rec_uapsd {
316 __le16 tag;
317 __le16 len;
318 u8 dac_map;
319 u8 tac_map;
320 u8 max_sp;
321 u8 rsv0;
322 __le16 listen_interval;
323 u8 rsv1[2];
324 } __packed;
325
326 struct sta_rec_ba {
327 __le16 tag;
328 __le16 len;
329 u8 tid;
330 u8 ba_type;
331 u8 amsdu;
332 u8 ba_en;
333 __le16 ssn;
334 __le16 winsize;
335 } __packed;
336
337 struct sta_rec_he {
338 __le16 tag;
339 __le16 len;
340
341 __le32 he_cap;
342
343 u8 t_frame_dur;
344 u8 max_ampdu_exp;
345 u8 bw_set;
346 u8 device_class;
347 u8 dcm_tx_mode;
348 u8 dcm_tx_max_nss;
349 u8 dcm_rx_mode;
350 u8 dcm_rx_max_nss;
351 u8 dcm_max_ru;
352 u8 punc_pream_rx;
353 u8 pkt_ext;
354 u8 rsv1;
355
356 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
357
358 u8 rsv2[2];
359 } __packed;
360
361 struct sta_rec_he_v2 {
362 __le16 tag;
363 __le16 len;
364 u8 he_mac_cap[6];
365 u8 he_phy_cap[11];
366 u8 pkt_ext;
367 /* 0: BW80, 1: BW160, 2: BW8080 */
368 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
369 } __packed;
370
371 struct sta_rec_amsdu {
372 __le16 tag;
373 __le16 len;
374 u8 max_amsdu_num;
375 u8 max_mpdu_size;
376 u8 amsdu_en;
377 u8 rsv;
378 } __packed;
379
380 struct sta_rec_state {
381 __le16 tag;
382 __le16 len;
383 __le32 flags;
384 u8 state;
385 u8 vht_opmode;
386 u8 action;
387 u8 rsv[1];
388 } __packed;
389
390 #define RA_LEGACY_OFDM GENMASK(13, 6)
391 #define RA_LEGACY_CCK GENMASK(3, 0)
392 #define HT_MCS_MASK_NUM 10
393 struct sta_rec_ra_info {
394 __le16 tag;
395 __le16 len;
396 __le16 legacy;
397 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM];
398 } __packed;
399
400 struct sta_rec_phy {
401 __le16 tag;
402 __le16 len;
403 __le16 basic_rate;
404 u8 phy_type;
405 u8 ampdu;
406 u8 rts_policy;
407 u8 rcpi;
408 u8 max_ampdu_len; /* connac3 */
409 u8 rsv[1];
410 } __packed;
411
412 struct sta_rec_he_6g_capa {
413 __le16 tag;
414 __le16 len;
415 __le16 capa;
416 u8 rsv[2];
417 } __packed;
418
419 struct sta_rec_pn_info {
420 __le16 tag;
421 __le16 len;
422 u8 pn[6];
423 u8 tsc_type;
424 u8 rsv;
425 } __packed;
426
427 struct sec_key {
428 u8 cipher_id;
429 u8 cipher_len;
430 u8 key_id;
431 u8 key_len;
432 u8 key[32];
433 } __packed;
434
435 struct sta_rec_sec {
436 __le16 tag;
437 __le16 len;
438 u8 add;
439 u8 n_cipher;
440 u8 rsv[2];
441
442 struct sec_key key[2];
443 } __packed;
444
445 struct sta_rec_bf {
446 __le16 tag;
447 __le16 len;
448
449 __le16 pfmu; /* 0xffff: no access right for PFMU */
450 bool su_mu; /* 0: SU, 1: MU */
451 u8 bf_cap; /* 0: iBF, 1: eBF */
452 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */
453 u8 ndpa_rate;
454 u8 ndp_rate;
455 u8 rept_poll_rate;
456 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */
457 u8 ncol;
458 u8 nrow;
459 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */
460
461 u8 mem_total;
462 u8 mem_20m;
463 struct {
464 u8 row;
465 u8 col: 6, row_msb: 2;
466 } mem[4];
467
468 __le16 smart_ant;
469 u8 se_idx;
470 u8 auto_sounding; /* b7: low traffic indicator
471 * b6: Stop sounding for this entry
472 * b5 ~ b0: postpone sounding
473 */
474 u8 ibf_timeout;
475 u8 ibf_dbw;
476 u8 ibf_ncol;
477 u8 ibf_nrow;
478 u8 nrow_gt_bw80;
479 u8 ncol_gt_bw80;
480 u8 ru_start_idx;
481 u8 ru_end_idx;
482
483 bool trigger_su;
484 bool trigger_mu;
485 bool ng16_su;
486 bool ng16_mu;
487 bool codebook42_su;
488 bool codebook75_mu;
489
490 u8 he_ltf;
491 u8 rsv[3];
492 } __packed;
493
494 struct sta_rec_bfee {
495 __le16 tag;
496 __le16 len;
497 bool fb_identity_matrix; /* 1: feedback identity matrix */
498 bool ignore_feedback; /* 1: ignore */
499 u8 rsv[2];
500 } __packed;
501
502 struct sta_rec_muru {
503 __le16 tag;
504 __le16 len;
505
506 struct {
507 bool ofdma_dl_en;
508 bool ofdma_ul_en;
509 bool mimo_dl_en;
510 bool mimo_ul_en;
511 u8 rsv[4];
512 } cfg;
513
514 struct {
515 u8 punc_pream_rx;
516 bool he_20m_in_40m_2g;
517 bool he_20m_in_160m;
518 bool he_80m_in_160m;
519 bool lt16_sigb;
520 bool rx_su_comp_sigb;
521 bool rx_su_non_comp_sigb;
522 u8 rsv;
523 } ofdma_dl;
524
525 struct {
526 u8 t_frame_dur;
527 u8 mu_cascading;
528 u8 uo_ra;
529 u8 he_2x996_tone;
530 u8 rx_t_frame_11ac;
531 u8 rx_ctrl_frame_to_mbss;
532 u8 rsv[2];
533 } ofdma_ul;
534
535 struct {
536 bool vht_mu_bfee;
537 bool partial_bw_dl_mimo;
538 u8 rsv[2];
539 } mimo_dl;
540
541 struct {
542 bool full_ul_mimo;
543 bool partial_ul_mimo;
544 u8 rsv[2];
545 } mimo_ul;
546 } __packed;
547
548 struct sta_phy {
549 u8 type;
550 u8 flag;
551 u8 stbc;
552 u8 sgi;
553 u8 bw;
554 u8 ldpc;
555 u8 mcs;
556 u8 nss;
557 u8 he_ltf;
558 };
559
560 struct sta_rec_ra {
561 __le16 tag;
562 __le16 len;
563
564 u8 valid;
565 u8 auto_rate;
566 u8 phy_mode;
567 u8 channel;
568 u8 bw;
569 u8 disable_cck;
570 u8 ht_mcs32;
571 u8 ht_gf;
572 u8 ht_mcs[4];
573 u8 mmps_mode;
574 u8 gband_256;
575 u8 af;
576 u8 auth_wapi_mode;
577 u8 rate_len;
578
579 u8 supp_mode;
580 u8 supp_cck_rate;
581 u8 supp_ofdm_rate;
582 __le32 supp_ht_mcs;
583 __le16 supp_vht_mcs[4];
584
585 u8 op_mode;
586 u8 op_vht_chan_width;
587 u8 op_vht_rx_nss;
588 u8 op_vht_rx_nss_type;
589
590 __le32 sta_cap;
591
592 struct sta_phy phy;
593 } __packed;
594
595 struct sta_rec_ra_fixed {
596 __le16 tag;
597 __le16 len;
598
599 __le32 field;
600 u8 op_mode;
601 u8 op_vht_chan_width;
602 u8 op_vht_rx_nss;
603 u8 op_vht_rx_nss_type;
604
605 struct sta_phy phy;
606
607 u8 spe_idx;
608 u8 short_preamble;
609 u8 is_5g;
610 u8 mmps_mode;
611 } __packed;
612
613 struct sta_rec_tx_proc {
614 __le16 tag;
615 __le16 len;
616 __le32 flag;
617 } __packed;
618
619 /* wtbl_rec */
620
621 struct wtbl_req_hdr {
622 u8 wlan_idx_lo;
623 u8 operation;
624 __le16 tlv_num;
625 u8 wlan_idx_hi;
626 u8 rsv[3];
627 } __packed;
628
629 struct wtbl_generic {
630 __le16 tag;
631 __le16 len;
632 u8 peer_addr[ETH_ALEN];
633 u8 muar_idx;
634 u8 skip_tx;
635 u8 cf_ack;
636 u8 qos;
637 u8 mesh;
638 u8 adm;
639 __le16 partial_aid;
640 u8 baf_en;
641 u8 aad_om;
642 } __packed;
643
644 struct wtbl_rx {
645 __le16 tag;
646 __le16 len;
647 u8 rcid;
648 u8 rca1;
649 u8 rca2;
650 u8 rv;
651 u8 rsv[4];
652 } __packed;
653
654 struct wtbl_ht {
655 __le16 tag;
656 __le16 len;
657 u8 ht;
658 u8 ldpc;
659 u8 af;
660 u8 mm;
661 u8 rsv[4];
662 } __packed;
663
664 struct wtbl_vht {
665 __le16 tag;
666 __le16 len;
667 u8 ldpc;
668 u8 dyn_bw;
669 u8 vht;
670 u8 txop_ps;
671 u8 rsv[4];
672 } __packed;
673
674 struct wtbl_tx_ps {
675 __le16 tag;
676 __le16 len;
677 u8 txps;
678 u8 rsv[3];
679 } __packed;
680
681 struct wtbl_hdr_trans {
682 __le16 tag;
683 __le16 len;
684 u8 to_ds;
685 u8 from_ds;
686 u8 no_rx_trans;
687 u8 rsv;
688 } __packed;
689
690 struct wtbl_ba {
691 __le16 tag;
692 __le16 len;
693 /* common */
694 u8 tid;
695 u8 ba_type;
696 u8 rsv0[2];
697 /* originator only */
698 __le16 sn;
699 u8 ba_en;
700 u8 ba_winsize_idx;
701 /* originator & recipient */
702 __le16 ba_winsize;
703 /* recipient only */
704 u8 peer_addr[ETH_ALEN];
705 u8 rst_ba_tid;
706 u8 rst_ba_sel;
707 u8 rst_ba_sb;
708 u8 band_idx;
709 u8 rsv1[4];
710 } __packed;
711
712 struct wtbl_smps {
713 __le16 tag;
714 __le16 len;
715 u8 smps;
716 u8 rsv[3];
717 } __packed;
718
719 /* mt7615 only */
720
721 struct wtbl_bf {
722 __le16 tag;
723 __le16 len;
724 u8 ibf;
725 u8 ebf;
726 u8 ibf_vht;
727 u8 ebf_vht;
728 u8 gid;
729 u8 pfmu_idx;
730 u8 rsv[2];
731 } __packed;
732
733 struct wtbl_pn {
734 __le16 tag;
735 __le16 len;
736 u8 pn[6];
737 u8 rsv[2];
738 } __packed;
739
740 struct wtbl_spe {
741 __le16 tag;
742 __le16 len;
743 u8 spe_idx;
744 u8 rsv[3];
745 } __packed;
746
747 struct wtbl_raw {
748 __le16 tag;
749 __le16 len;
750 u8 wtbl_idx;
751 u8 dw;
752 u8 rsv[2];
753 __le32 msk;
754 __le32 val;
755 } __packed;
756
757 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
758 sizeof(struct wtbl_generic) + \
759 sizeof(struct wtbl_rx) + \
760 sizeof(struct wtbl_ht) + \
761 sizeof(struct wtbl_vht) + \
762 sizeof(struct wtbl_tx_ps) + \
763 sizeof(struct wtbl_hdr_trans) +\
764 sizeof(struct wtbl_ba) + \
765 sizeof(struct wtbl_bf) + \
766 sizeof(struct wtbl_smps) + \
767 sizeof(struct wtbl_pn) + \
768 sizeof(struct wtbl_spe))
769
770 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
771 sizeof(struct sta_rec_basic) + \
772 sizeof(struct sta_rec_bf) + \
773 sizeof(struct sta_rec_ht) + \
774 sizeof(struct sta_rec_he) + \
775 sizeof(struct sta_rec_ba) + \
776 sizeof(struct sta_rec_vht) + \
777 sizeof(struct sta_rec_uapsd) + \
778 sizeof(struct sta_rec_amsdu) + \
779 sizeof(struct sta_rec_muru) + \
780 sizeof(struct sta_rec_bfee) + \
781 sizeof(struct sta_rec_ra) + \
782 sizeof(struct sta_rec_sec) + \
783 sizeof(struct sta_rec_ra_fixed) + \
784 sizeof(struct sta_rec_he_6g_capa) + \
785 sizeof(struct sta_rec_pn_info) + \
786 sizeof(struct sta_rec_tx_proc) + \
787 sizeof(struct tlv) + \
788 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE)
789
790 enum {
791 STA_REC_BASIC,
792 STA_REC_RA,
793 STA_REC_RA_CMM_INFO,
794 STA_REC_RA_UPDATE,
795 STA_REC_BF,
796 STA_REC_AMSDU,
797 STA_REC_BA,
798 STA_REC_STATE,
799 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */
800 STA_REC_HT,
801 STA_REC_VHT,
802 STA_REC_APPS,
803 STA_REC_KEY,
804 STA_REC_WTBL,
805 STA_REC_HE,
806 STA_REC_HW_AMSDU,
807 STA_REC_WTBL_AADOM,
808 STA_REC_KEY_V2,
809 STA_REC_MURU,
810 STA_REC_MUEDCA,
811 STA_REC_BFEE,
812 STA_REC_PHY = 0x15,
813 STA_REC_HE_6G = 0x17,
814 STA_REC_HE_V2 = 0x19,
815 STA_REC_MLD = 0x20,
816 STA_REC_EHT = 0x22,
817 STA_REC_PN_INFO = 0x26,
818 STA_REC_KEY_V3 = 0x27,
819 STA_REC_HDRT = 0x28,
820 STA_REC_HDR_TRANS = 0x2B,
821 STA_REC_MAX_NUM
822 };
823
824 enum {
825 WTBL_GENERIC,
826 WTBL_RX,
827 WTBL_HT,
828 WTBL_VHT,
829 WTBL_PEER_PS, /* not used */
830 WTBL_TX_PS,
831 WTBL_HDR_TRANS,
832 WTBL_SEC_KEY,
833 WTBL_BA,
834 WTBL_RDG, /* obsoleted */
835 WTBL_PROTECT, /* not used */
836 WTBL_CLEAR, /* not used */
837 WTBL_BF,
838 WTBL_SMPS,
839 WTBL_RAW_DATA, /* debug only */
840 WTBL_PN,
841 WTBL_SPE,
842 WTBL_MAX_NUM
843 };
844
845 #define STA_TYPE_STA BIT(0)
846 #define STA_TYPE_AP BIT(1)
847 #define STA_TYPE_ADHOC BIT(2)
848 #define STA_TYPE_WDS BIT(4)
849 #define STA_TYPE_BC BIT(5)
850
851 #define NETWORK_INFRA BIT(16)
852 #define NETWORK_P2P BIT(17)
853 #define NETWORK_IBSS BIT(18)
854 #define NETWORK_WDS BIT(21)
855
856 #define SCAN_FUNC_RANDOM_MAC BIT(0)
857 #define SCAN_FUNC_SPLIT_SCAN BIT(5)
858
859 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA)
860 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA)
861 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P)
862 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P)
863 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS)
864 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS)
865 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA)
866
867 #define CONN_STATE_DISCONNECT 0
868 #define CONN_STATE_CONNECT 1
869 #define CONN_STATE_PORT_SECURE 2
870
871 /* HE MAC */
872 #define STA_REC_HE_CAP_HTC BIT(0)
873 #define STA_REC_HE_CAP_BQR BIT(1)
874 #define STA_REC_HE_CAP_BSR BIT(2)
875 #define STA_REC_HE_CAP_OM BIT(3)
876 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4)
877 /* HE PHY */
878 #define STA_REC_HE_CAP_DUAL_BAND BIT(5)
879 #define STA_REC_HE_CAP_LDPC BIT(6)
880 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7)
881 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8)
882 /* STBC */
883 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9)
884 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10)
885 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11)
886 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12)
887 /* GI */
888 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13)
889 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14)
890 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15)
891 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16)
892 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17)
893 /* 242 TONE */
894 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18)
895 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19)
896 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20)
897
898 #define PHY_MODE_A BIT(0)
899 #define PHY_MODE_B BIT(1)
900 #define PHY_MODE_G BIT(2)
901 #define PHY_MODE_GN BIT(3)
902 #define PHY_MODE_AN BIT(4)
903 #define PHY_MODE_AC BIT(5)
904 #define PHY_MODE_AX_24G BIT(6)
905 #define PHY_MODE_AX_5G BIT(7)
906
907 #define PHY_MODE_AX_6G BIT(0) /* phymode_ext */
908 #define PHY_MODE_BE_24G BIT(1)
909 #define PHY_MODE_BE_5G BIT(2)
910 #define PHY_MODE_BE_6G BIT(3)
911
912 #define MODE_CCK BIT(0)
913 #define MODE_OFDM BIT(1)
914 #define MODE_HT BIT(2)
915 #define MODE_VHT BIT(3)
916 #define MODE_HE BIT(4)
917 #define MODE_EHT BIT(5)
918
919 #define STA_CAP_WMM BIT(0)
920 #define STA_CAP_SGI_20 BIT(4)
921 #define STA_CAP_SGI_40 BIT(5)
922 #define STA_CAP_TX_STBC BIT(6)
923 #define STA_CAP_RX_STBC BIT(7)
924 #define STA_CAP_VHT_SGI_80 BIT(16)
925 #define STA_CAP_VHT_SGI_160 BIT(17)
926 #define STA_CAP_VHT_TX_STBC BIT(18)
927 #define STA_CAP_VHT_RX_STBC BIT(19)
928 #define STA_CAP_VHT_LDPC BIT(23)
929 #define STA_CAP_LDPC BIT(24)
930 #define STA_CAP_HT BIT(26)
931 #define STA_CAP_VHT BIT(27)
932 #define STA_CAP_HE BIT(28)
933
934 enum {
935 PHY_TYPE_HR_DSSS_INDEX = 0,
936 PHY_TYPE_ERP_INDEX,
937 PHY_TYPE_ERP_P2P_INDEX,
938 PHY_TYPE_OFDM_INDEX,
939 PHY_TYPE_HT_INDEX,
940 PHY_TYPE_VHT_INDEX,
941 PHY_TYPE_HE_INDEX,
942 PHY_TYPE_BE_INDEX,
943 PHY_TYPE_INDEX_NUM
944 };
945
946 #define HR_DSSS_ERP_BASIC_RATE GENMASK(3, 0)
947 #define OFDM_BASIC_RATE (BIT(6) | BIT(8) | BIT(10))
948
949 #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX)
950 #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX)
951 #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX)
952 #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX)
953 #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX)
954 #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX)
955 #define PHY_TYPE_BIT_BE BIT(PHY_TYPE_BE_INDEX)
956
957 #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6)
958 #define MT_WTBL_RATE_MCS GENMASK(5, 0)
959 #define MT_WTBL_RATE_NSS GENMASK(12, 10)
960 #define MT_WTBL_RATE_HE_GI GENMASK(7, 4)
961 #define MT_WTBL_RATE_GI GENMASK(3, 0)
962
963 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5)
964 #define MT_WTBL_W5_SHORT_GI_20 BIT(8)
965 #define MT_WTBL_W5_SHORT_GI_40 BIT(9)
966 #define MT_WTBL_W5_SHORT_GI_80 BIT(10)
967 #define MT_WTBL_W5_SHORT_GI_160 BIT(11)
968 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12)
969 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23)
970 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26)
971 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29)
972
973 enum {
974 WTBL_RESET_AND_SET = 1,
975 WTBL_SET,
976 WTBL_QUERY,
977 WTBL_RESET_ALL
978 };
979
980 enum {
981 MT_BA_TYPE_INVALID,
982 MT_BA_TYPE_ORIGINATOR,
983 MT_BA_TYPE_RECIPIENT
984 };
985
986 enum {
987 RST_BA_MAC_TID_MATCH,
988 RST_BA_MAC_MATCH,
989 RST_BA_NO_MATCH
990 };
991
992 enum {
993 DEV_INFO_ACTIVE,
994 DEV_INFO_MAX_NUM
995 };
996
997 /* event table */
998 enum {
999 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
1000 MCU_EVENT_FW_START = 0x01,
1001 MCU_EVENT_GENERIC = 0x01,
1002 MCU_EVENT_ACCESS_REG = 0x02,
1003 MCU_EVENT_MT_PATCH_SEM = 0x04,
1004 MCU_EVENT_REG_ACCESS = 0x05,
1005 MCU_EVENT_LP_INFO = 0x07,
1006 MCU_EVENT_SCAN_DONE = 0x0d,
1007 MCU_EVENT_TX_DONE = 0x0f,
1008 MCU_EVENT_ROC = 0x10,
1009 MCU_EVENT_BSS_ABSENCE = 0x11,
1010 MCU_EVENT_BSS_BEACON_LOSS = 0x13,
1011 MCU_EVENT_CH_PRIVILEGE = 0x18,
1012 MCU_EVENT_SCHED_SCAN_DONE = 0x23,
1013 MCU_EVENT_DBG_MSG = 0x27,
1014 MCU_EVENT_RSSI_NOTIFY = 0x96,
1015 MCU_EVENT_TXPWR = 0xd0,
1016 MCU_EVENT_EXT = 0xed,
1017 MCU_EVENT_RESTART_DL = 0xef,
1018 MCU_EVENT_COREDUMP = 0xf0,
1019 };
1020
1021 /* ext event table */
1022 enum {
1023 MCU_EXT_EVENT_PS_SYNC = 0x5,
1024 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
1025 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
1026 MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
1027 MCU_EXT_EVENT_RDD_REPORT = 0x3a,
1028 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
1029 MCU_EXT_EVENT_WA_TX_STAT = 0x74,
1030 MCU_EXT_EVENT_BCC_NOTIFY = 0x75,
1031 MCU_EXT_EVENT_MURU_CTRL = 0x9f,
1032 };
1033
1034 /* unified event table */
1035 enum {
1036 MCU_UNI_EVENT_RESULT = 0x01,
1037 MCU_UNI_EVENT_FW_LOG_2_HOST = 0x04,
1038 MCU_UNI_EVENT_ACCESS_REG = 0x6,
1039 MCU_UNI_EVENT_IE_COUNTDOWN = 0x09,
1040 MCU_UNI_EVENT_COREDUMP = 0x0a,
1041 MCU_UNI_EVENT_BSS_BEACON_LOSS = 0x0c,
1042 MCU_UNI_EVENT_SCAN_DONE = 0x0e,
1043 MCU_UNI_EVENT_RDD_REPORT = 0x11,
1044 MCU_UNI_EVENT_ROC = 0x27,
1045 MCU_UNI_EVENT_TX_DONE = 0x2d,
1046 MCU_UNI_EVENT_THERMAL = 0x35,
1047 MCU_UNI_EVENT_NIC_CAPAB = 0x43,
1048 MCU_UNI_EVENT_WED_RRO = 0x57,
1049 MCU_UNI_EVENT_PER_STA_INFO = 0x6d,
1050 MCU_UNI_EVENT_ALL_STA_INFO = 0x6e,
1051 };
1052
1053 #define MCU_UNI_CMD_EVENT BIT(1)
1054 #define MCU_UNI_CMD_UNSOLICITED_EVENT BIT(2)
1055
1056 enum {
1057 MCU_Q_QUERY,
1058 MCU_Q_SET,
1059 MCU_Q_RESERVED,
1060 MCU_Q_NA
1061 };
1062
1063 enum {
1064 MCU_S2D_H2N,
1065 MCU_S2D_C2N,
1066 MCU_S2D_H2C,
1067 MCU_S2D_H2CN
1068 };
1069
1070 enum {
1071 PATCH_NOT_DL_SEM_FAIL,
1072 PATCH_IS_DL,
1073 PATCH_NOT_DL_SEM_SUCCESS,
1074 PATCH_REL_SEM_SUCCESS
1075 };
1076
1077 enum {
1078 FW_STATE_INITIAL,
1079 FW_STATE_FW_DOWNLOAD,
1080 FW_STATE_NORMAL_OPERATION,
1081 FW_STATE_NORMAL_TRX,
1082 FW_STATE_RDY = 7
1083 };
1084
1085 enum {
1086 CH_SWITCH_NORMAL = 0,
1087 CH_SWITCH_SCAN = 3,
1088 CH_SWITCH_MCC = 4,
1089 CH_SWITCH_DFS = 5,
1090 CH_SWITCH_BACKGROUND_SCAN_START = 6,
1091 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
1092 CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
1093 CH_SWITCH_SCAN_BYPASS_DPD = 9
1094 };
1095
1096 enum {
1097 THERMAL_SENSOR_TEMP_QUERY,
1098 THERMAL_SENSOR_MANUAL_CTRL,
1099 THERMAL_SENSOR_INFO_QUERY,
1100 THERMAL_SENSOR_TASK_CTRL,
1101 };
1102
1103 enum mcu_cipher_type {
1104 MCU_CIPHER_NONE = 0,
1105 MCU_CIPHER_WEP40,
1106 MCU_CIPHER_WEP104,
1107 MCU_CIPHER_WEP128,
1108 MCU_CIPHER_TKIP,
1109 MCU_CIPHER_AES_CCMP,
1110 MCU_CIPHER_CCMP_256,
1111 MCU_CIPHER_GCMP,
1112 MCU_CIPHER_GCMP_256,
1113 MCU_CIPHER_WAPI,
1114 MCU_CIPHER_BIP_CMAC_128,
1115 MCU_CIPHER_BIP_CMAC_256,
1116 MCU_CIPHER_BCN_PROT_CMAC_128,
1117 MCU_CIPHER_BCN_PROT_CMAC_256,
1118 MCU_CIPHER_BCN_PROT_GMAC_128,
1119 MCU_CIPHER_BCN_PROT_GMAC_256,
1120 MCU_CIPHER_BIP_GMAC_128,
1121 MCU_CIPHER_BIP_GMAC_256,
1122 };
1123
1124 enum {
1125 EE_MODE_EFUSE,
1126 EE_MODE_BUFFER,
1127 };
1128
1129 enum {
1130 EE_FORMAT_BIN,
1131 EE_FORMAT_WHOLE,
1132 EE_FORMAT_MULTIPLE,
1133 };
1134
1135 enum {
1136 MCU_PHY_STATE_TX_RATE,
1137 MCU_PHY_STATE_RX_RATE,
1138 MCU_PHY_STATE_RSSI,
1139 MCU_PHY_STATE_CONTENTION_RX_RATE,
1140 MCU_PHY_STATE_OFDMLQ_CNINFO,
1141 };
1142
1143 #define MCU_CMD_ACK BIT(0)
1144 #define MCU_CMD_UNI BIT(1)
1145 #define MCU_CMD_SET BIT(2)
1146
1147 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \
1148 MCU_CMD_SET)
1149 #define MCU_CMD_UNI_QUERY_ACK (MCU_CMD_ACK | MCU_CMD_UNI)
1150
1151 #define __MCU_CMD_FIELD_ID GENMASK(7, 0)
1152 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8)
1153 #define __MCU_CMD_FIELD_QUERY BIT(16)
1154 #define __MCU_CMD_FIELD_UNI BIT(17)
1155 #define __MCU_CMD_FIELD_CE BIT(18)
1156 #define __MCU_CMD_FIELD_WA BIT(19)
1157 #define __MCU_CMD_FIELD_WM BIT(20)
1158
1159 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \
1160 MCU_CMD_##_t)
1161 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \
1162 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
1163 MCU_EXT_CMD_##_t))
1164 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1165 #define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \
1166 FIELD_PREP(__MCU_CMD_FIELD_ID, \
1167 MCU_UNI_CMD_##_t))
1168 #define MCU_CE_CMD(_t) (__MCU_CMD_FIELD_CE | \
1169 FIELD_PREP(__MCU_CMD_FIELD_ID, \
1170 MCU_CE_CMD_##_t))
1171 #define MCU_CE_QUERY(_t) (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1172
1173 #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA)
1174 #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA)
1175 #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \
1176 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
1177 MCU_WA_PARAM_CMD_##_t))
1178
1179 #define MCU_WM_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \
1180 __MCU_CMD_FIELD_WM)
1181 #define MCU_WM_UNI_CMD_QUERY(_t) (MCU_UNI_CMD(_t) | \
1182 __MCU_CMD_FIELD_QUERY | \
1183 __MCU_CMD_FIELD_WM)
1184 #define MCU_WA_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \
1185 __MCU_CMD_FIELD_WA)
1186 #define MCU_WMWA_UNI_CMD(_t) (MCU_WM_UNI_CMD(_t) | \
1187 __MCU_CMD_FIELD_WA)
1188
1189 enum {
1190 MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
1191 MCU_EXT_CMD_RF_REG_ACCESS = 0x02,
1192 MCU_EXT_CMD_RF_TEST = 0x04,
1193 MCU_EXT_CMD_ID_RADIO_ON_OFF_CTRL = 0x05,
1194 MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
1195 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
1196 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
1197 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
1198 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
1199 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
1200 MCU_EXT_CMD_THERMAL_PROT = 0x23,
1201 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
1202 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
1203 MCU_EXT_CMD_EDCA_UPDATE = 0x27,
1204 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
1205 MCU_EXT_CMD_THERMAL_CTRL = 0x2c,
1206 MCU_EXT_CMD_WTBL_UPDATE = 0x32,
1207 MCU_EXT_CMD_SET_DRR_CTRL = 0x36,
1208 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
1209 MCU_EXT_CMD_ATE_CTRL = 0x3d,
1210 MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
1211 MCU_EXT_CMD_DBDC_CTRL = 0x45,
1212 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
1213 MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
1214 MCU_EXT_CMD_MUAR_UPDATE = 0x48,
1215 MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
1216 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a,
1217 MCU_EXT_CMD_SET_RX_PATH = 0x4e,
1218 MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f,
1219 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
1220 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
1221 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
1222 MCU_EXT_CMD_TXDPD_CAL = 0x60,
1223 MCU_EXT_CMD_CAL_CACHE = 0x67,
1224 MCU_EXT_CMD_RED_ENABLE = 0x68,
1225 MCU_EXT_CMD_CP_SUPPORT = 0x75,
1226 MCU_EXT_CMD_SET_RADAR_TH = 0x7c,
1227 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
1228 MCU_EXT_CMD_MWDS_SUPPORT = 0x80,
1229 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81,
1230 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94,
1231 MCU_EXT_CMD_FW_DBG_CTRL = 0x95,
1232 MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a,
1233 MCU_EXT_CMD_SET_RDD_TH = 0x9d,
1234 MCU_EXT_CMD_MURU_CTRL = 0x9f,
1235 MCU_EXT_CMD_SET_SPR = 0xa8,
1236 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
1237 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
1238 MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
1239 };
1240
1241 enum {
1242 MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01,
1243 MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02,
1244 MCU_UNI_CMD_STA_REC_UPDATE = 0x03,
1245 MCU_UNI_CMD_EDCA_UPDATE = 0x04,
1246 MCU_UNI_CMD_SUSPEND = 0x05,
1247 MCU_UNI_CMD_OFFLOAD = 0x06,
1248 MCU_UNI_CMD_HIF_CTRL = 0x07,
1249 MCU_UNI_CMD_BAND_CONFIG = 0x08,
1250 MCU_UNI_CMD_REPT_MUAR = 0x09,
1251 MCU_UNI_CMD_WSYS_CONFIG = 0x0b,
1252 MCU_UNI_CMD_REG_ACCESS = 0x0d,
1253 MCU_UNI_CMD_CHIP_CONFIG = 0x0e,
1254 MCU_UNI_CMD_POWER_CTRL = 0x0f,
1255 MCU_UNI_CMD_RX_HDR_TRANS = 0x12,
1256 MCU_UNI_CMD_SER = 0x13,
1257 MCU_UNI_CMD_TWT = 0x14,
1258 MCU_UNI_CMD_SET_DOMAIN_INFO = 0x15,
1259 MCU_UNI_CMD_SCAN_REQ = 0x16,
1260 MCU_UNI_CMD_RDD_CTRL = 0x19,
1261 MCU_UNI_CMD_GET_MIB_INFO = 0x22,
1262 MCU_UNI_CMD_GET_STAT_INFO = 0x23,
1263 MCU_UNI_CMD_SNIFFER = 0x24,
1264 MCU_UNI_CMD_SR = 0x25,
1265 MCU_UNI_CMD_ROC = 0x27,
1266 MCU_UNI_CMD_SET_DBDC_PARMS = 0x28,
1267 MCU_UNI_CMD_TXPOWER = 0x2b,
1268 MCU_UNI_CMD_SET_POWER_LIMIT = 0x2c,
1269 MCU_UNI_CMD_EFUSE_CTRL = 0x2d,
1270 MCU_UNI_CMD_RA = 0x2f,
1271 MCU_UNI_CMD_MURU = 0x31,
1272 MCU_UNI_CMD_BF = 0x33,
1273 MCU_UNI_CMD_CHANNEL_SWITCH = 0x34,
1274 MCU_UNI_CMD_THERMAL = 0x35,
1275 MCU_UNI_CMD_VOW = 0x37,
1276 MCU_UNI_CMD_FIXED_RATE_TABLE = 0x40,
1277 MCU_UNI_CMD_RRO = 0x57,
1278 MCU_UNI_CMD_OFFCH_SCAN_CTRL = 0x58,
1279 MCU_UNI_CMD_PER_STA_INFO = 0x6d,
1280 MCU_UNI_CMD_ALL_STA_INFO = 0x6e,
1281 MCU_UNI_CMD_ASSERT_DUMP = 0x6f,
1282 };
1283
1284 enum {
1285 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
1286 MCU_CMD_FW_START_REQ = 0x02,
1287 MCU_CMD_INIT_ACCESS_REG = 0x3,
1288 MCU_CMD_NIC_POWER_CTRL = 0x4,
1289 MCU_CMD_PATCH_START_REQ = 0x05,
1290 MCU_CMD_PATCH_FINISH_REQ = 0x07,
1291 MCU_CMD_PATCH_SEM_CONTROL = 0x10,
1292 MCU_CMD_WA_PARAM = 0xc4,
1293 MCU_CMD_EXT_CID = 0xed,
1294 MCU_CMD_FW_SCATTER = 0xee,
1295 MCU_CMD_RESTART_DL_REQ = 0xef,
1296 };
1297
1298 /* offload mcu commands */
1299 enum {
1300 MCU_CE_CMD_TEST_CTRL = 0x01,
1301 MCU_CE_CMD_START_HW_SCAN = 0x03,
1302 MCU_CE_CMD_SET_PS_PROFILE = 0x05,
1303 MCU_CE_CMD_SET_RX_FILTER = 0x0a,
1304 MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f,
1305 MCU_CE_CMD_SET_BSS_CONNECTED = 0x16,
1306 MCU_CE_CMD_SET_BSS_ABORT = 0x17,
1307 MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b,
1308 MCU_CE_CMD_SET_ROC = 0x1c,
1309 MCU_CE_CMD_SET_EDCA_PARMS = 0x1d,
1310 MCU_CE_CMD_SET_P2P_OPPPS = 0x33,
1311 MCU_CE_CMD_SET_CLC = 0x5c,
1312 MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d,
1313 MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61,
1314 MCU_CE_CMD_SCHED_SCAN_REQ = 0x62,
1315 MCU_CE_CMD_GET_NIC_CAPAB = 0x8a,
1316 MCU_CE_CMD_RSSI_MONITOR = 0xa1,
1317 MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0,
1318 MCU_CE_CMD_REG_WRITE = 0xc0,
1319 MCU_CE_CMD_REG_READ = 0xc0,
1320 MCU_CE_CMD_CHIP_CONFIG = 0xca,
1321 MCU_CE_CMD_FWLOG_2_HOST = 0xc5,
1322 MCU_CE_CMD_GET_WTBL = 0xcd,
1323 MCU_CE_CMD_GET_TXPWR = 0xd0,
1324 };
1325
1326 enum {
1327 PATCH_SEM_RELEASE,
1328 PATCH_SEM_GET
1329 };
1330
1331 enum {
1332 UNI_BSS_INFO_BASIC = 0,
1333 UNI_BSS_INFO_RA = 1,
1334 UNI_BSS_INFO_RLM = 2,
1335 UNI_BSS_INFO_BSS_COLOR = 4,
1336 UNI_BSS_INFO_HE_BASIC = 5,
1337 UNI_BSS_INFO_11V_MBSSID = 6,
1338 UNI_BSS_INFO_BCN_CONTENT = 7,
1339 UNI_BSS_INFO_BCN_CSA = 8,
1340 UNI_BSS_INFO_BCN_BCC = 9,
1341 UNI_BSS_INFO_BCN_MBSSID = 10,
1342 UNI_BSS_INFO_RATE = 11,
1343 UNI_BSS_INFO_QBSS = 15,
1344 UNI_BSS_INFO_SEC = 16,
1345 UNI_BSS_INFO_BCN_PROT = 17,
1346 UNI_BSS_INFO_TXCMD = 18,
1347 UNI_BSS_INFO_UAPSD = 19,
1348 UNI_BSS_INFO_PS = 21,
1349 UNI_BSS_INFO_BCNFT = 22,
1350 UNI_BSS_INFO_IFS_TIME = 23,
1351 UNI_BSS_INFO_OFFLOAD = 25,
1352 UNI_BSS_INFO_MLD = 26,
1353 UNI_BSS_INFO_PM_DISABLE = 27,
1354 };
1355
1356 enum {
1357 UNI_OFFLOAD_OFFLOAD_ARP,
1358 UNI_OFFLOAD_OFFLOAD_ND,
1359 UNI_OFFLOAD_OFFLOAD_GTK_REKEY,
1360 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT,
1361 };
1362
1363 enum UNI_ALL_STA_INFO_TAG {
1364 UNI_ALL_STA_TXRX_RATE,
1365 UNI_ALL_STA_TX_STAT,
1366 UNI_ALL_STA_TXRX_ADM_STAT,
1367 UNI_ALL_STA_TXRX_AIR_TIME,
1368 UNI_ALL_STA_DATA_TX_RETRY_COUNT,
1369 UNI_ALL_STA_GI_MODE,
1370 UNI_ALL_STA_TXRX_MSDU_COUNT,
1371 UNI_ALL_STA_MAX_NUM
1372 };
1373
1374 enum {
1375 MT_NIC_CAP_TX_RESOURCE,
1376 MT_NIC_CAP_TX_EFUSE_ADDR,
1377 MT_NIC_CAP_COEX,
1378 MT_NIC_CAP_SINGLE_SKU,
1379 MT_NIC_CAP_CSUM_OFFLOAD,
1380 MT_NIC_CAP_HW_VER,
1381 MT_NIC_CAP_SW_VER,
1382 MT_NIC_CAP_MAC_ADDR,
1383 MT_NIC_CAP_PHY,
1384 MT_NIC_CAP_MAC,
1385 MT_NIC_CAP_FRAME_BUF,
1386 MT_NIC_CAP_BEAM_FORM,
1387 MT_NIC_CAP_LOCATION,
1388 MT_NIC_CAP_MUMIMO,
1389 MT_NIC_CAP_BUFFER_MODE_INFO,
1390 MT_NIC_CAP_HW_ADIE_VERSION = 0x14,
1391 MT_NIC_CAP_ANTSWP = 0x16,
1392 MT_NIC_CAP_WFDMA_REALLOC,
1393 MT_NIC_CAP_6G,
1394 MT_NIC_CAP_CHIP_CAP = 0x20,
1395 };
1396
1397 #define UNI_WOW_DETECT_TYPE_MAGIC BIT(0)
1398 #define UNI_WOW_DETECT_TYPE_ANY BIT(1)
1399 #define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2)
1400 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3)
1401 #define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4)
1402 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5)
1403 #define UNI_WOW_DETECT_TYPE_BITMAP BIT(6)
1404
1405 enum {
1406 UNI_SUSPEND_MODE_SETTING,
1407 UNI_SUSPEND_WOW_CTRL,
1408 UNI_SUSPEND_WOW_GPIO_PARAM,
1409 UNI_SUSPEND_WOW_WAKEUP_PORT,
1410 UNI_SUSPEND_WOW_PATTERN,
1411 };
1412
1413 enum {
1414 WOW_USB = 1,
1415 WOW_PCIE = 2,
1416 WOW_GPIO = 3,
1417 };
1418
1419 struct mt76_connac_bss_basic_tlv {
1420 __le16 tag;
1421 __le16 len;
1422 u8 active;
1423 u8 omac_idx;
1424 u8 hw_bss_idx;
1425 u8 band_idx;
1426 __le32 conn_type;
1427 u8 conn_state;
1428 u8 wmm_idx;
1429 u8 bssid[ETH_ALEN];
1430 __le16 bmc_tx_wlan_idx;
1431 __le16 bcn_interval;
1432 u8 dtim_period;
1433 u8 phymode; /* bit(0): A
1434 * bit(1): B
1435 * bit(2): G
1436 * bit(3): GN
1437 * bit(4): AN
1438 * bit(5): AC
1439 * bit(6): AX2
1440 * bit(7): AX5
1441 * bit(8): AX6
1442 */
1443 __le16 sta_idx;
1444 __le16 nonht_basic_phy;
1445 u8 phymode_ext; /* bit(0) AX_6G */
1446 u8 pad[1];
1447 } __packed;
1448
1449 struct mt76_connac_bss_qos_tlv {
1450 __le16 tag;
1451 __le16 len;
1452 u8 qos;
1453 u8 pad[3];
1454 } __packed;
1455
1456 struct mt76_connac_beacon_loss_event {
1457 u8 bss_idx;
1458 u8 reason;
1459 u8 pad[2];
1460 } __packed;
1461
1462 struct mt76_connac_rssi_notify_event {
1463 __le32 rssi[4];
1464 } __packed;
1465
1466 struct mt76_connac_mcu_bss_event {
1467 u8 bss_idx;
1468 u8 is_absent;
1469 u8 free_quota;
1470 u8 pad;
1471 } __packed;
1472
1473 struct mt76_connac_mcu_scan_ssid {
1474 __le32 ssid_len;
1475 u8 ssid[IEEE80211_MAX_SSID_LEN];
1476 } __packed;
1477
1478 struct mt76_connac_mcu_scan_channel {
1479 u8 band; /* 1: 2.4GHz
1480 * 2: 5.0GHz
1481 * Others: Reserved
1482 */
1483 u8 channel_num;
1484 } __packed;
1485
1486 struct mt76_connac_mcu_scan_match {
1487 __le32 rssi_th;
1488 u8 ssid[IEEE80211_MAX_SSID_LEN];
1489 u8 ssid_len;
1490 u8 rsv[3];
1491 } __packed;
1492
1493 struct mt76_connac_hw_scan_req {
1494 u8 seq_num;
1495 u8 bss_idx;
1496 u8 scan_type; /* 0: PASSIVE SCAN
1497 * 1: ACTIVE SCAN
1498 */
1499 u8 ssid_type; /* BIT(0) wildcard SSID
1500 * BIT(1) P2P wildcard SSID
1501 * BIT(2) specified SSID + wildcard SSID
1502 * BIT(2) + ssid_type_ext BIT(0) specified SSID only
1503 */
1504 u8 ssids_num;
1505 u8 probe_req_num; /* Number of probe request for each SSID */
1506 u8 scan_func; /* BIT(0) Enable random MAC scan
1507 * BIT(1) Disable DBDC scan type 1~3.
1508 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan).
1509 */
1510 u8 version; /* 0: Not support fields after ies.
1511 * 1: Support fields after ies.
1512 */
1513 struct mt76_connac_mcu_scan_ssid ssids[4];
1514 __le16 probe_delay_time;
1515 __le16 channel_dwell_time; /* channel Dwell interval */
1516 __le16 timeout_value;
1517 u8 channel_type; /* 0: Full channels
1518 * 1: Only 2.4GHz channels
1519 * 2: Only 5GHz channels
1520 * 3: P2P social channel only (channel #1, #6 and #11)
1521 * 4: Specified channels
1522 * Others: Reserved
1523 */
1524 u8 channels_num; /* valid when channel_type is 4 */
1525 /* valid when channels_num is set */
1526 struct mt76_connac_mcu_scan_channel channels[32];
1527 __le16 ies_len;
1528 u8 ies[MT76_CONNAC_SCAN_IE_LEN];
1529 /* following fields are valid if version > 0 */
1530 u8 ext_channels_num;
1531 u8 ext_ssids_num;
1532 __le16 channel_min_dwell_time;
1533 struct mt76_connac_mcu_scan_channel ext_channels[32];
1534 struct mt76_connac_mcu_scan_ssid ext_ssids[6];
1535 u8 bssid[ETH_ALEN];
1536 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */
1537 u8 pad[63];
1538 u8 ssid_type_ext;
1539 } __packed;
1540
1541 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64
1542
1543 struct mt76_connac_hw_scan_done {
1544 u8 seq_num;
1545 u8 sparse_channel_num;
1546 struct mt76_connac_mcu_scan_channel sparse_channel;
1547 u8 complete_channel_num;
1548 u8 current_state;
1549 u8 version;
1550 u8 pad;
1551 __le32 beacon_scan_num;
1552 u8 pno_enabled;
1553 u8 pad2[3];
1554 u8 sparse_channel_valid_num;
1555 u8 pad3[3];
1556 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1557 /* idle format for channel_idle_time
1558 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms)
1559 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms)
1560 * 2: dwell time (16us)
1561 */
1562 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1563 /* beacon and probe response count */
1564 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1565 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1566 __le32 beacon_2g_num;
1567 __le32 beacon_5g_num;
1568 } __packed;
1569
1570 struct mt76_connac_sched_scan_req {
1571 u8 version;
1572 u8 seq_num;
1573 u8 stop_on_match;
1574 u8 ssids_num;
1575 u8 match_num;
1576 u8 pad;
1577 __le16 ie_len;
1578 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID];
1579 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH];
1580 u8 channel_type;
1581 u8 channels_num;
1582 u8 intervals_num;
1583 u8 scan_func; /* MT7663: BIT(0) eable random mac address */
1584 struct mt76_connac_mcu_scan_channel channels[64];
1585 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL];
1586 union {
1587 struct {
1588 u8 random_mac[ETH_ALEN];
1589 u8 pad2[58];
1590 } mt7663;
1591 struct {
1592 u8 bss_idx;
1593 u8 pad1[3];
1594 __le32 delay;
1595 u8 pad2[12];
1596 u8 random_mac[ETH_ALEN];
1597 u8 pad3[38];
1598 } mt7921;
1599 };
1600 } __packed;
1601
1602 struct mt76_connac_sched_scan_done {
1603 u8 seq_num;
1604 u8 status; /* 0: ssid found */
1605 __le16 pad;
1606 } __packed;
1607
1608 struct bss_info_uni_bss_color {
1609 __le16 tag;
1610 __le16 len;
1611 u8 enable;
1612 u8 bss_color;
1613 u8 rsv[2];
1614 } __packed;
1615
1616 struct bss_info_uni_he {
1617 __le16 tag;
1618 __le16 len;
1619 __le16 he_rts_thres;
1620 u8 he_pe_duration;
1621 u8 su_disable;
1622 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
1623 u8 rsv[2];
1624 } __packed;
1625
1626 struct bss_info_uni_mbssid {
1627 __le16 tag;
1628 __le16 len;
1629 u8 max_indicator;
1630 u8 mbss_idx;
1631 u8 tx_bss_omac_idx;
1632 u8 rsv;
1633 } __packed;
1634
1635 struct mt76_connac_gtk_rekey_tlv {
1636 __le16 tag;
1637 __le16 len;
1638 u8 kek[NL80211_KEK_LEN];
1639 u8 kck[NL80211_KCK_LEN];
1640 u8 replay_ctr[NL80211_REPLAY_CTR_LEN];
1641 u8 rekey_mode; /* 0: rekey offload enable
1642 * 1: rekey offload disable
1643 * 2: rekey update
1644 */
1645 u8 keyid;
1646 u8 option; /* 1: rekey data update without enabling offload */
1647 u8 pad[1];
1648 __le32 proto; /* WPA-RSN-WAPI-OPSN */
1649 __le32 pairwise_cipher;
1650 __le32 group_cipher;
1651 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */
1652 __le32 mgmt_group_cipher;
1653 u8 reserverd[4];
1654 } __packed;
1655
1656 #define MT76_CONNAC_WOW_MASK_MAX_LEN 16
1657 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128
1658
1659 struct mt76_connac_wow_pattern_tlv {
1660 __le16 tag;
1661 __le16 len;
1662 u8 index; /* pattern index */
1663 u8 enable; /* 0: disable
1664 * 1: enable
1665 */
1666 u8 data_len; /* pattern length */
1667 u8 pad;
1668 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN];
1669 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN];
1670 u8 rsv[4];
1671 } __packed;
1672
1673 struct mt76_connac_wow_ctrl_tlv {
1674 __le16 tag;
1675 __le16 len;
1676 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START
1677 * 0x2: PM_WOWLAN_REQ_STOP
1678 * 0x3: PM_WOWLAN_PARAM_CLEAR
1679 */
1680 u8 trigger; /* 0: NONE
1681 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT
1682 * BIT(1): NL80211_WOWLAN_TRIG_ANY
1683 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT
1684 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE
1685 * BIT(4): BEACON_LOST
1686 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT
1687 */
1688 u8 wakeup_hif; /* 0x0: HIF_SDIO
1689 * 0x1: HIF_USB
1690 * 0x2: HIF_PCIE
1691 * 0x3: HIF_GPIO
1692 */
1693 u8 pad;
1694 u8 rsv[4];
1695 } __packed;
1696
1697 struct mt76_connac_wow_gpio_param_tlv {
1698 __le16 tag;
1699 __le16 len;
1700 u8 gpio_pin;
1701 u8 trigger_lvl;
1702 u8 pad[2];
1703 __le32 gpio_interval;
1704 u8 rsv[4];
1705 } __packed;
1706
1707 struct mt76_connac_arpns_tlv {
1708 __le16 tag;
1709 __le16 len;
1710 u8 mode;
1711 u8 ips_num;
1712 u8 option;
1713 u8 pad[1];
1714 } __packed;
1715
1716 struct mt76_connac_suspend_tlv {
1717 __le16 tag;
1718 __le16 len;
1719 u8 enable; /* 0: suspend mode disabled
1720 * 1: suspend mode enabled
1721 */
1722 u8 mdtim; /* LP parameter */
1723 u8 wow_suspend; /* 0: update by origin policy
1724 * 1: update by wow dtim
1725 */
1726 u8 pad[5];
1727 } __packed;
1728
1729 enum mt76_sta_info_state {
1730 MT76_STA_INFO_STATE_NONE,
1731 MT76_STA_INFO_STATE_AUTH,
1732 MT76_STA_INFO_STATE_ASSOC
1733 };
1734
1735 struct mt76_sta_cmd_info {
1736 struct ieee80211_sta *sta;
1737 struct mt76_wcid *wcid;
1738
1739 struct ieee80211_vif *vif;
1740
1741 bool offload_fw;
1742 bool enable;
1743 bool newly;
1744 int cmd;
1745 u8 rcpi;
1746 u8 state;
1747 };
1748
1749 #define MT_SKU_POWER_LIMIT 161
1750
1751 struct mt76_connac_sku_tlv {
1752 u8 channel;
1753 s8 pwr_limit[MT_SKU_POWER_LIMIT];
1754 } __packed;
1755
1756 struct mt76_connac_tx_power_limit_tlv {
1757 /* DW0 - common info*/
1758 u8 ver;
1759 u8 pad0;
1760 __le16 len;
1761 /* DW1 - cmd hint */
1762 u8 n_chan; /* # channel */
1763 u8 band; /* 2.4GHz - 5GHz - 6GHz */
1764 u8 last_msg;
1765 u8 pad1;
1766 /* DW3 */
1767 u8 alpha2[4]; /* regulatory_request.alpha2 */
1768 u8 pad2[32];
1769 } __packed;
1770
1771 struct mt76_connac_config {
1772 __le16 id;
1773 u8 type;
1774 u8 resp_type;
1775 __le16 data_size;
1776 __le16 resv;
1777 u8 data[320];
1778 } __packed;
1779
1780 struct mt76_connac_mcu_uni_event {
1781 u8 cid;
1782 u8 pad[3];
1783 __le32 status; /* 0: success, others: fail */
1784 } __packed;
1785
1786 struct mt76_connac_mcu_reg_event {
1787 __le32 reg;
1788 __le32 val;
1789 } __packed;
1790
1791 static inline enum mcu_cipher_type
mt76_connac_mcu_get_cipher(int cipher)1792 mt76_connac_mcu_get_cipher(int cipher)
1793 {
1794 switch (cipher) {
1795 case WLAN_CIPHER_SUITE_WEP40:
1796 return MCU_CIPHER_WEP40;
1797 case WLAN_CIPHER_SUITE_WEP104:
1798 return MCU_CIPHER_WEP104;
1799 case WLAN_CIPHER_SUITE_TKIP:
1800 return MCU_CIPHER_TKIP;
1801 case WLAN_CIPHER_SUITE_AES_CMAC:
1802 return MCU_CIPHER_BIP_CMAC_128;
1803 case WLAN_CIPHER_SUITE_CCMP:
1804 return MCU_CIPHER_AES_CCMP;
1805 case WLAN_CIPHER_SUITE_CCMP_256:
1806 return MCU_CIPHER_CCMP_256;
1807 case WLAN_CIPHER_SUITE_GCMP:
1808 return MCU_CIPHER_GCMP;
1809 case WLAN_CIPHER_SUITE_GCMP_256:
1810 return MCU_CIPHER_GCMP_256;
1811 case WLAN_CIPHER_SUITE_BIP_GMAC_128:
1812 return MCU_CIPHER_BIP_GMAC_128;
1813 case WLAN_CIPHER_SUITE_BIP_GMAC_256:
1814 return MCU_CIPHER_BIP_GMAC_256;
1815 case WLAN_CIPHER_SUITE_BIP_CMAC_256:
1816 return MCU_CIPHER_BIP_CMAC_256;
1817 case WLAN_CIPHER_SUITE_SMS4:
1818 return MCU_CIPHER_WAPI;
1819 default:
1820 return MCU_CIPHER_NONE;
1821 }
1822 }
1823
1824 static inline u32
mt76_connac_mcu_gen_dl_mode(struct mt76_dev * dev,u8 feature_set,bool is_wa)1825 mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa)
1826 {
1827 u32 ret = 0;
1828
1829 ret |= feature_set & FW_FEATURE_SET_ENCRYPT ?
1830 DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0;
1831 if (is_mt7921(dev) || is_mt7925(dev))
1832 ret |= feature_set & FW_FEATURE_ENCRY_MODE ?
1833 DL_CONFIG_ENCRY_MODE_SEL : 0;
1834 ret |= FIELD_PREP(DL_MODE_KEY_IDX,
1835 FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set));
1836 ret |= DL_MODE_NEED_RSP;
1837 ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0;
1838
1839 return ret;
1840 }
1841
1842 #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id)
1843 #define to_wcid_hi(id) FIELD_GET(GENMASK(10, 8), (u16)id)
1844
1845 static inline void
mt76_connac_mcu_get_wlan_idx(struct mt76_dev * dev,struct mt76_wcid * wcid,u8 * wlan_idx_lo,u8 * wlan_idx_hi)1846 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid,
1847 u8 *wlan_idx_lo, u8 *wlan_idx_hi)
1848 {
1849 *wlan_idx_hi = 0;
1850
1851 if (!is_connac_v1(dev)) {
1852 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0;
1853 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0;
1854 } else {
1855 *wlan_idx_lo = wcid ? wcid->idx : 0;
1856 }
1857 }
1858
1859 struct sk_buff *
1860 __mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1861 struct mt76_wcid *wcid, int len);
1862 static inline struct sk_buff *
mt76_connac_mcu_alloc_sta_req(struct mt76_dev * dev,struct mt76_vif * mvif,struct mt76_wcid * wcid)1863 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1864 struct mt76_wcid *wcid)
1865 {
1866 return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid,
1867 MT76_CONNAC_STA_UPDATE_MAX_SIZE);
1868 }
1869
1870 struct wtbl_req_hdr *
1871 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid,
1872 int cmd, void *sta_wtbl, struct sk_buff **skb);
1873 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag,
1874 int len, void *sta_ntlv,
1875 void *sta_wtbl);
1876 static inline struct tlv *
mt76_connac_mcu_add_tlv(struct sk_buff * skb,int tag,int len)1877 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len)
1878 {
1879 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL);
1880 }
1881
1882 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy);
1883 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif);
1884 void mt76_connac_mcu_sta_basic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1885 struct ieee80211_vif *vif,
1886 struct ieee80211_sta *sta, bool enable,
1887 bool newly);
1888 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1889 struct ieee80211_vif *vif,
1890 struct ieee80211_sta *sta, void *sta_wtbl,
1891 void *wtbl_tlv);
1892 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb,
1893 struct ieee80211_vif *vif,
1894 struct mt76_wcid *wcid,
1895 void *sta_wtbl, void *wtbl_tlv);
1896 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev,
1897 struct ieee80211_vif *vif,
1898 struct mt76_wcid *wcid, int cmd);
1899 void mt76_connac_mcu_sta_he_tlv_v2(struct sk_buff *skb, struct ieee80211_sta *sta);
1900 u8 mt76_connac_get_phy_mode_v2(struct mt76_phy *mphy, struct ieee80211_vif *vif,
1901 enum nl80211_band band, struct ieee80211_sta *sta);
1902 int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev,
1903 struct ieee80211_vif *vif,
1904 struct ieee80211_sta *sta);
1905 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb,
1906 struct ieee80211_sta *sta,
1907 struct ieee80211_vif *vif,
1908 u8 rcpi, u8 state);
1909 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1910 struct ieee80211_sta *sta, void *sta_wtbl,
1911 void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc);
1912 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1913 struct ieee80211_ampdu_params *params,
1914 bool enable, bool tx, void *sta_wtbl,
1915 void *wtbl_tlv);
1916 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb,
1917 struct ieee80211_ampdu_params *params,
1918 bool enable, bool tx);
1919 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy,
1920 struct ieee80211_vif *vif,
1921 struct mt76_wcid *wcid,
1922 bool enable);
1923 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
1924 struct ieee80211_ampdu_params *params,
1925 int cmd, bool enable, bool tx);
1926 int mt76_connac_mcu_uni_set_chctx(struct mt76_phy *phy,
1927 struct mt76_vif *vif,
1928 struct ieee80211_chanctx_conf *ctx);
1929 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy,
1930 struct ieee80211_vif *vif,
1931 struct mt76_wcid *wcid,
1932 bool enable,
1933 struct ieee80211_chanctx_conf *ctx);
1934 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy,
1935 struct mt76_sta_cmd_info *info);
1936 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac,
1937 struct ieee80211_vif *vif);
1938 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band);
1939 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable,
1940 bool hdr_trans);
1941 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len,
1942 u32 mode);
1943 int mt76_connac_mcu_start_patch(struct mt76_dev *dev);
1944 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get);
1945 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option);
1946
1947 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif,
1948 struct ieee80211_scan_request *scan_req);
1949 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy,
1950 struct ieee80211_vif *vif);
1951 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy,
1952 struct ieee80211_vif *vif,
1953 struct cfg80211_sched_scan_request *sreq);
1954 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy,
1955 struct ieee80211_vif *vif,
1956 bool enable);
1957 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev,
1958 struct mt76_vif *vif,
1959 struct ieee80211_bss_conf *info);
1960 int mt76_connac_mcu_set_gtk_rekey(struct mt76_dev *dev, struct ieee80211_vif *vif,
1961 bool suspend);
1962 int mt76_connac_mcu_set_wow_ctrl(struct mt76_phy *phy, struct ieee80211_vif *vif,
1963 bool suspend, struct cfg80211_wowlan *wowlan);
1964 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw,
1965 struct ieee80211_vif *vif,
1966 struct cfg80211_gtk_rekey_data *key);
1967 int mt76_connac_mcu_set_suspend_mode(struct mt76_dev *dev,
1968 struct ieee80211_vif *vif,
1969 bool enable, u8 mdtim,
1970 bool wow_suspend);
1971 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend);
1972 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac,
1973 struct ieee80211_vif *vif);
1974 int mt76_connac_sta_state_dp(struct mt76_dev *dev,
1975 enum ieee80211_sta_state old_state,
1976 enum ieee80211_sta_state new_state);
1977 int mt76_connac_mcu_chip_config(struct mt76_dev *dev);
1978 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable);
1979 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb,
1980 struct mt76_connac_coredump *coredump);
1981 s8 mt76_connac_get_ch_power(struct mt76_phy *phy,
1982 struct ieee80211_channel *chan,
1983 s8 target_power);
1984 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy);
1985 int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw,
1986 struct ieee80211_vif *vif);
1987 u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset);
1988 void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val);
1989
1990 const struct ieee80211_sta_he_cap *
1991 mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif);
1992 const struct ieee80211_sta_eht_cap *
1993 mt76_connac_get_eht_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif);
1994 u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif,
1995 enum nl80211_band band, struct ieee80211_sta *sta);
1996 u8 mt76_connac_get_phy_mode_ext(struct mt76_phy *phy, struct ieee80211_vif *vif,
1997 enum nl80211_band band);
1998
1999 int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
2000 struct mt76_connac_sta_key_conf *sta_key_conf,
2001 struct ieee80211_key_conf *key, int mcu_cmd,
2002 struct mt76_wcid *wcid, enum set_key_cmd cmd);
2003
2004 void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif *mvif);
2005 void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb,
2006 struct ieee80211_vif *vif);
2007 int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb,
2008 struct ieee80211_vif *vif,
2009 struct ieee80211_sta *sta,
2010 struct mt76_phy *phy, u16 wlan_idx,
2011 bool enable);
2012 void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif,
2013 struct ieee80211_sta *sta);
2014 void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb,
2015 struct ieee80211_sta *sta,
2016 void *sta_wtbl, void *wtbl_tlv);
2017 int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter);
2018 int mt76_connac_mcu_restart(struct mt76_dev *dev);
2019 int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index,
2020 u8 rx_sel, u8 val);
2021 int mt76_connac_mcu_sta_wed_update(struct mt76_dev *dev, struct sk_buff *skb);
2022 int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm,
2023 const char *fw_wa);
2024 int mt76_connac2_load_patch(struct mt76_dev *dev, const char *fw_name);
2025 int mt76_connac2_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb,
2026 int cmd, int *wait_seq);
2027 #endif /* __MT76_CONNAC_MCU_H */
2028