1 #ifndef STLINK_CHIPID_H_ 2 #define STLINK_CHIPID_H_ 3 4 #ifdef __cplusplus 5 extern "C" { 6 #endif 7 8 /** 9 * Chip IDs are explained in the appropriate programming manual for the 10 * DBGMCU_IDCODE register (0xE0042000) 11 * stm32 chipids, only lower 12 bits... 12 */ 13 enum stlink_stm32_chipids { 14 STLINK_CHIPID_UNKNOWN = 0x000, 15 16 STLINK_CHIPID_STM32_F1_MEDIUM = 0x410, 17 STLINK_CHIPID_STM32_F2 = 0x411, 18 STLINK_CHIPID_STM32_F1_LOW = 0x412, 19 STLINK_CHIPID_STM32_F4 = 0x413, 20 STLINK_CHIPID_STM32_F1_HIGH = 0x414, 21 STLINK_CHIPID_STM32_L4 = 0x415, 22 STLINK_CHIPID_STM32_L1_MEDIUM = 0x416, 23 STLINK_CHIPID_STM32_L0 = 0x417, 24 STLINK_CHIPID_STM32_F1_CONN = 0x418, 25 STLINK_CHIPID_STM32_F4_HD = 0x419, 26 STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW = 0x420, 27 STLINK_CHIPID_STM32_F446 = 0x421, 28 STLINK_CHIPID_STM32_F3 = 0x422, 29 STLINK_CHIPID_STM32_F4_LP = 0x423, 30 STLINK_CHIPID_STM32_L0_CAT2 = 0x425, 31 STLINK_CHIPID_STM32_L1_MEDIUM_PLUS = 0x427, /* assigned to some L1 "Medium-plus" chips */ 32 STLINK_CHIPID_STM32_F1_VL_HIGH = 0x428, 33 STLINK_CHIPID_STM32_L1_CAT2 = 0x429, 34 STLINK_CHIPID_STM32_F1_XL = 0x430, 35 STLINK_CHIPID_STM32_F411RE = 0x431, 36 STLINK_CHIPID_STM32_F37x = 0x432, 37 STLINK_CHIPID_STM32_F4_DE = 0x433, 38 STLINK_CHIPID_STM32_F4_DSI = 0x434, 39 STLINK_CHIPID_STM32_L43X = 0x435, /* covers STM32L43xxx and STM32L44xxx devices */ 40 STLINK_CHIPID_STM32_L496X = 0x461, /* covers STM32L496xx and STM32L4A6xx devices */ 41 STLINK_CHIPID_STM32_L46X = 0x462, /* covers STM32L45xxx and STM32L46xxx devices */ 42 STLINK_CHIPID_STM32_L41X = 0x464, /* covers STM32L41xxx and STM32L42xxx devices */ 43 STLINK_CHIPID_STM32_L1_HIGH = 0x436, /* assigned to some L1 "Medium-Plus" and "High" chips */ 44 STLINK_CHIPID_STM32_L152_RE = 0x437, 45 STLINK_CHIPID_STM32_F334 = 0x438, 46 STLINK_CHIPID_STM32_F3_SMALL = 0x439, 47 STLINK_CHIPID_STM32_F0 = 0x440, 48 STLINK_CHIPID_STM32_F412 = 0x441, 49 STLINK_CHIPID_STM32_F09X = 0x442, 50 STLINK_CHIPID_STM32_F0_SMALL = 0x444, 51 STLINK_CHIPID_STM32_F04 = 0x445, 52 STLINK_CHIPID_STM32_F303_HIGH = 0x446, 53 STLINK_CHIPID_STM32_L0_CAT5 = 0x447, 54 STLINK_CHIPID_STM32_F0_CAN = 0x448, 55 STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the NucleoF746ZG board */ 56 STLINK_CHIPID_STM32_H74XXX = 0x450, /* Found on page 3189 in the RM0433*/ 57 STLINK_CHIPID_STM32_F7XXXX = 0x451, 58 STLINK_CHIPID_STM32_F72XXX = 0x452, /* ID found on the NucleoF722ZE board */ 59 STLINK_CHIPID_STM32_L011 = 0x457, 60 STLINK_CHIPID_STM32_F410 = 0x458, 61 STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ 62 STLINK_CHIPID_STM32_F413 = 0x463, 63 STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ 64 STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ 65 STLINK_CHIPID_STM32_G4_CAT3 = 0x469, 66 STLINK_CHIPID_STM32_L4RX = 0x470, /* ID found on the STM32L4R9I-DISCO board */ 67 STLINK_CHIPID_STM32_H7AX = 0x480, /* RM0455, p. 2863 */ 68 STLINK_CHIPID_STM32_H72X = 0x483, /* RM0468, p. 3199 */ 69 STLINK_CHIPID_STM32_WB55 = 0x495 70 }; 71 72 73 #define CHIP_F_HAS_DUAL_BANK (1 << 0) 74 #define CHIP_F_HAS_SWO_TRACING (1 << 1) 75 76 77 /** Chipid parameters */ 78 struct stlink_chipid_params { 79 uint32_t chip_id; 80 char *description; 81 enum stlink_flash_type flash_type; 82 uint32_t flash_size_reg; 83 uint32_t flash_pagesize; 84 uint32_t sram_size; 85 uint32_t bootrom_base; 86 uint32_t bootrom_size; 87 uint32_t option_base; 88 uint32_t option_size; 89 uint32_t flags; 90 }; 91 92 const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); 93 94 #ifdef __cplusplus 95 } 96 #endif 97 98 #endif // STLINK_CHIPID_H_ 99