1 /* 2 * File: stlink.h 3 * 4 * This should contain all the common top level stlink interfaces, 5 * regardless of how the backend does the work.... 6 */ 7 8 #ifndef STLINK_H 9 #define STLINK_H 10 11 #include <stdint.h> 12 #include <stddef.h> 13 #include <stdbool.h> 14 15 #include "stm32.h" 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 #define STLINK_ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) 22 23 /* Max data transfer size */ 24 // 6kB = max mem32_read block, 8kB sram 25 // #define Q_BUF_LEN 96 26 #define Q_BUF_LEN (1024 * 100) 27 28 // STLINK_DEBUG_RESETSYS, etc: 29 enum target_state { 30 TARGET_UNKNOWN = 0, 31 TARGET_RUNNING = 1, 32 TARGET_HALTED = 2, 33 TARGET_RESET = 3, 34 TARGET_DEBUG_RUNNING = 4, 35 }; 36 37 #define STLINK_CORE_RUNNING 0x80 38 #define STLINK_CORE_HALTED 0x81 39 40 #define STLINK_GET_VERSION 0xF1 41 #define STLINK_GET_CURRENT_MODE 0xF5 42 #define STLINK_GET_TARGET_VOLTAGE 0xF7 43 44 #define STLINK_DEBUG_COMMAND 0xF2 45 #define STLINK_DFU_COMMAND 0xF3 46 #define STLINK_DFU_EXIT 0x07 47 48 // STLINK_GET_CURRENT_MODE 49 #define STLINK_DEV_DFU_MODE 0x00 50 #define STLINK_DEV_MASS_MODE 0x01 51 #define STLINK_DEV_DEBUG_MODE 0x02 52 #define STLINK_DEV_UNKNOWN_MODE -1 53 54 // TODO - possible poor names... 55 #define STLINK_SWD_ENTER 0x30 56 #define STLINK_SWD_READCOREID 0x32 // TBD 57 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35 58 #define STLINK_JTAG_READDEBUG_32BIT 0x36 59 #define STLINK_JTAG_DRIVE_NRST 0x3C 60 61 /* NRST pin states */ 62 #define STLINK_JTAG_DRIVE_NRST_LOW 0x00 63 #define STLINK_JTAG_DRIVE_NRST_HIGH 0x01 64 #define STLINK_JTAG_DRIVE_NRST_PULSE 0x02 65 66 #define STLINK_DEBUG_APIV2_SWD_SET_FREQ 0x43 67 68 #define STLINK_APIV3_SET_COM_FREQ 0x61 69 #define STLINK_APIV3_GET_COM_FREQ 0x62 70 71 #define STLINK_APIV3_GET_VERSION_EX 0xFB 72 73 /* Baud rate divisors for SWDCLK */ 74 #define STLINK_SWDCLK_4MHZ_DIVISOR 0 75 #define STLINK_SWDCLK_1P8MHZ_DIVISOR 1 76 #define STLINK_SWDCLK_1P2MHZ_DIVISOR 2 77 #define STLINK_SWDCLK_950KHZ_DIVISOR 3 78 #define STLINK_SWDCLK_480KHZ_DIVISOR 7 79 #define STLINK_SWDCLK_240KHZ_DIVISOR 15 80 #define STLINK_SWDCLK_125KHZ_DIVISOR 31 81 #define STLINK_SWDCLK_100KHZ_DIVISOR 40 82 #define STLINK_SWDCLK_50KHZ_DIVISOR 79 83 #define STLINK_SWDCLK_25KHZ_DIVISOR 158 84 #define STLINK_SWDCLK_15KHZ_DIVISOR 265 85 #define STLINK_SWDCLK_5KHZ_DIVISOR 798 86 87 #define STLINK_SERIAL_LENGTH 24 88 #define STLINK_SERIAL_BUFFER_SIZE (STLINK_SERIAL_LENGTH + 1) 89 90 #define STLINK_V3_MAX_FREQ_NB 10 91 92 #define STLINK_TRACE_BUF_LEN 2048 93 #define STLINK_V2_MAX_TRACE_FREQUENCY 2000000 94 #define STLINK_V3_MAX_TRACE_FREQUENCY 24000000 95 #define STLINK_DEFAULT_TRACE_FREQUENCY 2000000 96 97 /* Map the relevant features, quirks and workaround for specific firmware version of stlink */ 98 #define STLINK_F_HAS_TRACE (1 << 0) 99 #define STLINK_F_HAS_SWD_SET_FREQ (1 << 1) 100 #define STLINK_F_HAS_JTAG_SET_FREQ (1 << 2) 101 #define STLINK_F_HAS_MEM_16BIT (1 << 3) 102 #define STLINK_F_HAS_GETLASTRWSTATUS2 (1 << 4) 103 #define STLINK_F_HAS_DAP_REG (1 << 5) 104 #define STLINK_F_QUIRK_JTAG_DP_READ (1 << 6) 105 #define STLINK_F_HAS_AP_INIT (1 << 7) 106 #define STLINK_F_HAS_DPBANKSEL (1 << 8) 107 #define STLINK_F_HAS_RW8_512BYTES (1 << 9) 108 109 #define C_BUF_LEN 32 110 111 enum stlink_flash_type { 112 STLINK_FLASH_TYPE_UNKNOWN = 0, 113 STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */ 114 STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank, apparently */ 115 STLINK_FLASH_TYPE_F4, // used by f2, f4 */ 116 STLINK_FLASH_TYPE_F7, 117 STLINK_FLASH_TYPE_L0, // l0, l1 */ 118 STLINK_FLASH_TYPE_L4, // l4, l4+ */ 119 STLINK_FLASH_TYPE_G0, 120 STLINK_FLASH_TYPE_G4, 121 STLINK_FLASH_TYPE_WB, 122 STLINK_FLASH_TYPE_H7, 123 }; 124 125 struct stlink_reg { 126 uint32_t r[16]; 127 uint32_t s[32]; 128 uint32_t xpsr; 129 uint32_t main_sp; 130 uint32_t process_sp; 131 uint32_t rw; 132 uint32_t rw2; 133 uint8_t control; 134 uint8_t faultmask; 135 uint8_t basepri; 136 uint8_t primask; 137 uint32_t fpscr; 138 }; 139 140 typedef uint32_t stm32_addr_t; 141 142 typedef struct flash_loader { 143 stm32_addr_t loader_addr; // loader sram addr 144 stm32_addr_t buf_addr; // buffer sram address 145 uint32_t rcc_dma_bkp; // backup RCC DMA enable state 146 uint32_t iwdg_kr; // IWDG key register address 147 } flash_loader_t; 148 149 typedef struct _cortex_m3_cpuid_ { 150 uint16_t implementer_id; 151 uint16_t variant; 152 uint16_t part; 153 uint8_t revision; 154 } cortex_m3_cpuid_t; 155 156 enum stlink_jtag_api_version { 157 STLINK_JTAG_API_V1 = 1, 158 STLINK_JTAG_API_V2, 159 STLINK_JTAG_API_V3, 160 }; 161 162 typedef struct stlink_version_ { 163 uint32_t stlink_v; 164 uint32_t jtag_v; 165 uint32_t swim_v; 166 uint32_t st_vid; 167 uint32_t stlink_pid; 168 // jtag api version supported 169 enum stlink_jtag_api_version jtag_api; 170 // one bit for each feature supported. See macros STLINK_F_* 171 uint32_t flags; 172 } stlink_version_t; 173 174 enum transport_type { 175 TRANSPORT_TYPE_ZERO = 0, 176 TRANSPORT_TYPE_LIBSG, 177 TRANSPORT_TYPE_LIBUSB, 178 TRANSPORT_TYPE_INVALID 179 }; 180 181 enum connect_type { 182 CONNECT_HOT_PLUG = 0, 183 CONNECT_NORMAL = 1, 184 CONNECT_UNDER_RESET = 2, 185 }; 186 187 enum reset_type { 188 RESET_AUTO = 0, 189 RESET_HARD = 1, 190 RESET_SOFT = 2, 191 RESET_SOFT_AND_HALT = 3, 192 }; 193 194 enum run_type { 195 RUN_NORMAL = 0, 196 RUN_FLASH_LOADER = 1, 197 }; 198 199 200 typedef struct _stlink stlink_t; 201 202 #include <backend.h> 203 204 struct _stlink { 205 struct _stlink_backend *backend; 206 void *backend_data; 207 208 // room for the command header 209 unsigned char c_buf[C_BUF_LEN]; 210 // data transferred from or to device 211 unsigned char q_buf[Q_BUF_LEN]; 212 int q_len; 213 214 // transport layer verboseness: 0 for no debug info, 10 for lots 215 int verbose; 216 int opt; 217 uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID 218 uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram 219 enum target_state core_stat; // set by stlink_status() 220 221 char serial[STLINK_SERIAL_BUFFER_SIZE]; 222 int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR 223 224 enum stlink_flash_type flash_type; 225 // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx 226 227 stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() 228 size_t flash_size; // calculated by stlink_load_device_params() 229 size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() 230 231 /* sram settings */ 232 stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() 233 size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() 234 235 /* option settings */ 236 stm32_addr_t option_base; 237 size_t option_size; 238 239 // bootloader 240 // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code 241 // (see tests/sg.c) 242 stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() 243 size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() 244 245 struct stlink_version_ version; 246 247 uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx 248 249 uint32_t max_trace_freq; // set by stlink_open_usb() 250 }; 251 252 int stlink_enter_swd_mode(stlink_t *sl); 253 int stlink_enter_jtag_mode(stlink_t *sl); 254 int stlink_exit_debug_mode(stlink_t *sl); 255 int stlink_exit_dfu_mode(stlink_t *sl); 256 void stlink_close(stlink_t *sl); 257 int stlink_core_id(stlink_t *sl); 258 int stlink_reset(stlink_t *sl, enum reset_type type); 259 int stlink_run(stlink_t *sl, enum run_type type); 260 int stlink_status(stlink_t *sl); 261 int stlink_version(stlink_t *sl); 262 int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); 263 int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); 264 int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); 265 int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); 266 int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); 267 int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); 268 int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); 269 int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); 270 int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); 271 int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, struct stlink_reg *regp); 272 int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); 273 int stlink_step(stlink_t *sl); 274 int stlink_current_mode(stlink_t *sl); 275 int stlink_force_debug(stlink_t *sl); 276 int stlink_target_voltage(stlink_t *sl); 277 int stlink_set_swdclk(stlink_t *sl, int freq_khz); 278 int stlink_trace_enable(stlink_t* sl, uint32_t frequency); 279 int stlink_trace_disable(stlink_t* sl); 280 int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); 281 int stlink_erase_flash_mass(stlink_t* sl); 282 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); 283 int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); 284 uint8_t stlink_get_erased_pattern(stlink_t *sl); 285 int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); 286 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); 287 int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); 288 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); 289 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); 290 291 int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); 292 int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); 293 294 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); 295 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); 296 uint16_t read_uint16(const unsigned char *c, const int pt); 297 void stlink_core_stat(stlink_t *sl); 298 void stlink_print_data(stlink_t *sl); 299 unsigned int is_bigendian(void); 300 uint32_t read_uint32(const unsigned char *c, const int pt); 301 void write_uint32(unsigned char* buf, uint32_t ui); 302 void write_uint16(unsigned char* buf, uint16_t ui); 303 bool stlink_is_core_halted(stlink_t *sl); 304 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); 305 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); 306 int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); 307 int stlink_load_device_params(stlink_t *sl); 308 309 int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); 310 int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); 311 int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte); 312 int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte); 313 314 int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); 315 int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); 316 int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_control_register); 317 int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_control_register1); 318 319 int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); 320 int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); 321 322 int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); 323 int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); 324 int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); 325 326 int stlink_target_connect(stlink_t *sl, enum connect_type connect); 327 328 #include <sg.h> 329 #include <usb.h> 330 #include <reg.h> 331 #include <commands.h> 332 #include <chipid.h> 333 #include <flash_loader.h> 334 #include <version.h> 335 #include <logging.h> 336 337 #ifdef __cplusplus 338 } 339 #endif 340 341 #endif // STLINK_H 342