1 /* ESA390.H (c) Copyright Roger Bowler, 1994-2010 */ 2 /* ESA/390 Data Areas */ 3 4 /* Interpretive Execution - (c) Copyright Jan Jaeger, 1999-2009 */ 5 /* z/Architecture support - (c) Copyright Jan Jaeger, 1999-2009 */ 6 7 #ifndef _ESA390_H 8 #define _ESA390_H 9 10 /* Platform-independent storage operand definitions */ 11 12 #include "htypes.h" 13 14 #if defined(WORDS_BIGENDIAN) 15 16 typedef union { 17 U16 H; 18 struct { BYTE H; BYTE L; } B; 19 } HW; 20 typedef union { 21 U32 F; 22 struct { HW H; HW L; } H; 23 struct { BYTE B; U32 A:24; } A; 24 } FW; 25 typedef union { 26 U64 D; 27 struct { FW H; FW L; } F; 28 } DW; 29 typedef union { 30 struct { DW H; DW L; } D; 31 struct { FW HH; FW HL; FW LH; FW LL; } F; 32 } QW; 33 34 #else // !defined(WORDS_BIGENDIAN) 35 36 typedef union { 37 U16 H; 38 struct { BYTE L; BYTE H; } B; 39 } HW; 40 typedef union { 41 U32 F; 42 struct { HW L; HW H; } H; 43 struct { U32 A:24, B:8; } A; 44 } FW; 45 typedef union { 46 U64 D; 47 struct { FW L; FW H; } F; 48 } DW; 49 typedef union { 50 struct { DW L; DW H; } D; 51 struct { FW LL; FW LH; FW HL; FW HH; } F; 52 } QW; 53 54 #endif // defined(WORDS_BIGENDIAN) 55 56 typedef union { 57 HWORD H; 58 struct { BYTE H; BYTE L; } B; 59 } HWORD_U; 60 typedef union { 61 FWORD F; 62 struct { HWORD_U H; HWORD_U L; } H; 63 } FWORD_U; 64 typedef union { 65 DBLWRD D; 66 struct { FWORD_U H; FWORD_U L; } F; 67 } DWORD_U; 68 69 /* Internal-format PSW structure definition */ 70 typedef struct _PSW { 71 BYTE sysmask; /* System mask (0 - 7) */ 72 BYTE pkey; /* PSW Key (8 - 11) */ 73 BYTE states; /* EC,M,W,P bits (12 - 15) */ 74 BYTE asc; /* Address space control */ 75 /* (16 - 17) */ 76 BYTE cc; /* Condition code (18 - 19) */ 77 BYTE progmask; /* Program mask (20 - 23) */ 78 BYTE zerobyte; /* Zeroes (24 - 31) */ 79 /* or (esame) (24 - 30) */ 80 u_int /* Addressing mode (31 - 32) */ 81 amode64:1, /* 64-bit addressing (31) */ 82 amode:1, /* 31-bit addressing (32) */ 83 zeroilc:1; /* 1=Zero ILC */ 84 U32 zeroword; /* esame only (33 - 63) */ 85 DW ia; /* Instruction addrress */ 86 /* (33 - 63) */ 87 /* or (esame) (64 -127) */ 88 DW amask; /* Address wraparound mask */ 89 U16 intcode; /* Interruption code */ 90 BYTE ilc; /* Instruction length count */ 91 BYTE unused; 92 } PSW; 93 94 #define IA_G ia.D 95 #define IA_H ia.F.H.F 96 #define IA_L ia.F.L.F 97 #define IA_LA24 ia.F.L.A.A 98 99 #define AMASK_G amask.D 100 #define AMASK_L amask.F.L.F 101 #define AMASK_H amask.F.H.F 102 #define AMASK24 0x00FFFFFF 103 #define AMASK31 0x7FFFFFFF 104 #define AMASK64 0xFFFFFFFFFFFFFFFFULL 105 106 /* System mask (0 - 7) */ 107 #define PSW_PERMODE 0x40 /* Program event recording */ 108 #define PSW_DATMODE 0x04 /* Dynamic addr translation */ 109 #define PSW_IOMASK 0x02 /* I/O interrupt mask */ 110 #define PSW_EXTMASK 0x01 /* External interrupt mask */ 111 112 /* PSW key mask (8 - 11) */ 113 #define PSW_KEYMASK 0xF0 /* PSW key mask */ 114 115 /* (12 - 15) */ 116 #define PSW_EC_BIT 3 /* 0x08 ECMODE */ 117 #define PSW_MACH_BIT 2 /* 0x04 Machine check mask */ 118 #define PSW_WAIT_BIT 1 /* 0x02 Wait state */ 119 #define PSW_PROB_BIT 0 /* 0x01 Problem state */ 120 #define PSW_NOTESAME_BIT PSW_EC_BIT 121 122 /* Address space control (16 - 17) */ 123 #define PSW_ASCMASK 0xC0 /* Address space control mask*/ 124 #define PSW_SPACE_BIT 7 /* 0x80 Space mode bit */ 125 #define PSW_AR_BIT 6 /* 0x40 Access register mode bit */ 126 #define PSW_PRIMARY_SPACE_MODE 0x00 /* Primary-space mode */ 127 #define PSW_SECONDARY_SPACE_MODE 0x80 /* Secondary-space mode */ 128 #define PSW_ACCESS_REGISTER_MODE 0x40 /* Access-register mode */ 129 #define PSW_HOME_SPACE_MODE 0xC0 /* Home-space mode */ 130 131 /* Condition code (18 - 19) */ 132 #define PSW_CCMASK 0x30 /* Condition code mask */ 133 134 /* Program mask (20 - 23) */ 135 #define PSW_PROGMASK 0x0F /* Program-mask bits */ 136 #define PSW_FOBIT 3 /* 0x08 Fixed-point overflow bit */ 137 #define PSW_DOBIT 2 /* 0x04 Decimal overflow bit */ 138 #define PSW_EUBIT 1 /* 0x02 Exponent underflow bit */ 139 #define PSW_SGBIT 0 /* 0x01 Significance bit */ 140 141 /* Address mode (31 - 32) */ 142 #define PSW_AMODE64_BIT 0 /* Extended addressing (31) */ 143 #define PSW_AMODE31_BIT 7 /* Basic addressing (32) */ 144 145 /* Macros for testing states (EC, M, W, P bits) */ 146 #define ECMODE(p) (((p)->states & BIT(PSW_EC_BIT)) != 0) 147 #define NOTESAME(p) (((p)->states & BIT(PSW_NOTESAME_BIT)) != 0) 148 #define MACHMASK(p) (((p)->states & BIT(PSW_MACH_BIT)) != 0) 149 #define WAITSTATE(p) (((p)->states & BIT(PSW_WAIT_BIT)) != 0) 150 #define PROBSTATE(p) (((p)->states & BIT(PSW_PROB_BIT)) != 0) 151 152 /* Macros for testing program mask */ 153 #define FOMASK(p) ( (p)->progmask & BIT(PSW_FOBIT) ) 154 #define DOMASK(p) ( (p)->progmask & BIT(PSW_DOBIT) ) 155 #define EUMASK(p) ( (p)->progmask & BIT(PSW_EUBIT) ) 156 #define SGMASK(p) ( (p)->progmask & BIT(PSW_SGBIT) ) 157 158 /* Structure definition for translation-lookaside buffer entry */ 159 #define TLBN 1024 /* Number TLB entries */ 160 #define TLB_MASK 0x3FF /* Mask for 1024 entries */ 161 #define TLB_REAL_ASD_L 0xFFFFFFFF /* ASD values for real mode */ 162 #define TLB_REAL_ASD_G 0xFFFFFFFFFFFFFFFFULL 163 #define TLB_HOST_ASD 0x800 /* Host entry for XC guest */ 164 typedef struct _TLB { 165 DW asd[TLBN]; /* Address space designator */ 166 #define TLB_ASD_G(_n) asd[(_n)].D 167 #define TLB_ASD_L(_n) asd[(_n)].F.L.F 168 DW vaddr[TLBN]; /* Virtual page address */ 169 #define TLB_VADDR_G(_n) vaddr[(_n)].D 170 #define TLB_VADDR_L(_n) vaddr[(_n)].F.L.F 171 DW pte[TLBN]; /* Copy of page table entry */ 172 #define TLB_PTE_G(_n) pte[(_n)].D 173 #define TLB_PTE_L(_n) pte[(_n)].F.L.F 174 BYTE *main[TLBN]; /* Mainstor address */ 175 BYTE *storkey[TLBN]; /* -> Storage key */ 176 BYTE skey[TLBN]; /* Storage key key-value */ 177 BYTE common[TLBN]; /* 1=Page in common segment */ 178 BYTE protect[TLBN]; /* 1=Page in protected segmnt*/ 179 BYTE acc[TLBN]; /* Access type flags */ 180 } TLB; 181 182 /* TLB Notes - 183 * Fields set by translate_addr() are asd, vaddr, pte, id, common and 184 * protect. 185 * Fields set by logical_to_main() are main, storkey, skey, read and 186 * write and are used for accelerated address lookup (formerly AEA). 187 */ 188 189 /* Structure for Dynamic Address Translation */ 190 typedef struct _DAT { 191 RADR raddr; /* Real address */ 192 RADR aaddr; /* Absolute address */ 193 RADR rpfra; /* Real page frame address */ 194 RADR asd; /* Address space designator: */ 195 /* STD or ASCE */ 196 int stid; /* Address space indicator */ 197 BYTE *storkey; /* ->Storage key */ 198 U16 xcode; /* Translation exception code*/ 199 u_int private:1, /* 1=Private address space */ 200 protect:2; /* 1=Page prot, 2=ALE prot */ 201 } DAT; 202 203 /* Bit definitions for control register 0 */ 204 #define CR0_MCX_AUTH 0x0001000000000000 /* Measurement Counter 205 Extraction Authority */ 206 #define CR0_BMPX 0x80000000 /* Block multiplex ctl S/370*/ 207 #define CR0_SSM_SUPP 0x40000000 /* SSM suppression control */ 208 #define CR0_TOD_SYNC 0x20000000 /* TOD clock sync control */ 209 #define CR0_LOW_PROT 0x10000000 /* Low-address protection */ 210 #define CR0_EXT_AUTH 0x08000000 /* Extraction auth control */ 211 #define CR0_SEC_SPACE 0x04000000 /* Secondary space control */ 212 #define CR0_FETCH_OVRD 0x02000000 /* Fetch protection override */ 213 #define CR0_STORE_OVRD 0x01000000 /* Store protection override */ 214 #define CR0_STORKEY_4K 0x01000000 /* Storkey exception control */ 215 #define CR0_TRAN_FMT 0x00F80000 /* Translation format bits...*/ 216 #define CR0_TRAN_ESA390 0x00B00000 /* ...1M/4K ESA/390 format */ 217 #define CR0_PAGE_SIZE 0x00C00000 /* Page size for S/370... */ 218 #define CR0_PAGE_SZ_2K 0x00400000 /* ...2K pages */ 219 #define CR0_PAGE_SZ_4K 0x00800000 /* ...4K pages */ 220 #define CR0_ED 0x00800000 /* Enhanced DAT enable ESAME*/ 221 #define CR0_SEG_SIZE 0x00380000 /* Segment size for S/370... */ 222 #define CR0_SEG_SZ_64K 0x00000000 /* ...64K segments */ 223 #define CR0_SEG_SZ_1M 0x00100000 /* ...1M segments */ 224 #define CR0_ASN_LX_REUS 0x00080000 /* ASN-and-LX-reuse control */ 225 #define CR0_AFP 0x00040000 /* AFP register control */ 226 #define CR0_VOP 0x00020000 /* Vector control 390*/ 227 #define CR0_ASF 0x00010000 /* AS function control 390*/ 228 #define CR0_XM_MALFALT 0x00008000 /* Malfunction alert mask */ 229 #define CR0_XM_EMERSIG 0x00004000 /* Emergency signal mask */ 230 #define CR0_XM_EXTCALL 0x00002000 /* External call mask */ 231 #define CR0_XM_TODSYNC 0x00001000 /* TOD clock sync mask */ 232 #define CR0_XM_CLKC 0x00000800 /* Clock comparator mask */ 233 #define CR0_XM_PTIMER 0x00000400 /* CPU timer mask */ 234 #define CR0_XM_SERVSIG 0x00000200 /* Service signal mask */ 235 #define CR0_XM_ITIMER 0x00000080 /* Interval timer mask S/370*/ 236 #define CR0_XM_INTKEY 0x00000040 /* Interrupt key mask */ 237 #define CR0_XM_EXTSIG 0x00000020 /* External signal mask S/370*/ 238 #define CR0_XM_MALERT 0x00000020 /* Measurement alert mask */ 239 #define CR0_XM_ETR 0x00000010 /* External timer mask */ 240 #define CR0_PC_FAST 0x00000008 /* PC fast control 390*/ 241 #define CR0_CRYPTO 0x00000004 /* Crypto control ESAME*/ 242 #define CR0_IUCV 0x00000002 /* IUCV interrupt mask */ 243 244 #define SERVSIG_PEND 0x00000001 /* Event buffer pending */ 245 #define SERVSIG_ADDR 0xFFFFFFF8 /* Parameter address */ 246 247 /* Bit definitions for control register 1 */ 248 /* CR1 is the primary segment table descriptor or primary ASCE */ 249 250 /* Bit definitions for control register 2 */ 251 #define CR2_DUCTO 0x7FFFFFC0 /* DUCT origin */ 252 /* For S/370, CR2 contains channel masks for channels 0-31 */ 253 254 /* Bit definitions for control register 3 */ 255 #define CR3_SASTEIN 0xFFFFFFFF00000000ULL /* SASN STE instance# */ 256 #define CR3_KEYMASK 0xFFFF0000 /* PSW key mask */ 257 #define CR3_SASN 0x0000FFFF /* Secondary ASN */ 258 259 /* Bit definitions for control register 4 */ 260 #define CR4_PASTEIN 0xFFFFFFFF00000000ULL /* PASN STE instance# */ 261 #define CR4_AX 0xFFFF0000 /* Authorization index */ 262 #define CR4_PASN 0x0000FFFF /* Primary ASN */ 263 264 /* Bit definitions for control register 5 */ 265 /* When CR0_ASF=0 (ESA/390): */ 266 #define CR5_SSLINK 0x80000000 /* Subsystem-Linkage control */ 267 #define CR5_LTO 0x7FFFFF80 /* Linkage-Table origin */ 268 #define CR5_LTL 0x0000007F /* Linkage-Table length */ 269 /* When CR0_ASF=1 or ESAME: */ 270 #define CR5_PASTEO 0x7FFFFFC0 /* Primary-ASTE origin */ 271 272 /* Bit definitions for control register 6 */ 273 /* CR6 is the I/O interruption subclass mask */ 274 275 /* Bit definitions for control register 7 */ 276 /* CR7 is the secondary segment table descriptor or secondary ASCE */ 277 278 /* Bit definitions for control register 8 */ 279 #define CR8_ENHMCMASK 0x0000FFFF00000000ULL /* Enh Monitor masks */ 280 #define CR8_EAX 0xFFFF0000 /* Extended auth index */ 281 #define CR8_MCMASK 0x0000FFFF /* Monitor masks */ 282 283 /* Bit definitions for PER */ 284 #define CR9_SB 0x80000000 /* Successful Branching */ 285 #define CR9_IF 0x40000000 /* Instruction Fetch */ 286 #define CR9_SA 0x20000000 /* Storage Alteration */ 287 #define CR9_GRA 0x10000000 /* General Register Alt. */ 288 #define CR9_STURA 0x08000000 /* Store using real addr */ 289 #define CR9_IFNUL 0x01000000 /* IF nullification @PER3*/ 290 #define CR9_GRMASK 0x0000FFFF /* GR mask bits */ 291 #define CR9_BAC 0x00800000 /* Br addr control PER2 only */ 292 #define CR9_SAC 0x00200000 /* Stor. alter. c. PER2 only */ 293 294 /* Bit definitions for control register 12 */ 295 #define S_CR12_BRTRACE 0x80000000 /* Branch trace control */ 296 #define Z_CR12_BRTRACE 0x8000000000000000ULL /* Branch trace control*/ 297 #define CR12_MTRACE 0x4000000000000000ULL /* Mode trace control */ 298 #define S_CR12_TRACEEA 0x7FFFFFFC /* Trace entry address */ 299 #define Z_CR12_TRACEEA 0x3FFFFFFFFFFFFFFCULL /* Trace entry address */ 300 #define CR12_ASNTRACE 0x00000002 /* ASN trace control */ 301 #define CR12_EXTRACE 0x00000001 /* Explicit trace control */ 302 303 /* Bit definitions for control register 13 */ 304 /* CR13 is the home segment table descriptor or home ASCE */ 305 306 /* Bit definitions for control register 14 */ 307 #define CR14_CHKSTOP 0x80000000 /* Check-stop control S/370*/ 308 #define CR14_SYNCMCEL 0x40000000 /* Synchronous MCEL S/370*/ 309 #define CR14_IOEXTLOG 0x20000000 /* I/O extended logout S/370*/ 310 #define CR14_CHANRPT 0x10000000 /* Channel report mask */ 311 #define CR14_RCVYRPT 0x08000000 /* Recovery report mask */ 312 #define CR14_DGRDRPT 0x04000000 /* Degradation report mask */ 313 #define CR14_XDMGRPT 0x02000000 /* External damage mask */ 314 #define CR14_WARNING 0x01000000 /* Warning mask */ 315 #define CR14_ASYNMCEL 0x00800000 /* Asynchronous MCEL S/370*/ 316 #define CR14_ASYNFIXL 0x00400000 /* Asynch fixed log S/370*/ 317 #define CR14_TODCTLOV 0x00200000 /* TOD clock control override*/ 318 #define CR14_ASN_TRAN 0x00080000 /* ASN translation control */ 319 #define CR14_AFTO 0x0007FFFF /* ASN first table origin */ 320 321 /* Bit definitions for control register 15 */ 322 #define CR15_LSEA_390 0x7FFFFFF8 /* Linkage stack address 390*/ 323 #define CR15_LSEA_900 0xFFFFFFFFFFFFFFF8ULL /* Linkage stack ESAME*/ 324 #define CR15_MCEL 0x00FFFFF8 /* MCEL address S/370*/ 325 326 /* Linkage table designation bit definitions */ 327 #define LTD_SSLINK 0x80000000 /* Subsystem-Linkage control */ 328 #define LTD_LTO 0x7FFFFF80 /* Linkage-Table origin */ 329 #define LTD_LTL 0x0000007F /* Linkage-Table length */ 330 331 /* Linkage first table designation bit definitions (ASN-and-LX-reuse)*/ 332 #define LFTD_SSLINK 0x80000000 /* Subsystem-Linkage control */ 333 #define LFTD_LFTO 0x7FFFFF00 /* Linkage-First-Table origin*/ 334 #define LFTD_LFTL 0x000000FF /* Linkage-First-Table length*/ 335 336 /* Values for designation type and table type (ESAME mode) */ 337 #define TT_R1TABL 0xC /* Region first table */ 338 #define TT_R2TABL 0x8 /* Region second table */ 339 #define TT_R3TABL 0x4 /* Region third table */ 340 #define TT_SEGTAB 0x0 /* Segment table */ 341 342 /* Address space control element bit definitions (ESAME mode) */ 343 #define ASCE_TO 0xFFFFFFFFFFFFF000ULL /* Table origin */ 344 #define ASCE_G 0x200 /* Subspace group indicator */ 345 #define ASCE_P 0x100 /* Private space indicator */ 346 #define ASCE_S 0x080 /* Storage alteration event */ 347 #define ASCE_X 0x040 /* Space switch event */ 348 #define ASCE_R 0x020 /* Real space */ 349 #define ASCE_DT 0x00C /* Designation type */ 350 #define ASCE_TL 0x003 /* Table length */ 351 #define ASCE_RESV 0xC10 /* Reserved bits - ignored */ 352 353 /* Region table entry bit definitions (ESAME mode) */ 354 #define REGTAB_TO 0xFFFFFFFFFFFFF000ULL /* Table origin */ 355 #define REGTAB_RFAA 0xFFFFFFFF80000000ULL /* Region addr EDAT2*/ 356 #define REGTAB_AV 0x10000 /* ACCF validity bit EDAT2*/ 357 #define REGTAB_ACC 0xF000 /* Access control bits EDAT2*/ 358 #define REGTAB_F 0x800 /* Fetch protect bit EDAT2*/ 359 #define REGTAB_FC 0x400 /* Format control bit EDAT2*/ 360 #define REGTAB_P 0x200 /* DAT Protection bit EDAT*/ 361 #define REGTAB_CO 0x100 /* Change override bit EDAT2*/ 362 #define REGTAB_TF 0x0C0 /* Table offset */ 363 #define REGTAB_I 0x020 /* Region invalid */ 364 #define REGTAB_CR 0x010 /* Common region bit EDAT2*/ 365 #define REGTAB_TT 0x00C /* Table type */ 366 #define REGTAB_TL 0x003 /* Table length */ 367 #define REGTAB_RESV 0xD10 /* Reserved bits - ignored */ 368 369 /* Segment table entry bit definitions (ESAME mode) */ 370 #define ZSEGTAB_PTO 0xFFFFFFFFFFFFF800ULL /* Page table origin */ 371 #define ZSEGTAB_SFAA 0xFFFFFFFFFFF00000ULL /* Seg Fr Abs Addr EDAT*/ 372 #define ZSEGTAB_AV 0x10000 /* ACCF Validity Control EDAT*/ 373 #define ZSEGTAB_ACC 0x0F000 /* Access Control Bits EDAT*/ 374 #define ZSEGTAB_F 0x800 /* Fetch Protection EDAT*/ 375 #define ZSEGTAB_FC 0x400 /* Format control EDAT*/ 376 #define ZSEGTAB_P 0x200 /* Page protection bit */ 377 #define ZSEGTAB_CO 0x100 /* Change-rec override EDAT*/ 378 #define ZSEGTAB_I 0x020 /* Invalid segment */ 379 #define ZSEGTAB_C 0x010 /* Common segment */ 380 #define ZSEGTAB_TT 0x00C /* Table type */ 381 #define ZSEGTAB_RESV 0x0C3 /* Reserved bits - ignored */ 382 383 /* Page table entry bit definitions (ESAME mode) */ 384 #define ZPGETAB_PFRA 0xFFFFFFFFFFFFF000ULL /* Page frame real addr*/ 385 #define ZPGETAB_I 0x400 /* Invalid page */ 386 #define ZPGETAB_P 0x200 /* Protected page */ 387 #define ZPGETAB_ESVALID 0x100 /* Valid in expanded storage */ 388 #define ZPGETAB_CO 0x100 /* Change-rec override EDAT*/ 389 #define ZPGETAB_ESREF 0x080 /* ES Referenced */ 390 #define ZPGETAB_ESCHA 0x040 /* ES Changed */ 391 #define ZPGETAB_ESLCK 0x020 /* ES Locked */ 392 #define ZPGETAB_RESV 0x800 /* Reserved bits - must be 0 */ 393 394 /* Segment table designation bit definitions (ESA/390 mode) */ 395 #define STD_SSEVENT 0x80000000 /* Space switch event */ 396 #define STD_STO 0x7FFFF000 /* Segment table origin */ 397 #define STD_RESV 0x00000C00 /* Reserved bits - must be 0 */ 398 #define STD_GROUP 0x00000200 /* Subspace group indicator */ 399 #define STD_PRIVATE 0x00000100 /* Private space indicator */ 400 #define STD_SAEVENT 0x00000080 /* Storage alteration event */ 401 #define STD_STL 0x0000007F /* Segment table length */ 402 403 /* Segment table entry bit definitions (ESA/390 mode) */ 404 #define SEGTAB_PTO 0x7FFFFFC0 /* Page table origin */ 405 #define SEGTAB_INVALID 0x00000020 /* Invalid segment */ 406 #define SEGTAB_COMMON 0x00000010 /* Common segment */ 407 #define SEGTAB_PTL 0x0000000F /* Page table length */ 408 #define SEGTAB_RESV 0x80000000 /* Reserved bits - must be 0 */ 409 410 /* Page table entry bit definitions (ESA/390 mode) */ 411 #define PAGETAB_PFRA 0x7FFFF000 /* Page frame real address */ 412 #define PAGETAB_ESNK 0x00000800 /* ES NK bit */ 413 #define PAGETAB_INVALID 0x00000400 /* Invalid page */ 414 #define PAGETAB_PROT 0x00000200 /* Protected page */ 415 #define PAGETAB_ESVALID 0x00000100 /* Valid in expanded storage */ 416 #define PAGETAB_ESREF 0x00000004 /* ES Referenced */ 417 #define PAGETAB_ESCHA 0x00000002 /* ES Changed */ 418 #define PAGETAB_PGLOCK 0x00000001 /* Page lock (LKPG) */ 419 #define PAGETAB_RESV 0x80000900 /* Reserved bits - must be 0 */ 420 421 /* Segment table designation bit definitions (S/370 mode) */ 422 #define STD_370_STL 0xFF000000 /* 370 segment table length */ 423 #define STD_370_STO 0x00FFFFC0 /* 370 segment table origin */ 424 #define STD_370_SSEVENT 0x00000001 /* 370 space switch event */ 425 426 /* Segment table entry bit definitions (S/370 mode) */ 427 #define SEGTAB_370_PTL 0xF0000000 /* Page table length */ 428 #define SEGTAB_370_PTO 0x00FFFFF8 /* Page table origin */ 429 #define SEGTAB_370_PROT 0x00000004 /* Protected segment */ 430 #define SEGTAB_370_CMN 0x00000002 /* Common segment */ 431 #define SEGTAB_370_INVL 0x00000001 /* Invalid segment */ 432 #define SEGTAB_370_RSV 0x0F000000 /* Reserved bits - must be 0 */ 433 434 /* Page table entry bit definitions (S/370 mode) */ 435 #define PAGETAB_PFRA_4K 0xFFF0 /* Page frame real address */ 436 #define PAGETAB_INV_4K 0x0008 /* Invalid page */ 437 #define PAGETAB_EA_4K 0x0006 /* Extended physical address */ 438 #define PAGETAB_PFRA_2K 0xFFF8 /* Page frame real address */ 439 #define PAGETAB_INV_2K 0x0004 /* Invalid page */ 440 #define PAGETAB_RSV_2K 0x0002 /* Reserved bit - must be 0 */ 441 442 /* Access-list entry token special value definitions */ 443 #define ALET_PRIMARY 0 /* Primary address-space */ 444 #define ALET_SECONDARY 1 /* Secondary address-space */ 445 #define ALET_HOME 2 /* Home address-space */ 446 447 /* Access-list entry token bit definitions */ 448 #define ALET_RESV 0xFE000000 /* Reserved bits - must be 0 */ 449 #define ALET_PRI_LIST 0x01000000 /* Primary space access-list */ 450 #define ALET_ALESN 0x00FF0000 /* ALE sequence number */ 451 #define ALET_ALEN 0x0000FFFF /* Access-list entry number */ 452 453 /* Access-list designation bit definitions */ 454 #if FEATURE_ALD_FORMAT == 0 || defined(_900) 455 #define ALD_ALO 0x7FFFFF80 /* Access-list origin (fmt0) */ 456 #define ALD_ALL 0x0000007F /* Access-list length (fmt0) */ 457 #define ALD_ALL_SHIFT 3 /* Length units are 2**3 */ 458 #else 459 #define ALD_ALO 0x7FFFFF00 /* Access-list origin (fmt1) */ 460 #define ALD_ALL 0x000000FF /* Access-list length (fmt1) */ 461 #define ALD_ALL_SHIFT 4 /* Length units are 2**4 */ 462 #endif 463 464 /* Access-list entry bit definitions */ 465 #define ALE0_INVALID 0x80000000 /* ALEN invalid */ 466 #define ALE0_FETCHONLY 0x02000000 /* Fetch only address space */ 467 #define ALE0_PRIVATE 0x01000000 /* Private address space */ 468 #define ALE0_ALESN 0x00FF0000 /* ALE sequence number */ 469 #define ALE0_ALEAX 0x0000FFFF /* ALE authorization index */ 470 #define ALE2_ASTE 0x7FFFFFC0 /* ASTE address */ 471 #define ALE3_ASTESN 0xFFFFFFFF /* ASTE sequence number */ 472 473 /* Address-space number (ASN) bit definitions */ 474 #define ASN_AFX 0xFFC0 /* ASN first table index */ 475 #define ASN_ASX 0x003F /* ASN second table index */ 476 477 /* ASN first table entry bit definitions */ 478 #define AFTE_INVALID 0x80000000 /* ASN invalid */ 479 #define AFTE_ASTO_0 0x7FFFFFF0 /* ASTE origin (CR0_ASF=0) */ 480 #define AFTE_RESV_0 0x0000000F /* Reserved bits (CR0_ASF=0) */ 481 #define AFTE_ASTO_1 0x7FFFFFC0 /* ASTE origin (CR0_ASF=1) */ 482 #define AFTE_RESV_1 0x0000003F /* Reserved bits (CR0_ASF=1) */ 483 484 /* ASN second table entry bit definitions */ 485 #define ASTE0_INVALID 0x80000000 /* ASX invalid */ 486 #define ASTE0_ATO 0x7FFFFFFC /* Authority-table origin */ 487 #define ASTE0_RESV 0x00000002 /* Must be 0 for ESA/390 */ 488 #define ASTE0_BASE 0x00000001 /* Base space of group */ 489 #define ASTE1_AX 0xFFFF0000 /* Authorization index */ 490 #define ASTE1_ATL 0x0000FFF0 /* Authority-table length */ 491 #define ASTE1_RESV 0x0000000F /* Must be 0 for ESA/390 */ 492 #define ASTE1_CA 0x00000002 /* Controlled ASN */ 493 #define ASTE1_RA 0x00000001 /* Reusable ASN */ 494 /* ASTE word 2 is the segment table designation for ESA/390 */ 495 /* ASTE word 3 is the linkage-table designation for ESA/390 */ 496 /* ASTE words 2 and 3 are the ASCE (RTD, STD, or RSD) for ESAME */ 497 /* ASTE word 4 is the access-list designation */ 498 #define ASTE5_ASTESN 0xFFFFFFFF /* ASTE sequence number */ 499 #define ASTE6_RESV 0xFFFFFFFF /* Must be zero for ESA/390 */ 500 /* ASTE word 6 is the LTD or LFTD for ESAME */ 501 /* ASTE words 7-9 are reserved for control program use */ 502 /* ASTE word 10 is unused */ 503 #define ASTE11_ASTEIN 0xFFFFFFFF /* ASTE instance number */ 504 /* ASTE words 12-15 are unused */ 505 506 /* Authority table entry bit definitions */ 507 #define ATE_PRIMARY 0x80 /* Primary authority bit */ 508 #define ATE_SECONDARY 0x40 /* Secondary authority bit */ 509 510 /* Dispatchable unit control table bit definitions */ 511 #define DUCT0_BASTEO 0x7FFFFFC0 /* Base ASTE origin */ 512 #define DUCT1_SA 0x80000000 /* Subspace active */ 513 #define DUCT1_SSASTEO 0x7FFFFFC0 /* Subspace ASTE origin */ 514 /* DUCT word 2 is unused */ 515 #define DUCT3_SSASTESN 0xFFFFFFFF /* Subspace ASTE seq number */ 516 /* DUCT word 4 is the access-list designation */ 517 /* DUCT word 5 is unused for ESA/390 */ 518 /* DUCT word 5 contains PKM/KEY/RA/PROB for ESAME */ 519 /* DUCT word 6 is unused */ 520 /* DUCT word 7 is for control program use */ 521 /* DUCT words 8 and 9 are the return address for ESAME. In 24-bit and 522 31-bit mode, word 8 contains zero and word 9 contains AM31/IA31 */ 523 /* DUCT word 8 contains AM31/IA31 for ESA/390 */ 524 /* DUCT word 9 contains PKM/KEY/RA/PROB for ESA/390 */ 525 /* DUCT word 10 is unused */ 526 #define DUCT11_TCBA 0x7FFFFFF8 /* Trap control block address*/ 527 #define DUCT11_TE 0x00000001 /* Trap enabled */ 528 /* DUCT word 12 is unused */ 529 /* DUCT word 13 is unused */ 530 /* DUCT word 14 is unused */ 531 /* DUCT word 15 is unused */ 532 /* Bit definitions for DUCT word 5 (ESAME) or word 9 (ESA/390) */ 533 #define DUCT_PKM 0xFFFF0000 /* PSW key mask */ 534 #define DUCT_KEY 0x000000F0 /* PSW key */ 535 #define DUCT_RA 0x00000008 /* Reduced authority state */ 536 #define DUCT_PROB 0x00000001 /* Problem state */ 537 /* Bit definitions for DUCT word 9 (ESAME) or word 8 (ESA/390) */ 538 #define DUCT_AM31 0x80000000 /* 1=31-bit, 0=24-bit address*/ 539 #define DUCT_IA31 0x7FFFFFFF /* 24/31 return address */ 540 541 #define TCB0_P 0x00040000 /* Bit 13 PSW Control (P) */ 542 #define TCB0_R 0x00020000 /* Bit 14 GR Control (R) */ 543 544 #define TRAP0_EXECUTE 0x80000000 /* TRAP is target of execute */ 545 #define TRAP0_TRAP4 0x40000000 /* TRAP is TRAP4 */ 546 547 /* Linkage stack entry descriptor structure definition */ 548 typedef struct _LSED { 549 BYTE uet; /* U-bit and entry type */ 550 BYTE si; /* Section identification */ 551 HWORD rfs; /* Remaining free space */ 552 HWORD nes; /* Next entry size */ 553 HWORD resv; /* Reserved bits - must be 0 */ 554 } LSED; 555 556 /* Stack type definitions */ 557 #define LSED_UET_U 0x80 /* Unstack suppression bit */ 558 #define LSED_UET_ET 0x7F /* Entry type... */ 559 560 #define S_LSED_UET_HDR 0x01 /* ...header entry */ 561 #define S_LSED_UET_TLR 0x02 /* ...trailer entry */ 562 #define S_LSED_UET_BAKR 0x04 /* ...branch state entry */ 563 #define S_LSED_UET_PC 0x05 /* ...call state entry */ 564 565 #define Z_LSED_UET_HDR 0x09 /* ...header entry */ 566 #define Z_LSED_UET_TLR 0x0A /* ...trailer entry */ 567 #define Z_LSED_UET_BAKR 0x0C /* ...branch state entry */ 568 #define Z_LSED_UET_PC 0x0D /* ...call state entry */ 569 570 /* Program call number bit definitions */ 571 #define PC_LFX1 0xFFF00000 /* Linkage first index (high)*/ 572 #define PC_BIT44 0x00080000 /* 1=LFX1 is significant */ 573 #define PC_LFX2 0x0007E000 /* Linkage first index (low) */ 574 #define PC_LSX 0x00001F00 /* Linkage second index */ 575 #define PC_LX 0x000FFF00 /* Linkage index */ 576 #define PC_EX 0x000000FF /* Entry index */ 577 578 /* Linkage table entry bit definitions */ 579 #define LTE_INVALID 0x80000000 /* LX invalid */ 580 #define LTE_ETO 0x7FFFFFC0 /* Entry table origin */ 581 #define LTE_ETL 0x0000003F /* Entry table length */ 582 583 /* Linkage first table entry bit definitions (ASN-and-LX-reuse) */ 584 #define LFTE_INVALID 0x80000000 /* LFX invalid */ 585 #define LFTE_LSTO 0x7FFFFF00 /* Linkage second table orig */ 586 587 /* Linkage second table entry bit definitions (ASN-and-LX-reuse) */ 588 #define LSTE0_INVALID 0x80000000 /* LSX invalid */ 589 #define LSTE0_ETO 0x7FFFFFC0 /* Entry table origin */ 590 #define LSTE0_ETL 0x0000003F /* Entry table length */ 591 #define LSTE1_LSTESN 0xFFFFFFFF /* LSTE sequence number */ 592 593 /* Entry table bit entry definitions */ 594 /* ETE word 0 is the left half of the EIA for ESAME if ETE4_G is set */ 595 #define ETE0_AKM 0xFFFF0000 /* Authorization key mask 390*/ 596 #define ETE0_ASN 0x0000FFFF /* Address space number 390*/ 597 #define ETE1_AMODE 0x80000000 /* Addressing mode */ 598 #define ETE1_EIA 0x7FFFFFFE /* Instruction address */ 599 #define ETE1_PROB 0x00000001 /* Problem state bit */ 600 /* ETE word 2 is the entry parameter for ESA/390 */ 601 #define ETE2_AKM 0xFFFF0000 /* Auth.key mask ESAME*/ 602 #define ETE2_ASN 0x0000FFFF /* Address space number ESAME*/ 603 #define ETE3_EKM 0xFFFF0000 /* Entry key mask */ 604 #define ETE4_T 0x80000000 /* 0=Basic PC, 1=Stacking PC */ 605 #define ETE4_G 0x40000000 /* 1=64-bit EIA/EPARM ESAME*/ 606 #define ETE4_K 0x10000000 /* 1=Replace PSW key by EK */ 607 #define ETE4_M 0x08000000 /* 1=Replace PKM by EKM, 0=or*/ 608 #define ETE4_E 0x04000000 /* 1=Replace EAX by EEAX */ 609 #define ETE4_C 0x02000000 /* 0=Primary mode, 1=AR mode */ 610 #define ETE4_S 0x01000000 /* SASN:0=old PASN,1=new PASN*/ 611 #define ETE4_EK 0x00F00000 /* Entry key */ 612 #define ETE4_EEAX 0x0000FFFF /* Entry extended AX */ 613 #define ETE5_ASTE 0x7FFFFFC0 /* ASTE address */ 614 /* ETE words 6 and 7 are unused for ESA/390 */ 615 /* ETE words 6 and 7 are the entry parameter for ESAME */ 616 617 /* Clock states */ 618 #define CC_CLOCK_SET 0 /* Clock in set state */ 619 #define CC_CLOCK_NOTSET 1 /* Clock in not-set state */ 620 #define CC_CLOCK_ERROR 2 /* Clock in error state */ 621 #define CC_CLOCK_STOP 3 /* Clock in stopped state or 622 not-operational state */ 623 624 /* SIGP order codes */ 625 #define SIGP_SENSE 0x01 /* Sense */ 626 #define SIGP_EXTCALL 0x02 /* External call */ 627 #define SIGP_EMERGENCY 0x03 /* Emergency signal */ 628 #define SIGP_START 0x04 /* Start */ 629 #define SIGP_STOP 0x05 /* Stop */ 630 #define SIGP_RESTART 0x06 /* Restart */ 631 #define SIGP_IPR 0x07 /* Initial program reset 370*/ 632 #define SIGP_PR 0x08 /* Program reset 370*/ 633 #define SIGP_STOPSTORE 0x09 /* Stop and store status */ 634 #define SIGP_IMPL 0x0A /* Initial uprogram load 370*/ 635 #define SIGP_INITRESET 0x0B /* Initial CPU reset */ 636 #define SIGP_RESET 0x0C /* CPU reset */ 637 #define SIGP_SETPREFIX 0x0D /* Set prefix */ 638 #define SIGP_STORE 0x0E /* Store status at address */ 639 #define SIGP_STOREX 0x11 /* Store ext stat at addr 390*/ 640 #define SIGP_SETARCH 0x12 /* Set architecture mode */ 641 #define SIGP_COND_EMERGENCY 0x13 /* Conditional Emergency */ 642 #define SIGP_SENSE_RUNNING_STATE 0x15 /* Sense Running State */ 643 644 #define MAX_SIGPORDER 0x15 /* Maximum SIGP order value */ 645 #define LOG_SIGPORDER 0x03 /* Log any SIGP > this value */ 646 647 /* SIGP status codes */ 648 #define SIGP_STATUS_EQUIPMENT_CHECK 0x80000000 649 #define SIGP_STATUS_NOT_RUNNING 0x00000400 650 #define SIGP_STATUS_INCORRECT_STATE 0x00000200 651 #define SIGP_STATUS_INVALID_PARAMETER 0x00000100 652 #define SIGP_STATUS_EXTERNAL_CALL_PENDING 0x00000080 653 #define SIGP_STATUS_STOPPED 0x00000040 654 #define SIGP_STATUS_OPERATOR_INTERVENING 0x00000020 655 #define SIGP_STATUS_CHECK_STOP 0x00000010 656 #define SIGP_STATUS_INOPERATIVE 0x00000004 657 #define SIGP_STATUS_INVALID_ORDER 0x00000002 658 #define SIGP_STATUS_RECEIVER_CHECK 0x00000001 659 660 /* Storage key bit definitions */ 661 #define STORKEY_KEY 0xF0 /* Storage key */ 662 #define STORKEY_FETCH 0x08 /* Fetch protect bit */ 663 #define STORKEY_REF 0x04 /* Reference bit */ 664 #define STORKEY_CHANGE 0x02 /* Change bit */ 665 #define STORKEY_BADFRM 0x01 /* Unusable frame */ 666 667 /* Prefixed storage area structure definition */ 668 typedef struct _PSA_3XX { /* Prefixed storage area */ 669 /*000*/ DBLWRD iplpsw; /* IPL PSW, Restart new PSW */ 670 /*008*/ DBLWRD iplccw1; /* IPL CCW1, Restart old PSW */ 671 /*010*/ DBLWRD iplccw2; /* IPL CCW2 */ 672 /*018*/ DBLWRD extold; /* External old PSW */ 673 /*020*/ DBLWRD svcold; /* SVC old PSW */ 674 /*028*/ DBLWRD pgmold; /* Program check old PSW */ 675 /*030*/ DBLWRD mckold; /* Machine check old PSW */ 676 /*038*/ DBLWRD iopold; /* I/O old PSW */ 677 /*040*/ DBLWRD csw; /* Channel status word (S370)*/ 678 /*048*/ FWORD caw; /* Channel address word(S370)*/ 679 /*04C*/ FWORD resv04C; /* Reserved */ 680 /*050*/ FWORD inttimer; /* Interval timer */ 681 /*054*/ FWORD resv054; /* Reserved */ 682 /*058*/ DBLWRD extnew; /* External new PSW */ 683 /*060*/ DBLWRD svcnew; /* SVC new PSW */ 684 /*068*/ DBLWRD pgmnew; /* Program check new PSW */ 685 /*070*/ DBLWRD mcknew; /* Machine check new PSW */ 686 /*078*/ DBLWRD iopnew; /* I/O new PSW */ 687 /*080*/ FWORD extparm; /* External interrupt param */ 688 /*084*/ HWORD extcpad; /* External interrupt CPU# */ 689 /*086*/ HWORD extint; /* External interrupt code */ 690 /*088*/ FWORD svcint; /* SVC interrupt code */ 691 /*08C*/ FWORD pgmint; /* Program interrupt code */ 692 /*090*/ FWORD tea; /* Translation exception addr*/ 693 /*094*/ HWORD monclass; /* Monitor class */ 694 /*096*/ HWORD perint; /* PER interrupt code */ 695 /*098*/ FWORD peradr; /* PER address */ 696 /*09C*/ FWORD moncode; /* Monitor code */ 697 /*0A0*/ BYTE excarid; /* Exception access id */ 698 /*0A1*/ BYTE perarid; /* PER access id */ 699 /*0A2*/ BYTE opndrid; /* Operand access id */ 700 /*0A3*/ BYTE arch; /* Architecture mode ID */ 701 /*0A4*/ FWORD resv0A4; /* Reserved */ 702 /*0A8*/ FWORD chanid; /* Channel id (S370) */ 703 /*0AC*/ FWORD ioelptr; /* I/O extended logout (S370)*/ 704 /*0B0*/ FWORD lcl; /* Limited chan logout (S370)*/ 705 /*0B4*/ FWORD resv0B0; /* Reserved */ 706 /*0B8*/ FWORD ioid; /* I/O interrupt device id */ 707 /*0BC*/ FWORD ioparm; /* I/O interrupt parameter */ 708 /*0C0*/ FWORD iointid; /* I/O interrupt ID */ 709 /*0C4*/ FWORD resv0C4; /* Reserved */ 710 /*0C8*/ FWORD stfl; /* Facilities list (STFL) */ 711 /*0CC*/ FWORD resv0CC; /* Reserved */ 712 /*0D0*/ DBLWRD resv0D0; /* Reserved */ 713 /*0D8*/ DBLWRD storeptmr; /* CPU timer save area */ 714 /*0E0*/ DBLWRD storeclkc; /* Clock comparator save area*/ 715 /*0E8*/ DBLWRD mckint; /* Machine check int code */ 716 /*0F0*/ FWORD resv0F0; /* Reserved */ 717 /*0F4*/ FWORD xdmgcode; /* External damage code */ 718 /*0F8*/ FWORD mcstorad; /* Failing storage address */ 719 /*0FC*/ FWORD resv0FC; /* Reserved */ 720 /*100*/ DBLWRD storepsw; /* Store status PSW save area*/ 721 /*108*/ FWORD storepfx; /* Prefix register save area */ 722 /*10C*/ FWORD resv10C; /* Reserved */ 723 /*110*/ DBLWRD resv110; /* Reserved */ 724 /*118*/ DBLWRD resv118; /* Reserved */ 725 /*120*/ FWORD storear[16]; /* Access register save area */ 726 /*160*/ FWORD storefpr[8]; /* FP register save area */ 727 /*180*/ FWORD storegpr[16]; /* General register save area*/ 728 /*1C0*/ FWORD storecr[16]; /* Control register save area*/ 729 } PSA_3XX; 730 731 /* ESAME Prefixed storage area structure definition */ 732 typedef struct _PSA_900 { /* Prefixed storage area */ 733 /*0000*/ DBLWRD iplpsw; /* IPL PSW */ 734 /*0008*/ DBLWRD iplccw1; /* IPL CCW1 */ 735 /*0010*/ DBLWRD iplccw2; /* IPL CCW2 */ 736 /*0018*/ BYTE resv0018[104]; /* Reserved */ 737 /*0080*/ FWORD extparm; /* External interrupt param */ 738 /*0084*/ HWORD extcpad; /* External interrupt CPU# */ 739 /*0086*/ HWORD extint; /* External interrupt code */ 740 /*0088*/ FWORD svcint; /* SVC interrupt code */ 741 /*008C*/ FWORD pgmint; /* Program interrupt code */ 742 /*0090*/ FWORD dataexc; /* Data exception code */ 743 /*0094*/ HWORD monclass; /* Monitor class */ 744 /*0096*/ HWORD perint; /* PER interrupt code */ 745 /*0098*/ DBLWRD peradr; /* PER address */ 746 /*00A0*/ BYTE excarid; /* Exception access id */ 747 /*00A1*/ BYTE perarid; /* PER access id */ 748 /*00A2*/ BYTE opndrid; /* Operand access id */ 749 /*00A3*/ BYTE arch; /* Architecture mode ID */ 750 /*00A4*/ FWORD mpladdr; /* MPL addr */ 751 /*00A8*/ DWORD_U tea; /* Translation exception addr*/ 752 #define TEA_G tea.D 753 #define TEA_L tea.F.L.F 754 #define TEA_H tea.F.H.F 755 /*00B0*/ DBLWRD moncode; /* Monitor code */ 756 /*00B8*/ FWORD ioid; /* I/O interrupt subsys id */ 757 /*00BC*/ FWORD ioparm; /* I/O interrupt parameter */ 758 /*00C0*/ FWORD iointid; /* I/O interrupt ID */ 759 /*00C4*/ FWORD resv00C0; /* Reserved */ 760 /*00C8*/ FWORD stfl; /* Facilities list (STFL) */ 761 /*00CC*/ FWORD resv00CC; /* Reserved */ 762 /*00D0*/ DBLWRD resv00D0; /* Reserved */ 763 /*00D8*/ DBLWRD resv00D8; /* Reserved */ 764 /*00E0*/ DBLWRD resv00E0; /* Reserved */ 765 /*00E8*/ DBLWRD mckint; /* Machine check int code */ 766 /*00F0*/ FWORD mckext; /* Machine check int code ext*/ 767 /*00F4*/ FWORD xdmgcode; /* External damage code */ 768 /*00F8*/ DBLWRD mcstorad; /* Failing storage address */ 769 /*0100*/ DBLWRD cao; /* Enh Mon Counter Array Orig*/ 770 /*0108*/ FWORD cal; /* Enh Mon Counter Array Len */ 771 /*010C*/ FWORD ec; /* Enh Mon Exception Count */ 772 /*0110*/ DBLWRD bea; /* Breaking event address @Z9*/ 773 /*0118*/ DBLWRD resv0118; /* Reserved */ 774 /*0120*/ QWORD rstold; /* Restart old PSW */ 775 /*0130*/ QWORD extold; /* External old PSW */ 776 /*0140*/ QWORD svcold; /* SVC old PSW */ 777 /*0150*/ QWORD pgmold; /* Program check old PSW */ 778 /*0160*/ QWORD mckold; /* Machine check old PSW */ 779 /*0170*/ QWORD iopold; /* I/O old PSW */ 780 /*0180*/ BYTE resv0180[32]; /* Reserved */ 781 /*01A0*/ QWORD rstnew; /* Restart new PSW */ 782 /*01B0*/ QWORD extnew; /* External new PSW */ 783 /*01C0*/ QWORD svcnew; /* SVC new PSW */ 784 /*01D0*/ QWORD pgmnew; /* Program check new PSW */ 785 /*01E0*/ QWORD mcknew; /* Machine check new PSW */ 786 /*01F0*/ QWORD iopnew; /* I/O new PSW */ 787 /*0200*/ BYTE resv0200[4096]; /* Reserved */ 788 /*1200*/ FWORD storefpr[32]; /* FP register save area */ 789 /*1280*/ DBLWRD storegpr[16]; /* General register save area*/ 790 /*1300*/ QWORD storepsw; /* Store status PSW save area*/ 791 /*1310*/ DBLWRD resv1310; /* Reserved */ 792 /*1318*/ FWORD storepfx; /* Prefix register save area */ 793 /*131C*/ FWORD storefpc; /* FP control save area */ 794 /*1320*/ FWORD resv1320; /* Reserved */ 795 /*1324*/ FWORD storetpr; /* TOD prog reg save area */ 796 /*1328*/ DBLWRD storeptmr; /* CPU timer save area */ 797 /*1330*/ DBLWRD storeclkc; /* Clock comparator save area*/ 798 /*1338*/ DBLWRD resv1338; /* Reserved */ 799 /*1340*/ FWORD storear[16]; /* Access register save area */ 800 /*1380*/ DBLWRD storecr[16]; /* Control register save area*/ 801 } PSA_900; 802 803 /* Bit settings for translation exception address */ 804 #define TEA_SECADDR 0x80000000 /* Secondary addr (370,390) */ 805 #define TEA_FETCH 0x800 /* Fetch exception 810*/ 806 #define TEA_STORE 0x400 /* Store exception 810*/ 807 #define TEA_PROT_A 0x008 /* Access-list prot (ESAME) */ 808 #define TEA_PROT_AP 0x004 /* Access-list/page protected*/ 809 #define TEA_MVPG 0x004 /* MVPG exception (ESAME) */ 810 #define TEA_ST 0x003 /* Address space indication..*/ 811 #define TEA_ST_PRIMARY 0x000 /* ..primary STO/ASCE used */ 812 #define TEA_ST_ARMODE 0x001 /* ..access register mode */ 813 #define TEA_ST_SECNDRY 0x002 /* ..secondary STO/ASCE used */ 814 #define TEA_ST_HOME 0x003 /* ..home STO/ASCE used */ 815 #define TEA_SSEVENT 0x80000000 /* Space switch event bit */ 816 #define TEA_ASN 0x0000FFFF /* Address space number */ 817 #define TEA_PCN 0x000FFFFF /* Program call number */ 818 819 /* Bit settings for machine check interruption code */ 820 #define MCIC_SD 0x8000000000000000ULL /* System damage */ 821 #define MCIC_P 0x4000000000000000ULL /* Instruction proc damage */ 822 #define MCIC_SR 0x2000000000000000ULL /* System recovery */ 823 #define MCIC_CD 0x0800000000000000ULL /* Timing facility damage */ 824 #define MCIC_ED 0x0400000000000000ULL /* External damage */ 825 #define MCIC_VF 0x0200000000000000ULL /* Vector facility failure */ 826 #define MCIC_DG 0x0100000000000000ULL /* Degradation */ 827 828 #define MCIC_W 0x0080000000000000ULL /* Warning */ 829 #define MCIC_CP 0x0040000000000000ULL /* Channel report pending */ 830 #define MCIC_SP 0x0020000000000000ULL /* Service processor damage */ 831 #define MCIC_CK 0x0010000000000000ULL /* Channel subsystem damage */ 832 #define MCIC_VS 0x0004000000000000ULL /* Vector facility source */ 833 #define MCIC_B 0x0002000000000000ULL /* Backed up */ 834 835 #define MCIC_SE 0x0000800000000000ULL /* Storage error uncorrected */ 836 #define MCIC_SC 0x0000400000000000ULL /* Storage error corrected */ 837 #define MCIC_KE 0x0000200000000000ULL /* Storkey error uncorrected */ 838 #define MCIC_DS 0x0000100000000000ULL /* Storage degradation */ 839 #define MCIC_WP 0x0000080000000000ULL /* PSW-MWP validity */ 840 #define MCIC_MS 0x0000040000000000ULL /* PSW mask and key validity */ 841 #define MCIC_PM 0x0000020000000000ULL /* PSW pm and cc validity */ 842 #define MCIC_IA 0x0000010000000000ULL /* PSW ia validity */ 843 844 #define MCIC_FA 0x0000008000000000ULL /* Failing stor addr validity*/ 845 #define MCIC_EC 0x0000002000000000ULL /* External damage code val. */ 846 #define MCIC_FP 0x0000001000000000ULL /* Floating point reg val. */ 847 #define MCIC_GR 0x0000000800000000ULL /* General register validity */ 848 #define MCIC_CR 0x0000000400000000ULL /* Control register validity */ 849 #define MCIC_ST 0x0000000100000000ULL /* Storage logical validity */ 850 851 #define MCIC_IE 0x0000000080000000ULL /* Indirect storage error */ 852 #define MCIC_AR 0x0000000040000000ULL /* Access register validity */ 853 #define MCIC_DA 0x0000000020000000ULL /* Delayed access exeption */ 854 855 #define MCIC_PR 0x0000000000200000ULL /* TOD prog. reg. validity */ 856 #define MCIC_XF 0x0000000000100000ULL /* Extended float reg val. */ 857 #define MCIC_AP 0x0000000000080000ULL /* Ancillary report */ 858 #define MCIC_CT 0x0000000000020000ULL /* CPU timer validity */ 859 #define MCIC_CC 0x0000000000010000ULL /* Clock comparator validity */ 860 861 /* Channel Report Word definitions */ 862 #define CRW_SOL 0x40000000 /* Solicited CRW */ 863 #define CRW_OVER 0x20000000 /* Overflow, CRW's lost */ 864 #define CRW_CHAIN 0x10000000 /* More CRW's describe event */ 865 #define CRW_RSC 0x0F000000 /* Reporting resource mask */ 866 #define CRW_MONIT 0x02000000 /* Channel monitor is source */ 867 #define CRW_SUBCH 0x03000000 /* Subchannel is source */ 868 #define CRW_CHPID 0x04000000 /* Channel path is source */ 869 #define CRW_CAF 0x09000000 /* Configuration alert */ 870 #define CRW_CSS 0x0B000000 /* Channel subsys is source */ 871 #define CRW_AR 0x00800000 /* Ancillary report indicator*/ 872 #define CRW_ERC 0x003F0000 /* Error recovery code */ 873 #define CRW_AVAIL 0x00010000 /* Available */ 874 #define CRW_INIT 0x00020000 /* Initialized no parm. chg. */ 875 #define CRW_TEMP 0x00030000 /* Temporary error */ 876 #define CRW_ALERT 0x00040000 /* Installed, subch changed */ 877 #define CRW_TERM 0x00050000 /* Terminal */ 878 #define CRW_PERM 0x00060000 /* Permanent error / not init*/ 879 #define CRW_PERMI 0x00070000 /* Permanent, initialized */ 880 #define CRW_IPM 0x00080000 /* PIM / PAM / CHPIDs changed*/ 881 #define CRW_RSID 0x0000FFFF /* Resource identifier */ 882 883 /* Bit settings for channel id */ 884 #define CHANNEL_TYPE 0xF0000000 /* Bits 0-3=Channel type... */ 885 #define CHANNEL_SEL 0x00000000 /* ...selector channel */ 886 #define CHANNEL_MPX 0x10000000 /* ...byte multiplexor */ 887 #define CHANNEL_BMX 0x20000000 /* ...block multiplexor */ 888 #define CHANNEL_MODEL 0x0FFF0000 /* Bits 4-15=Channel model */ 889 #define CHANNEL_MAXIOEL 0x0000FFFF /* Bits 16-31=Max.IOEL length*/ 890 891 /* Program interruption codes */ 892 #define PGM_OPERATION_EXCEPTION 0x0001 893 #define PGM_PRIVILEGED_OPERATION_EXCEPTION 0x0002 894 #define PGM_EXECUTE_EXCEPTION 0x0003 895 #define PGM_PROTECTION_EXCEPTION 0x0004 896 #define PGM_ADDRESSING_EXCEPTION 0x0005 897 #define PGM_SPECIFICATION_EXCEPTION 0x0006 898 #define PGM_DATA_EXCEPTION 0x0007 899 #define PGM_FIXED_POINT_OVERFLOW_EXCEPTION 0x0008 900 #define PGM_FIXED_POINT_DIVIDE_EXCEPTION 0x0009 901 #define PGM_DECIMAL_OVERFLOW_EXCEPTION 0x000A 902 #define PGM_DECIMAL_DIVIDE_EXCEPTION 0x000B 903 #define PGM_EXPONENT_OVERFLOW_EXCEPTION 0x000C 904 #define PGM_EXPONENT_UNDERFLOW_EXCEPTION 0x000D 905 #define PGM_SIGNIFICANCE_EXCEPTION 0x000E 906 #define PGM_FLOATING_POINT_DIVIDE_EXCEPTION 0x000F 907 #define PGM_SEGMENT_TRANSLATION_EXCEPTION 0x0010 908 #define PGM_PAGE_TRANSLATION_EXCEPTION 0x0011 909 #define PGM_TRANSLATION_SPECIFICATION_EXCEPTION 0x0012 910 #define PGM_SPECIAL_OPERATION_EXCEPTION 0x0013 911 #define PGM_OPERAND_EXCEPTION 0x0015 912 #define PGM_TRACE_TABLE_EXCEPTION 0x0016 913 #define PGM_ASN_TRANSLATION_SPECIFICATION_EXCEPTION 0x0017 914 #define PGM_VECTOR_OPERATION_EXCEPTION 0x0019 915 #define PGM_SPACE_SWITCH_EVENT 0x001C 916 #define PGM_SQUARE_ROOT_EXCEPTION 0x001D 917 #define PGM_UNNORMALIZED_OPERAND_EXCEPTION 0x001E 918 #define PGM_PC_TRANSLATION_SPECIFICATION_EXCEPTION 0x001F 919 #define PGM_AFX_TRANSLATION_EXCEPTION 0x0020 920 #define PGM_ASX_TRANSLATION_EXCEPTION 0x0021 921 #define PGM_LX_TRANSLATION_EXCEPTION 0x0022 922 #define PGM_EX_TRANSLATION_EXCEPTION 0x0023 923 #define PGM_PRIMARY_AUTHORITY_EXCEPTION 0x0024 924 #define PGM_SECONDARY_AUTHORITY_EXCEPTION 0x0025 925 #define PGM_LFX_TRANSLATION_EXCEPTION 0x0026 926 #define PGM_LSX_TRANSLATION_EXCEPTION 0x0027 927 #define PGM_ALET_SPECIFICATION_EXCEPTION 0x0028 928 #define PGM_ALEN_TRANSLATION_EXCEPTION 0x0029 929 #define PGM_ALE_SEQUENCE_EXCEPTION 0x002A 930 #define PGM_ASTE_VALIDITY_EXCEPTION 0x002B 931 #define PGM_ASTE_SEQUENCE_EXCEPTION 0x002C 932 #define PGM_EXTENDED_AUTHORITY_EXCEPTION 0x002D 933 #define PGM_LSTE_SEQUENCE_EXCEPTION 0x002E 934 #define PGM_ASTE_INSTANCE_EXCEPTION 0x002F 935 #define PGM_STACK_FULL_EXCEPTION 0x0030 936 #define PGM_STACK_EMPTY_EXCEPTION 0x0031 937 #define PGM_STACK_SPECIFICATION_EXCEPTION 0x0032 938 #define PGM_STACK_TYPE_EXCEPTION 0x0033 939 #define PGM_STACK_OPERATION_EXCEPTION 0x0034 940 #define PGM_ASCE_TYPE_EXCEPTION 0x0038 941 #define PGM_REGION_FIRST_TRANSLATION_EXCEPTION 0x0039 942 #define PGM_REGION_SECOND_TRANSLATION_EXCEPTION 0x003A 943 #define PGM_REGION_THIRD_TRANSLATION_EXCEPTION 0x003B 944 #define PGM_MONITOR_EVENT 0x0040 945 #define PGM_PER_EVENT 0x0080 946 #define PGM_CRYPTO_OPERATION_EXCEPTION 0x0119 947 948 /* External interrupt codes */ 949 #define EXT_INTERRUPT_KEY_INTERRUPT 0x0040 950 #define EXT_INTERVAL_TIMER_INTERRUPT 0x0080 951 #define EXT_TOD_CLOCK_SYNC_CHECK_INTERRUPT 0x1003 952 #define EXT_CLOCK_COMPARATOR_INTERRUPT 0x1004 953 #define EXT_CPU_TIMER_INTERRUPT 0x1005 954 #define EXT_MALFUNCTION_ALERT_INTERRUPT 0x1200 955 #define EXT_EMERGENCY_SIGNAL_INTERRUPT 0x1201 956 #define EXT_EXTERNAL_CALL_INTERRUPT 0x1202 957 #define EXT_ETR_INTERRUPT 0x1406 958 #define EXT_MEASUREMENT_ALERT_INTERRUPT 0x1407 959 #define EXT_SERVICE_SIGNAL_INTERRUPT 0x2401 960 #define EXT_IUCV_INTERRUPT 0x4000 961 #if defined(FEATURE_ECPSVM) 962 #define EXT_VINTERVAL_TIMER_INTERRUPT 0x0100 963 #endif 964 #if defined(FEATURE_VM_BLOCKIO) 965 #define EXT_BLOCKIO_INTERRUPT 0x2603 966 #endif 967 968 /* Macros for classifying CCW operation codes */ 969 #define IS_CCW_WRITE(c) (((c)&0x03)==0x01) 970 #define IS_CCW_READ(c) (((c)&0x03)==0x02) 971 #define IS_CCW_CONTROL(c) (((c)&0x03)==0x03) 972 #define IS_CCW_NOP(c) ((c)==0x03) 973 #define IS_CCW_SENSE(c) (((c)&0x0F)==0x04) 974 #define IS_CCW_TIC(c) (((c)&0x0F)==0x08) 975 #define IS_CCW_RDBACK(c) (((c)&0x0F)==0x0C) 976 977 /* Operation request block structure definition */ 978 typedef struct _ORB { 979 FWORD intparm; /* Interruption parameter */ 980 BYTE flag4; /* Flag byte 4 */ 981 BYTE flag5; /* Flag byte 5 */ 982 BYTE lpm; /* Logical path mask */ 983 BYTE flag7; /* Flag byte 7 */ 984 FWORD ccwaddr; /* CCW address */ 985 } ORB; 986 987 /* Bit definitions for ORB flag byte 4 */ 988 #define ORB4_KEY 0xF0 /* Subchannel protection key */ 989 #define ORB4_S 0x08 /* Suspend control */ 990 #define ORB4_C 0x04 /* Streaming mode (FICON) */ 991 #define ORB4_M 0x02 /* Modification (FICON) */ 992 #define ORB4_Y 0x01 /* Synchronization (FICON) */ 993 994 /* Bit definitions for ORB flag byte 5 */ 995 #define ORB5_F 0x80 /* CCW format */ 996 #define ORB5_P 0x40 /* Prefetch */ 997 #define ORB5_I 0x20 /* Initial status interrupt */ 998 #define ORB5_A 0x10 /* Address limit checking */ 999 #define ORB5_U 0x08 /* Suppress susp interrupt */ 1000 #define ORB5_RESV 0x04 /* Reserved bit - must be 0 */ 1001 #define ORB5_H 0x02 /* Format-2 IDAW control */ 1002 #define ORB5_T 0x01 /* 2K format-2 IDAW control */ 1003 1004 /* Bit definitions for ORB flag byte 7 */ 1005 #define ORB7_L 0x80 /* Suppress incorrect length */ 1006 #define ORB7_D 0x40 /* MIDAW control @MW*/ 1007 #define ORB7_RESV 0x3E /* Reserved - must be 0 @MW*/ 1008 #define ORB7_X 0x01 /* ORB extension control */ 1009 1010 /* Path management control word structure definition */ 1011 typedef struct _PMCW { 1012 FWORD intparm; /* Interruption parameter */ 1013 BYTE flag4; /* Flag byte 4 */ 1014 BYTE flag5; /* Flag byte 5 */ 1015 HWORD devnum; /* Device number */ 1016 BYTE lpm; /* Logical path mask */ 1017 BYTE pnom; /* Path not operational mask */ 1018 BYTE lpum; /* Last path used mask */ 1019 BYTE pim; /* Path installed mask */ 1020 HWORD mbi; /* Measurement block index */ 1021 BYTE pom; /* Path operational mask */ 1022 BYTE pam; /* Path available mask */ 1023 BYTE chpid[8]; /* Channel path identifiers */ 1024 BYTE zone; /* SIE zone */ 1025 BYTE flag25; /* Flag byte 25 */ 1026 BYTE flag26; /* Reserved byte - must be 0 */ 1027 BYTE flag27; /* Flag byte 27 */ 1028 } PMCW; 1029 1030 /* Bit definitions for PMCW flag byte 4 */ 1031 #define PMCW4_Q 0x80 /* QDIO available */ 1032 #define PMCW4_ISC 0x38 /* Interruption subclass */ 1033 #define PMCW4_A 0x01 /* Alternate Block Control */ 1034 #define PMCW4_RESV 0x46 /* Reserved bits - must be 0 */ 1035 1036 /* Bit definitions for PMCW flag byte 5 */ 1037 #define PMCW5_E 0x80 /* Subchannel enabled */ 1038 #define PMCW5_LM 0x60 /* Limit mode... */ 1039 #define PMCW5_LM_NONE 0x00 /* ...no limit checking */ 1040 #define PMCW5_LM_LOW 0x20 /* ...lower limit specified */ 1041 #define PMCW5_LM_HIGH 0x40 /* ...upper limit specified */ 1042 #define PMCW5_LM_RESV 0x60 /* ...reserved value */ 1043 #define PMCW5_MM 0x18 /* Measurement mode enable...*/ 1044 #define PMCW5_MM_MBU 0x10 /* ...meas.block.upd enabled */ 1045 #define PMCW5_MM_DCTM 0x08 /* Dev.conn.time.meas enabled*/ 1046 #define PMCW5_D 0x04 /* Multipath mode enabled */ 1047 #define PMCW5_T 0x02 /* Timing facility available */ 1048 #define PMCW5_V 0x01 /* Subchannel valid */ 1049 1050 /* Bit definitions for PMCW flag byte 25 */ 1051 #define PMCW25_VISC 0x07 /* Guest ISC */ 1052 #define PMCW25_TYPE 0xE0 /* Subchannel Type */ 1053 #define PMCW25_TYPE_0 0x00 /* I/O Subchannel */ 1054 #define PMCW25_TYPE_1 0x20 /* CHSC subchannel */ 1055 #define PMCW25_TYPE_2 0x40 /* Message subchannel */ 1056 #define PMCW25_TYPE_3 0x60 /* ADM subchannel */ 1057 #define PMCW25_RESV 0x18 /* Reserved bits */ 1058 1059 1060 /* Bit definitions for PMCW flag byte 27 */ 1061 #define PMCW27_I 0x80 /* Interrupt Interlock Cntl */ 1062 #define PMCW27_S 0x01 /* Concurrent sense mode */ 1063 #define PMCW27_RESV 0x7E /* Reserved bits - must be 0 */ 1064 1065 /* Extended status word structure definition */ 1066 typedef struct _ESW { 1067 BYTE scl0; /* Subchannel logout byte 0 */ 1068 BYTE lpum; /* Last path used mask */ 1069 BYTE scl2; /* Subchannel logout byte 2 */ 1070 BYTE scl3; /* Subchannel logout byte 3 */ 1071 BYTE erw0; /* Extended report word byte0*/ 1072 BYTE erw1; /* Extended report word byte1*/ 1073 BYTE erw2; /* Extended report word byte2*/ 1074 BYTE erw3; /* Extended report word byte3*/ 1075 FWORD failaddr; /* Failing storage address */ 1076 FWORD resv2; /* Reserved word - must be 0 */ 1077 FWORD resv3; /* Reserved word - must be 0 */ 1078 } ESW; 1079 1080 /* Bit definitions for subchannel logout byte 0 */ 1081 #define SCL0_ESF 0x7F /* Extended status flags... */ 1082 #define SCL0_ESF_KEY 0x40 /* ...key check */ 1083 #define SCL0_ESF_MBPGK 0x20 /* ...meas.block prog.check */ 1084 #define SCL0_ESF_MBDCK 0x10 /* ...meas.block data check */ 1085 #define SCL0_ESF_MBPTK 0x08 /* ...meas.block prot.check */ 1086 #define SCL0_ESF_CCWCK 0x04 /* ...CCW check */ 1087 #define SCL0_ESF_IDACK 0x02 /* ...IDAW check */ 1088 1089 /* Bit definitions for subchannel logout byte 2 */ 1090 #define SCL2_R 0x80 /* Ancillary report bit */ 1091 #define SCL2_FVF 0x7C /* Field validity flags... */ 1092 #define SCL2_FVF_LPUM 0x40 /* ...LPUM valid */ 1093 #define SCL2_FVF_TC 0x20 /* ...termination code valid */ 1094 #define SCL2_FVF_SC 0x10 /* ...sequence code valid */ 1095 #define SCL2_FVF_USTAT 0x08 /* ...device status valid */ 1096 #define SCL2_FVF_CCWAD 0x04 /* ...CCW address valid */ 1097 #define SCL2_SA 0x03 /* Storage access code... */ 1098 #define SCL2_SA_UNK 0x00 /* ...access type unknown */ 1099 #define SCL2_SA_RD 0x01 /* ...read */ 1100 #define SCL2_SA_WRT 0x02 /* ...write */ 1101 #define SCL2_SA_RDBK 0x03 /* ...read backward */ 1102 1103 /* Bit definitions for subchannel logout byte 3 */ 1104 #define SCL3_TC 0xC0 /* Termination code... */ 1105 #define SCL3_TC_HALT 0x00 /* ...halt signal issued */ 1106 #define SCL3_TC_NORM 0x40 /* ...stop, stack, or normal */ 1107 #define SCL3_TC_CLEAR 0x80 /* ...clear signal issued */ 1108 #define SCL3_TC_RESV 0xC0 /* ...reserved */ 1109 #define SCL3_D 0x20 /* Device status check */ 1110 #define SCL3_E 0x10 /* Secondary error */ 1111 #define SCL3_A 0x08 /* I/O error alert */ 1112 #define SCL3_SC 0x07 /* Sequence code */ 1113 1114 /* Bit definitions for extended report word byte 0 */ 1115 #define ERW0_A 0x10 /* Authorization check */ 1116 #define ERW0_P 0x08 /* Path verification required*/ 1117 #define ERW0_T 0x04 /* Channel path timeout */ 1118 #define ERW0_F 0x02 /* Failing storage addr valid*/ 1119 #define ERW0_S 0x01 /* Concurrent sense */ 1120 1121 /* Bit definitions for extended report word byte 1 */ 1122 #define ERW1_SCNT 0x3F /* Concurrent sense count */ 1123 1124 /* Subchannel status word structure definition */ 1125 typedef struct _SCSW { 1126 BYTE flag0; /* Flag byte 0 */ 1127 BYTE flag1; /* Flag byte 1 */ 1128 BYTE flag2; /* Flag byte 2 */ 1129 BYTE flag3; /* Flag byte 3 */ 1130 FWORD ccwaddr; /* CCW address */ 1131 BYTE unitstat; /* Device status */ 1132 BYTE chanstat; /* Subchannel status */ 1133 HWORD count; /* Residual byte count */ 1134 } SCSW; 1135 1136 /* Bit definitions for SCSW flag byte 0 */ 1137 #define SCSW0_KEY 0xF0 /* Subchannel protection key */ 1138 #define SCSW0_S 0x08 /* Suspend control */ 1139 #define SCSW0_L 0x04 /* ESW format (logout stored)*/ 1140 #define SCSW0_CC 0x03 /* Deferred condition code...*/ 1141 #define SCSW0_CC_0 0x00 /* ...condition code 0 */ 1142 #define SCSW0_CC_1 0x01 /* ...condition code 1 */ 1143 #define SCSW0_CC_3 0x03 /* ...condition code 3 */ 1144 1145 /* Bit definitions for SCSW flag byte 1 */ 1146 #define SCSW1_F 0x80 /* CCW format */ 1147 #define SCSW1_P 0x40 /* Prefetch */ 1148 #define SCSW1_I 0x20 /* Initial status interrupt */ 1149 #define SCSW1_A 0x10 /* Address limit checking */ 1150 #define SCSW1_U 0x08 /* Suppress susp interrupt */ 1151 #define SCSW1_Z 0x04 /* Zero condition code */ 1152 #define SCSW1_E 0x02 /* Extended control */ 1153 #define SCSW1_N 0x01 /* Path not operational */ 1154 1155 /* Bit definitions for SCSW flag byte 2 */ 1156 #define SCSW2_Q 0x80 /* QDIO active */ 1157 #define SCSW2_FC 0x70 /* Function control bits... */ 1158 #define SCSW2_FC_START 0x40 /* ...start function */ 1159 #define SCSW2_FC_HALT 0x20 /* ...halt function */ 1160 #define SCSW2_FC_CLEAR 0x10 /* ...clear function */ 1161 #define SCSW2_AC 0x0F /* Activity control bits... */ 1162 #define SCSW2_AC_RESUM 0x08 /* ...resume pending */ 1163 #define SCSW2_AC_START 0x04 /* ...start pending */ 1164 #define SCSW2_AC_HALT 0x02 /* ...halt pending */ 1165 #define SCSW2_AC_CLEAR 0x01 /* ...clear pending */ 1166 1167 /* Bit definitions for SCSW flag byte 3 */ 1168 #define SCSW3_AC 0xE0 /* Activity control bits... */ 1169 #define SCSW3_AC_SCHAC 0x80 /* ...subchannel active */ 1170 #define SCSW3_AC_DEVAC 0x40 /* ...device active */ 1171 #define SCSW3_AC_SUSP 0x20 /* ...suspended */ 1172 #define SCSW3_SC 0x1F /* Status control bits... */ 1173 #define SCSW3_SC_ALERT 0x10 /* ...alert status */ 1174 #define SCSW3_SC_INTER 0x08 /* ...intermediate status */ 1175 #define SCSW3_SC_PRI 0x04 /* ...primary status */ 1176 #define SCSW3_SC_SEC 0x02 /* ...secondary status */ 1177 #define SCSW3_SC_PEND 0x01 /* ...status pending */ 1178 1179 /* CSW unit status flags */ 1180 #define CSW_ATTN 0x80 /* Attention */ 1181 #define CSW_SM 0x40 /* Status modifier */ 1182 #define CSW_CUE 0x20 /* Control unit end */ 1183 #define CSW_BUSY 0x10 /* Busy */ 1184 #define CSW_CE 0x08 /* Channel end */ 1185 #define CSW_DE 0x04 /* Device end */ 1186 #define CSW_UC 0x02 /* Unit check */ 1187 #define CSW_UX 0x01 /* Unit exception */ 1188 1189 /* CSW channel status flags */ 1190 #define CSW_PCI 0x80 /* Program control interrupt */ 1191 #define CSW_IL 0x40 /* Incorrect length */ 1192 #define CSW_PROGC 0x20 /* Program check */ 1193 #define CSW_PROTC 0x10 /* Protection check */ 1194 #define CSW_CDC 0x08 /* Channel data check */ 1195 #define CSW_CCC 0x04 /* Channel control check */ 1196 #define CSW_ICC 0x02 /* Interface control check */ 1197 #define CSW_CHC 0x01 /* Chaining check */ 1198 1199 /* CCW flags */ 1200 #define CCW_FLAGS_CD 0x80 /* Chain data flag */ 1201 #define CCW_FLAGS_CC 0x40 /* Chain command flag */ 1202 #define CCW_FLAGS_SLI 0x20 /* Suppress incorrect length 1203 indication flag */ 1204 #define CCW_FLAGS_SKIP 0x10 /* Skip flag */ 1205 #define CCW_FLAGS_PCI 0x08 /* Program controlled 1206 interrupt flag */ 1207 #define CCW_FLAGS_IDA 0x04 /* Indirect data address flag*/ 1208 #define CCW_FLAGS_SUSP 0x02 /* Suspend flag */ 1209 #define CCW_FLAGS_MIDAW 0x01 /* Modified IDAW flag @MW*/ 1210 1211 /* MIDAW flags (bits 40-47) @MW*/ 1212 #define MIDAW_LAST 0x80 /* Last MIDAW flag @MW*/ 1213 #define MIDAW_SKIP 0x40 /* Skip flag @MW*/ 1214 #define MIDAW_DTI 0x20 /* Data transfer interrupt@MW*/ 1215 #define MIDAW_RESV 0x1F /* Reserved bits @MW*/ 1216 1217 /* Device independent bit settings for sense byte 0 */ 1218 #define SENSE_CR 0x80 /* Command reject */ 1219 #define SENSE_IR 0x40 /* Intervention required */ 1220 #define SENSE_BOC 0x20 /* Bus-out check */ 1221 #define SENSE_EC 0x10 /* Equipment check */ 1222 #define SENSE_DC 0x08 /* Data check */ 1223 #define SENSE_OR 0x04 /* Overrun */ 1224 #define SENSE_US 0x04 /* Unit specify */ 1225 #define SENSE_CC 0x02 /* Control check */ 1226 #define SENSE_OC 0x01 /* Operation check */ 1227 1228 /* Device dependent bit settings for sense byte 1 */ 1229 #define SENSE1_PER 0x80 /* Permanent Error */ 1230 #define SENSE1_ITF 0x40 /* Invalid Track Format */ 1231 #define SENSE1_EOC 0x20 /* End of Cylinder */ 1232 #define SENSE1_MTO 0x10 /* Message to Operator */ 1233 #define SENSE1_NRF 0x08 /* No Record Found */ 1234 #define SENSE1_FP 0x04 /* File Protected */ 1235 #define SENSE1_WRI 0x02 /* Write Inhibited */ 1236 #define SENSE1_IE 0x01 /* Imprecise Ending */ 1237 1238 /* Subchannel information block structure definition */ 1239 typedef struct _SCHIB { 1240 PMCW pmcw; /* Path management ctl word */ 1241 SCSW scsw; /* Subchannel status word */ 1242 BYTE moddep[12]; /* Model dependent area */ 1243 } SCHIB; 1244 1245 /* Interruption response block structure definition */ 1246 typedef struct _IRB { 1247 SCSW scsw; /* Subchannel status word */ 1248 ESW esw; /* Extended status word */ 1249 BYTE ecw[32]; /* Extended control word */ 1250 } IRB; 1251 1252 /* Measurement Block */ 1253 typedef struct _MBK { 1254 HWORD srcount; /* SSCH + RSCH count */ 1255 HWORD samplecnt; /* Sample count */ 1256 FWORD dct; /* Device connect time */ 1257 FWORD fpt; /* Function pending time */ 1258 FWORD ddt; /* Device disconnect time */ 1259 FWORD cuqt; /* Control unit queueing time*/ 1260 FWORD resv[3]; /* Reserved */ 1261 } MBK; 1262 1263 /* Bit definitions for SCHM instruction */ 1264 #define CHM_GPR1_MBK 0xF0000000 /* Measurement Block Key */ 1265 #define CHM_GPR1_M 0x00000002 /* Measurement mode control */ 1266 #define CHM_GPR1_D 0x00000001 /* Block update Mode */ 1267 #define CHM_GPR1_A 0x01000000 /* Alternate mode */ 1268 #define CHM_GPR1_ZONE 0x00FF0000 /* Zone */ 1269 #define CHM_GPR1_RESV 0x0E00FFFC /* Reserved, must be zero */ 1270 1271 /* Measurement Block Origin */ 1272 #define S_CHM_GPR2_RESV 0x8000001F /* Reserved, must be zero */ 1273 #define Z_CHM_GPR2_RESV 0x0000001F /* Reserved, must be zero */ 1274 1275 /* Definitions for PLO instruction */ 1276 #define PLO_GPR0_FC 0x000000FF /* Function code mask */ 1277 #define PLO_GPR0_T 0x00000100 /* Function test mask */ 1278 #define PLO_GPR0_RESV 0xFFFFFE00 /* Reserved bits */ 1279 #define PLO_CL 0 /* Compare and load */ 1280 #define PLO_CLG 1 /* Compare and load */ 1281 #define PLO_CLGR 2 /* Compare and load ESAME */ 1282 #define PLO_CLX 3 /* Compare and load ESAME */ 1283 #define PLO_CS 4 /* Compare and swap */ 1284 #define PLO_CSG 5 /* Compare and swap */ 1285 #define PLO_CSGR 6 /* Compare and swap ESAME */ 1286 #define PLO_CSX 7 /* Compare and swap ESAME */ 1287 #define PLO_DCS 8 /* Double compare and swap */ 1288 #define PLO_DCSG 9 /* Double compare and swap */ 1289 #define PLO_DCSGR 10 /* Double c and s ESAME */ 1290 #define PLO_DCSX 11 /* Double c and s ESAME */ 1291 #define PLO_CSST 12 /* Compare and swap and store*/ 1292 #define PLO_CSSTG 13 /* Compare and swap and store*/ 1293 #define PLO_CSSTGR 14 /* C/S/S ESAME */ 1294 #define PLO_CSSTX 15 /* C/S/S ESAME */ 1295 #define PLO_CSDST 16 /* C/S and double store */ 1296 #define PLO_CSDSTG 17 /* C/S and double store */ 1297 #define PLO_CSDSTGR 18 /* C/S/DS ESAME */ 1298 #define PLO_CSDSTX 19 /* C/S/DS ESAME */ 1299 #define PLO_CSTST 20 /* C/S and triple store */ 1300 #define PLO_CSTSTG 21 /* C/S and triple store */ 1301 #define PLO_CSTSTGR 22 /* C/S/TS ESAME */ 1302 #define PLO_CSTSTX 23 /* C/S/TS ESAME */ 1303 1304 /* Perform Frame Management Function definitions */ 1305 #define PFMF_FMFI 0x000f0000 /* Frame mgmt function indic */ 1306 #define PFMF_FMFI_RESV 0x000c0000 /* Reserved must be zero */ 1307 #define PFMF_FMFI_SK 0x00020000 /* Set-Key Control */ 1308 #define PFMF_FMFI_CF 0x00010000 /* Clear-Frame Control */ 1309 #define PFMF_UI 0x00008000 /* Usage Indication */ 1310 #define PFMF_FSC 0x00007000 /* Frame-Size Code */ 1311 #define PFMF_FSC_4K 0x00000000 /* 4K */ 1312 #define PFMF_FSC_1M 0x00001000 /* 1M */ 1313 #define PFMF_FSC_2G 0x00002000 /* 2G */ 1314 #define PFMF_NQ 0x00000800 /* Quiesce (SK must be one) */ 1315 #define PFMF_MR 0x00000400 /* Reference Bit Update Mask */ 1316 #define PFMF_MC 0x00000200 /* Change Bit Update Mask */ 1317 #define PFMF_KEY 0x000000F7 /* Storage Key */ 1318 #define PFMF_RESERVED 0xFFF00101 /* Reserved */ 1319 1320 /* Bit definitions for Store Facilities List instruction */ 1321 /* Byte STFL_0: STFL/STFLE bits 0-7 */ 1322 #define STFL_0_N3 0x80 /* Instructions marked N3 in 1323 the reference summary are 1324 available in ESA/390 mode */ 1325 #define STFL_0_ESAME_INSTALLED 0x40 /* ESAME mode is available on 1326 this processor */ 1327 #define STFL_0_ESAME_ACTIVE 0x20 /* ESAME mode is active on 1328 this processor */ 1329 #define STFL_0_IDTE_INSTALLED 0x10 /* IDTE installed ESAME mode */ 1330 #define STFL_0_IDTE_SC_SEGTAB 0x08 /* IDTE selective clearing 1331 when segtab invalidated */ 1332 #define STFL_0_IDTE_SC_REGTAB 0x04 /* IDTE selective clearing 1333 when regtab invalidated */ 1334 #define STFL_0_ASN_LX_REUSE 0x02 /* ASN-and-LX-reuse facility 1335 is installed */ 1336 #define STFL_0_STFL_EXTENDED 0x01 /* Store facility list @Z9 1337 extended is installed @Z9*/ 1338 /* Byte STFL_1: STFL/STFLE bits 8-15 */ 1339 #define STFL_1_ENHANCED_DAT 0x80 /* Enhanced-DAT facility 208 1340 is installed 208*/ 1341 #define STFL_1_SENSE_RUN_STATUS 0x40 /* Sense running status @Z9 1342 facility is installed @Z9*/ 1343 #define STFL_1_CONDITIONAL_SSKE 0x20 /* Conditional SSKE facility 1344 is installed 407*/ 1345 #define STFL_1_CONFIG_TOPOLOGY 0x10 /* STSI-enhancement for 1346 configuration topology */ 1347 #define STFL_1_IPTE_RANGE 0x04 /* IPTE-Range facility 810 1348 installed 810*/ 1349 #define STFL_1_NONQ_KEY_SET 0x02 /* Nonquiescing Key-Setting 810 1350 Facility installed 810*/ 1351 /* Byte STFL_2: STFL/STFLE bits 16-23 */ 1352 #define STFL_2_TRAN_FAC2 0x80 /* Extended translation 1353 facility 2 is installed */ 1354 #define STFL_2_MSG_SECURITY 0x40 /* Message security assist 1355 feature is installed */ 1356 #define STFL_2_LONG_DISPL_INST 0x20 /* Long displacement facility 1357 is installed */ 1358 #define STFL_2_LONG_DISPL_HPERF 0x10 /* Long displacement facility 1359 has high performance */ 1360 #define STFL_2_HFP_MULT_ADD_SUB 0x08 /* HFP multiply-add/subtract 1361 facility is installed */ 1362 #define STFL_2_EXTENDED_IMMED 0x04 /* Extended immediate @Z9 1363 facility is installed @Z9*/ 1364 #define STFL_2_TRAN_FAC3 0x02 /* Extended translation 1365 facility 3 is installed */ 1366 #define STFL_2_HFP_UNNORM_EXT 0x01 /* HFP unnormalized extension 1367 facility is installed @Z9*/ 1368 /* Byte STFL_3: STFL/STFLE bits 24-31 */ 1369 #define STFL_3_ETF2_ENHANCEMENT 0x80 /* Extended translation @Z9 1370 facility 2 enhancement @Z9*/ 1371 #define STFL_3_STORE_CLOCK_FAST 0x40 /* Store clock fast @Z9 1372 enhancement installed @Z9*/ 1373 #define STFL_3_PARSING_ENHANCE 0x20 /* Parsing-Enhancement 208 1374 facility is installed 208*/ 1375 #define STFL_3_MVCOS 0x10 /* MVCOS instruction 1376 is installed 407*/ 1377 #define STFL_3_TOD_CLOCK_STEER 0x08 /* TOD clock steering @Z9 1378 facility is installed @Z9*/ 1379 #define STFL_3_ETF3_ENHANCEMENT 0x02 /* Extended translation @Z9 1380 facility 3 enhancement @Z9*/ 1381 #define STFL_3_EXTRACT_CPU_TIME 0x01 /* Extract CPU time facility 1382 is installed 407*/ 1383 /* Byte STFL_4: STFLE bits 32-39 */ 1384 #define STFL_4_CSSF 0x80 /* Compare-and-Swap-and-Store 1385 facility is installed */ 1386 #define STFL_4_CSSF2 0x40 /* Compare-and-Swap-and-Store 1387 facility 2 is installed */ 1388 #define STFL_4_GEN_INST_EXTN 0x20 /* General-Instr-Extn 208 1389 facility is installed 208*/ 1390 #define STFL_4_EXECUTE_EXTN 0x10 /* Execute-Extensions 208 1391 facility is installed 208*/ 1392 #define STFL_4_ENH_MONITOR 0x08 /* Enhanced-Monitor 1393 facility installed 810*/ 1394 #define STFL_4_FP_EXTENSION 0x04 /* Floating-point extension 1395 facility installed 810*/ 1396 /* Byte STFL_5: STFLE bits 40-47 */ 1397 #define STFL_5_LOAD_PROG_PARAM 0x80 /* Load-Program-Parameter 1398 facility installed (ESAME)*/ 1399 #define STFL_5_FPS_ENHANCEMENT 0x40 /* Floating point support 1400 enhancements (FPR-GR-loading 1401 FPS-sign-handling, and 1402 DFP-rounding) installed */ 1403 #define STFL_5_DECIMAL_FLOAT 0x20 /* Decimal floating point 1404 (DFP) facility */ 1405 #define STFL_5_DFP_HPERF 0x10 /* DFP has high performance */ 1406 #define STFL_5_PFPO 0x08 /* PFPO instruction installed*/ 1407 #define STFL_5_FAST_BCR_SERIAL 0x04 /* Fast-BCR-serialization 1408 Facility installed 810*/ 1409 #define STFL_5_CMPSC_ENH 0x01 /* CMPSC-enhancement 1410 Facility installed 810*/ 1411 /* Byte STFL_6: STFLE bits 48-55 */ 1412 #define STFL_6_DFP_ZONED_CONV 0x80 /* DFP zoned-conversion 1413 facility is installed 912*/ 1414 #define STFL_6_MISC_INST_EXT 0x40 /* Execution-hint,load-and-trap 1415 misc-inst-ext,processor-asst 1416 facilities installed 912*/ 1417 #define STFL_6_CONSTRAINED_TEF 0x20 /* Constrained-transactn-execn 1418 facility is installed 912*/ 1419 #define STFL_6_LOCAL_TLB_CLEAR 0x10 /* Local-TLB-clearing 1420 facility is installed 912*/ 1421 #define STFL_6_INTERLOCK_ACC_2 0x08 /* Interlocked-access 1422 facility 2 installed 912*/ 1423 /* Byte STFL_7: STFLE bits 56-63 */ 1424 /* Byte STFL_8: STFLE bits 64-71 */ 1425 #define STFL_8_RES_REF_BITS_MUL 0x20 /* Reset-Reference-Bits-Multiple 1426 Facility installed 810*/ 1427 #define STFL_8_CPU_MEAS_COUNTER 0x10 /* CPU-measurement counter 1428 facility installed (ESAME)*/ 1429 #define STFL_8_CPU_MEAS_SAMPLNG 0x08 /* CPU-measurement sampling 1430 facility installed (ESAME)*/ 1431 /* Byte STFL_9: STFLE bits 72-79 */ 1432 #define STFL_9_TRANSACT_EXEC 0x40 /* Transactional execution 1433 facility is installed 912*/ 1434 #define STFL_9_ACC_EX_FS_INDIC 0x10 /* Access-exception fetch/store 1435 indication facility 810*/ 1436 #define STFL_9_MSA_EXTENSION_3 0x08 /* Message Security Assist 1437 Extension 3 installed 810*/ 1438 #define STFL_9_MSA_EXTENSION_4 0x04 /* Message Security Assist 1439 Extension 4 installed 810*/ 1440 #define STFL_9_ENHANCED_DAT_2 0x02 /* Enhanced-DAT facility 2 1441 is installed 912*/ 1442 1443 /* Bit definitions for the Vector Facility */ 1444 #define VSR_M 0x0001000000000000ULL /* Vector mask mode bit */ 1445 #define VSR_VCT 0x0000FFFF00000000ULL /* Vector count */ 1446 #define VSR_VIX 0x00000000FFFF0000ULL /* Vector interruption index */ 1447 #define VSR_VIU 0x000000000000FF00ULL /* Vector in-use bits */ 1448 #define VSR_VIU0 0x0000000000008000ULL /* Vector in-use bit vr0 */ 1449 #define VSR_VCH 0x00000000000000FFULL /* Vector change bits */ 1450 #define VSR_VCH0 0x0000000000000080ULL /* Vector change bit vr0 */ 1451 #define VSR_RESV 0xFFFE000000000000ULL /* Reserved bits */ 1452 1453 #define VAC_MASK 0x00FFFFFFFFFFFFFFULL /* Vector Activity Count mask*/ 1454 1455 /* SIE Format 1 State Descriptor Block */ 1456 typedef struct _SIE1BK { /* SIE State Descriptor */ 1457 /*000*/ BYTE v; /* Intervention requests */ 1458 #define SIE_V v 1459 #define SIE_V_WAIT 0x10 /* Wait/Run bit */ 1460 #define SIE_V_EXTCALL 0x08 /* External call pending */ 1461 #define SIE_V_STOP 0x04 /* SIE Stop control */ 1462 #define SIE_V_IO 0x02 /* I/O Interrupt pending */ 1463 #define SIE_V_EXT 0x01 /* EXT Interrupt pending */ 1464 /*001*/ BYTE s; /* State controls */ 1465 #define SIE_S s 1466 #define SIE_S_T 0x80 /* Interval timer irpt pend */ 1467 #define SIE_S_RETENTION 0x40 /* SIE State retained */ 1468 #define SIE_S_EXP_TIMER 0x02 /* Expedite timer enabled */ 1469 #define SIE_S_EXP_RUN 0x01 /* Expedite run enabled */ 1470 /*002*/ BYTE mx; /* Machine mode control */ 1471 #define SIE_MX mx 1472 #define SIE_MX_RRF 0x80 /* Region Relocate Installed */ 1473 #define SIE_MX_XC 0x01 /* XC mode guest */ 1474 /*003*/ BYTE m; /* Mode controls */ 1475 #define SIE_M m 1476 #define SIE_M_VCC 0x40 /* Vector change control */ 1477 #define SIE_M_XA 0x20 /* XA mode guest */ 1478 #define SIE_M_370 0x10 /* 370 mode guest */ 1479 #define SIE_M_VR 0x08 /* V=R mode guest */ 1480 #define SIE_M_ITMOF 0x04 /* Guest ival timer disabled */ 1481 #define SIE_M_GPE 0x01 /* Guest per enhancement */ 1482 /*004*/ FWORD prefix; /* Guest prefix register */ 1483 /*008*/ HWORD mso; /* Main Storage Origin */ 1484 /*00A*/ HWORD mse; /* Main Storage Extent */ 1485 /*00C*/ FWORD resv0cf; 1486 /*010*/ FWORD gr14; /* Guest gr 14 */ 1487 /*014*/ FWORD gr15; /* Guest gr 15 */ 1488 /*018*/ DBLWRD psw; /* Guest PSW */ 1489 /*020*/ FWORD resv20f; 1490 /*024*/ FWORD residue; /* Residue counter */ 1491 /*028*/ DBLWRD cputimer; /* CPU timer */ 1492 /*030*/ DBLWRD clockcomp; /* Clock comparator */ 1493 /*038*/ DBLWRD epoch; /* Guest/Host epoch diff. */ 1494 /*040*/ FWORD svc_ctl; /* SVC Controls */ 1495 #define SIE_SVC0 svc_ctl[0] 1496 #define SIE_SVC0_ALL 0x80 /* Intercept all SVCs */ 1497 #define SIE_SVC0_1N 0x40 /* Intercept SVC 1n */ 1498 #define SIE_SVC0_2N 0x20 /* Intercept SVC 2n */ 1499 #define SIE_SVC0_3N 0x10 /* Intercept SVC 3n */ 1500 /*044*/ HWORD lctl_ctl; /* LCTL Control */ 1501 #define SIE_LCTL0 lctl_ctl[0] 1502 #define SIE_LCTL0_CR0 0x80 /* Intercept LCTL 0 */ 1503 #define SIE_LCTL0_CR1 0x40 /* Intercept LCTL 1 */ 1504 #define SIE_LCTL0_CR2 0x20 /* Intercept LCTL 2 */ 1505 #define SIE_LCTL0_CR3 0x10 /* Intercept LCTL 3 */ 1506 #define SIE_LCTL0_CR4 0x08 /* Intercept LCTL 4 */ 1507 #define SIE_LCTL0_CR5 0x04 /* Intercept LCTL 5 */ 1508 #define SIE_LCTL0_CR6 0x02 /* Intercept LCTL 6 */ 1509 #define SIE_LCTL0_CR7 0x01 /* Intercept LCTL 7 */ 1510 #define SIE_LCTL1 lctl_ctl[1] 1511 #define SIE_LCTL1_CR8 0x80 /* Intercept LCTL 8 */ 1512 #define SIE_LCTL1_CR9 0x40 /* Intercept LCTL 9 */ 1513 #define SIE_LCTL1_CR10 0x20 /* Intercept LCTL 10 */ 1514 #define SIE_LCTL1_CR11 0x10 /* Intercept LCTL 11 */ 1515 #define SIE_LCTL1_CR12 0x08 /* Intercept LCTL 12 */ 1516 #define SIE_LCTL1_CR13 0x04 /* Intercept LCTL 13 */ 1517 #define SIE_LCTL1_CR14 0x02 /* Intercept LCTL 14 */ 1518 #define SIE_LCTL1_CR15 0x01 /* Intercept LCTL 15 */ 1519 /*046*/ HWORD cpuad; /* Virtual CPU address */ 1520 /*048*/ FWORD ic; /* Interception Controls */ 1521 #define SIE_IC0 ic[0] 1522 #define SIE_IC0_OPEREX 0x80 /* Intercept operation exc. */ 1523 #define SIE_IC0_PRIVOP 0x40 /* Intercept priv. op. exc. */ 1524 #define SIE_IC0_PGMALL 0x20 /* Intercept program ints */ 1525 #define SIE_IC0_STFL 0x10 /* Intercept STFL/STFLE */ 1526 #define SIE_IC0_TS1 0x08 /* Intercept TS cc1 */ 1527 #define SIE_IC0_CS1 0x04 /* Intercept CS cc1 */ 1528 #define SIE_IC0_CDS1 0x02 /* Intercept CDS cc1 */ 1529 #define SIE_IC0_IPTECSP 0x01 /* Intercept IPTE or CSP */ 1530 #define SIE_IC1 ic[1] 1531 #define SIE_IC1_LPSW 0x40 /* Intercept LPSW */ 1532 #define SIE_IC1_PXLB 0x20 /* Intercept PTLB or PALB */ 1533 #define SIE_IC1_SSM 0x10 /* Intercept SSM */ 1534 #define SIE_IC1_BSA 0x08 /* Intercept BSA */ 1535 #define SIE_IC1_STCTL 0x04 /* Intercept STCTL */ 1536 #define SIE_IC1_STNSM 0x02 /* Intercept STNSM */ 1537 #define SIE_IC1_STOSM 0x01 /* Intercept STOSM */ 1538 #define SIE_IC2 ic[2] 1539 #define SIE_IC2_STCK 0x80 /* Intercept STCK */ 1540 #define SIE_IC2_ISKE 0x40 /* Intercept ISK/ISKE */ 1541 #define SIE_IC2_SSKE 0x20 /* Intercept SSK/SSKE */ 1542 #define SIE_IC2_RRBE 0x10 /* Intercept RRB/RRBE */ 1543 #define SIE_IC2_PC 0x08 /* Intercept PC */ 1544 #define SIE_IC2_PT 0x04 /* Intercept PT */ 1545 #define SIE_IC2_TPROT 0x02 /* Intercept TPROT */ 1546 #define SIE_IC2_LASP 0x01 /* Intercept LASP */ 1547 #define SIE_IC3 ic[3] 1548 #define SIE_IC3_VACSV 0x80 /* Intercept VACSV */ 1549 #define SIE_IC3_SPT 0x40 /* Intercept SPT and STPT */ 1550 #define SIE_IC3_SCKC 0x20 /* Intercept SCKC and STCKC */ 1551 #define SIE_IC3_VACRS 0x10 /* Intercept VACRS */ 1552 #define SIE_IC3_PR 0x08 /* Intercept PR */ 1553 #define SIE_IC3_BAKR 0x04 /* Intercept BAKR */ 1554 #define SIE_IC3_PGX 0x02 /* Intercept PGIN/PGOUT */ 1555 /*04C*/ FWORD ec; /* Execution Controls */ 1556 #define SIE_EC0 ec[0] 1557 #define SIE_EC0_EXTA 0x80 /* External Interrupt Assist */ 1558 #define SIE_EC0_INTA 0x40 /* Intervention Bypass Assist*/ 1559 #define SIE_EC0_WAIA 0x20 /* Wait State Assist */ 1560 #define SIE_EC0_SIGPA 0x10 /* SIGP Assist */ 1561 #define SIE_EC0_ALERT 0x08 /* Alert Monitoring */ 1562 #define SIE_EC0_IOA 0x04 /* I/O Assist */ 1563 #define SIE_EC0_MVPG 0x01 /* Interpret MVPG and IESBE */ 1564 #define SIE_EC1 ec[1] 1565 #define SIE_EC1_EC370 0x20 /* 370 I/O Assist */ 1566 #define SIE_EC1_VFONL 0x04 /* Virtual VF online */ 1567 #define SIE_EC2 ec[2] 1568 #define SIE_EC2_PROTEX 0x20 /* Intercept prot exception */ 1569 #define SIE_EC3 ec[3] 1570 #define SIE_EC3_SIGAA 0x04 /* SIGA Assist */ 1571 /*050*/ BYTE c; /* Interception Code */ 1572 #define SIE_C_INST 4 /* Instruction interception */ 1573 #define SIE_C_PGMINT 8 /* Program interruption */ 1574 #define SIE_C_PGMINST 12 /* Program/instruction int */ 1575 #define SIE_C_EXTREQ 16 /* External request */ 1576 #define SIE_C_EXTINT 20 /* External interruption */ 1577 #define SIE_C_IOREQ 24 /* I/O request */ 1578 #define SIE_C_WAIT 28 /* Wait state */ 1579 #define SIE_C_VALIDITY 32 /* Validity */ 1580 #define SIE_C_STOPREQ 40 /* Stop request */ 1581 #define SIE_C_OPEREXC 44 /* Operation Exception */ 1582 #define SIE_C_IOINT 60 /* I/O Interruption */ 1583 #define SIE_C_IOINST 64 /* I/O Instruction */ 1584 #define SIE_C_EXP_RUN 68 /* Expedited Run Intercept */ 1585 #define SIE_C_EXP_TIMER 72 /* Expedited Timer Intercept */ 1586 /*051*/ BYTE f; /* Interception Status */ 1587 #define SIE_F f 1588 #define SIE_F_IN 0x80 /* Intercept format 2 */ 1589 #define SIE_F_IF 0x02 /* Instruction fetch PER */ 1590 #define SIE_F_EX 0x01 /* Icept for target of EX */ 1591 /*052*/ HWORD lhcpu; /* Last Host CPU addr */ 1592 /*054*/ HWORD todpf; /* TOD programmable field */ 1593 /*056*/ HWORD ipa; /* Instruction parameter A */ 1594 /*058*/ FWORD ipb; /* Instruction parameter B */ 1595 /*05C*/ FWORD ipc; /* Instruction parameter C */ 1596 /*060*/ FWORD rcpo; /* RCP area origin */ 1597 #define SIE_RCPO0 rcpo[0] 1598 #define SIE_RCPO0_SKA 0x80 /* Storage Key Assist */ 1599 #define SIE_RCPO0_SKAIP 0x40 /* SKA in progress */ 1600 #define SIE_RCPO2 rcpo[2] 1601 #define SIE_RCPO2_RCPBY 0x10 /* RCP Bypass */ 1602 /*064*/ FWORD scao; /* SCA area origin */ 1603 /*068*/ FWORD subchtabo; /* Subchannel table origin */ 1604 /*06C*/ FWORD resv6Cf; 1605 /*070*/ HWORD tch_ctl; /* Test Channel control */ 1606 /*072*/ HWORD resv72h; 1607 /*074*/ BYTE zone; /* Zone Number */ 1608 /*075*/ BYTE resv075; 1609 /*076*/ BYTE tschds; /* TSCH device status */ 1610 /*077*/ BYTE tschsc; /* TSCH subchannel status */ 1611 /*078*/ BYTE xslim[3]; /* Extended stor upper lim */ 1612 /*07B*/ BYTE resv7Bb; 1613 /*07C*/ FWORD resv7Cf; 1614 /*080*/ FWORD cr[16]; /* Guest Control registers */ 1615 /*0C0*/ BYTE ip[34]; /* Interruption parameters */ 1616 #define SIE_IP_PSA_OFFSET 0x40 /* Offset of the IP field 1617 relative to the ipfields 1618 in the PSA */ 1619 #define SIE_II_PSA_OFFSET 0x30 /* Offset of the IP field 1620 relative to the I/O fields 1621 in the PSA for ESAME guest*/ 1622 /*0E2*/ BYTE xso[3]; /* Expanded storage origin */ 1623 /*0E5*/ BYTE xsl[3]; /* Expanded storage limit */ 1624 /*0E8*/ BYTE resvE8b[24]; 1625 } SIE1BK; 1626 1627 /* SIE Format 2 State Descriptor Block */ 1628 typedef struct _SIE2BK { /* SIE State Descriptor */ 1629 /*000*/ BYTE v; /* Intervention requests */ 1630 #define SIE_V v 1631 #define SIE_V_WAIT 0x10 /* Wait/Run bit */ 1632 #define SIE_V_EXTCALL 0x08 /* External call pending */ 1633 #define SIE_V_STOP 0x04 /* SIE Stop control */ 1634 #define SIE_V_IO 0x02 /* I/O Interrupt pending */ 1635 #define SIE_V_EXT 0x01 /* EXT Interrupt pending */ 1636 /*001*/ BYTE s; /* State controls */ 1637 #define SIE_S s 1638 #define SIE_S_T 0x80 /* Interval timer irpt pend */ 1639 #define SIE_S_RETENTION 0x40 /* SIE State retained */ 1640 #define SIE_S_EXP_TIMER 0x02 /* Expedite timer enabled */ 1641 #define SIE_S_EXP_RUN 0x01 /* Expedite run enabled */ 1642 /*002*/ BYTE mx; /* Machine mode control */ 1643 #define SIE_MX mx 1644 #define SIE_MX_RRF 0x80 /* Region Relocate Installed */ 1645 #define SIE_MX_XC 0x01 /* XC mode guest */ 1646 #define SIE_MX_ESAME 0x08 /* ESAME mode guest */ 1647 /*003*/ BYTE m; /* Mode controls */ 1648 #define SIE_M m 1649 #define SIE_M_VCC 0x40 /* Vector change control */ 1650 #define SIE_M_XA 0x20 /* XA mode guest */ 1651 #define SIE_M_370 0x10 /* 370 mode guest */ 1652 #define SIE_M_VR 0x08 /* V=R mode guest */ 1653 #define SIE_M_ITMOF 0x04 /* Guest ival timer disabled */ 1654 #define SIE_M_GPE 0x01 /* Guest per enhancement */ 1655 /*004*/ FWORD prefix; /* Guest prefix register */ 1656 /*008*/ FWORD resv008f; 1657 /*00C*/ FWORD resv00cf; 1658 /*010*/ DBLWRD resv010d; 1659 /*018*/ DBLWRD resv018d; 1660 /*020*/ DBLWRD resv020d; 1661 /*028*/ DBLWRD cputimer; /* CPU timer */ 1662 /*030*/ DBLWRD clockcomp; /* Clock comparator */ 1663 /*038*/ DBLWRD epoch; /* Guest/Host epoch diff. */ 1664 /*040*/ FWORD svc_ctl; /* SVC Controls */ 1665 #define SIE_SVC0 svc_ctl[0] 1666 #define SIE_SVC0_ALL 0x80 /* Intercept all SVCs */ 1667 #define SIE_SVC0_1N 0x40 /* Intercept SVC 1n */ 1668 #define SIE_SVC0_2N 0x20 /* Intercept SVC 2n */ 1669 #define SIE_SVC0_3N 0x10 /* Intercept SVC 3n */ 1670 /*044*/ HWORD lctl_ctl; /* LCTL Control */ 1671 #define SIE_LCTL0 lctl_ctl[0] 1672 #define SIE_LCTL0_CR0 0x80 /* Intercept LCTL 0 */ 1673 #define SIE_LCTL0_CR1 0x40 /* Intercept LCTL 1 */ 1674 #define SIE_LCTL0_CR2 0x20 /* Intercept LCTL 2 */ 1675 #define SIE_LCTL0_CR3 0x10 /* Intercept LCTL 3 */ 1676 #define SIE_LCTL0_CR4 0x08 /* Intercept LCTL 4 */ 1677 #define SIE_LCTL0_CR5 0x04 /* Intercept LCTL 5 */ 1678 #define SIE_LCTL0_CR6 0x02 /* Intercept LCTL 6 */ 1679 #define SIE_LCTL0_CR7 0x01 /* Intercept LCTL 7 */ 1680 #define SIE_LCTL1 lctl_ctl[1] 1681 #define SIE_LCTL1_CR8 0x80 /* Intercept LCTL 8 */ 1682 #define SIE_LCTL1_CR9 0x40 /* Intercept LCTL 9 */ 1683 #define SIE_LCTL1_CR10 0x20 /* Intercept LCTL 10 */ 1684 #define SIE_LCTL1_CR11 0x10 /* Intercept LCTL 11 */ 1685 #define SIE_LCTL1_CR12 0x08 /* Intercept LCTL 12 */ 1686 #define SIE_LCTL1_CR13 0x04 /* Intercept LCTL 13 */ 1687 #define SIE_LCTL1_CR14 0x02 /* Intercept LCTL 14 */ 1688 #define SIE_LCTL1_CR15 0x01 /* Intercept LCTL 15 */ 1689 /*046*/ HWORD cpuad; /* Virtual CPU address */ 1690 /*048*/ FWORD ic; /* Interception Controls */ 1691 #define SIE_IC0 ic[0] 1692 #define SIE_IC0_OPEREX 0x80 /* Intercept operation exc. */ 1693 #define SIE_IC0_PRIVOP 0x40 /* Intercept priv. op. exc. */ 1694 #define SIE_IC0_PGMALL 0x20 /* Intercept program ints */ 1695 #define SIE_IC0_TS1 0x08 /* Intercept TS cc1 */ 1696 #define SIE_IC0_CS1 0x04 /* Intercept CS cc1 */ 1697 #define SIE_IC0_CDS1 0x02 /* Intercept CDS cc1 */ 1698 #define SIE_IC0_IPTECSP 0x01 /* Intercept IPTE or CSP */ 1699 #define SIE_IC1 ic[1] 1700 #define SIE_IC1_LPSW 0x40 /* Intercept LPSW/LPSWE */ 1701 #define SIE_IC1_PXLB 0x20 /* Intercept PTLB or PALB */ 1702 #define SIE_IC1_SSM 0x10 /* Intercept SSM */ 1703 #define SIE_IC1_BSA 0x08 /* Intercept BSA */ 1704 #define SIE_IC1_STCTL 0x04 /* Intercept STCTL */ 1705 #define SIE_IC1_STNSM 0x02 /* Intercept STNSM */ 1706 #define SIE_IC1_STOSM 0x01 /* Intercept STOSM */ 1707 #define SIE_IC2 ic[2] 1708 #define SIE_IC2_STCK 0x80 /* Intercept STCK */ 1709 #define SIE_IC2_ISKE 0x40 /* Intercept ISK/ISKE */ 1710 #define SIE_IC2_SSKE 0x20 /* Intercept SSK/SSKE */ 1711 #define SIE_IC2_RRBE 0x10 /* Intercept RRB/RRBE */ 1712 #define SIE_IC2_PC 0x08 /* Intercept PC */ 1713 #define SIE_IC2_PT 0x04 /* Intercept PT */ 1714 #define SIE_IC2_TPROT 0x02 /* Intercept TPROT */ 1715 #define SIE_IC2_LASP 0x01 /* Intercept LASP */ 1716 #define SIE_IC3 ic[3] 1717 #define SIE_IC3_VACSV 0x80 /* Intercept VACSV */ 1718 #define SIE_IC3_SPT 0x40 /* Intercept SPT and STPT */ 1719 #define SIE_IC3_SCKC 0x20 /* Intercept SCKC and STCKC */ 1720 #define SIE_IC3_VACRS 0x10 /* Intercept VACRS */ 1721 #define SIE_IC3_PR 0x08 /* Intercept PR */ 1722 #define SIE_IC3_BAKR 0x04 /* Intercept BAKR */ 1723 #define SIE_IC3_PGX 0x02 /* Intercept PGIN/PGOUT */ 1724 /*04C*/ FWORD ec; /* Execution Controls */ 1725 #define SIE_EC0 ec[0] 1726 #define SIE_EC0_EXTA 0x80 /* External Interrupt Assist */ 1727 #define SIE_EC0_INTA 0x40 /* Intervention Bypass Assist*/ 1728 #define SIE_EC0_WAIA 0x20 /* Wait State Assist */ 1729 #define SIE_EC0_SIGPA 0x10 /* SIGP Assist */ 1730 #define SIE_EC0_ALERT 0x08 /* Alert Monitoring */ 1731 #define SIE_EC0_IOA 0x04 /* I/O Assist */ 1732 #define SIE_EC0_MVPG 0x01 /* Interpret MVPG and IESBE */ 1733 #define SIE_EC1 ec[1] 1734 #define SIE_EC1_EC370 0x20 /* 370 I/O Assist */ 1735 #define SIE_EC1_VFONL 0x04 /* Virtual VF online */ 1736 #define SIE_EC2 ec[2] 1737 #define SIE_EC2_PROTEX 0x20 /* Intercept prot exception */ 1738 #define SIE_EC3 ec[3] 1739 #define SIE_EC3_SIGAA 0x04 /* SIGA Assist */ 1740 /*050*/ BYTE c; /* Interception Code */ 1741 #define SIE_C_INST 4 /* Instruction interception */ 1742 #define SIE_C_PGMINT 8 /* Program interruption */ 1743 #define SIE_C_PGMINST 12 /* Program/instruction int */ 1744 #define SIE_C_EXTREQ 16 /* External request */ 1745 #define SIE_C_EXTINT 20 /* External interruption */ 1746 #define SIE_C_IOREQ 24 /* I/O request */ 1747 #define SIE_C_WAIT 28 /* Wait state */ 1748 #define SIE_C_VALIDITY 32 /* Validity */ 1749 #define SIE_C_STOPREQ 40 /* Stop request */ 1750 #define SIE_C_OPEREXC 44 /* Operation Exception */ 1751 #define SIE_C_EXP_RUN 68 /* Expedited Run Intercept */ 1752 #define SIE_C_EXP_TIMER 72 /* Expedited Timer Intercept */ 1753 /*051*/ BYTE f; /* Interception Status */ 1754 #define SIE_F f 1755 #define SIE_F_IN 0x80 /* Intercept format 2 */ 1756 #define SIE_F_IF 0x02 /* Instruction fetch PER */ 1757 #define SIE_F_EX 0x01 /* Icept for target of EX */ 1758 /*052*/ HWORD lhcpu; /* Last Host CPU addr */ 1759 /*054*/ HWORD resv054h; 1760 /*056*/ HWORD ipa; /* Instruction parameter A */ 1761 #define vi_who ipa[0] 1762 #define vi_when ipa[1] 1763 #define vi_why ipb 1764 #define vi_zero ipb+2 1765 /*058*/ FWORD ipb; /* Instruction parameter B */ 1766 /*05C*/ FWORD ipc; /* Instruction parameter C */ 1767 /*060*/ FWORD rcpo; /* RCP area origin */ 1768 #define SIE_RCPO0 rcpo[0] 1769 #define SIE_RCPO0_SKA 0x80 /* Storage Key Assist */ 1770 #define SIE_RCPO0_SKAIP 0x40 /* SKA in progress */ 1771 #define SIE_RCPO2 rcpo[2] 1772 #define SIE_RCPO2_RCPBY 0x10 /* RCP Bypass */ 1773 /*064*/ FWORD scao; /* SCA area origin */ 1774 /*068*/ FWORD resv068f; 1775 /*06C*/ HWORD todpfh; /* TOD pf high half */ 1776 /*06E*/ HWORD todpf; /* TOD programmable field */ 1777 /*070*/ FWORD resv070f; 1778 /*074*/ BYTE zone; /* Zone Number */ 1779 /*075*/ BYTE resv075; 1780 /*076*/ BYTE tschds; /* TSCH device status */ 1781 /*077*/ BYTE tschsc; /* TSCH subchannel status */ 1782 /*078*/ FWORD resv078f; 1783 /*07C*/ FWORD resv07cf; 1784 /*080*/ DBLWRD mso; /* Main Storage Origin */ 1785 /*088*/ DBLWRD mse; /* Main Storage Extend 1786 The actual guest machine 1787 size is (mse+1)-mso */ 1788 #define SIE2_MS_MASK 0xFFFFFFFFFFF00000ULL 1789 /*090*/ QWORD psw; /* Guest PSW */ 1790 /*0A0*/ DBLWRD gr14; /* Guest gr 14 */ 1791 /*0A8*/ DBLWRD gr15; /* Guest gr 15 */ 1792 /*0B0*/ DBLWRD recv0b0d; 1793 /*0B8*/ HWORD recv0b8d; 1794 /*0BA*/ BYTE xso[3]; /* Expanded storage origin */ 1795 /*0BD*/ BYTE xsl[3]; /* Expanded storage limit */ 1796 /*0C0*/ BYTE ip[52]; /* Interruption parameters */ 1797 #define SIE_IP_PSA_OFFSET 0x40 /* Offset of the IP field 1798 relative to the ipfields 1799 in the PSA for ESAME guest*/ 1800 #define SIE_II_PSA_OFFSET 0x30 /* Offset of the IP field 1801 relative to the I/O fields 1802 in the PSA for ESAME guest*/ 1803 /*0F4*/ BYTE resv0f4b[6]; 1804 /*0FA*/ HWORD ief; /* Migration Emulation cnlt */ 1805 /*0FC*/ FWORD resv0fcf; 1806 /*100*/ DBLWRD cr[16]; /* Control registers */ 1807 /*180*/ BYTE resv180b[128]; 1808 } SIE2BK; 1809 1810 1811 #define SIE_VI_WHO_LVLM 0xF0 /* Mask for "source level" field: 1812 If non-zero, this is the inter- 1813 pretive-execution depth at which 1814 the problem was originally 1815 detected. It is set to 1 (or 2 1816 for Interpreted SIE) by the 1817 entity (hardware or vSIE software) 1818 that reports the problem, and is 1819 incremented (to a max of 15) by 1820 every level of vSIE that passes 1821 the interception along. */ 1822 #define SIE_VI_WHO_LVL1 0x10 /* Condition recognized one level 1823 down in interpretive execution */ 1824 #define SIE_VI_WHO_LVLMX 0xF0 /* Maximum source level reported */ 1825 #define SIE_VI_WHO_INITM 0x0F /* Mask for "initiator" field, 1826 identifying the type of entity 1827 that detected the problem. */ 1828 #define SIE_VI_WHO_CPU 0x01 /* Initiator was a CPU */ 1829 #define SIE_VI_WHO_VSIE 0x08 /* Initiator was vSIE software */ 1830 #define SIE_VI_WHEN_RECPM 0xF0 /* Mask for "recognition point" field 1831 the normal processing that 1832 recognized the condition 1833 necessitating the validity 1834 interception. */ 1835 #define SIE_VI_WHEN_SIENT 0x10 /* Condition recognized during SIE 1836 entry */ 1837 #define SIE_VI_WHEN_INST 0x20 /* Condition recognized during 1838 instruction interpretation */ 1839 #define SIE_VI_WHEN_IRPT 0x30 /* Condition recognized during 1840 interruption interpretation */ 1841 #define SIE_VI_WHEN_SIEXT 0x40 /* Condition recognized during SIE 1842 exit */ 1843 #define SIE_VI_WHY_MODE 0x0001 /* Invalid guest mode or invalid 1844 combination of modes */ 1845 #define SIE_VI_WHY_ARCHM 0x0002 /* Invalid architecture mode specified 1846 (neither or both S/370 and ESA/390) */ 1847 #define SIE_VI_WHY_370NI 0x0003 /* S/370 interpretation requested but 1848 not installed */ 1849 #define SIE_VI_WHY_PRMCS 0x0004 /* Preferred and MCDS modes specified 1850 together */ 1851 #define SIE_VI_WHY_MCS37 0x0005 /* MCDS and S/370 modes specified 1852 together */ 1853 #define SIE_VI_WHY_RRFNI 0x0006 /* RRF requested but not installed */ 1854 #define SIE_VI_WHY_ISINI 0x0007 /* iSIE requested but not installed */ 1855 #define SIE_VI_WHY_PFOUT 0x0010 /* Guest prefix outside guest extent */ 1856 #define SIE_VI_WHY_SCHPF 0x0011 /* SCA origin nonzero and its frame 1857 address matches host prefix reg */ 1858 #define SIE_VI_WHY_SDOVL 0x0030 /* State description overlaps guest 1859 storage */ 1860 #define SIE_VI_WHY_SCOVL 0x0031 /* SCA overlaps guest storage */ 1861 #define SIE_VI_WHY_APOVL 0x0032 /* APCB overlaps guest storage */ 1862 #define SIE_VI_WHY_SCADR 0x0034 /* SCA at invalid host address */ 1863 #define SIE_VI_WHY_APADR 0x0035 /* APCB at invalid host address */ 1864 #define SIE_VI_WHY_PFACC 0x0037 /* Access exception on guest prefix 1865 area */ 1866 #define SIE_VI_WHY_SCZER 0x0038 /* SCA origin nonzero but under 4K 1867 (8K for ESAME host) */ 1868 #define SIE_VI_WHY_APZER 0x0039 /* APCB origin is zero when an 1869 APCB is needed */ 1870 #define SIE_VI_WHY_PSADR 0x003A /* PGSTE at invalid host address */ 1871 #define SIE_VI_WHY_SCBDY 0x003B /* SCA crosses 4KB boundary */ 1872 #define SIE_VI_WHY_APBDY 0x003C /* APCB crosses 4KB boundary */ 1873 #define SIE_VI_WHY_MSLEX 0x003D /* MSL exceeds maximum host 1874 address supported for guest 1875 storage (ESAME SIE only) */ 1876 #define SIE_VI_WHY_MSDEF 0x0041 /* MSO exceeds MSL (ESAME SIE only) */ 1877 #define SIE_VI_WHY_MSDF2 0x0042 /* Alternate for MSDEF detected 1878 during guest prefix access */ 1879 #define SIE_VI_WHY_RRHPF 0x0046 /* RRF guest extent (zone) includes 1880 host prefix area */ 1881 #define SIE_VI_WHY_PRHPF 0x0050 /* Preferred guest extent includes 1882 host prefix area */ 1883 #define SIE_VI_WHY_MSONZ 0x0051 /* MSO not zero for preferred guest */ 1884 #define SIE_VI_WHY_CDXNI 0x0070 /* Crypto Domain Index not installed */ 1885 #define SIE_VI_WHY_DRFNI 0x1001 /* DRF requested but not installed */ 1886 #define SIE_VI_WHY_PRALE 0x1002 /* Alerting enabled for preferred 1887 non-DRF guest */ 1888 #define SIE_VI_WHY_AZNNI 0x1005 /* Zone identified by AZN is not 1889 installed */ 1890 #define SIE_VI_WHY_AZNNZ 0x1006 /* Nonzero AZN for non-RRF/DRF guest 1891 (or level-1 DSC nonzero for 1892 pageable guest) */ 1893 /* The following occur only under ESA/390 SIE: */ 1894 #define SIE_VI_WHY_MSSTL 0x0043 /* Guest extent exceeds host STL */ 1895 #define SIE_VI_WHY_HOSTF 0x0060 /* Invalid host translation format 1896 (CR0.8-12) */ 1897 #define SIE_VI_WHY_MSOFL 0x0061 /* Pageable guest extent exceeds 1898 2G-1 */ 1899 #define SIE_VI_WHY_RCOFL 0x0062 /* RCP area extends beyond 2G-1 in 1900 host virtual */ 1901 #define SIE_VI_WHY_RCSTL 0x0063 /* RCP area exceeds host STL */ 1902 #define SIE_VI_WHY_SCOFL 0x0064 /* SCA extends beyond 2G-1 */ 1903 #define SIE_VI_WHY_APOFL 0x0065 /* APCB extends beyond 2G-1 */ 1904 #define SIE_VI_WHY_RCZER 0x0067 /* RCP area origin is zero */ 1905 #define SIE_VI_WHY_PFSTL 0x0068 /* Guest prefix exceeds host STL */ 1906 #define SIE_VI_WHY_PTBDY 0x0069 /* PTO/PGST not on 2K boundary */ 1907 #define SIE_VI_WHY_MSODS 0x006A /* MSO nonzero for MCDS guest */ 1908 #define SIE_VI_WHY_SNOVL 0x1009 /* SNT overlaps guest storage */ 1909 #define SIE_VI_WHY_SNHPF 0x100C /* SNT overlaps host prefix area */ 1910 /* The following occur only in virtual machines under VM/ESA: */ 1911 #define SIE_VI_WHY_PFRDO 0xF000 /* Guest prefix maps to read-only 1912 storage (e.g. in a DCSS) */ 1913 #define SIE_VI_WHY_SCRDO 0xF001 /* SCA in read-only storage */ 1914 #define SIE_VI_WHY_OBMSB 0xF003 /* MSO/MSE not multiple of 1Meg... 1915 ..not supported in ESAME gen */ 1916 1917 /* Zone Parameter Block */ 1918 typedef struct _ZPB1 { 1919 FWORD mso; /* Main Storage Origin 1920 bits 0-15 must be 0 */ 1921 FWORD msl; /* Main Storage Limit 1922 bits 0-15 must be 0 */ 1923 FWORD eso; /* Expanded Storage Origin 1924 bits 0-7 must be 0 */ 1925 FWORD esl; /* Expanded Storage Limit 1926 bits 0-7 must be 0 */ 1927 FWORD res[4]; /* Reserved bits - must be 0 */ 1928 } ZPB1; 1929 1930 typedef struct _ZPB2 { 1931 DBLWRD mso; /* Main Storage Origin 1932 bits 0-19 must be 0 */ 1933 DBLWRD msl; /* Main Storage Limit 1934 bits 0-19 must be 0 */ 1935 #define ZPB2_MS_VALID 0x00000FFFFFFFFFFFULL 1936 DBLWRD eso; /* Expanded Storage Origin 1937 bits 0-7 must be 0 */ 1938 DBLWRD esl; /* Expanded Storage Limit 1939 bits 0-7 must be 0 */ 1940 #define ZPB2_ES_VALID 0x00FFFFFFFFFFFFFFULL 1941 } ZPB2; 1942 1943 typedef struct _SCAENT { 1944 FWORD scn; 1945 FWORD resv1; 1946 DBLWRD sda; /* Address of SIEBK */ 1947 DBLWRD resv2[2]; 1948 } SCAENT; 1949 1950 typedef struct _SCABLK { 1951 DBLWRD ipte_control; 1952 DBLWRD resv1[5]; 1953 DBLWRD mcn; /* Bitmap of VCPUs config */ 1954 DBLWRD resv2; 1955 SCAENT vcpu[64]; 1956 } SCABLK; 1957 1958 #define LKPG_GPR0_LOCKBIT 0x00000200 1959 #define LKPG_GPR0_RESV 0x0000FD00 1960 1961 #define STSI_GPR0_FC_MASK 0xF0000000 1962 #define STSI_GPR0_FC_CURRNUM 0x00000000 1963 #define STSI_GPR0_FC_BASIC 0x10000000 1964 #define STSI_GPR0_FC_LPAR 0x20000000 1965 #define STSI_GPR0_FC_VM 0x30000000 1966 #define STSI_GPR0_FC_CURRINFO 0xF0000000 1967 #define STSI_GPR0_SEL1_MASK 0x000000FF 1968 #define STSI_GPR0_RESERVED 0x0FFFFF00 1969 1970 #define STSI_GPR1_SEL2_MASK 0x0000FFFF 1971 #define STSI_GPR1_RESERVED 0xFFFF0000 1972 1973 typedef struct _SYSIB111 { /* Basic Machine Config */ 1974 BYTE flag1; /* 1.1.1 SYSIB Flag */ 1975 #define SYSIB111_PFLAG 0x80 /* Type percentage present */ 1976 BYTE resv1[3]; /* Reserved */ 1977 FWORD resv2[7]; /* Reserved */ 1978 BYTE manufact[16]; /* Manufacturer */ 1979 BYTE type[4]; /* Type */ 1980 FWORD resv3[3]; /* Reserved */ 1981 BYTE modcapaid[16]; /* Model capacity identifier */ 1982 BYTE seqc[16]; /* Sequence Code */ 1983 BYTE plant[4]; /* Plant of manufacture */ 1984 BYTE model[16]; /* System Model */ 1985 BYTE mpci[16]; /* Model Perm Capacity ID */ 1986 BYTE mtci[16]; /* Model Temp Capacity ID */ 1987 FWORD mcaprating; /* Model Capacity Rating */ 1988 FWORD mpcaprating; /* Model Perm Capacity Rating*/ 1989 FWORD mtcaprating; /* Model temp Capacity Rating*/ 1990 BYTE typepct[5]; /* Secondary CPU types pct */ 1991 } SYSIB111; 1992 1993 typedef struct _SYSIB121 { /* Basic Machine CPU */ 1994 FWORD resv1[20]; /* Reserved */ 1995 BYTE seqc[16]; /* Sequence Code */ 1996 BYTE plant[4]; /* Plant of manufacture */ 1997 HWORD resv2; /* Reserved */ 1998 HWORD cpuad; /* CPU address */ 1999 } SYSIB121; 2000 2001 typedef struct _SYSIB122 { /* Basic Machine CPUs */ 2002 BYTE format; /* Format 0 or 1 */ 2003 BYTE resv1; /* Reserved */ 2004 HWORD accoff; /* Offset to accap field */ 2005 FWORD resv2[6]; /* Reserved */ 2006 FWORD sccap; /* Secondary CPU Capability */ 2007 FWORD cap; /* CPU capability */ 2008 HWORD totcpu; /* Total CPU count */ 2009 HWORD confcpu; /* Configured CPU count */ 2010 HWORD sbcpu; /* Standby CPU count */ 2011 HWORD resvcpu; /* Reserved CPU count */ 2012 HWORD mpfact[MAX_CPU_ENGINES-1]; /* MP factors */ 2013 #if ((MAX_CPU_ENGINES-1) % 2) /* if prev is odd #of HWORDs */ 2014 HWORD resv3; /* then need some alignment */ 2015 #endif 2016 FWORD accap; /* Alternate CPU Capability */ 2017 HWORD ampfact[MAX_CPU_ENGINES-1]; /* Alternate MP factors */ 2018 #if ((MAX_CPU_ENGINES-1) % 2) /* if prev is odd #of HWORDs */ 2019 HWORD resv4; /* then need some alignment */ 2020 #endif 2021 } SYSIB122; 2022 2023 typedef struct _SYSIB221 { /* Logical partition CPU */ 2024 FWORD resv1[20]; /* Reserved */ 2025 BYTE seqc[16]; /* Logical CPU Sequence Code */ 2026 BYTE plant[4]; /* Plant of manufacture */ 2027 HWORD lcpuid; /* Logical CPU ID */ 2028 HWORD cpuad; /* CPU address */ 2029 } SYSIB221; 2030 2031 typedef struct _SYSIB222 { /* Logical partition CPUs */ 2032 FWORD resv1[8]; /* Reserved */ 2033 HWORD lparnum; /* LPAR number */ 2034 BYTE resv2; /* Reserved */ 2035 BYTE lcpuc; /* Logical CPU characteristic*/ 2036 #define SYSIB222_LCPUC_DEDICATED 0x80 2037 #define SYSIB222_LCPUC_SHARED 0x40 2038 #define SYSIB222_LCPUC_CAPPED 0x20 2039 HWORD totcpu; /* Total CPU count */ 2040 HWORD confcpu; /* Configured CPU count */ 2041 HWORD sbcpu; /* Standby CPU count */ 2042 HWORD resvcpu; /* Reserved CPU count */ 2043 BYTE lparname[8]; /* LPAR name */ 2044 FWORD lparcaf; /* LPAR capability adjustment*/ 2045 FWORD mdep[2]; /* Model Dependent */ 2046 FWORD resv3[2]; /* Reserved */ 2047 HWORD dedcpu; /* Dedicated CPU count */ 2048 HWORD shrcpu; /* Shared CPU count */ 2049 } SYSIB222; 2050 2051 typedef struct _SYSIB322 { /* Virtual Machines CPUs */ 2052 BYTE resv1[4*7]; /* Reserved */ 2053 BYTE resv2[3*1]; /* Reserved */ 2054 BYTE dbct; /* Four bit desc block count */ 2055 BYTE vmdb[4*16]; /* Virtual Machine desc block*/ 2056 } SYSIB322; 2057 2058 typedef struct _SYSIB1512 { /* Configuration Topology */ 2059 HWORD resv1; /* Reserved */ 2060 HWORD len; /* Length */ 2061 BYTE mag[6]; /* Magnitudes 6, 5, ... 1 */ 2062 BYTE resv2; /* Reserved */ 2063 BYTE mnest; /* Nesting Level */ 2064 FWORD resv3; /* Reserved */ 2065 BYTE tles[FLEXIBLE_ARRAY]; /* Topology List Entries */ 2066 } SYSIB1512; 2067 2068 typedef struct _TLECNTNR { /* Container TLE */ 2069 BYTE nl; /* Nesting Level */ 2070 BYTE resv1[3]; /* Reserved */ 2071 BYTE resv2; /* Reserved */ 2072 BYTE resv3[2]; /* Reserved */ 2073 BYTE cntnrid; /* Container Id */ 2074 } TLECNTNR; 2075 2076 typedef struct _TLECPU { /* CPU TLE */ 2077 BYTE nl; /* Nesting Level */ 2078 BYTE resv1[3]; /* Reserved */ 2079 BYTE flags; /* Flags */ 2080 BYTE cputype; /* CPU Type */ 2081 U16 cpuadorg; /* CPU Address Origin */ 2082 DW cpumask; /* CPU Mask */ 2083 } TLECPU; 2084 2085 /* Bit definitions for TLECPU flag byte */ 2086 #define CPUTLE_FLAG_DEDICATED 0x04 /* Dedicated CPU */ 2087 #define CPUTLE_FLAG_HORIZ 0x00 /* Horizontally polarized */ 2088 #define CPUTLE_FLAG_VERTLOW 0x01 /* Vertical low entitlement */ 2089 #define CPUTLE_FLAG_VERTMED 0x02 /* Vertical med entitlement */ 2090 #define CPUTLE_FLAG_VERTHIGH 0x03 /* Vertical high entitlement */ 2091 2092 typedef struct _SYSIBVMDB { /* Virtual Machine Desc Block*/ 2093 BYTE resv1[4*1]; /* Reserved */ 2094 HWORD totcpu; /* Total CPU count */ 2095 HWORD confcpu; /* Configured CPU count */ 2096 HWORD sbcpu; /* Standby CPU count */ 2097 HWORD resvcpu; /* Reserved CPU count */ 2098 BYTE vmname[8]; /* VM userid */ 2099 FWORD vmcaf; /* VM capability adjustment */ 2100 BYTE cpid[4*4]; /* Control Program ID */ 2101 } SYSIBVMDB; 2102 2103 #define PTFF_GPR0_RESV 0x00000080 2104 #define PTFF_GPR0_FC_MASK 0x0000007F 2105 #define PTFF_GPR0_FC_QAF 0x00 2106 #define PTFF_GPR0_FC_QTO 0x01 2107 #define PTFF_GPR0_FC_QSI 0x02 2108 #define PTFF_GPR0_FC_QPT 0x03 2109 #define PTFF_GPR0_FC_ATO 0x40 2110 #define PTFF_GPR0_FC_STO 0x41 2111 #define PTFF_GPR0_FC_SFS 0x42 2112 #define PTFF_GPR0_FC_SGS 0x43 2113 2114 typedef struct _PTFFQAF { /* Query Available Functions */ 2115 FWORD sb[4]; /* Status Bits words */ 2116 } PTFFQAF; 2117 2118 typedef struct _PTFFQTO { /* Query TOD Offset */ 2119 DBLWRD physclk; /* Physical Clock */ 2120 DBLWRD todoff; /* TOD Offset */ 2121 DBLWRD ltodoff; /* Logical TOD Offset */ 2122 DBLWRD todepoch; /* TOD Epoch Difference */ 2123 } PTFFQTO; 2124 2125 typedef struct _PTFFQSI { /* Query Steering Information*/ 2126 DBLWRD physclk; /* Physical Clock */ 2127 DBLWRD oldestart; /* Old Episode Start Time */ 2128 DBLWRD oldebase; /* Old Episode Base Offset */ 2129 FWORD oldfsr; /* Old Episode Fine St. Rate */ 2130 FWORD oldgsr; /* Old Episode Gross St. Rate*/ 2131 DBLWRD newestart; /* New Episode Start Time */ 2132 DBLWRD newebase; /* New Episode Base Offset */ 2133 FWORD newfsr; /* New Episode Fine St. Rate */ 2134 FWORD newgsr; /* New Episode Gross St. Rate*/ 2135 } PTFFQSI; 2136 2137 2138 #define SIGA_FC_W 0 /* Initiate Output */ 2139 #define SIGA_FC_R 1 /* Initiate Input */ 2140 #define SIGA_FC_S 2 /* Synchronize */ 2141 2142 #define SIGA_FC_MAX SIGA_FC_S 2143 2144 /* Bit definitions for floating-point-control register */ 2145 #define FPC_MASK 0xFC000000 /*810*/ 2146 #define FPC_MASK_IMI 0x80000000 2147 #define FPC_MASK_IMZ 0x40000000 2148 #define FPC_MASK_IMO 0x20000000 2149 #define FPC_MASK_IMU 0x10000000 2150 #define FPC_MASK_IMX 0x08000000 2151 #define FPC_MASK_IMQ 0x04000000 /*810*/ 2152 #define FPC_FLAG 0x00FC0000 /*810*/ 2153 #define FPC_FLAG_SFI 0x00800000 2154 #define FPC_FLAG_SFZ 0x00400000 2155 #define FPC_FLAG_SFO 0x00200000 2156 #define FPC_FLAG_SFU 0x00100000 2157 #define FPC_FLAG_SFX 0x00080000 2158 #define FPC_FLAG_SFQ 0x00040000 /*810*/ 2159 #define FPC_DXC 0x0000FF00 2160 #define FPC_DXC_I 0x00008000 2161 #define FPC_DXC_Z 0x00004000 2162 #define FPC_DXC_O 0x00002000 2163 #define FPC_DXC_U 0x00001000 2164 #define FPC_DXC_X 0x00000800 2165 #define FPC_DXC_Y 0x00000400 2166 #define FPC_DRM 0x00000070 2167 #define FPC_BRM_3BIT 0x00000007 /*810*/ 2168 #define FPC_BIT29 0x00000004 /*810*/ 2169 #define FPC_BRM_2BIT 0x00000003 /*810*/ 2170 #define FPC_RESV_FPX 0x03030088 /*810*/ 2171 #define FPC_RESERVED 0x0707008C 2172 2173 /* Shift counts to allow alignment of each field in the FPC register */ 2174 #define FPC_MASK_SHIFT 24 /*810*/ 2175 #define FPC_FLAG_SHIFT 16 /*810*/ 2176 #define FPC_DXC_SHIFT 8 2177 #define FPC_DRM_SHIFT 4 2178 #define FPC_BRM_SHIFT 0 2179 2180 /* Data exception codes */ 2181 #define DXC_DECIMAL 0x00 /* Decimal operand exception */ 2182 #define DXC_AFP_REGISTER 0x01 /* AFP register exception */ 2183 #define DXC_BFP_INSTRUCTION 0x02 /* BFP instruction exception */ 2184 #define DXC_DFP_INSTRUCTION 0x03 /* DFP instruction exception */ 2185 #define DXC_QUANTUM 0x04 /* Quantum exception 810*/ 2186 #define DXC_QUANTUM_IISE 0x07 /* Quantum simulated 810*/ 2187 #define DXC_IEEE_INEXACT_TRUNC 0x08 /* IEEE inexact, truncated */ 2188 #define DXC_IEEE_INEXACT_IISE 0x0B /* IEEE inexact (IISE) DFP*/ 2189 #define DXC_IEEE_INEXACT_INCR 0x0C /* IEEE inexact, incremented */ 2190 #define DXC_IEEE_UF_EXACT 0x10 /* IEEE underflow. exact */ 2191 #define DXC_IEEE_UF_EXACT_IISE 0x13 /* IEEE u/flow,exact(IISE)DFP*/ 2192 #define DXC_IEEE_UF_INEX_TRUNC 0x18 /* IEEE u/flow,inexact,trunc */ 2193 #define DXC_IEEE_UF_INEX_IISE 0x1B /* IEEE u/flow,inex(IISE) DFP*/ 2194 #define DXC_IEEE_UF_INEX_INCR 0x1C /* IEEE u/flow,inexact,incr */ 2195 #define DXC_IEEE_OF_EXACT 0x20 /* IEEE overflow. exact */ 2196 #define DXC_IEEE_OF_EXACT_IISE 0x23 /* IEEE o/flow,exact(IISE)DFP*/ 2197 #define DXC_IEEE_OF_INEX_TRUNC 0x28 /* IEEE o/flow,inexact,trunc */ 2198 #define DXC_IEEE_OF_INEX_IISE 0x2B /* IEEE o/flow,inex(IISE) DFP*/ 2199 #define DXC_IEEE_OF_INEX_INCR 0x2C /* IEEE o/flow,inexact,incr */ 2200 #define DXC_IEEE_DIV_ZERO 0x40 /* IEEE division by zero */ 2201 #define DXC_IEEE_DIV_ZERO_IISE 0x43 /* IEEE div by zero(IISE) DFP*/ 2202 #define DXC_IEEE_INVALID_OP 0x80 /* IEEE invalid operation */ 2203 #define DXC_IEEE_INV_OP_IISE 0x83 /* IEEE invalid op (IISE) DFP*/ 2204 #define DXC_COMPARE_AND_TRAP 0xFF /* Compare-and-trap exception*/ 2205 /* Note: IISE = IEEE-interruption-simulation event */ 2206 2207 /* Decimal rounding modes */ 2208 #define DRM_RNE 0 /* Round to nearest tie even */ 2209 #define DRM_RTZ 1 /* Round toward zero */ 2210 #define DRM_RTPI 2 /* Round toward +infinity */ 2211 #define DRM_RTMI 3 /* Round toward -infinity */ 2212 #define DRM_RNAZ 4 /* Round nearest tie away 0 */ 2213 #define DRM_RNTZ 5 /* Round nearest tie toward 0*/ 2214 #define DRM_RAFZ 6 /* Round away from zero */ 2215 #define DRM_RFSP 7 /* Prepare shorter precision */ 2216 2217 /* Binary rounding modes */ 2218 #define BRM_RNE 0 /* Round to nearest tie even */ 2219 #define BRM_RTZ 1 /* Round toward zero */ 2220 #define BRM_RTPI 2 /* Round toward +infinity */ 2221 #define BRM_RTMI 3 /* Round toward -infinity */ 2222 #define BRM_RESV4 4 /* Reserved (invalid) 810*/ 2223 #define BRM_RESV5 5 /* Reserved (invalid) 810*/ 2224 #define BRM_RESV6 6 /* Reserved (invalid) 810*/ 2225 #define BRM_RFSP 7 /* Prep shorter precision 810*/ 2226 2227 /* Mask bits for conditional SSKE facility */ 2228 #define SSKE_MASK_NQ 0x08 /* NonQuiesce */ 2229 #define SSKE_MASK_MR 0x04 /* Reference bit update mask */ 2230 #define SSKE_MASK_MC 0x02 /* Change bit update mask */ 2231 #define SSKE_MASK_MB 0x01 /* Multiple Block */ 2232 2233 /* Measurement alert external interruption parameter */ 2234 #define MAEIP_IEA 0x80000000 /* Invalid Entry Address */ 2235 #define MAEIP_ISDBTE 0x80000000 /* Incorrect sample-data-block- 2236 table entry */ 2237 #define MAEIP_PRA 0x20000000 /* Program request alert */ 2238 #define MAEIP_SACA 0x00800000 /* Sampling authorisation 2239 change alert */ 2240 #define MAEIP_LSDA 0x00400000 /* Loss of sample data alert */ 2241 #define MAEIP_CACA 0x00000080 /* Counter Authorisation 2242 change alert */ 2243 #define MAEIP_LCDA 0x00000040 /* Loss of counter data alert */ 2244 2245 #endif // _ESA390_H 2246